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| product specification asd1000 octal ultra low power 20/40/50/65/80msps 13-bit analog-to-digital converter features 20/40/50/65/80 msps maximum sampling rate ultra low power dissipation C 23 mw/channel at 20msps C 35 mw/channel at 40msps C 41 mw/channel at 50msps C 51 mw/channel at 65msps C 59 mw/channel at 80msps 72.2 db snr at 8mhz f in 0.5 s startup from sleep, 15 s from power down reduced power dissipation modes available C 71.5 db snr at 8mhz f in C 34 mw/channel at 50msps internal reference circuitry with no external components required coarse and fine gain control internal offset correction 1.8v supply voltage serial lvds output C 12 and 14-bit output available package alternatives C 9mm x 9mm, 64 pin qfn C 14mm x 14mm, 80 pin tqfp applications medical imaging wireless infrastructure test and measurement instrumentation description asd1000 is a high performance low power octal analog- to-digital converter (adc). the adc is based on a proprietary structure and employs internal reference circuitry, a serial control interface and serial lvds output data. data and frame synchronization output clocks are supplied for data capture at the receiver. various modes and configuration settings can be applied to the adc through the serial control interface (spi). each channel can be powered down independently and data format can be selected through this interface. a full chip idle mode can be set by a single external pin. register settings determine the exact function of this external pin. there are two options for the serial lvds outputs, 12- bit or 14-bit. in 12-bit mode, the lsb bit from the adcs are removed in the output stream. in 14-bit mode, a '0' is added in the lsb position. asd1000 is designed to easily interface with field- programmable gate arrays (fpgas) from several vendors. the very low start up times for asd1000 allows significant power reduction in duty-cycled systems, by utilizing the sleep modes or power down mode when the receive path is idle. vestre rosten 81, 7075 tiller, norway org. no: no 991 265 163mva phone: +47 73 10 29 00, fax: +47 73 10 29 19 www.arcticsilicon.com page 1 of 30 confidential lvds pll serial control interface c l k p c l k n s d a t a s c l k c s n d v d d a v s s a v d d fclkp fclkn lclkp lclkn p d r e s e t n d v s s dp1 dn1 ip1 in1 adc digital gain lvds dp2 dn2 ip2 in2 adc digital gain lvds dp8 dn8 ip8 in8 adc digital gain lvds clock input figure 1 : functional block diagram
product specification table of contents features ................................................................................................................................................................................. 1 applications .......................................................................................................................................................................... 1 description ............................................................................................................................................................................ 1 specifications ........................................................................................................................................................................ 3 asd1000l20 .................................................................................................................................................................. 4 asd1000l40 .................................................................................................................................................................. 5 asd1000l50 .................................................................................................................................................................. 6 asd1000l65 .................................................................................................................................................................. 7 asd1000l80 .................................................................................................................................................................. 8 digital and switching specifications .................................................................................................................................... 9 absolute maximum ratings ............................................................................................................................................... 10 pin configuration and description ..................................................................................................................................... 11 64 pin qfn ................................................................................................................................................................... 11 80 pin tqfp .................................................................................................................................................................. 13 serial interface .................................................................................................................................................................... 15 timing diagram ............................................................................................................................................................ 15 start up initialization .......................................................................................................................................................... 15 timing diagrams ................................................................................................................................................................ 16 serial register map ............................................................................................................................................................ 17 description of serial registers ........................................................................................................................................... 18 software reset .............................................................................................................................................................. 18 power-down modes ..................................................................................................................................................... 18 lvds drive strength programmability ........................................................................................................................ 19 lvds internal termination programmability ............................................................................................................... 19 analog input invert ....................................................................................................................................................... 20 lvds test patterns ....................................................................................................................................................... 20 programmable gain ...................................................................................................................................................... 21 lvds clock programmability and data output modes ............................................................................................... 22 number of serial output bits and lvds output timing ............................................................................................... 23 full-scale control ......................................................................................................................................................... 23 clock frequency ........................................................................................................................................................... 24 performance control .................................................................................................................................................... 24 theory of operation ........................................................................................................................................................... 26 recommended usage ......................................................................................................................................................... 26 analog input ................................................................................................................................................................. 26 clock input and jitter considerations ........................................................................................................................... 27 package mechanical data ................................................................................................................................................... 28 qfn64 ........................................................................................................................................................................... 28 tqfp80 ......................................................................................................................................................................... 29 product information ............................................................................................................................................................ 30 ordering information .......................................................................................................................................................... 30 datasheet status .................................................................................................................................................................. 30 asd1000 rev v3.1 , 2010.03.05 confidential page 2 of 30 product specification specifications avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 50msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14 bit output, unless otherwise noted parameter description min typ max unit dc accuracy no missing codes guaranteed offset error offset error after internal digital offset correction 1 lsb gain error 6 %fs gain matching gain matching between channels. 3sigma value at worst case conditions 0.5 %fs dnl differential nonlinearity (12-bit level) 0.2 lsb inl integral nonlinearity (12-bit level) 0.6 lsb v cm common mode voltage output v avdd /2 analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range differential input voltage range 2.0 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply analog supply voltage 1.7 1.8 2.0 v digital supply voltage digital and output driver supply voltage (up to 65 msps) 1.7 1.8 2.0 v digital supply voltage digital and output driver supply voltage (above 65 msps) 1.8 1.9 2.0 v ovdd supply voltage digital cmos input supply voltage 1.7 1.8 3.6 v temperature operating temperature operating free-air temperature -40 85 c asd1000 rev v3.1 , 2010.03.05 confidential page 3 of 30 product specification asd1000l20 avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14 bit output, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio f in = 8 mhz 70 72.2 dbfs f in = 30 mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8 mhz 69 71.5 dbfs f in = 30 mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc hd2 second order harmonic distortion f in = 8 mhz 85 95 dbc f in = 30 mhz 95 dbc hd3 third order harmonic distortion f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc enob effective number of bits f in = 8 mhz 11.6 bits f in = 30 mhz 11.5 bits crosstalk signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog supply current 47 ma digital supply current digital and output driver supply 54 ma analog power dissipation 84 mw digital power dissipation 97 mw total power dissipation 180 mw power down dissipation power down mode dissipation 10 w sleep mode dissipation deep sleep mode power dissipation 30 mw sleep channel mode dissipation power dissipation with all channels in sleep channel mode (light sleep) 46 mw sleep channel savings power dissipation savings per channel off 17 mw clock inputs max. conversion rate 20 msps min. conversion rate 15 msps asd1000 rev v3.1 , 2010.03.05 confidential page 4 of 30 product specification asd1000l40 avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14 bit output, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio f in = 8 mhz 70 72.2 dbfs f in = 30 mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8 mhz 69 71.5 dbfs f in = 30 mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc hd2 second order harmonic distortion f in = 8 mhz 85 95 dbc f in = 30 mhz 95 dbc hd3 third order harmonic distortion f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc enob effective number of bits f in = 8 mhz 11.6 bits f in = 30 mhz 11.5 bits crosstalk signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog supply current 90 ma digital supply current digital and output driver supply 67 ma analog power 162 mw digital power 120 mw total power dissipation 280 mw power down power down mode dissipation 10 w sleep mode deep sleep mode power dissipation 41 mw sleep channel mode power dissipation with all channels in sleep channel mode (light sleep) 71 mw sleep channel savings power dissipation savings per channel off 26 mw clock inputs max. conversion rate 40 msps min. conversion rate 20 msps asd1000 rev v3.1 , 2010.03.05 confidential page 5 of 30 product specification asd1000l50 avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 50msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14 bit output, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio f in = 8 mhz 70 72.2 dbfs f in = 30 mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8 mhz 69 71.5 dbfs f in = 30 mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc hd2 second order harmonic distortion f in = 8 mhz 85 95 dbc f in = 30 mhz 95 dbc hd3 third order harmonic distortion f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc enob effective number of bits f in = 8 mhz 11.6 bits f in = 30 mhz 11.5 bits crosstalk signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog supply current 111 ma digital supply current digital and output driver supply 73 ma analog power 200 mw digital power 132 mw total power dissipation 331 mw power down power down mode dissipation 10 w sleep mode deep sleep mode power dissipation 46 mw sleep channel mode power dissipation with all channels in sleep channel mode (light sleep) 83 mw sleep channel savings power dissipation savings per channel off 31 mw clock inputs max. conversion rate 50 msps min. conversion rate 20 msps asd1000 rev v3.1 , 2010.03.05 confidential page 6 of 30 product specification asd1000l65 avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14 bit output, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio f in = 8 mhz 70 72.2 dbfs f in = 30 mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8 mhz 69 71.5 dbfs f in = 30 mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc hd2 second order harmonic distortion f in = 8 mhz 85 95 dbc f in = 30 mhz 95 dbc hd3 third order harmonic distortion f in = 8 mhz 75 82 dbc f in = 30 mhz 77 dbc enob effective number of bits f in = 8 mhz 11.6 bits f in = 30 mhz 11.5 bits crosstalk signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog supply current 143 ma digital supply current digital and output driver supply 83 ma analog power 257 mw digital power 149 mw total power dissipation 405 mw power down power down mode dissipation 10 w sleep mode deep sleep mode power dissipation 54 mw sleep channel mode power dissipation with all channels in sleep channel mode (light sleep) 103 mw sleep channel savings power dissipation savings per channel off 38 mw clock inputs max. conversion rate 65 msps min. conversion rate 20 msps asd1000 rev v3.1 , 2010.03.05 confidential page 7 of 30 product specification asd1000l80 avdd=1.8v, dvdd=1.8v, ovdd=1.8v, 65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 12 bit output, unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio f in = 8 mhz 68.5 70.1 dbfs f in = 30 mhz 70 dbfs sinad signal to noise and distortion ratio f in = 8 mhz 68 69.6 dbfs f in = 30 mhz 69.5 dbfs sfdr spurious free dynamic range f in = 8 mhz 74 77 dbc f in = 30 mhz 76 dbc hd2 second order harmonic distortion f in = 8 mhz 85 90 dbc f in = 30 mhz 90 dbc hd3 third order harmonic distortion f in = 8 mhz 75 77 dbc f in = 30 mhz 76 dbc enob effective number of bits f in = 8 mhz 11.3 bits f in = 30 mhz 11.3 bits crosstalk signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog supply current 173 ma digital supply current digital and output driver supply 88 ma analog power 312 mw digital power 158 mw total power dissipation 470 mw power down power down mode dissipation 10 w sleep mode deep sleep mode power dissipation 56 mw sleep channel mode power dissipation with all channels in sleep channel mode (light sleep) 116 mw sleep channel savings power dissipation savings per channel off 44 mw clock inputs max. conversion rate 80 msps min. conversion rate 20 msps asd1000 rev v3.1 , 2010.03.05 confidential page 8 of 30 product specification digital and switching specifications avdd=1.8v, dvdd=1.8v, ovdd=1.8v, unless otherwise noted parameter description min typ max unit clock inputs duty cycle 20 80 % high compliance cmos, lvds, lvpecl input range, diff differential input swing +/-200 mvpp input range, sine differential input swing, sine wave clock input +/-800 mvpp input range, cmos voltage input range cmos (clkn connected to ground) v ovdd input common mode voltage keep voltages within ground and voltage of ovdd 0.3 v ovdd -0.3 v input capacitance differential 2 pf logic inputs (cmos) v hi high level input voltage. v ovdd 3.0v 2 v v hi high level input voltage. v ovdd = 1.7v C 3.0v 0.8 v ovdd v v li low level input voltage. v ovdd 3.0v 0 0.8 v v li low level input voltage. v ovdd = 1.7v C 3.0v 0 0.2 v ovdd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf data outputs (lvds) compliance lvds v out differential output voltage 350 mv v cm output common mode voltage 1.2 v output coding default/optional offset binary/ 2's complement timing characteristics aperture delay 0.8 ns aperture jitter <0.5 ps t su start up time from power down mode and deep sleep mode to active mode. references have reached 99% of final value. see section "clock frequency" 260 992 clock cycles start up time from power down mode and deep sleep mode to active mode in s. 15 s t slpch start up time from sleep channel mode to active mode 0.5 s t ovr out of range recovery time 1 clock cycles t lat pipeline delay 14 clock cycles lvds output timing characteristics t data lclk to data delay time (excluding programmable phase shift) 250 ps t prop clock propagation delay. 7*t lvds + 2.6 7*t lvds + 3.5 7*t lvds + 4.2 ns lvds bit-clock duty-cycle 45 55 %lclk cycle frame clock cycle-to-cycle jitter 2.5 %lclk cycle t edge data rise- and fall time 20% to 80% 0.4 ns t clkedge clock rise- and fall time 20% to 80% 0.4 ns asd1000 rev v3.1 , 2010.03.05 confidential page 9 of 30 product specification absolute maximum ratings applying voltages to the pins beyond those specified in table 1 could cause permanent damage to the circuit. table 1 : maximum voltage ratings pin reference pin rating avdd avss -0.3v to +2.3v dvdd dvss -0.3v to +2.3v ovdd avss -0.3v to +3.9v avss / dvss dvss / avss -0.3v to +0.3v analog inputs and outputs avss -0.3v to +2.3v clkx avss -0.3v to +3.9v lvds outputs dvss -0.3v to +2.3v digital inputs dvss -0.3v to +3.9v table 2 shows the maximum external temperature ratings. table 2 : maximum temperature ratings operating temperature -40 to +85 o c storage temperature -60 to +150 o c soldering profile qualification j-std-020 this device can be damaged by esd. even though this product is protected with state-of-the-art esd protection circuitry, damage may occur if the device is not handled with appropriate precautions. esd damage may range from device failure to performance degradation. analog circuitry may be more susceptible to damage as vary small parametric changes can result in specification noncompliance. asd1000 rev v3.1 , 2010.03.05 confidential page 10 of 30 product specification pin configuration and description there are two package options: 64-pin qfn and 80-pin tqfp. 64 pin qfn table 3 : pin descriptions for 64 pin qfn pin name description pin number # of pins avdd analog power supply, 1.8v 49, 50, 57 4 ovdd digital cmos inputs supply voltage 60 1 avss analog ground 3, 6, 9, 37, 40, 43, 46 7 ip1 positive differential input signal, channel 1 1 1 in1 negative differential input signal, channel 1 2 1 ip2 positive differential input signal, channel 2 4 1 in2 negative differential input signal, channel 2 5 1 ip3 positive differential input signal, channel 3 7 1 in3 negative differential input signal, channel 3 8 1 ip4 positive differential input signal, channel 4 10 1 in4 negative differential input signal, channel 4 11 1 ip5 positive differential input signal, channel 5 38 1 in5 negative differential input signal, channel 5 39 1 ip6 positive differential input signal, channel 6 41 1 asd1000 rev v3.1 , 2010.03.05 confidential page 11 of 30 figure 2 : package diagram for 64 pin qfn a v d d in8 ip8 avss in7 ip7 in6 ip6 avss in5 avss ip5 dvss dvdd d8p d 2 p d 2 n d 3 p d 3 n ip1 in1 avss in2 ip2 ip3 in3 ip4 avss in4 dvss pd dvss d1p avss d1n d 4 p d 4 n f c l k p f c l k n l c l k p l c l k n d 5 p d 5 n d 6 p d 6 n d 7 p d8n avss a v d d n c t p v c m n c n c n c a v d d c l k p c l k n o v d d c s n s d a t a d 7 n s c l k r e s e t n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 exposed pad, pin 0 (bottom of package) product specification pin name description pin number # of pins in6 negative differential input signal, channel 6 42 1 ip7 positive differential input signal, channel 7 44 1 in7 negative differential input signal, channel 7 45 1 ip8 positive differential input signal, channel 8 47 1 in8 negative differential input signal, channel 8 48 1 dvss digital ground 0, 12, 14, 36 4 dvdd digital and i/o power supply, 1.8v 35 1 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature 13 1 d1p lvds channel 1, positive output 15 1 d1n lvds channel 1, negative output 16 1 d2p lvds channel 2, positive output 17 1 d2n lvds channel 2, negative output 18 1 d3p lvds channel 3, positive output 19 1 d3n lvds channel 3, negative output 20 1 d4p lvds channel 4, positive output 21 1 d4n lvds channel 4, negative output 22 1 d5p lvds channel 5, positive output 27 1 d5n lvds channel 5, negative output 28 1 d6p lvds channel 6, positive output 29 1 d6n lvds channel 6, negative output 30 1 d7p lvds channel 7, positive output 31 1 d7n lvds channel 7, negative output 32 1 d8p lvds channel 8, positive output 33 1 d8n lvds channel 8, negative output 34 1 fclkp lvds frame clock (1x), positive output 23 1 fclkn lvds frame clock (1x), negative output 24 1 lckp lvds bit clock, positive output 25 1 lckn lvds bit clock, negative output 26 1 nc not connected 51 1 tp test pin, leave unconnected or connect to ground 52 1 vcm common mode output pin, 0.5*avdd 53 1 nc not connected 54 1 nc not connected 55 1 nc not connected 56 1 clkp positive differential input clock 58 1 clkn negative differential input clock. 59 1 csn chip select enable. active low 61 1 sdata serial data input 62 1 sclk serial clock input 63 1 resetn reset spi interface. active low 64 1 asd1000 rev v3.1 , 2010.03.05 confidential page 12 of 30 product specification 80 pin tqfp figure 3 : package diagram for 80 pin tqfp table 4 : pin descriptions for 80 pin tqfp pin name description pin number # of pins avdd analog power supply, 1.8v 1, 7, 14, 47, 54, 60, 63, 70 8 ovdd digital cmos inputs supply voltage 75 1 avss analog ground 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 11 ip1 positive differential input signal, channel 1 2 1 in1 negative differential input signal, channel 1 3 1 ip2 positive differential input signal, channel 2 5 1 in2 negative differential input signal, channel 2 6 1 ip3 positive differential input signal, channel 3 9 1 in3 negative differential input signal, channel 3 10 1 ip4 positive differential input signal, channel 4 12 1 in4 negative differential input signal, channel 4 13 1 ip5 positive differential input signal, channel 5 48 1 in5 negative differential input signal, channel 5 49 1 ip6 positive differential input signal, channel 6 51 1 asd1000 rev v3.1 , 2010.03.05 confidential page 13 of 30 in8 ip8 avss in7 ip7 in6 ip6 avss in5 avss ip5 dvss d v d d d 8 p d 2 p d 2 n d 3 p d 3 n ip1 in1 avss in2 ip2 ip3 in3 ip4 avss in4 dvss pd dvss d 1 p avss d 1 n d 4 p d 4 n fclkp fclkn lclkp lclkn d 5 p d 5 n d 6 p d 6 n d 7 p d 8 n dvss a v d d n c a v s s v c m n c n c n c a v d d c l k p c l k n o v d d c s n s d a t a d 7 n s c l k resetn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 17 18 19 20 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 60 59 58 57 56 55 54 53 52 51 50 49 6 8 6 7 6 6 6 5 6 9 7 0 7 4 7 3 7 2 7 1 7 8 7 7 7 6 7 5 7 9 8 0 avdd avdd dvss avdd avdd avdd avdd dvss d v s s d v d d d v s s a v s s a v s s a v s s a v s s n c t p product specification pin name description pin number # of pins in6 negative differential input signal, channel 6 52 | ip7 positive differential input signal, channel 7 55 1 in7 negative differential input signal, channel 7 56 1 ip8 positive differential input signal, channel 8 58 1 in8 negative differential input signal, channel 8 59 1 dvss digital ground 15, 17, 18, 26, 36, 43, 44, 46 8 dvdd digital and i/o power supply, 1.8v 25, 35 2 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature 16 1 lckp lvds bit clock, positive output 19 1 lckn lvds bit clock, negative output 20 1 d1p lvds channel 1, positive output 21 1 d1n lvds channel 1, negative output 22 1 d2p lvds channel 2, positive output 23 1 d2n lvds channel 2, negative output 24 1 d3p lvds channel 3, positive output 27 1 d3n lvds channel 3, negative output 28 1 d4p lvds channel 4, positive output 29 1 d4n lvds channel 4, negative output 30 1 d5p lvds channel 5, positive output 31 1 d5n lvds channel 5, negative output 32 1 d6p lvds channel 6, positive output 33 1 d6n lvds channel 6, negative output 34 1 d7p lvds channel 7, positive output 37 1 d7n lvds channel 7, negative output 38 1 d8p lvds channel 8, positive output 39 1 d8n lvds channel 8, negative output 40 1 fclkp lvds frame clock (1x), positive output 41 1 fclkn lvds frame clock (1x), negative output 42 1 resetn reset spi interface. active low 45 1 tp test pin, leave unconnected or connect to ground 61 1 nc not connected 62 1 nc not connected 64 1 vcm common mode output pin, 0.5*avdd 65 1 nc not connected 66 1 nc not connected 67 1 nc not connected 69 1 clkp positive differential input clock 71 1 clkn negative differential input clock. 72 1 csn chip select enable. active low 76 1 sdata serial data input 77 1 sclk serial clock input 78 1 asd1000 rev v3.1 , 2010.03.05 confidential page 14 of 30 product specification serial interface the asd1000 configuration registers can be accessed through a serial interface formed by the pins sdata (serial interface data), sclk (serial interface clock) and csn (chip select, active low). the following occurs when csn is set low: serial data are shifted into the chip at every rising edge of sclk, the value present at sdata is latched sdata is loaded into the register every 24th rising edge of sclk multiples of 24-bit words data can be loaded within a single active csn pulse. if more than 24 bits are loaded into sdata during one active csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word is divided into two parts: the first eight bits form the register address the remaining 16 bits form the register data acceptable sclk frequencies are from 20mhz down to a few hertz. duty-cycle does not have to be tightly controlled. timing diagram figure 4 shows the timing of the serial port interface. table 5 explains the timing variables used in figure 4 . table 5 : serial port interface timing definitions parameter description minimum value unit t cs setup time between csn and sclk 8 ns t ch hold time between csn and sclk 8 ns t hi sclk high time 20 ns t lo sclk low time 20 ns t ck sclk period 50 ns t s data setup time 5 ns t h data hold time 5 ns start up initialization before asd1000 can be used, the internal registers must be initialized to their default values and power down must be activated. this can be done immediately after applying supply voltage to the circuit. register initialization can be done in one of two ways: 1. b y applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the 'rst' bit high. internal registers are reset to default values when this bit is set. the 'rst' bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down initialization can be done in one of two ways: 1. by applying a high-going pulse (minimum 20 ns) on the pd pin (asynchronous). 2. by cycling the spi register 0f hex 'pd' bit to high (reg value '0200' hex ) and then low (reg value '0000' hex ). asd1000 rev v3.1 , 2010.03.05 confidential page 15 of 30 figure 4 : serial port interface timing csn sclk sdata t s t h t cs t chi t hi t lo t ck t ch a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 product specification timing diagrams figure 5 : lvds timing 12 bit output, ddr mode figure 6 : lvds timing 14 bit output, ddr mode figure 7 : lvds timing 12 bit output, sdr mode figure 8 : lvds data timing, ddr mode asd1000 rev v3.1 , 2010.03.05 confidential page 16 of 30 t lvds d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n+14 n+15 analog input adc clock lclk p lclk n fclk n fclk p dxx<1:0> n-2 n-2 d10 d11 t prop d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 n n n n n n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n+14 n+15 analog input adc clock lclk n lclk p fclk n fclk p dxx<1:0> t prop t lvds t lvds d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n+14 n+15 analog input adc clock lclk n lclk p fclk n fclk p dxx<1:0> n-2 n-2 d10 d11 t prop t lvds t lvds /2 dxx<1:0> t data lclk p lclk n product specification serial register map table 6 : summary of functions supported by the serial interface name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex rst self-clearing software reset inactive x 00 pd_ch<8:1> channel-specific power-down inactive x x x x x x x x 0f sleep go to sleep-mode inactive x pd go to power-down inactive x pd_pin_cfg<1:0> configures the pd pin for sleep- modes pd pin configured for power-down mode x x ilvds_lclk<2:0> lvds current drive programmability for lclkp and lclkn pins 3.5 ma drive x x x 11 ilvds_frame<2:0> lvds current drive programmability for fclkp and fclkn pins 3.5 ma drive x x x ilvds_dat<2:0> lvds current drive programmability for output data pins 3.5 ma drive x x x en_lvds_term enables internal termination for lvds buffers termination disabled x 12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers termination disabled 1 x x x term_frame<2:0> programmable termination for fclkn and fclkp buffers termination disabled 1 x x x term_dat<2:0> programmable termination for output data buffers termination disabled 1 x x x invert_ch<8:1> swaps the polarity of the analog input pins ipx is positive input x x x x x x x x 24 en_ramp enables a repeating full-scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_pat enables the mode wherein the output toggles between two defined codes inactive 0 x 0 single_custom_pat enables the mode wherein the output is a constant specified code inactive 0 0 x bits_custom1 <13:0> bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the lsb inactive x x x x x x x x x x x x x x 26 bits_custom2 <13:0> bits for the second code of the dual custom pattern inactive x x x x x x x x x x x x x x 27 gain_ch1<3:0> programmable gain for channel 1 0db gain x x x x 2a gain_ch2<3:0> programmable gain for channel 2 0db gain x x x x gain_ch3<3:0> programmable gain for channel 3 0db gain x x x x gain_ch4<3:0> programmable gain for channel 4 0db gain x x x x gain_ch5<3:0> programmable gain for channel 5 0db gain x x x x 2b gain_ch6<3:0> programmable gain for channel 6 0db gain x x x x gain_ch7<3:0> programmable gain for channel 7 0db gain x x x x gain_ch8<3:0> programmable gain for channel 8 0db gain x x x x phase_ddr<1:0> controls the phase of lclk output relative to data 90 degrees x x 42 pat_deskew enables deskew pattern mode inactive 0 x 45 pat_sync enables sync pattern mode inactive x 0 asd1000 rev v3.1 , 2010.03.05 confidential page 17 of 30 product specification name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex btc_mode binary two's complement format for adc output data straight offset binary x 46 msb_first serialized adc output data comes out with msb first lsb-first output x en_sdr enable sdr output mode. lclk becomes a 12x/14x input clock ddr output mode x fall_sdr rising edge of lclk comes in the middle of the data window in sdr mode rising edge x 1 perfm_cntrl<2:0> adc performance control nominal x x x 50 ext_vcm_bc<1:0> vcm buffer driving strength control nominal x x lvds_pd_mode controls lvds power down mode high z mode x 52 lvds_num_bits sets the number of lvds output bits 12 bit x 53 lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 55 clk_freq<1:0> input clock frequency 65 mhz x x 56 description of serial registers software reset name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex rst self-clearing software reset inactive x 00 setting the rst register bit to '1', resets all internal registers including the rst register bit itself. power-down modes name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex pd_ch<8:1> channel-specific power-down. inactive x x x x x x x x 0f sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg<1:0> configures the pd pin for sleep- modes. pd pin configured for power-down mode x x lvds_pd_mode controls lvds power down mode high z mode x 52 there are several ways to power down asd1000, from sleep modes with short start up time to full power down with extremely low power dissipation. there are two sleep modes, both with the lvds clocks (fclk, lclk) running, such that the synchronization with the receiver is maintained. the first is a light sleep mode ( pd_ch<8:1> ) with short start up time, and the second a deep sleep mode ( sleep ) with the same start up time as full power down. setting pd_ch product specification pin. setting pdn_pin_cfg<1:0> = '10' configures the circuit to enter (deep) sleep mode when pd pin is set high (equal to setting sleep ='1'. when pdn_pin_cfg <1:0>= '00', which is the default, the circuit enters power down mode when the pd pin is set high. the lvds_pd_mode register configures whether the lvds data output drivers are powered down or kept alive in sleep and sleep channel modes. lclk and fclk drivers are not affected by this register, and are always on in sleep and sleep channel modes. if lvds_pd_mode is set low (default), the lvds output is put in high z mode, and the driver is completely powered down. if lvds_pd_mode is set high, the lvds output is set to constant 0, and the driver is still on during sleep and sleep channel modes. lvds drive strength programmability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex ilvds_lclk<2:0> lvds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 11 ilvds_frame<2:0> lvds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat<2:0> lvds current drive programmability for output data pins. 3.5 ma drive x x x the current delivered by the lvds output drivers can be configured as shown in table 7 . the default current is 3.5ma, which is what the lvds standard specifies. setting the ilvds_lclk<2:0> register controls the current drive strength of the lvds clock output on the lclkp and lclkn pins. setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the fclkp and fclkn pins. setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the d[8:1]p and d[8:1]n pins. table 7 : lvds output drive strength for lclk, fclk and data ilvds_*<2:0> lvds drive strength 000 3.5 ma (default) 001 2.5 ma 010 1.5 ma 011 0.5 ma 100 7.5 ma 101 6.5 ma 110 5.5 ma 111 4.5 ma lvds internal termination programmability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex en_lvds_term enables internal termination for lvds buffers termination disabled x 12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers termination disabled 1 x x x term_frame<2:0> programmable termination for fclkn and fclkp buffers termination disabled 1 x x x term_dat<2:0> programmable termination for dxp and dxn buffers termination disabled 1 x x x the off-chip load on the lvds buffers may represent a characteristic impedance that is not perfectly matched with the pcb traces. this may result in reflections back to the lvds outputs and loss of signal integrity. this effect can be mitigated by enabling an internal termination between the positive and negative outputs of each lvds buffer. internal asd1000 rev v3.1 , 2010.03.05 confidential page 19 of 30 product specification termination mode can be selected by setting the en_lvds_term bit to '1'. once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. table 8 shows how the internal termination of the lvds buffers are programmed. the values are typical values and can vary by up to 20% from device to device and across temperature. table 8 : lvds output internal termination for lclk, fclk and data term_*<2:0> lvds internal termination 000 termination disabled 001 280 ? 010 165 ? 011 ???? 100 125 ? 101 ??? 110 ??? 111 ??? analog input invert name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex invert_ch<8:1> swaps the polarity of the analog input pins ipx is positive input x x x x x x x x 24 the ipx pin represents the positive analog input pin, and inx represents the negative (complementary) input. setting the bits marked invert_ch<8:1> (individual control for each channel) causes the inputs to be swapped. inx would then represent the positive input, and ipx the negative input. lvds test patterns name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex en_ramp enables a repeating full-scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_pat enables the mode wherein the output toggles between two defined codes inactive 0 x 0 single_custom_pat enables the mode wherein the output is a constant specified code inactive 0 0 x bits_custom1 <13:0> bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the lsb inactive. x x x x x x x x x x x x x x 26 bits_custom2 <13:0> bits for the second code of the dual custom pattern inactive. x x x x x x x x x x x x x x 27 pat_deskew enables deskew pattern mode inactive 0 x 45 pat_sync enables sync pattern mode inactive x 0 to ease the lvds synchronization setup of asd1000 , several test patterns can be set up on the outputs. normal adc data are replaced by the test pattern in these modes. setting en_ramp to '1' sets up a repeating full-scale ramp pattern on all data outputs. the ramp starts at code zero and is increased 1lsb every clock cycle. it returns to zero code and starts the ramp again after reaching the full-scale code. a constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value in bits_custom1<13:0> . in this mode, bits_custom1<13:0> replaces the adc data at the output, and is controlled by lsb- first and msb-first modes in the same way as normal adc data are. the device may also be made to alternate between two codes by programming dual_custom_pat to '1'. the two codes are the contents of bits_custom1<13:0> and bits_custom2<13:0> . two preset patterns can also be selected: 1. deskew pattern: s et using pat_deskew , this mode replaces the adc output with '01010101010101' (two lsbs asd1000 rev v3.1 , 2010.03.05 confidential page 20 of 30 product specification removed in 12 bit mode). 2. sync pattern: set u sing pat_sync , the normal adc word is replaced by a fixed '11111110000000' word ('111111000000' in 12 bit mode) note: only one of the above patterns should be selected at the same time. programmable gain name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex gain_ch1<3:0> programmable gain for channel 1 0db gain x x x x 2a gain_ch2<3:0> programmable gain for channel 2 0db gain x x x x gain_ch3<3:0> programmable gain for channel 3 0db gain x x x x gain_ch4<3:0> programmable gain for channel 4 0db gain x x x x gain_ch5<3:0> programmable gain for channel 5 0db gain x x x x 2b gain_ch6<3:0> programmable gain for channel 6 0db gain x x x x gain_ch7<3:0> programmable gain for channel 7 0db gain x x x x gain_ch8<3:0> programmable gain for channel 8 0db gain x x x x asd1000 includes a purely digital programmable gain option in addition to the full-scale control. the programmable gain of each channel can be individually set using four bits, indicated as gain_chx<3:0> for channel x. the gain setting is coded in binary from 0db to 12db, as shown in table 9 . table 9 : gain setting for channels 1-8 gain_chx<3:0> channel x gain setting 0000 0db 0001 1db 0010 2db 0011 3db 0100 4db 0101 5db 0110 6db 0111 7db 1000 8db 1001 9db 1010 10db 1011 11db 1100 12db 1101 do not use 1110 do not use 1111 do not use asd1000 rev v3.1 , 2010.03.05 confidential page 21 of 30 product specification lvds clock programmability and data output modes name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex phase_ddr<1:0> controls the phase of lclk output relative to data. 90 degrees. x x 42 btc_mode binary two's complement format for adc output data. straight offset binary. x 46 msb_first serialized adc output data comes out with msb first. lsb-first output. x en_sdr enable sdr output mode. lclk becomes a 12x input clock. ddr output mode. x fall_sdr controls whether the lclk rising or falling edge comes in the middle of the data window when operating in sdr mode. rising edge of lclk comes in the middle of the data window. x 1 the output interface of asd1000 is normally a ddr interface, with the lclk rising and falling edge transitions in the middle of alternate data windows. the phase for lclk can be programmed relative to the output frame clock and data bits using phase_ddr<1:0> . the lclk phase modes are shown in figure 9 . the default timing is identical to setting phase_ddr<1:0> ='10'. figure 9 : phase programmability modes for lclk the device can also be made to operate in sdr mode by setting the en_sdr bit to '1'. the bit clock (lclk) is output at 12x times the input clock in this mode, two times the rate in ddr mode. depending on the state of fall_sdr , lclk may be output in either of the two manners shown in figure 10 . as can be seen in figure 10 , only the lclk rising (or falling) edge is used to capture the output data in sdr mode. the sdr mode is not recommended beyond 40 msps because the lclk frequency becomes very high. figure 10 : sdr interface modes the default data output format is offset binary. two's complement mode can be selected by setting the btc_mode bit to '1' which inverts the msb. the first bit of the frame (following the rising edge of fclkp) is the lsb of the adc output for default settings. programming the msb_first mode results in reverse bit order, and the msb is output as the first bit following the fclkp rising edge. asd1000 rev v3.1 , 2010.03.05 confidential page 22 of 30 fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> en_sdr='1', fall_sdr_'0' en_sdr='1', fall_sdr_'1' fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> fclk n fclk p lclk p lclk n dxx<1:0> phase_ddr<1:0>='00' (270 deg) phase_ddr<1:0>='10' (90 deg) phase_ddr<1:0>='01' (180 deg) phase_ddr<1:0>='11' (0 deg) product specification number of serial output bits and lvds output timing name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex lvds_num_bits sets the number of lvds output bits 12 bit x 53 lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 the adc channels have 13 bits of resolution. there are two options for the serial lvds outputs, 12 bits or 14 bits, selected by setting lvds_num_bits to '0' or '1', respectively. in 12 bits mode, the lsb bit from the adcs are removed in the output stream. in 14 bit mode, a '0' is added in the lsb position. power down mode must be activated after or during a change in the number of output bits. to ease timing in the receiver when using multiple adc chips, asd1000 has the option to adjust the timing of the output data and the frame clock. the propagation delay with respect to the adc input clock can be moved one lvds clock cycle forward or backward, by using lvds_delay and lvds_advance , respectively. see figure 11 for details. note that lclk is not affected by lvds_delay or lvds_advance settings. full-scale control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 55 the full-scale voltage range of asd1000 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. this leads to a maximum range of 10% adjustment. table 10 shows how the register settings correspond to the full-scale range. note that the values for full-scale range adjustment are approximate. the dac is, however, guaranteed to be monotonous. the full-scale control and the programmable gain features differ in two major ways: 1. the full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. the programmable gain feature has much coarser gain steps and larger range than the full-scale control. asd1000 rev v3.1 , 2010.03.05 confidential page 23 of 30 figure 11 : lvds output timing adjustment d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 n n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 adc clock lclk p lclk n fclk p fclk n dxx<1:0> d0 d1 d2 d3 d4 d5 d6 d7 d8 n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 fclk p fclk n dxx<1:0> d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 n n n n n n n n n n n n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 fclk p fclk n dxx<1:0> lvds_delay = '1': lvds_advance = '1': default: t lvds d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 t lvds t lvds t prop t prop t prop product specification table 10 : register values with corresponding change in full-scale range fs_cntrl<5:0> full-scale range adjustment 111111 +9.7% 111110 +9.4% ... ... 100001 +0.3% 100000 +0% 011111 ?0.3% ... ... 000001 ?9.7% 000000 ?10% clock frequency name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex clk_freq<1:0> input clock frequency 50 - 80 mhz x x 56 to optimize start up time, a register is provided where the input clock frequency can be set. some internal circuitry have start up times that are clock frequency independent. default counter values are set to accommodate these start up times at the maximum clock frequency. this will lead to increased start up times at low clock frequency. setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. the start up times from power down mode and deep sleep mode are changed by this register setting. table 11 : clock frequency settings clk_freq <1:0> clock frequency range startup delay (clock cycles) startup delay (s) 0 0 50 - 80 mhz 992 12.4 - 19.8 0 1 32,5 - 50 mhz 640 12.8 - 19.7 1 0 20 - 32,5 mhz 420 12.9 - 21 1 1 15 - 20 mhz 260 13 - 17.3 performance control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex perfm_cntrl<2:0> adc performance control nominal x x x 50 ext_vcm_bc<1:0> vcm buffer driving strength control nominal x x there are two registers that impact performance and power dissipation. the perfm_cntrl register adjusts the performance level of the adc core. if full performance is required, the nominal setting must be used. the lowest code can be used in situations where power dissipation is critical and performance is less important. for most conditions the performance at the minimum setting will be similar to nominal setting. however, only 11 bit performance can be expected at worst case conditions. the power dissipation savings shown in table 12 are only approximate numbers for the adc current alone. asd1000 rev v3.1 , 2010.03.05 confidential page 24 of 30 product specification table 12 : performance control settings perfm_cntrl<2:0> analog power dissipation 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) nominal 001 do not use 010 do not use 011 do not use the ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the vcm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the vcm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. table 13 : external common mode voltage buffer driving strength ext_vcm_bc<1:0> vcm buffer driving strength 00 off (vcm floating) 01 (default) low 10 high 11 max asd1000 rev v3.1 , 2010.03.05 confidential page 25 of 30 product specification theory of operation asd1000 is an 8-channel, high-speed, cmos adc. the 13 bits given out by each channel are serialized to 12 or 14 bits and sent out on a single pair of pins in lvds format. all eight channels of asd1000 operate from one clock input, which can be differential or single ended. the sampling clocks for each of the eight channels are generated from the clock input using a carefully matched clock buffer tree. the 12x/14x clock required for the serializer is generated internally from fclk using a phase-locked loop (pll). a 6x/7x and 1x clock are also output in lvds format, along with the data to enable easy data capture. asd1000 uses internally generated references. the differential reference value is 1v. this results in a differential input o f ?1v to correspond to the zero code of the adc, and a differential input of +1v to correspond to the full-scale code (code 8191). the adc employs a pipelined converter architecture. each stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at 13-bit level. asd1000 operates from two sets of supplies and grounds. the analog supply and ground set is identified as avdd and avss, while the digital set is identified by dvdd and dvss. recommended usage analog input the analog input to asd1000 is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the vcm pin provides a voltage suitable as common mode voltage reference. the internal buffer for the vcm voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc<1:0> register. figure 12 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. dc-coupling figure 13 shows a recommended configuration for dc- coupling. note that the common mode input voltage must be controlled according to specified values. preferably, the cm_ext output should be used as reference to set the common mode voltage. figure 13 : dc coupled input the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with asd1000 input specifications. detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 13 must be varied according to the recommendations for the driver. ac-coupling figure 14 : transformer coupled input a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 14 shows a recommended configuration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most asd1000 rev v3.1 , 2010.03.05 confidential page 26 of 30 figure 12 : input configuration track track track track hold hold inx ipx 2.1 pf 2.1 pf ipx inx cm_ext input input amplifier 43 43 33 pf ipx inx cm_ext input 33 33 r t 47 product specification differential amplifiers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in figure 16 can be used. figure 15 shows ac-coupling using capacitors. resistors from the cm_ext output, r cm , should be used to bias the differential input signals to the correct voltage. the series capacitor, c i , form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. note that start up time from sleep mode and power down mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc are not effectively terminated at the signal source, the input network of figure 16 can be used. the configuration in figure 16 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. values of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. this capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in asd1000 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally, hence a wide common mode voltage range is accepted. differential clock sources such as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least +/- 0.8 vpp. no additional configuration is needed to set up the clock source format. the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1 . snr jitter = 20 ? log 2 ? ? f in ? t ( 1 ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. asd1000 rev v3.1 , 2010.03.05 confidential page 27 of 30 figure 16 : alternative input network ipx inx cm_ext input 1:1 r t 68 120nh 120nh 33 33 220 22pf optional figure 15 : ac coupled input ipx inx cm_ext 22 22 22 pf c i c i r cm r cm innx inpx product specification package mechanical data qfn64 table 14 : qfn64 dimensions millimeter inch symbol min typ max min typ max a 0.9 0.035 a1 0.00 0.01 0.05 0.00 0.0004 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 ref. 0.008 ref. b 0.2 0.25 0.3 0.008 0.010 0.012 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc d2 5.0 5.2 5.4 0.197 0.205 0.213 l 0.3 0.4 0.5 0.012 0.016 0.020 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 1.3 0.05 g 0.24 0.42 0.6 0.0096 0.0168 0.024 asd1000 rev v3.1 , 2010.03.05 confidential page 28 of 30 e 1.14 f a2 a3 1 b d d2 d 1 d d 2 a pin 1 id dia 0.20 a1 l g pin 0, exposed pad bottom view pin 1 id (top side) dia 0.50 0.45 1 64 16 17 32 33 48 49 1.14 product specification tqfp80 table 15 : tqfp80 dimensions millimeter inch symbol min typ max min typ max a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 d 14.00 bsc 0.551 bsc d1 12.00 bsc 0.472 bsc d2 9.50 0.374 e 0.50 bsc 0.020 bsc b 0.17 0.20 0.27 0.007 0.008 0.011 c 0.09 0.20 0.004 0.008 0 3.5 7 0 3.5 7 1 0 0 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 0.008 asd1000 rev v3.1 , 2010.03.05 confidential page 29 of 30 c b a a2 l1 s l 1 e d1 d d2 d 1 d d 2 a1 top view pin 1 id 1 20 21 40 41 60 61 80 product specification product information product status datasheet revision date asd1000 product specification v3.1 2010.03.05 ordering information model temp. range package type package drawing msl, peak temp (1) transport media asd1000 l80-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd1000 l80-ipt -40 to +85 c 80 pin tqfp tqfp80 level 3 tray asd1000 l65-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd1000 l65-ipt -40 to +85 c 80 pin tqfp tqfp80 level 3 tray asd1000 l50-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd1000 l50-ipt -40 to +85 c 80 pin tqfp tqfp80 level 3 tray asd1000 l40-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd1000 l40-ipt -40 to +85 c 80 pin tqfp tqfp80 level 3 tray (1) msl, peak temp: the moisture sensitivity level rating classified according to the jedec industry standard and to peak solder temperature. datasheet status objective product specification: the values and functionality describe design targets only. specifications and functionality can be changed without notice. preliminary product specification: the specifications are based on initial design results. specifications and functionality can be changed without notice. product specification: information is current as of publication data. products conform to specifications according to the terms of arctic silicon devices as standard warranty. production does not necessarily require all parameters to be tested. arctic silicon devices as vestre rosten 81 n-7075 tiller norway tel: +47 73 10 29 00 fax: +47 73 10 29 19 information provided in this document is believed to be accurate and reliable. however, no responsibility is assumed by arctic silicon devices as for its use. neither is any responsibility assumed for any infringement of patents or other third party rights that may result from the use of the product or information described herein. no license is implicitly or otherwise granted under any patent or patent right of arctic silicon devices as. arctic silicon devices as specifically disclaims any and all liability, including without limitation incidental or consequential damages. it is the responsibility of the user to ensure that in all respects the application in which arctic silicon devices as products are used is suited to the purpose of the end user. life support applications : products of arctic silicon devices as (asd) are not designed for use in life support appliances, devices or systems, where malfunction can result in personal injury. customers using or selling asd products for use in such applications do so at their own risk and agree to fully indemnify asd for any damages resulting from such improper use or sale. all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. asd1000 rev v3.1 , 2010.03.05 confidential page 30 of 30 template rev. date: 2008.01.02 |
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