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| 1/22 march 2002 AN1429 application note interfacing the 3v psd813fxv family with the ti tms320vc5402 dsp contents n purpose n psd813f1 architecture n development systems n programming the psd813f5v in-circuit using the jtag interface n interfacing the psd813f5v with the tms320vc5402 C psd813f5v bus inter- face C tms320vc5402 bus in- terface timing calcula- tion C tms320vc5402 memo- ry map C interfacing to the tms320vc5402 exter- nal memory bus C define the 320vc5402 interface in psdsoft ex- press define psd and mcu utility C accessing slower exter- nal i/o and peripherals C define the psd813f5v dpld functions in psd- soft express edit/add logic statements C accessing the psd813f5v internal registers n in-application re- programming (iap) using the psd813f5v n tms320vc5402 bootloader n summary n appendix the digital signal processing marketplace is typically divided into two specific areas: function and algorithm specific ics.are non-programmable dsps integrated with other peripherals. they consist of modem chips, dvds, mpeg and video decoders, etc. general purpose programmable dsps .are flexible dsps that are used in a broad spectrum of products. they typically use a microcontroller for control, as well as additional i/o and programmable logic. most general purpose dsps have internal 8-bit boot load rou- tines imbedded in rom which take advantage of slower, less expensive external flash and eproms to store non-volatile program code to upload into fast internal sram at reset. purpose although the flash psd8xx family has become an ideal pe- ripheral for 8-bit microcontrollers, many companies using the psd in dsp-based products have shown that it makes an ex- cellent peripheral for dsps. the psd8xx provides program- mable logic and the required bus interfacing to implement a clean two-chip solution. the psd jtag port allows in-system programming (isp) of a completely blank psd8xx device soldered to the board with no involvement of the dsp, which is ideal for first time program- ming during manufacturing. the psd8xx also offers in appli- cation re-programming (iap), in which the dsp participates by executing uart download code from the small flash memory in the psd while writing new code into the large flash memory in the psd. this unique concurrent operation of psd memories offers many iap options. after iap is complete, the dsp can copy the contents of the psd main flash memory into the fast dsp sram for full speed operation. this application note addresses the ease of interfacing the psd813f5v with the tms32vc5402 dsp. familiarity with the psd813f is assumed. please reference psd813f data sheet for a detailed description of the device. the vc5402 dsp is designed for use in wireless communications and tele- phony systems where low power, low voltage and size are crit- ical. the 3v psd813fxv family of zero power parts meets
AN1429 - application note 2/22 these criteria and enables the core dsp design to be done with two chips. psd813f1 architecture the psd8xx family is complemented by a lower-cost psd9xx family. figure 1 is a block diagram of the psd8xx and psd9xxf. table 1 shows a comparison of the functional differences in the memory and cpld options. on-chip features supply the key elements to implement a two-chip dsp system. some de- vices have 32k bytes of byte-erasable eeprom that may be used in place of external sram in some designs. flash psd features include: n programmable bus interface to dsps that are capable of accessing external 8-bit boot code and/or program code. n programmable bus interface to dsps with external 8-bit boot code and/or program code. n 128-256 kbytes of main flash memory, divided into eight equal individually protected sectors. n separate 32 kbytes eeprom or flash boot memory divided into four equal blocks. n concurrent programming of the flash or eeprom/boot flash memories allows execution from one memory while reprogramming the other. n 2kbytes or 8 kbytes scratch-pad sram. n two flash-based plds with 16 output micro ? cells and 24 input micro ? cells. n 27 individually configurable i/o port pins. each may be defined as dsp i/os, pld i/os, latched dsp address outputs or special function i/os. n 8-bit page register to expand the address space by a factor of 256. n jtag compliant serial port for true in-system programming (isp) of blank devices and reprogramming of devices in the factory or field. table 1. psd8xxf and psd9xx product matrix device flash main memory kbit (8 sectors) additional memory for boot and/or data (4 sectors) sram kbit pld psd813f1 1024 256 kbit eeprom 16 sequential psd813f2 1024 256 kbit flash 16 sequential psd813f3 1024 none 16 sequential psd813f4 1024 256 kbit flash none sequential psd813f5 1024 none none sequential psd833f2 1024 256 kbit flash 64 sequential psd834f2 2048 256 kbit flash 64 sequential psd913f2 1024 256 kbit flash 16 combinatorial psd934f2 2048 256 kbit flash 64 combinatorial 3/22 AN1429 - application note figure 1. psd8xx/psd9xx block diagrams mcu addr/data mcu control page reg decode pld gpld 19 combinatorial logicoutputs 128k byte main flash 8 segments 32k byte secondary flash 4 segments 2k byte sram i/o port a i/o port b i/o port c i/o port d power mngt device security jtag-isc controller mcu addr/data/cntl bus pld bus i/o bus psd913f2 mcu addr/data mcu control page reg decode pld cpld 16 macro cells 3 combinatorial 128k byte main flash 8 segments eeprom 2k byte sram i/o port a i/o port b i/o port c i/o port d power mngt device security jtag-isc controller mcu addr/data/cntl bus pld bus i/o bus psd813f1 ai06091 AN1429 - application note 4/22 the vc5402 has a basic on-chip boot loader and 16k words of on-chip daram. program code is down- loaded from external flash memory to fast internal daram for execution after system reset. the low-cost psd813f5v (no secondary boot memory) is selected for this design to take advantage of the tms320vc5402 resident boot loader. the following design parameters are assumed for using the psd813f5v without the flash boot memory: 1. the initial firmware is programmed into the psd flash memory through the jtag interface on port c of the psd during manufacturing. 2. the firmware, containing the vc5402 serial port control code to download future code updates into the psd813f5v flash memory, is downloaded to the dsp daram during the boot operation after power on reset is over. 3. the psd813f5v page register is used to expand external local memory beyond 64k words . development systems the psd family is supported by psdsoft express, a software development tool that runs on windows 95 and 98 and windows nt. this tool has point and click features for dsp bus interface configuration, and uses an hdl (psdabel) to define general programmable logic within the pld. dsp firmware is imported and merged to create a single object file to program into the psd. psdsoft express supports two device programmers directly (st psdpro, st flashlink). the generated object file is also compatible with third- party programmers. see web site for list ( www.st.com/psm ). st offers two low-cost device programmers: psdpro plugs into a pc/laptop parallel port and replaces the st magicpro iii. flashlink is a low cost cable that plugs into a pc/laptop parallel port to support jtag-isp program- ming. flashlink is controlled by psdsoft and supports device chaining of multiple psds and devices from other manufacturers. flashlink is available on www.st.com/psm for $69usd. programming the psd813f5v in-circuit using the jtag interface the ability to initially program a new system board with a blank flash memory soldered directly to it has solved many manufacturing logistics problems C no sockets or individual labels are required; inventory of non-volatile program memory chips is reduced to one package; the pld is programmed at the same time as the memory chip. one system board can be built and inventoried. any options can be programmed into the flash memory at board level testing. port c i/o lines are used to interface to the standard jtag signals C tms, tck, tdi and tdo. tstat and terr are optional jtag-isp extensions that can be monitored to decrease the programming time of the psd813f. the psd configuration, pld logic, flash memory and optional flash boot/ eeprom can be programmed through this interface. port c also gives the option to multiplex its jtag pins with the psd813f5v general i/o lines. this option, if used, frees up the jtag pins for i/o functions after jtag programming is completed. this option is en- abled by the following three lines of code in psdabel, and its hardware implementation is illustrated in ap- plication note 054 jtag information C psd813f: jen pin 11; port c pin pc7 is used as external jtag multiplex enable jtagsel node; selects jtag port active using internal product term jtagsel = !jen; switches port c between jtag and i/o 5/22 AN1429 - application note interfacing the psd813f5v with the tms320vc5402 figure 2 is a block diagram that shows the implementation of a two-chip system (three, if external sram is required) using the psd813f5v and the tms320vc5402. all glue logic, flash memory, bus interface logic, i/o, chip selects and plds are contained in one chip. figure 2. block diagram C minimized dsp system psd813f5v bus interface the psd813f5v has a user-friendly programmable bus interface that is quickly configured to interface directly to most general purpose dsps with no glue logic. table 2 lists the bus interface signals from the tms320vc5402 used to access the flash memory, pld logic and i/o inside the psd813f5v. note: these bus signals are also used to access the eeprom/flash boot and sram inside the psd813fxv family, if these options are required. table 2. bus interface pin functions tms320vc5402 pin functions psd813f5v pin functions pin description a15 C a0 ad15 C ad0 external address bus addresses all external memory C program, data and i/o. a19 C a16 n.c. external address lines which address only external program space. d15 C d8 n.c. 8 high byte bi-directional external data bus lines. d7 C d0 por t a pa7 C pa0 8 low byte bi-directional external data bus lines. port a is used as the 8-bit data bus into the zpsd813fv. tms320vc5402 sram 128k x 16 /rd control lines a0-a16 d0-d7 d0-d15 /chip select psd813f port a port b port c port d /wr /mstrb jtag & i/o port d15-d0 a18-a0 control ad15-ad0 cntl[2..0] ai06092 AN1429 - application note 6/22 tms320vc5402 bus interface timing calculation the tms320vc5402 has an internal software-programmable wait-state generator (swwsr) which can extend external data, program and i/o bus cycles up to fourteen machine cycles. at reset, the swwsr is initialized for seven wait states on all external memory accesses. all calculations are based on the r/w, / mstrb and /iostrb. /ds, /ps and /is are active low for the duration of a valid address and do not figure in the calculations. figure 3 compares the critical read/write timing differences between the tms320vc5402-20 mhz (-50ns) and psd813f5v-150ns. the timing diagram is based on the following parameters: 1. the tms320vc5402 rev.b must be operated with the on-chip oscillator. it does not support an external clock source. 2. the maximum crystal frequency is 20mhz, but the internal pll circuitry can multiply the crystal frequency by one of 31 possible ratios. for this application, the dsp clock mode register (clkmd is set by the external mode pins C clkmd1, clkmd2 and clkmd3 to generate a system clock of pllx1 (system clock frequency = crystal frequency). r/w cntl0 read/write signal is used to access external memory and devices. /ds cntl1 data, program and i/o select signal is driven low to access external memory space. /mstrb por t b pb7 memory strobe signal is driven low when accessing external data or program memory. /iostrb por t d pd0 i/o strobe signal is driven low when accessing external i/o. 7/22 AN1429 - application note figure 3. tms320vc5402 read / write memory timing clkout a[19:0] d[15:0] /mstrb r/w a[19:0] d[15:0] /mstrb r/w 3 max t su (a)m = 43 t avqv = 150 t a (mstrbl ) =42 t rlqv = 52 t su(aw) = 48 t avwl = 30 t en(d-rwl) = 20 t theh = 18 t w(sl)ms = 48 memory write (/mstrb) = 0 memory read (/mstrb) = 0 note: the timing values are referenced as: tms320vc5402 - 20 mhz psd813fv - 150 ns ai06093 AN1429 - application note 8/22 tms320vc5402 memory map the tms320vc5402 memory map is illustrated in figure 4. the tms320vc5402 has 20 address lines (a0-a19) which can access 64k words of external data and up to 1m words of program memory. a16-a19 are only used to access program memory via the internal programmable bank-switching logic. the internal 8-bit page register of the psd813f5v is used to allow the dsp to access external data in excess of 64k words. figure 4. tms320vc5402 memory map the processor mode status register (pmst) shown in table 3 shows the various memory mapping op- tions available to configure the tms320vc5402 memory map for optimum system performance: table 3. processor mode status register 15-76543210 iptr mp/mc ovly avis drom clkoff smul sst program - page 0 program - page 0 data reserved (ovly = 1) external (ovly = 0) 0000 0000 0000 007f 007f 007f 0080 0080 0080 on-chip daram (ovly = 1) external (ovly = 0) on-chip daram (ovly = 1) external (ovly = 0) on-chip daram (16k x 16-bit) memory mapped registers reserved (ovly = 1) external (ovly = 0) scratch-pad ram 3fff 3fff 3fff 4000 4000 4000 external ff7f ff80 ffff interrupts (external) ff7f ff80 ffff interrupts (on-chip) reserved external external efff efff f000 f000 feff feff on-chip rom (4k x 16-bit) ff00 ff00 ffff rom (drom = 1) or external (drom = 0) reserved (drom = 1) or external (drom = 0) mp/ mc = 1 (microprocessor mode) mp/ mc = 0 (microcomputor mode) ai06094 9/22 AN1429 - application note table 4 describes only the control bits and their settings that are used to set up the system memory map for this application note: table 4. processor mode status register bit summary interfacing to the tms320vc5402 external memory bus the block diagram of figure 5 shows the bus interface between the tms320vc5402 and the psd813f5v. the tms320vc5402 has 20 address lines (the four high-order address lines are used for paging external program memory. because the flash memory in the psd813f5v is placed in data space, a19-a16 are not used. the psd813f5v internal page register is used to configure the flash memory into multiple pages. a16 for the external sram is generated by one of the page register bits. for this applica- tion, the sram is used for data storage, but the bus interface can be reconfigured to split the external sram between data and program memory. bit name reset value function 6 mp/ mc mp/ mc pin microprocessor / microcontroller mode. mp/ mc enables / disables the on-chip rom that is addressable in program memory space. mp/ mc = 0 the on-chip rom is enabled. mp/ mc is set to the external logic level on the mp/ mc pin that is sampled at reset. this pin is not sampled again until the next reset. this bit is also set or cleared by software 5ovly 0 ram overlay. ovly enables on-chip dual-access data ram blocks to be mapped into program space. ovly = 1. the on-chip ram is mapped into program and data space. data page 0 (0h C7fh) is not mapped into program space. 3drom 0 data rom. drom enables on-chip rom to be mapped into data space. drom = 0. the on-chip rom is not mapped into data space. AN1429 - application note 10/22 figure 5. block diagram C tms320vc5402 system block diagram define the 320vc5402 interface in psdsoft express define psd and mcu utility figure 6 is the mcu and psd selection screen from the psdsoft express development software. for more information on the psdsoft express, see the on-line user manual on the st website listed on the back page. the bus configuration between the tms320vc5402 and psd813f5v is quickly configured by selecting the appropriate signals in this screen, as shown below: n type: other n data bus width: 8-bit n address / data mode: non-mux n control setting: r/w, /ds figure 7 is the schematic diagram of the tms320vc5402 / psd813f5v bus interface. the 128k words are used for data storage, but the /ps signal has been wired into the psd813fv so that the external sram can be divided between program and data. the sram_cs sram chip select signal generated by the psd and the system memory map would have to be modified by software to allow this feature. tms320vc5402 sram 128k x 16 /rd a0-a15 d0-d15 d0-d7 d0-d15 /chip select psd813f port a port b port c port d /wr jtag & i/o port a16 /mstrb r/ w r/ w /ds /ds /iostrb sram 128k x 16 port a port b port c port d /mstrb r/ w r/ w /ds /ds /iostrb sram 128k x 16 port a port b port c port d /mstrb r/ w r/ w /ds /ds /iostrb sram 128k x 16 port a port b port c port d /mstrb r/ w /iostrb d15-d0 a16-a0 ad15-ad0 cntlo-r/w cntl1-/ds cntl2 a0-a15 ai06095 11/22 AN1429 - application note figure 6. psdsoft bus configuration AN1429 - application note 12/22 figure 7. schematic diagram C tms320vc5402 to psd813f5v bus interface vcc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d7 d0 d1 d2 d3 d4 d5 d6 sram_a16 ready sram_cs /rd /wr u? km68v1000 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 24 29 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 cs1 cs2 oe we d1 d2 d3 d4 d5 d6 d7 d8 tms320vc5402 41 43 45 51 53 55 59 60 61 82 85 94 96 20 21 22 23 24 25 26 27 28 29 131 132 133 134 136 137 138 139 140 141 5 7 8 9 10 11 80 31 77 78 79 39 46 62 13 64 65 66 67 63 98 32 19 30 97 42 47 17 127 129 18 92 89 88 87 86 48 83 84 49 44 54 99 100 101 102 103 104 113 114 115 116 117 118 119 121 122 123 58 69 81 95 120 124 135 6 105 107 108 109 bclkr0 bfsr0 bdr0 hint/out1 bfsx hrdy bdx bdx1 iack tout0 tdo clkout x1 ps ds is r/w mstrb iostrb msc xf holda iaq a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 cnt bio clkmd1 clkmd2 clkmd3 hcntl0 hcntl1 hbil has int0 int1 int2 int3 nmi rs mp/mc ready hold x2/clkin bclkr1 bdr1 hcs hds1 hds2 hr/w hpiena tms tck trst tdi bclkx0 emu0 emu1/off bclkx1 bfsr1 tfsx/tfrm d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 a16 a17 a18 a19 u2 psd813f5v 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pco/tms pc1/tck vstby pc3/tstat pc4/terr pc5/tdi pc6/tdo pc7/bhe cntl0-r/w,wr cntl1-e,rd,ds cntl2-psen pd0-as-ale pd1-clkin pd2-csi reset 1 2 3 4 u? km68v1000 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 24 29 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 cs1 cs2 oe we d1 d2 d3 d4 d5 d6 d7 d8 6mhz clk dsp interrupt jtag cable flashlink rdy/bsy signal (optional) 100k ai06097 13/22 AN1429 - application note accessing slower external i/o and peripherals it sometimes becomes necessary to access slower external i/o and peripherals. this can be accom- plished either by increasing the number of wait states or by stretching the external ready pulse. figure 8 illustrates one method of utilizing the available cpld micro ? cells to accomplish this task in hardware. while iostrb is inactive (high), the 3-bit ripple counter is held in reset, the ready signal is high, and the external clock is disabled. when iostrb goes active (low), the ready pulse is forced low and the 3-bit counter begins to count up until the q output of bit-3 goes high and forces the ready pulse high. the ready pulse in turn forces the iostrb signal high, disabling the counter. figure 8. using the psd813fv cpld to stretch the external ready pulse define the psd813f5v dpld functions in psdsoft express edit/add logic statements figure 9 is the system memory map created for this a/n. the data, i/o and program addresses are defined in the psdsoft express edit/add logic statements screen and implemented in the internal psd813f5v decoding pld (dpld). three bits of the psd813f5v page register are used to extend the external data address range beyond the 64k limitation of the tms320vc5402. since paging is used, an area in data memory containing routines common to all data memory pages C memory-mapped registers, scratch-pad ram, i/o and external peripheral C must be accessible independent of which page the dsp is addressing. there are also several dsp system requirements that dictate the basic format of the system data memory map: 1. the dsp ovly bit controls address 0 to 0x3fff as being internal /external program space. when ovly = 1, this range is always internal data space when accessed by the dsp as data. 2. if an sram block is not included in page 0, program code can only be downloaded to sram under dsp supervision. the boot loader by itself can not perform this procedure. 3. the first 32k words of sram are lost because the region 0 to 0x3fff can not be accessed as data; program code can not be written into the sram. q q set cl r d q q set cl r d q q set cl r d 6 mhz clock /iostrb ready ai06098 AN1429 - application note 14/22 figure 9. system memory map with paging accessing the psd813f5v internal registers the bank of internal control registers in the psd813f5v (csiop + hxx) are 8-bits wide. the dsp data bus is 16-bits wide and accesses external memory locations on a word basis. when an internal register in the psd813f5 is accessed, the dsp reads or writes a 16-bit word; only the lower 8 lines of the data bus are used to transfer data between the dsp and psd. for this application, the internal psd813f5v control registers are mapped into data space and enabled during /mstrb active. when data is read from the internal registers, 16-bit data is read into the dsp accumulator. the high byte in the dsp accumulator is either ignored or masked out. when data is written to the internal registers, valid data must be located in the lower byte of the accumulator. the high byte is ignored by the psd813f5v. page 0 page 1 page 2 page 3 page 4 page 5 data space progr am space page 0 reserved (ovly = 1) 0000 007f 0080 3fff 4000 on-chip daram (ovly = 1) mp/ mc = 0 on-chip daram (16k x 16-bit) memory mapped registers & scratch-pad ram csioip 4100 duart 4110 8000 c000 ffff sram 0 sram 0 sram 0 sram 1 sram 1 sram 1 fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 external program memory sram0 sram1 internal boot loader f800 source addr. ai06099 15/22 AN1429 - application note in-application re-programming (iap) using the psd813f5v the psd813f5v (without internal boot flash) was selected to reduce the system cost and take advantage of the external sram or internal daram that can contain the program code to isp the flash memory through the dsp serial port interface (spi). the tms320vc5402 transmit and receive data buffers of the spi are 16-bit buffers. the spi control reg- isters (spc and spce) control the spi communication format. when the fo bit in the spc register = 1, and the fe bit in the spce register = 0, the spi is formatted for 8-bit interface. an 8-bit word is stored in the lower eight bits of the 16-bit receive and transmit buffers. when a boot program update is received by the serial port, the 8-bit data in the receive data buffer is written to the accumulator to store either in an assigned section of the dsp daram allocated as a buffer for the uploaded program code, or write to the flash memory on a byte-by-byte basis. the byte-by byte write sequence to the flash memory can be speeded up dramatically by configuring the rdy/busy polling bit to port c (pin pc3) and using it as an interrupt input to the dsp. once a byte write command is issued, the time required to program the byte can now be executed in background mode. the dsp can perform other tasks until the rdy/busy pin signals that the byte has been successfully pro- grammed and generates an interrupt. the rdy/busy bit is hardware configured as an output interrupt pin as shown in figure 11 with the configuration sequence as follows: figure 10. additional psd configuration screen 1. select pc3 from the psdsoft express additional psd configuration screen. 2. type tstat in name block. 3. select rdy/busy output under other block. AN1429 - application note 16/22 tms320vc5402 bootloader the internal bootloader is used to transfer program code from an external source to the selected program memory at power-up. five different routines are available to download code depending on the system re- quirements. since the code to be downloaded is stored in 8-bit flash memory in global data space, the parallel boot option is selected. if the mp/mc pin of the tms320vc5402 is sampled low during a hard reset, execution begins at location ff80h of the on-chip rom, which contains a branch instruction to the start of the bootloader program. the on-chip rom is factory programmed with the boot load program. the boot load program sets up the dsp status registers before initializing the boot load routine. interrupts are globally disabled (intm = 1), internal daram and external sram is mapped in program/data space (ovly = 1), and seven wait states are programmed for the entire program and data spaces. the boot loader checks the host port interface (hpi) first by sampling interrupt 2 (int2). if int2 is not latched, the boot routine skips hpi mode and samples interrupt 3 (int3). if int3 is not latched, the boot loader will try to read the source address from external i/o location 0ffffh, which is accessed by iostrb. this entails having a non-volatile value (either 10aa or 08aa) at this address. if this is not possible, one way to bypass booting from i/o address is to pull up d0 of the dsp data bus with a weak resistor (100k) when accessing a non-existent address at 0ffff in i/o space to guarantee that a logic 1 is present during this read. this will ensure that a valid keyword will not be present on the data bus, which will be tri-state during the read access. the boot loader next reads the source address of the boot code from external data space located in flash data memory sector fs1 to determine if the interface is 8-bit or 16-bit. once the boot loader determines that the vc5402 daram will be uploaded from external 8-bit memory (w = 08aa), the bootloader com- mences with the 8-bit upload subroutine. figure 11 is the flowchart for the 16-bit/8-bit parallel boot load routine. 17/22 AN1429 - application note figure 11. flowchart - 16-bit / 8-bit parallel boot load hpi boot int2 begin reset int3 serial eeprom boot read 16 bit boot table source address from i/o space 0ffffh 10aah or 08aah parallel boot read 16 bit boot table source address from data space 0ffffh read first word from boot table in data space 10aah 16 bit boot lsb = xx08h check other boot modes read lsb of boot table address at 0ffffh read msb of boot table address at 0ffeh msb = xxaah 8 bit boot mode load r-1 words to reinitialize the registers. in 8-bit mode, a read is required for each byte of the word. load xpc of entry point load entry point load section size r r = 0 load xpc and destination address transfer r words of data from source to destination load xpc of entry point load entry point branch to the entry point start execution of program yes no yes no yes no yes no no no yes yes yes no ai06501 AN1429 - application note 18/22 summary as dsps continue to rapidly proliferate into markets such as communications, industrial, medical, signal conditioning, and hand held test equipment, the psd813fx and dsp form an ideal 2-chip core with on- chip pld and 27 i/o lines that can be individually configured to perform any function required by the sys- tem design. using the psd813fx as an 8-bit boot loader in both high speed and low speed systems is an ideal and rapid design alternative to a discrete solution. inexpensive slower memory and plds integrated in the psd813fx now become both cost and performance effective. several features internal to the psd813f5v were used to expand the limitations of the tms320vc5402, and dsps in general: 1. the jtag-isp channel is used to eliminate manufacturing complications associated with flash memory and programmable logic. 2. the page register was used to expand the address range of the external data memory accessible to the dsp. 3. flash memory allows the program code to be field updated through the serial port of the dsp while the dsp is running program code in the internal daram. 4. expanded i/o was added to the system. 5. the internal pld allows functional modifications to the i/o, these changes being made in software. these changes have added to both the versatility and performance of the tms320vc5402; future chang- es most likely will not require a hardware change to the 2-chip core. appendix the appendix contains the psdsoft express design assistant summary listing all logic equations and showing how the psd813f5v is configured to implement the example in this application note. application note an1356 presents a step-by-step illustration of how to configure the flash psd family. although an1356 uses the 16-bit flash psd4235g2 in the example, the software and procedure is the same for the 8-bit psd813f5v. *********************************************************************** psdsoft express version 6.02 summary of design assistant *********************************************************************** project : tivc5402 date : 09/20/2000 device : zpsd813f5v time : 21:42:37 mcu : 19/22 AN1429 - application note adio10 a10 address line adio11 a11 address line adio12 a12 address line adio13 a13 address line adio14 a14 address line adio15 a15 address line cntl0 r_w mcu bus control signal cntl2 _iostrb logic or address cntl1 _ds mcu bus control signal reset _reset reset input pa0 d0 data line pa1 d1 data line pa2 d2 data line pa3 d3 data line pa4 d4 data line pa5 d5 data line pa6 d6 data line pa7 d7 data line pb0 pb0 mcu i/o mode pb1 ready combinatorial pb2 pb2 logic or address pb3 sram_a16 combinatorial pb4 sram_cs external chip select - active-lo pb5 _rd combinatorial pb6 _wr combinatorial pb7 pb7 mcu i/o mode pc0 tms dedicated jtag - tms pc1 tck dedicated jtag - tck pc3 tstat rdy/bsy output pc5 tdi dedicated jtag - tdi pc6 tdo dedicated jtag - tdo pd0 pd0 mcu i/o mode pd1 clkin common clock input, clkin user defined nodes: =================== node node name type ------------ ------------ bit1 register bit2 register bit3 register page register settings: ======================= pgr0 is used for paging pgr1 is used for paging pgr2 is used for paging pgr3 is not used pgr4 is not used pgr5 is not used pgr6 is not used pgr7 is used for logic, signal name: la16 equations: ========== AN1429 - application note 20/22 csiop = ((address >= ^h4000) & (address <= ^h40ff)); fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hbfff)); fs1 = ((page == 0) & (address >= ^hc000) & (address <= ^hffff)); fs2 = ((page == 1) & (address >= ^h8000) & (address <= ^hbfff)); fs3 = ((page == 1) & (address >= ^hc000) & (address <= ^hffff)); fs4 = ((page == 2) & (address >= ^h8000) & (address <= ^hbfff)); fs5 = ((page == 2) & (address >= ^hc000) & (address <= ^hffff)); fs6 = ((page == 3) & (address >= ^h8000) & (address <= ^hbfff)); fs7 = ((page == 3) & (address >= ^hc000) & (address <= ^hffff)); ! sram_cs = ((address >= ^h4100) & (address <= ^h7fff) & (!sram_a16)) # ((address >= ^h4100) & (address <= ^h7fff) & (sram_a16)) # ((page == 4) & (address >= ^h8000) & (address <= ^hffff) & (!sram_a16)) # ((page == 5) & (address >= ^h8000) & (address <= ^hffff) & (sram_a16)); ready = bit3 # _iostrb; bit1.ck = clkin # !_iostrb; bit1.re = _iostrb; bit2.ck = !bit1; bit2.re = _iostrb; bit3.ck = !bit2; bit3.re = _iostrb; 21/22 AN1429 - application note table 5. document revision history date rev. description of revision oct-2000 1.0 document written in the wsi format (an073) 01-mar-2002 2.0 document converted to the st format (AN1429) AN1429 - application note 22/22 for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com |
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