security & chip card ics sle 88c f x 400 2 p 32 - bit multi application security controller with powerful memory management & protection unit in 0.13 m cmos technology, 240 kbytes rom, 400 kb ytes configurable eeprom , 1 6 kbytes ram, and 140 8 - bit crypto engine (crypto@1408bit) preliminary short product information 01.04
sle 88c f x 400 2 p preliminary short product information this document contains preliminary information on a new product under devel opment. details are subject to change without notice. revision history: current version 01.04 previous releases: - page subjects (changes since last revision) important : further information is confidential and on request. please contact: infineon technologies ag in munich, germany, secure and mobile solutions - security group fax +49 89 234 - 81000 published by infineon technologies ag, secure and mobile solutions - security group st. - martin - strasse 76 , d - 81541 mnchen ? infineon technologies ag 2004 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non - infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. infor mation for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives world - wide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life - support devices or systems with the expr ess written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
sle 88c f x 400 2 p preliminary short product information 3 / 10 01.04 32 - bit multi application security controller with powerful memory manage ment and protection unit in 0.13 m cmos technology , 24 0 kbytes rom, 400 kb ytes configurable eeprom , 16 kb ytes ram a nd 1 408 - b it crypto engine (crypto@1408bit) features dedicated smart card core : pipelined 32 - b it risc micro - controller in 0.13 m cmos technology with integral s ecurity c oncept designed for maximum security and maximum performance at ultra low power consumption instruction set acceleration of virtual machine languages (e.g. java card tm , multos tm , . ..) 4 gbytes address range controlled by a powerful memory management and protection unit (mmu) package concept: application oriented memory partitioning secure hardware controlled execution of applications and application data access controlled access to peripherals hardware e rror c orrection c ode for rom, ram and eeprom efficient task switch capability 80 kbytes of reserved rom for the platform support layer (psl) and sts 160 kbytes of user rom for libraries, operating system and applications 400 kbytes of eeprom , software configurable in code/data memory spaces with 4 kbytes granularity , for appl ication programs and data. example: 272 kbytes of code and 128 kbytes of data or 144 kbytes of code and 256 kbytes of data 16 kbytes of ram for local variables , buffers, and stacks 1k and 2k high performance instruction and data cache memories for instruction fetch and data access internal clock generation adjustment of internal clock according to available power and required performance: increase inte rnal clo ck for maximum speed (66 mhz) reduce internal clock for lowest power consumption integral security concept hardware memory management and protection unit enhanced on - chip encryption of internal data low and high voltage sensors low and high frequency sen sors spike filter for clk reset filter temperature sensor glitch sensor light sensor watch dog timer for sensors initialization user mode sensor life control detection of forbidden states sensor unique chip identification number for each chip security opti mized layout hardware encryption of memories targeted certification: common criteria level eal5+
sle 88c f x 400 2 p preliminary short product information 4 / 10 01.04 features (cont?d) eeprom self timed programming 500,000 write/erase cycles per page data retention: min. 10 years @ 25c eeprom programming voltage generated on chip erase cycle time 1,3 ms write cycle time 1 ms page mode for programming up to 128 bytes at one shot peripherals 1408 - bit crypto engine (crypto@1408bit, formerly crypto2000) for fast execution of public key crypto algorithms optimized for rsa and e lliptic curves gf(p) and gf(2 m ) key lengths up to 2048 - bit dedicated 880 bytes of crypto - coprocessor ram des accelerator des and 3des in hardware flexible key management optimized for data throughput (parallel load) true random number generator (trng), ais - 31 compliant three 16 - bit timers dedicated smart card uart , two i/o ports (io1 and io2), half and full duplex transmission, support for t=0, t=1 platform support layer (psl) including device drivers for rng, des, crypto@1408bit, eeprom, etc. electrical c haracteristics pin configuration and serial interface in accordance with iso 7816 power saving sleep mode (< 100 a) external clock freq.: 1 to 10 mhz supply voltage range: 1.62 v to 5.5 v current consumption: 0.35 ma/mhz internal clock frequency temperatu re range: - 25c to +85c esd protection larger than 6 kv (mil - standard, hbm) support i ntegrated d evelopment e nvironment (windows 2000 tm , nt tm and unix workstation) for high - end software development and validation integrated simulator / debugger emulator for real - time debugging programmer?s manual with application notes (e.g.: t=0, t=1, 3 des, aes, rsa , e lliptic c urves , sha1, crc etc.) and software developer guidelines c libraries (e.g. crypto library)
sle 88c f x 400 2 p preliminary short product information 5 / 10 01.04 features (cont?d) best crypto performance o peration modulus exponent crypto@1408bit perf. at 5mhz [ms] crypto@1408bit perf. at 66mhz [ms] rsa signature (without crt) 512 bit 512 bit 53 4 rsa signature (without crt) 1024 bit 1024 bit 238 18 rsa signature (without crt) 2048 bit 2048 bit 25.080 1.9 00 rsa signature (with crt) 1024 bit 1024 bit 53 4 rsa signature (with crt) 2048 bit 2048 bit 475 35 rsa verification 1024 bit 32 bit 8 0,5 rsa verification 2048 bit f_4 132 11 rsa key generation (n=5) 1024 bit 4.356 330 rsa key generation (n=5) 2048 bit 35.640 2.700 ec dsa over gf(p) signature 160 bit 160 bit 99 8 ec dsa over gf(p) verification 160 bit 160 bit 198 15 ec dsa over gf(2 n ) signature 160 bit 160 bit 158 12 ec dsa over gf(2 n ) verification 160 bit 160 bit 317 24 note s : crypto@14 08bit works independently of i/o operations or des calculations. n is the number of miller - rabin rounds
sle 88c f x 400 2 p preliminary short product information 6 / 10 01.04 pin description sle 88 cfx4002p vdd gnd clk rst port 1 port 2 figure 1 : pin configuration pin definitions and functions pin symbol function vdd operating voltage rst reset input clk processor clock input gnd ground port 1, 2 d ata ports
sle 88c f x 400 2 p preliminary short product information 7 / 10 01.04 block diagram sensor/filter: voltage clock reset temperature voltage regulator random number generator 32-bit bus scalable clk 16-bit timers des accelerator crypto@1408bit 880 byte ram uart 32-bit bus 32-bit cpu with memory management and protection unit ram 16 kbyte eeprom 400 kbyte code/data rom 240 kbyte figure 2 : s le 88c f x 400 2 p, 32 - bit cpu and peripherals general description sle 88c f x 400 2p is the most sophisticate d smart card microcontroller on the market . it is manufactured in 0.13 micron cmos technology and only differs from sle 88cfx4000p in its additional 160 kbytes user rom . in this product family, infineon technologies realise s increased security and performa nce while reducing power consumption , and additionally provides a platform for real multi - application and multi - tasking operating systems. performance and virtual machine a cceleration performance is first of all enhanced by the 32 - bit architecture that p rocesses instructions and data 32 - bit wise. this is supported by the implementation of cache memories in the core that a llow fast er access to instructions and data. performance is also enhanced by a clock frequency of up to 66mhz. and finally, efficient su pport and an additional performance increase of multi - application schemes are gained by a hardware accel eration of virtual machine l anguages like java c ard tm or multos tm . large memories the 32 - bit architecture allows the linear addressing of large memori es for a more convenient code implementation. with the 0.13 micron process, sle 88cfx4002 p offers largest on - chip - memories with 24 0 kb ytes of rom (160 kbytes user rom and 80 kbytes reserved rom) , 400 kb ytes of eeprom, and 16 kb ytes of ram. the separate rom is reserved for the platform support layer (psl) and the self test software (sts) that are provided by infineon technologies , so that these lower code layers do not occupy the user memory space . the large eeprom space is the basis of infineon technologies ?flash? concept where the entire eeprom is configurable in code and data sections with 4 kb ytes granularity, and so it can be used to store operating system program code and data , as well as application code and data. each application can be tailored to fi t its targeted project. this customization provides added value to the system and the possibility to serve multiple projects with the same platform. the 400k eeprom are e.g. configurable as 256 kbytes of code and 144 kbytes of data or 320 kbytes of code an d 80 kbytes of data. this concept offers the flexibility and convenience of flash memory, but takes advantage of the eeprom cell quality ( timing, cycling and endurance) .
sle 88c f x 400 2 p preliminary short product information 8 / 10 01.04 figure 3: memory configuration real memory manageme nt unit the memory management and protection unit (mmu) handles a virtual address range of 4 gbytes, and serves as a hardware firewall to enable secure separation of adjacent application codes and data. a very efficient context/application switching mechan ism allows fast switching between multiple tasks. program and data modules are organised as packages. and each package has a defined memory range of 16 mbytes with dedicated access rights for memories and peripherals. the flexible mmu concept also shortens development cycles for additional applications. it furthermore enables the secure downloading of applications in the field. power consumption sle 88cfx4002 p includes an intelligent power management module that covers the voltage classes a, b and c of the 3 rd generation specification for mobile communication ts102 221 . 128 kbyte data 272 kbyte code 256 kbyte data 144 kbyte code psl psl data code 400 kbyte configurable eeprom rom examples : psl code code code
sle 88c f x 400 2 p preliminary short product information 9 / 10 01.04 peripherals a number of powerful peripherals offer hardware support for time and code intensive operations. the crypto@1408bit is equipped with its own ram of 880 bytes and supports all of the known public - key algorithms based on large integer modular arithmetic with configurable register lengths of up to 1408 bits . it allows fast and efficient calculation of e.g. rsa operations with key lengths up to 2048 bit but also elliptic curves ove r gf(p) as well as gf(2 m ). a 1024 - bit rsa signature with chinese remainder theorem can be performed in 4ms at 66mhz. for symmetric crypto operations, a des accelerator supporting also triple - des is implemented. a triple - des can be performed in 1.5 microsec onds at 66mhz. using the crypto@1408bit and des module a secure transmission for downloading of additional applications can be ensured. the uart supports the chip card protocols t=0 and t=1 and is also able to manage full - duplex data transfer. the true r andom number generator (trng) is able to supply the cpu with true random numbers whose quality is ensured according to ais - 31 strict evaluation guidelines . an interrupt control unit supports a programmable interrupt system with uart, timers , and the other peripherals as interrupt sources. a variety of different trap vectors informs the operating system about exceptions (e.g. access violation). security as security is infineon first priority, an innovative security concept has been created that is based o n the entire integration of security measures in the sle88 at each design phase of the core, architecture and modules, at every level, and does not exclusively rely on the addition of security features to an existing system. with this integral security con cept, the sle 88 takes a quantum leap in terms of improved on - chip security. targeted c ertification is common criteria level eal5+. support a broad range of hardware and software based development tools offers to the user the facilities for high - end opera ting system development and validation. the psl provides all devices drivers necessary to use the chip resources and peripherals such as opti mu m eeprom programming, memory management, crypto implementations, and many others. it also allows an easier and fa ster code implementation on a high level, without detailed knowledge of the hardware, and independently of its eventual changes and evolutions. as a consequence, porting an existing code from a derivative of the sle88 family to the other is easy and quick. conclusion sle 88c f x 400 2 p fully meets the requirements for real multi - application operating systems. it allows secure operation of banking, access control, loyalty , gsm/usim, pay - tv, health care and identification applications all in one chip . the advanc ed 0.13 micron technology, the integral security c oncept, the low power optimised 32 - bit core supported by various powerful peripherals, and the possibility to adapt the performance to application requirements establish the foundation for a completely new chip card era.
sle 88c f x 400 2 p preliminary short product information 10 / 10 01.04 glossary aes advanced encryption standard , successor of des. ais - 31 anwendungshinweise und interpretation zum schema : functionality classes and evaluation methodol o gy guidelines for physical random number generators defined by the german i nstitu t e for the security of the information technology . caches cache memories are random access m emor ies that the cpu can access more quickly than it can access regular ram . clk clock cpu central processing unit cmos c omplementary metal - oxide s emiconducto r , the technology used to manufacture most of today's microchips. crt chinese remainder theorem, computing technique des, 3des data encryption standard dsa digital signature algorithm eal 5+ common criteria certification level e c elliptic curves eeprom e l ectrically erasable programmable read - only m emory esd electrostatic discharge, release of static electricity that can damage a chip exponent component of rsa key f_4 fermat number f 4 , computing term. gf(2 m ) galois field : finite field of 2 m elements repres ented by polynomials with degree < m gf(p) galois field, set of whole numbers less than prime number p io input/output miller - rabin test for prime numbers. modulus component of rsa key ram random access m emor y risc reduced instruction set computer rng, trng random number generator, true rand om number generator psl platform support layer rom read - only m emory rsa rivest, shamir and adleman , inventors of the rsa cryptosystem sha - 1 secure hash algorithm revision 1 sts self test software t=0, t=1 communication protocols defined in iso 7816 stand ard uart universal asynchronous receiver/transmitter
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