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9-12 august 1997 icm7217 4-digit led display, programmable up/down counter features ? four decade, presettable up-down counter with parallel zero detect ? settable register with contents continuously compared to counter ? directly drives multiplexed 7 segment common anode or common cathode led displays ? on-board multiplex scan oscillator ? schmitt trigger on count input ? ttl compatible bcd i/o port, carry/borrow, equal, and zero outputs ? display blank control for lower power operation; quiescent power dissipation <5mw ? all terminals fully protected against static discharge ? single 5v supply operation description the icm7217 is a four digit, presettable up/down counter with an onboard presettable register continuously compared to the counter. the icm7217 is intended for use in hard-wired applications where thumbwheel switches are used for loading data, and simple spdt switches are used for chip control. this circuit provides multiplexed 7 segment led display outputs, with common anode or common cathode con?gurations available. digit and segment drivers are provided to directly drive displays of up to 0.8 inch character height (common anode) at a 25% duty cycle. the frequency of the onboard multiplex oscillator may be controlled with a single capacitor, or the oscillator may be allowed to free run. leading zeros can be blanked. the data appearing at the 7 segment and bcd outputs is latched; the content of the counter is transferred into the latches under external control by means of the store pin. the icm7217 (common anode) and icm7217a (common cathode) versions are decade counters, providing a maximum count of 9999, while the icm7217b (common anode) and icm7217c (common cathode) are intended for timing purposes, providing a maximum count of 5959. this circuit provides 3 main outputs; a carry/borrow output, which allows for direct cascading of counters, a zer o output, which indicates when the count is zero, and an eq u al output, which indicates when the count is equal to the value contained in the register. data is multiplexed to and from the device by means of a three-state bcd i/o port. the carry/borrow, eq u al, zer o outputs, and the bcd port will each drive one standard ttl load. to permit operation in noisy environments and to prevent multiple triggering with slowly changing inputs, the count input is provided with a schmitt trigger. input frequency is guaranteed to 2mhz, although the device will typically run with f in as high as 5mhz. counting and comparing (equal output) will typically run 750khz maximum. ordering information part number temp. range ( o c) package display driver type count option/ max count pkg. no. icm7217aipi -25 to 85 28 ld pdip common cathode decade/9999 e28.6 icm7217cipl -25 to 85 28 ld pdip common cathode timing/5959 e28.6 icm7217iji -25 to 85 28 ld cerdip common anode decade/9999 f28.6 LCM7217BLJL -25 to 85 28 ld cerdip common anode timing/5959 f28.6 file number 3167.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
9-13 pinouts functional block diagram icm7217 (pdip) common anode top view icm7217 (cerdip) common cathode top view carry/borrow zer o eq u al bcd i/o 8s bcd i/o 4s bcd i/o 2s bcd i/o 1s count input st ore up/ do wn load register/ off load counter/ i/o off scan reset d1 d3 d4 v dd display cont. seg b seg e seg f seg d seg a seg c d2 seg g v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 icm7217 icm7217b carry/borrow zer o eq u al bcd i/o 8s bcd i/o 4s bcd i/o 2s bcd i/o 1s count input st ore up/ do wn load register/ off load counter/ i/o off scan reset seg d seg f seg c v dd seg a seg g v ss d1 d2 d3 d4 seg b seg e display cont. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 icm7217a icm7217c t.g. d4 10 rs zero u/d cl carry t.g. latch mux 4 4 4 4 t.g. d2 10 rs zero u/d cl carry t.g. latch mux 4 4 4 4 t.g. d3 10 rs zero u/d cl carry t.g. latch mux 4 4 4 4 t.g. d1 10 rs zero u/d cl carry t.g. latch mux 4 4 4 4 1 2 3 4 t.g. 4 4 d1 comp. 4 reg. 1 2 3 4 123 4 123 4 4 4 t.g. 4 4 d2 comp. 4 reg. 4 t.g. 4 4 d3 comp. 4 reg. 4 t.g. 4 4 d4 comp. 4 reg. 4 bdc i/o 8 s 4 s 2 s 1 s zer o up/ dn count v dd v ss segment decoder segment drivers (7) digit drivers (4) a d4 d3 d2 d1 display blank + off g b c d e f mux. oscillator mux. i/o and display control logic 4 4 digit mux scan display load load reset st ore eq u al carry/barrow control register counter l.r. l.c. reset bcd i/o inputs com. anode: pull down com. cathode: pull up v dd v dd v dd v ss v dd v ss v dd v ss icm7217
9-14 absolute maximum ratings thermal information supply voltage (v dd - v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v input voltage (any terminal) . . . . . . . .(v ss - 0.3v) to (v dd + 0.3v) (note 1) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c thermal resistance (typical, note 2) q ja ( o c/w) q jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 55 14 pdip package . . . . . . . . . . . . . . . . . . . 55 n/a maximum junction temperature pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering, 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. notes: 1. due to the scr structure inherent in the cmos process used to fabricate these devices, connecting any terminal to a voltage g reater than v dd or less than v ss may cause destructive device latchup. for this reason it is recommended that the power supply to the device be established before any inputs are applied and that in multiple systems the supply to the icm7217 be turned on ?rst. 2. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations v dd = 5v, v ss = 0v, t a = 25 o c, display diode drop 1 .7v, unless otherwise speci?ed parameter test conditions min typ max unit supply current (lowest power mode), idd (7217) display off, lc, dc, up/dn, st, rs, bcd i/o floating or at v dd (note 1) - 350 500 m a supply current, operating, i op common anode, display on, all 8s 140 200 - ma supply current, operating, i op common cathode, display on, all 8s 50 100 - ma v supply , v dd 4.5 5 5.5 v digit driver output current, i dig common anode, v out = v dd - 2.0v 140 200 - ma peak segment driver output current, iseg common anode, v out = +1.5v 20 35 - ma peak digit driver, output current, i dig common cathode, v out = +1.0v -50 -75 - ma peak segment driver output current, iseg common cathode v out = v dd - 2v -9 -12.5 - ma peak st, rs, up/ dn input pullup current, ip v in = v dd - 2v (note 1) 5 25 - m a 3 level input impendance, zin 40 - 350 k w bcd i/o input, high voltage vbih icm7217 common anode (note 2) 1.5 - - v icm7217 common cathode (note 2) 4.40 - - v bcd i/o input, low voltage vbil icm7217 common anode (note 2) - - 0.60 v icm7217 common cathode (note 2) - - 3.2v v bcd i/o input, pullup current ibpu icm7217 common cathode v in = v dd - 2v (note 2) 525 - m a bcd i/o input pulldown current, ibpd icm7217 common anode v in = +2v (note 2) 5 25 - m a bcd i/o, zer o, eq u al outputs output high voltage, voh i oh = -100 m a 3.5 - - v bcd i/o, carry/borrow zer o, eq u al outputs output low voltage, v ol i ol = 1.6ma - - 0.4 v count input frequency, f in -20 o c to 70 o c - 5 - mhz guaranteed 0 - 2 mhz count input threshold, vth (note 3) - 2 - v count input hysteresis, vhys (note 3) - 0.5 - v count input lo, vcil - - 0.40 v count input hi, vcih 3.5 - - v display scan oscillator frequency, f ds free-running (scan terminal open circuit) - 2.5 10 khz icm7217
9-15 switching speci?cations v dd = 5v, v ss = 0v, t a = 25 o c parameter min typ max unit up/ do wn setup time, t ucs 300 - - ns up/ do wn hold time, t uch 1500 750 - ns count pulse width high, t cwh 250 100 - ns count pulse width low, t cwi 250 100 - ns count to carry/borrow delay, t cb - 750 - ns carry/borrow pulse width t bw - 100 - ns count to eq u al delay, t ce - 500 - ns count to zer o delay, t cz - 300 - ns reset pulse width, t rst 1000 500 - ns notes: 1. in the icm7217 the up/ do wn, st ore, reset and the bcd i/o as inputs have pullup or pulldown devices which consume power when connected to the opposite supply. under these conditions, with the display off, the device will consume typically 750 m a. 2. these voltages are adjusted to allow the use of thumbwheel switches for the icm7217. note that a high level is taken as an in put logic zero for icm7217 common-cathode versions. 3. parameters not tested (guaranteed by design). timing waveforms figure 1. multiplex timing 10 m s typ 400 m s typ free-running free-running interdigit blank d4 d3 d2 d1 scan internal osc output internal (bcd and segment enable) internal (common anode digit strobes) d4 d3 d2 d1 icm7217
9-16 figure 2. count and outputs timing figure 3. bcd i/o and loading timing timing waveforms carry/borrow zer o eq u al count input up/ do wn t uch t cwh t bw t cel t czl t czh t ceh t cwl t cb t ucs d4 d3 d2 d1 scan input output internal operating mode bcd i/o d n out load counter (or load register) d4 in d3 in d2 in d1 in d4 out d3 out count inhibited if load counter = high impedance = three-state w/pulldown icm7217
9-17 typical performance curves figure 4. typical idig vs v+ figure 5. typical iseg vs v out figure 6. typical iseg vs v out figure 7. typical idigit vs v out figure 8. typical idigit vs v out figure 9. typical iseg vs v dd - v out v dd - v out (v) idig (ma) 300 200 100 0 0123 4.5 v dd 6v 85 o c 25 o c -20 o c icm7217 icm7217b v out (v) 012 3 60 40 20 0 80 iseg (ma) v+ = 5.5v v+ = 5v v+ = 4.5v t a = 25 o c icm7217 icm7217b v out (v) 0123 60 40 20 0 80 iseg (ma) 85 o c 25 o c -20 o c v+ = 5v icm7217 icm7217b 85 o c 25 o c -20 o c v+ = 5v v out (v) idigit (ma) 150 100 50 0 200 0123 icm7217a icm7217c v out (v) 0123 v+ = 5.5v v+ = 5v v+ = 4.5v t a = 25 o c idigit (ma) 100 50 0 150 200 icm7217a icm7217c v dd - v out (v) 0123 30 20 10 0 iseg (ma) -20 o c 25 o c 85 o c 4.5 v dd - v ss 6v icm7217a icm7217c icm7217
9-18 detailed description control outputs the carry/borrow output is a positive going pulse occurring typically 500ns after the positive going edge of the count input. it occurs when the counter is clocked from 9999 to 0000 when counting up and from 0000 to 9999 when counting down. this output allows direct cascading of counters. the carry/borrow output is not valid during load counter and reset operation. when the count is 6000 or higher, a reset generates a carry/borrow pulse. the eq u al output assumes a negative level when the contents of the counter and register are equal. the zer o output assumes a negative level when the content of the counter is 0000. the carry/borrow, eq u al and zer o outputs will drive a single ttl load over the full range of supply voltage and ambient temperature; for a logic zero, these outputs will sink 1.6ma at 0.4v and for a logic one, the outputs will source >60 m a. a 10k w pull-up resistor to v dd on the eq u al or zer o outputs is recommended for highest speed operation, and on the carry/borrow output when it is being used for cascading. figure 2 shows control outputs timing diagram. display outputs and control the digit and segment drivers provide a decoded 7-segment display system, capable of directly driving com- mon anode led displays at typical peak currents of 35ma/seg. this corresponds to average currents of 8ma/seg at 25% multiplex duty cycle. for the common cath- ode versions, peak segment currents are 12.5ma, corre- sponding to average segment currents of 3.1ma. figure 1 shows the multiplex timing. the display pin controls the display output using three level logic. the pin is self-biased to a voltage approximately 1 / 2 (v dd ); this corresponds to normal operation. when this pin is connected to v dd , the segments are disabled and when connected to v ss , the leading zero blanking feature is inhibited. for normal opera- tion (display on with leading zero blanking) the pin should be left open. the display may be controlled with a 3 position spdt switch; see test circuit. multiplex scan oscillator the on-board multiplex scan oscillator has a nominal free- running frequency of 2.5khz. this may be reduced by the addition of a single capacitor between the scan pin and the positive supply. capacitor values and corresponding nominal oscillator frequencies, digit repetition rates, and loading times are shown in table 1. figure 10a. figure 10b. figure 10c. figure 10. brightness control circuits r2 20k w 1m w 0.01 m f c scan input icm7217 r1 10k w 1m w 0.01 m f scan input icm7217 500 w 500 w 3k w 0.05 m f scan input icm7217 10k w 200 w 0.05 m f 74 8 3 2 61 8s icm7555 0v v dd = 5v icm7217
9-19 the internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse occurring at the oscillator frequency. this pulse clocks the four-state counter which provides the four multiplex phases. the short pulse width is used to delay the digit driver outputs, thereby provid- ing inter-digit blanking which prevents ghosting. the digits are scanned from msd (d4) to lsd (d1). see figure 1 for the display digit multiplex timing. during load counter and load register operations, the multiplex oscillator is disconnected from the scan input and is allowed to free-run. in all other conditions, the oscillator may be directly overdriven to about 20khz, however the external oscillator signal should have the same duty cycle as the internal signal, since the digits are blanked during the time the external signal is at a positive level (see figure 1). to insure proper leading zero blanking, the interdigit blank- ing time should not be less than about 2 m s. overdriving the oscillator at less than 200hz may cause display ?ickering. the display brightness may be altered by varying the duty cycle. figure 10 shows several variable-duty-cycle oscilla- tors suitable for brightness control at the icm7217 scan input. the inverters should be cmos cd4000 series and the diodes may be any inexpensive device such as ln914. counting control, st ore, reset as shown in figure 2, the counter is incremented by the rising edge of the count input signal when up/ do wn is high. it is decremented when up/ do wn is low. a schmitt trigger on the count input provides hysteresis to prevent double triggering on slow rising edges and permits operation in noisy environments. the count input is inhibited dur- ing reset and load counter operations. the st ore pin controls the internal latches and consequently the signals appearing at the 7-segment and bcd outputs. bringing the st ore pin low transfers the con- tents of the counter into the latches. the counter is asynchronously reset to 0000 by bringing the reset pin low. the circuit performs the reset operation by forcing the bcd input lines to zero, and presetting all four decades of counter in parallel. this affects register loading; if load register is activated when the reset input is low, the register will also be set to zero. the st ore, reset and up/ do wn pins are provided with pullup resistors of approxi- mately 75k w . bcd i/o pins the bcd i/o port provides a means of transferring data to and from the device. the icm7217 versions can multiplex data into the counter or register via thumbwheel switches, depending on inputs to the load counter or load register pins; (see below). when functioning as outputs, the bcd i/o pins will drive one standard ttl load. common anode versions have internal pull down resistors and com- mon cathode versions have internal pull up resistors on the four bcd i/o lines when used as inputs. loading the counter and register the bcd i/o pins, the load counter (lc), and load register (lr) pins combine to provide presetting and compare functions. lc and lr are 3-level inputs, being self- biased at approximately 1 / 2 v dd for normal operation. with both lc and lr open, the bcd i/o pins provide a multi- plexed bcd output of the latch contents, scanned from msd to lsd by the display multiplex. when either the load counter (pin 12) or load register (pin 11) is taken low, the drivers are turned off and the bcd pins become high-impedance inputs. when lc is connected to v dd , the count input is inhibited and the lev- els at the bcd pins are multiplexed into the counter. when lr is connected to v dd , the levels at the bcd pins are mul- tiplexed into the register without disturbing the counter. when both are connected to v dd , the count is inhibited and both register and counter will be loaded. the load counter and load register inputs are edge-triggered, and pulsing them high for 500ns at room temperature will initiate a full sequence of data entry cycle operations (see figure 3). when the circuit recognizes that either or both of the lc or lr pins input is high, the multiplex oscillator and counter are reset (to d4). the internal oscillator is then disconnected from the scan pin and the preset circuitry is enabled. the oscillator starts and runs with a frequency determined by its internal capacitor, (which may vary from chip to chip). when the chip ?nishes a full 4-digit multiplex cycle (loading each digit from d4 to d3 to d2 to d1 in turn), it again samples the load register and load counter inputs. if either or both is still high, it repeats the load cycle, if both are ?oating or low, the oscillator is reconnected to the scan pin and the chip returns to normal operation. total load time is digit on time multiplied by 4. lf the digit outputs are used to strobe the bcd data into the bcd i/o inputs, the input must be synchronized to the appropriate digit (figure 3). input data must be valid at the trailing edge of the digit output. when lr is connected to ground, the oscillator is inhibited, the bcd i/o pins go to the high impedance state, and the segment and digit drivers are turned off. this allows the display to be used for other purposes and minimizes power consumption. in this display off condition, the circuit will continue to count, and the carry/borrow, eq u al, zer o, up/ do wn, reset and st ore functions operate as normal. when lc is connected to ground, the bcd i/o pins are forced to the high impedance state without disturb- ing the counter or register. see control input de?nitions (table 2) for a list of the pins that function as three-state self- biased inputs and their respective operations. note that the icm7217 and icm7217b have been designed to drive common anode displays. the bcd inputs are high true, as are the bcd outputs. table 1. icm7217 multiplexed rate control scan capacitor nominal oscillator frequency digit repetition rate scan cycle time (4 digits) none 2.5khz 625hz 1.6ms 20pf 1.25khz 300hz 3.2ms 90pf 600hz 150hz 8ms icm7217
9-20 input output input output high high high disconnected low disconnected low high figure 11a. cmos inverter figure 11b. cmos inverter input b input a output input b input a output high high low high high disconnected high low disconnected high low disconnected low high disconnected low high high low low disconnected low low low figure 11c. cmos open drain figure 11d. cmos three-state buffer figure 11. driving 3-level inputs of icm7217 input cd4069 1n4148 output input cd4069 output 1n4148 input a cd74hc03 output input b input a cd4502b output input b figure 12a. common anode figure 12b. common cathode figure 12. forcing leading zero display figure 13a. common anode display figure 13b. common cathode display figure 13. driving high current displays d n digit line v dd 50k w display control icm7217 icm7217b d n digit line v dd display icm7217a icm7217c 50k w 50k w control v dd icm7217 digit drive segment drive v ss v dd icm7217b 2n2219 or similar 2n6034 or similar v ss v dd icm7217 segment drive digit drive v ss v ss icm7217c 2n6034 or similar 2n2219 or similar v dd icm7217
9-21 the lcm7217a and the icm7217c are used to drive com- mon cathode displays, and the bcd inputs are low true. bcd outputs are high true. notes on thumbwheel switches and multiplexing as it was mentioned, the icm7217 is basically designed to be used with thumbwheel switches for loading the data to the device. see figure 14 and figure 17. the thumbwheel switches used with these circuits (both common anode and common cathode) are true bcd coded; i.e. all switches open corresponds to 0000. since the thumbwheel switches are connected in parallel, diodes must be provided to prevent crosstalk between digits. in order to maintain reasonable noise margins, these diodes should be speci?ed with low forward voltage drops (in914). similarly, if the bcd outputs are to be used, resistors should be inserted in the digit lines to avoid loading problems. output and input restrictions load counter and load register operations take 1.6ms typical (5ms maximum) after lc or lr are released. during this load period the eq u al and zer o outputs are not valid (see figure 3). since the counter and register are compared by xor gates, loading the counter or register can cause erroneous glitches on the eq u al and zer o outputs when codes cross. load counter or load register, and reset input can not be activated at the same time or within a short period of each other. operation of each input must be delayed 1.6ms typical (5ms for guaranteed proper operation) relating to the preceding one. counter and register can be loaded together with the same value if lc and lr inputs become activated exactly at the same time. notice the setup and hold time of up/down input when it is changing during counting operation. violation of up/ do wn hold time will result in incrementing or decrementing the counter by 1000, 100 or 10 where the preceding digit is transitioning from 5 to 6 or 6 to 5. the reset input may be susceptible to noise if its input rise time is greater than about 500 m s this will present no prob- lems when this input is driven by active devices (i.e., ttl or cmos logic) but in hardwired systems adding virtually any capacitance to the reset input can cause trouble. a simple circuit which provides a reliable power-up reset and a fast rise time on the reset input is shown on figure 15. figure 14. lcd display interface (with thumbwheel switches) 8 4 2 1 c 8 4 2 1 c 8 4 2 1 c 8 4 2 1 c d4 d3 d2 d1 db3 db2 db1 db0 35 34 33 32 31 30 29 28 27 37 - 40 2 - 26 icm7211 28 segments and backplane lcd display icm7217 iji d1 d2 d3 d4 4 5 6 7 8s 4s 2s 1s v dd dc 24 23 20 8 9 10 14 reset st ore up/dn count 28 27 26 25 v dd = 5v v dd = 5v 10k w - 20k w icm7217
9-22 when using the circuit as a programmable divider (? by n with equal outputs) a short time delay (about 1 m s) is needed from the eq u al output to the reset input to establish a pulse of adequate duration. (see figure 16). when the circuit is con?gured to reload the counter or regis- ter with a new value from the bcd lines (upon reaching eq u al), loading time will be digit on time multiplied by four. if this load time is longer than one period of the input count, a count can be lost. since the circuit will retain data in the register, the register need only be updated when a new value is to be entered. reset will not clear the register. test circuit n.o. v dd icm7217 0.047 m f reset input 10 w v ss 10k w 5k w figure 15. power on reset v dd reset eq u al 47pf 33k figure 16. eq u al to reset delay carry zer o eq u al bcd i/o 8s bcd i/o 4s bcd i/o 2s bcd i/o 1s count input st ore up/ do wn load register load counter scan reset display 28 27 26 25 24 23 22 21 20 19 18 17 16 15 icm7217 icm7217b 9999 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d f g e a b c d f g e a b c d f g e a b c d f g e g b e f d a c common anode display d1 d3 d2 d4 d1 d3 d2 d4 n.o. v dd v ss control v dd thumbwheel switches +5v icm7217
9-23 applications 3-level inputs icm7217 has three inputs with 3-level logic states; high, low and disconnected. these inputs are: load register/ off, load counter/ i/o off and display cont. the circuits illustrated on figure 11 can be used to drive these inputs in different applications. fixed decimal point in the common anode versions, a ?xed decimal point may be activated by connecting the dp segment lead from the appro- priate digit (with separate digit displays) through a 39 w series resistor to ground. with common cathode devices, the dp segment lead should be connected through a 75 w series resistor to v dd . to force the device to display leading zeroes after a ?xed decimal point, use a bipolar transistor and base resistor in a con?guration like that shown in figure 12 with the resistor connected to the digit output driving the dp for left hand dp displays, and to the next least signi?cant digit output for right hand dp display. driving larger displays for displays requiring more current than the icm7217 can provide, the circuits of figure 13 can be used. lcd display interface the low-power operation of the icm7217 makes an lcd interface desirable. the intersil icm7211 4-digit, bcd-to-lcd display driver easily interfaces to the icm7217 as shown in figure 14. total system power consumption is less than 5mw. system timing margins can be improved by using capacitance to ground to slow down the bcd lines. the 10k w - 20k w resistors on the switch bcd lines serve to isolate the switches during bcd output. unit counter with bcd output the simplest application of the icm7217 is a 4-digit unit counter (figure 18). all that is required is an icm7217, a power supply and a 4 digit display. add a momentary switch for reset, an spdt center-off switch to blank the display or view leading zeroes, and one more spdt switch for up/ down control. using an icm7217a with a common-cathode calculator-type display results in the least expensive digital counter/display system available. inexpensive frequency counter/ tachometer this circuit uses the low power icm7555 (cmos 555) to generate the gating, st ore and reset signals as shown in figure 19. to provide the gating signal, the timer is con- ?gured as an a stable multivibrator, using r a , r b and c to provide an output that is positive for approximately one sec- ond and negative for approximately 300 m s - 500 m s. the pos- itive waveform time is given by t wp = 0.693 (r a + r b )c while the negative waveform is given by two = 0.693 r b c. the system is calibrated by using a 5m w potentiometer for r a as a coarse control and a 1k w potentiometer for r b as a ?ne control. cd40106bs are used as a monostable multivibrator and reset time delay. tape recorder position indicator/controller the circuit in figure 20 shows an application which uses the up/down counting feature of the icm7217 to keep track of tape position. this circuit is representative of the many applications of up/down counting in monitoring dimensional position. in the tape recorder application, the load register, eq u al and zer o outputs are used to control the recorder. to make the recorder stop at a particular point on the tape, the register can be set with the stop point and the eq u al output used to stop the recorder either on fast forward, play or rewind. to make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. resetting the counter at the starting point of the tape, a few feet from the end of the leader, allows the zer o output to be used to stop the recorder on rewind, leaving the leader on the reel. the 1m w resistor and 0.0047 m f capacitor on the count input provide a time constant of about 5ms to debounce the reel switch. the schmitt trigger on the count input of the icm7217 squares up the signal before applying it to the counter. this technique may be used to debounce switch-closure inputs in other applications. precision elapsed time/countdown timer the circuit in figure 21 uses an icm7213 precision one minute/one second timebase generator using a 4.1943mhz crystal for generating pulses counted by an icm7217b. the thumbwheel switches allow a starting time to be entered into the counter for a preset-countdown type timer, and allow the register to be set for compare functions. for instance, to make a 24-hour clock with bcd output the register can be preset with 2400 and the eq u al output used to reset the counter. note the 10k resistor connected between the load counter terminal and ground. this resistor pulls the load counter input low when not loading, thereby inhibiting the bcd output drivers. this resistor should be eliminated and sw4 replaced with an spdt center-off switch if the bcd outputs are to be used. this technique may be used on any 3-level input. the 100k w pullup resistor on the count input is used to ensure proper logic voltage swing from the icm7213. for a less expensive (and less accurate) timebase, an icm7555 timer may be used in a con?guration like that shown in figure 19 to generate a 1hz reference. 8-digit up/down counter this circuit (figure 22) shows how to cascade counters and retain correct leading zero blanking. the nand gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. the ?ip ?op is clocked by the least signi?cant digit of the high order counter, and if this digit is not blanked, the q output of the ?ip ?op goes high and turns on the npn transistor, thereby inhibiting leading zero blanking on the low order counter. icm7217
9-24 it is possible to use separate thumbwheel switches for presetting, but since the devices load data with the oscillator free-running, the multiplexing of the two devices is dif?cult to synchronize. precision frequency counter/tachometer the circuit shown in figure 23 is a simple implementation of a four digit frequency counter, using an icm7207a to provide the one second gating window and the st ore and reset signals. in this con?guration, the display reads hertz directly. with pin 11 of the icm7027a connected to v dd , the gating time will be 0.1s; this will display tens of hertz at the least signi?cant digit. for shorter gating times, an icm7207 may be used (with a 6.5536mhz crystal), giving a 0.01s gating with pin 11 connected to v dd , and a 0.1s gating with pin 11 open. to implement a four digit tachometer, the icm7207a with one second gating should be used. to get the display to read directly in rpm, the rotational frequency of the object to be measured must be multiplied by 60. this can be done electronically using a phase-locked loop, or mechanically by using a disc rotating with the object with the appropriate number of holes drilled around its edge to interrupt the light from an led to a photo-dector. for faster updating, use 0.1s gating, and multiply the rotational frequency by 600. auto-tare system this circuit uses the count-up and count-down functions of the icm7217, controlled via the eq u al and zer o outputs, to count in sync with an icl7109a and icl7109d con- verter as shown in figure 24. by reseting the icm7217 on a tare value conversion, and st ore-ing the result of a true value conversion, an automatic fare subtraction occurs in the result. the icm7217 stays in step with the icl7109 by counting up and down between 0 and 4095, for 8192 total counts, the same number as the icl7109 cycle. see applications note no. a047 for more details. table 2. control input definitions icm7217 input terminal voltage function store 9 v dd (or floating) v ss output latches not updated output latches updated up/ do wn 10 v dd (or floating) v ss counter counts up counter counts down reset 14 v dd (or floating) v ss normal operation counter reset load counter/ i/o off 12 unconnected v dd v ss normal operation counter loaded with bcd data bcd port forced to hi-z condition load reglster/ off 11 unconnected v dd v ss normal operation register loaded with bcd data display drivers disabled; bcd port forced to hi-z condition, mpx counter reset to d4; mpx oscillator inhibited display control 23 common anode 20 common cathode unconnected v dd v ss normal operation segment drivers disabled leading zero blanking inhibited icm7217
9-25 figure 17. thumbwheel switch/diode connections figure 18. unit counter 8 4 2 1 c 8 4 2 1 c to d4 strobe to d1 strobe 8421 to bcd inputs of icm7217, icm7217b 8 4 2 1 c 8 4 2 1 c to d4 strobe to d1 strobe 8421 to bcd inputs of icm7217a, icm7217c in914 or equivalent 21 - 23 25 - 28 24 20 19 15 - 18 1 2 4 5 6 7 8 9 14 carry zer o bcd i/o count input st ore reset v dd display icm7217a 4-digit control blank normal inhibit lzb common cathode led display 7 segments icm7217
9-26 figure 19a. figure 19b. figure 19. inexpensive frequency counter figure 20. tape recorder position indicator icm7217 4 5 6 7 v dd 24 8 9 14 reset st ore count v ss 20 led display 8 2 1 v ss cv th tr dis out v dd rs r a r b 0.47 m f c 1k 5m 3 0.047 m f 3k 10k count input gnd gate inverters: cd40106b nands: cd4011b 300 m s1s 50 m s gate st ore reset g 7 segments b e f d a v dd 4 digits blank normal inhibit lzb common cathode led display d4 d3 d2 d1 carry zer o bcd i/o count in st ore reset c eq u al up/down load reg load ctr scan zer o eq stop 9999 4 digit reset n.o. n.o. v dd v dd forward rewind 0.0047 m f reel switch closed once/rev v dd 1m thumbwheel switches logic to generate recorder control signals set pt 128 v dd icm7217
9-27 figure 21. precision timer 1 2 3 4 5 6 7 14 13 12 11 10 9 8 run min/sec stop run hrs/min v dd (4v max) sw1 g 4 b e f d a v dd 7 blank sw6 inhibit common anode led display d4 d3 d2 d1 carry zer o bcd count in st ore reset c eq u al up/down load reg load ctr scan lzb v dd digits v dd dis. cont. i/o v ss segments 5959 4 4 v dd v dd v dd reset preset display off load set pt. 10k sw3 sw2 countdown elapsed sw4 sw5 eq u al zer o to logic generating signals for control of external equipment 100k v dd thumbwheel switches icm7217 icm7213 30pf 30pf 4.1943mhz crystal r s < 75 w icm7217
9-28 figure 22. 8-digit up/down counter 1 4 - 7 8 9 10 14 25 - 28 24 20 23 15 - 19 21, 22 icm7217 low order v+ 1 4 - 7 8 9 10 14 25 - 28 24 20 15 - 19 21, 22 icm7217 high order v+ 50k w 3k w v+ d q cl cd4013 1 / 2 v+ carry out bcd outputs count input up/down 4 digits reset 4 d1 n.o. high order digits 50k w npn transistor bcd outputs high order digits 4 carry/borrow 7 segments 1b 1a cd4011 1 / 4 4 digits 7 segments common-anode led display icm7217
9-29 figure 23. precision frequency counter (mhz maximum) figure 24. auto-tare system for a/d converter 4 8 9 14 25 - 28 24 20 15 - 19 21, 22 icm7217 4 digits 7 segments common anode led display 5 6 7 bcd count st ore reset out icm7207a 4 5 6 2 13 14 10 cd4011 1 / 4 input 10k w 22pf 22pf crystal f = 5.24288mhz r s = 75 w v+ = 5v 10k w 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 icm7109 v dd ref in - ref cap - ref cap + ref in + in hi in lo common int az buf ref out v ss send run/ hold buf osc out osc sel osc out osc in mode gnd status pol or b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 test lben hben ce/lo ad carry/ zer o eq u al bcd 8 bcd 4 bcd 2 bcd 1 count st ore up/ do wn load reg. load ctr. scan reset d0 d2 d3 v dd disp. b e f d a c d1 g v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 borrow cont. icm7217 7 7 tare 10 m f +5v +5v 5 x 1n4148 minus sign led 270 +5v 4 digit common anode led display q d q d q q r r s s 47 m f 100k 10k 100k +5v 0.1 m f + 100k 100pf +5v 47k 0.22 m f 0.1 m f 1 m f +5v - +5v 400mv full scale input icm7217
9-30 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 icm7217

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