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? 2001 microchip technology inc. ds00754a-page 1 m AN754 introduction the controller area network (can) protocol is an asynchronous serial bus with non-return to zero (nrz) bit coding designed for fast, robust communica- tions in harsh environments, such as automotive and industrial applications. the can protocol allows the user to program the bit rate, the sample point of the bit, and the number of times the bit is sampled. with these features, the network can be optimized for a given application. there are relationships between bit timing parameters, the physical bus propagation delays, and the oscillator tolerances throughout the system. this application note investigates these relationships as they pertain to microchip?s can module and assists in optimizing the bit timing for given physical system attributes. the can bit time the can bit time is made up of non-overlapping seg- ments. each of these segments are made up of integer units called time quanta (tq) and are explained later in this application note. the nominal bit rate (nbr) is defined in the can specification as the number of bits per second transmitted by an ideal transmitter with no resynchronization and can be described with the equation: nominal bit time the nominal bit time (nbt), or t bit , is made up of non- overlapping segments (figure 1), therefore, the nbt is the summation of the following segments: associated with the nbt are the sample point, syn- chronization jump width (sjw), and information pro- cessing time (ipt), which are explained later. synchronization segment the synchronization segment (syncseg) is the first segment in the nbt and is used to synchronize the nodes on the bus. bit edges are expected to occur within the syncseg. this segment is fixed at 1tq. propagation segment the propagation segment (propseg) exists to com- pensate for physical delays between nodes. the prop- agation delay is defined as twice the sum of the signal?s propagation time on the bus line, including the delays associated with the bus driver. the propseg is pro- grammable from 1 - 8tq. phase segment 1 and phase segment 2 the two phase segments, ps1 and ps2 are used to compensate for edge phase errors on the bus. ps1 can be lengthened or ps2 can be shortened by resyncroni- zation. ps1 is programmable from 1 - 8tq and ps2 is programmable from 2 - 8tq. figure 1: can bit time segments author: pat richards microchip technology inc. nbr f bit 1 t bit ------- == t bit t syncseg t propseg t ps1 t ps2 +++ = nominal bit time (nbt), t bit sample point syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) understanding microchip?s can module bit timing
AN754 ds00754a-page 2 ? 2001 microchip technology inc. sample point the sample point is the point in the bit time in which the logic level is read and interpreted. the sample point is located at the end of phase segment 1. the exception to this rule is, if the sample mode is configured to sam- ple three times per bit. in this case, the bit is still sam- pled at the end of ps1, however, two additional samples are taken at one-half tq intervals prior to the end of ps1 and the value of the bit is determined by a majority decision. information processing time the information processing time (ipt) is the time required for the logic to determine the bit level of a sam- pled bit. the ipt begins at the sample point, is mea- sured in tq and is fixed at 2tq for the microchip can module. since phase segment 2 also begins at the sample point and is the last segment in the bit time, it is required that ps2 minimum is not less than the ipt. therefore: synchronization jump width the synchronization jump width (sjw) adjusts the bit clock as necessary by 1 - 4tq (as configured) to main- tain synchronization with the transmitted message. more on synchronization is covered later. time quantum each of the segments that make up a bit time are made up of integer units called time quanta (tq). the length of each time quantum is based on the oscillator period (t osc ). the base tq equals twice the oscillator period. figure 2 shows how the bit period is derived from t osc and tq. the tq length equals one tq clock period (t brpclk ), which is programmable using a programma- ble prescaler named the baud rate prescaler (brp). this is shown in the following equation: where: brp equals the configuration as shown in figure 3. bit timing control registers the can bit timing control (cnf) registers are the three registers that configure the can bit time. figure 3 details the function of the cnf registers. by adjusting the length of the tq (t tq ) and the number of tqs in each segment, both the nominal bit time and the sample point can easily be configured as desired. programming the timing segments the are several requirements for programming the can bit timing segments. 1. propseg + ps1 ps2 2. propseg + ps1 t prop 3. ps2 > sjw figure 2: tq and the bit period ps2 min ipt 2tq == tq 2 brp t osc 2 brp ? f osc ------------------ - = ?? = t osc t brpclk t bit sync (fixed) propseg (programmable) ps2 (programmable) ps1 (programmable) tq (t tq ) can bit time
? 2001 microchip technology inc. ds00754a-page 3 AN754 figure 3: can bit timing control registers (mcp2510 cnf registers) brp.2 brp.3 brp.4 sjw.1 bit 7 bit 0 brp.5 sjw.0 brp.0 brp.1 prseg.2 ps1.0 ps1.1 btlmode bit 7 bit 0 ps1.2 sam prseg.0 prseg.1 phseg21 --- --- bit 7 bit 0 --- wakfil phseg22 --- phseg20 sjw<1:0> (synchronization jump width length as measured in tq): 11 = 4tq 10 = 3tq 01 = 2tq 00 = 1tq brp<5:0> (baud rate prescaler tq length as a multiple of t osc ) 111111 = tq = 2 x 64 x t osc . . . . . . 000010 = tq = 2 x 3 x t osc 000001 = tq = 2 x 2 x t osc 000000 = tq = 2 x 1 x t osc btlmode (determines how ps2 is calculated) 1 = ps2 is determined by cnf3.ps2<2:0> 0 = ps2 is the greater of ps1 and the information processing time (ipt) sam (configures the sample point as one sample or three samples 1 = sample three times per bit 0 = sample once per bit ps1<2:0> (configures phase segment 1) 111 = 8tq . . . . 001 = 2tq 000 = 1tq prseg<2:0> (configures the propagation segment) 111 = 8tq . . . . 001 = 2tq 000 = 1tq wakfil (enables/disables the wakeup filter) 1 = filter enabled 0 = filter disabled ps2<2:0> (configures phase segment 2) 111 = 8tq . . . . 001 = 2tq 000 = not valid (ps2 min = ipt = 2tq) cnf1 cnf3 cnf2
AN754 ds00754a-page 4 ? 2001 microchip technology inc. synchronizing the bit time all nodes on the can bus must have the same nominal bit rate. noise, phase shifts, and oscillator drift create situations where the nominal bit rate does not equal the actual bit rate in a real system. therefore, the nodes must have a method for achieving and maintaining syn- chronization with bus messages. oscillator tolerance the bit timing for each node in a can system is derived from the reference frequency (f osc ) of its node. this creates a situation where phase shifting and oscillator drift will occur between nodes due to less than ideal oscillator tolerances between the nodes. the can specification indicates that the worst case oscillator tolerance is 1.58% and is only suitable for low bit rates (125 kb/s or less). this application note does not cover oscillator tolerances in detail, however, the references at the end of this application note provide more information on the subject. propagation delay the can protocol has defined a recessive (logic 1) and dominant (logic 0) state to implement a non-destructive bit-wise arbitration scheme. it is this arbitration method- ology that is affected the most by propagation delays. each node involved with arbitration must be able to sample each bit level within the same bit time. for example, if two nodes at opposite ends of the bus start to transmit their messages at the same time, they must arbitrate for control of the bus. this arbitration is only effective if both nodes are able to sample during the same bit time. figure 4 shows a one-way propagation delay between two nodes. extreme propagation delays (beyond the sample point) will result in invalid arbitra- tion. this implies that bus lengths are limited at given can data rates. a can system?s propagation delay is calculated as being a signal?s round trip time on the physical bus (t bus ), the output driver delay (t drv ), and the input com- parator delay (t cmp ). assuming all nodes in the system have similar component delays, the propagation delay is explained mathematically as: synchronization all nodes on a given can bus must have the same nbt. the nrz bit coding does not encode a clock into the message. the receivers must synchronize to the transmitted data stream to insure messages are prop- erly decoded. there are two methods used for achiev- ing and maintaining synchronization. hard synchronization hard synchronization only occurs on the first reces- sive-to-dominant (logic ?1? to ?0?) edge during a bus idle condition, which indicates a start-of-frame (sof) con- dition. hard synchronization causes the bit timing counter to be reset to the syncseg which causes the edge to lie within the syncseg. at this point, all of the receivers will be synchronized to the transmitter. hard synchronization occurs only once during a mes- sage. also, resynchronization may not occur during the same bit time (sof) that hard synchronization occurred. t prop 2t bus t cmp t drv ++ () ? =
? 2001 microchip technology inc. ds00754a-page 5 AN754 figure 4: one way propagation delay syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) sample point syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) transmitted bit from ?node a? ?node a? bit received by ?node b? propagation delay time (t)
AN754 ds00754a-page 6 ? 2001 microchip technology inc. resynchronization resynchronization is implemented to maintain the ini- tial synchronization that was established by the hard synchronization. without resynchronization, the receiv- ing nodes could get out of synchronization due to oscil- lator drift between nodes. resynchronization is achieved by implementing a dig- ital phase lock loop (dpll) function which compares the actual position of a recessive-to-dominant edge on the bus to the position of the expected edge (within the syncseg) and adjusting the bit time as necessary. the phase error of a bit is given by the position of the edge in relation to the syncseg, measured in tq, and is defined as follows: ? e = 0; the edge lies within the syncseg. ? e > 0; the edge lies before the sample point. (tq added to ps1). ? e < 0; the edge lies after the sample point of the previous bit. (tq subtracted from ps2) figure 5: synchronizing the bit time syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) sample point syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) sample point syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) sample point nominal bit time (nbt) sjw (ps1) sjw (ps2) nominal bit time (nbt) sjw (ps1) sjw (ps2) actual bit time resynchronization to a slower transmitter (e > 0) input signal input signal (e < 0) sjw (ps1) sjw (ps2) nominal bit time (nbt) actual bit time resynchronization to a faster transmitter (e < 0) input signal (e = 0) no resynchronization (e = 0) (e > 0)
? 2001 microchip technology inc. ds00754a-page 7 AN754 figure 5 shows how phase errors, other than zero, cause the bit time to be lengthened or shortened. synchronization rules: 1. only recessive-to-dominant edges will be used for synchronization. 2. only one synchronization within one bit time is allowed. 3. an edge will be used for synchronization only if the value at the previous sample point differs from the bus value immediately after the edge. 4. a transmitting node will not resynchronize on a positive phase error (e > 0). this implies that a transmitter will not resynchronize due to propa- gation delays of it?s own transmitted message. the receivers will synchronize normally. 5. if the absolute magnitude of the phase error is greater than the sjw, then the appropriate phase segment will be adjusted by an amount equal to the sjw. putting it all together as indicated previously, the can protocol implements a non-destructive bitwise arbitration scheme that allows multiple nodes to arbitrate for control of the bus. therefore, it is necessary for all the nodes to detect/ sample the bits within the same bit time. the relation- ship between propagation delay and oscillator toler- ance effect both the can data rate and the bus length. table 1 shows some commonly accepted bus lengths versus data rates. this application note does not cover all of the details for configuring the bit time for all scenarios, however, some general methodologies for configuring the can bit time are covered. calculating oscillator tolerance for sjw the bit stuffing rule guarantees that no more than five like bits in a row will be transmitted during a message frame. the only exception is at the end of the message that includes ten recessive bits (one ack delimiter, seven end-of-frame bits, and three interframe space bits). resynchronization can only occur on recessive-to- dominant edges. this implies that there can be a max- imum of ten bits between resynchronization due to bit stuffing (figure 6). the oscillator tolerance between the slowest node and the fastest node can be used to determine the mini- mum sjw. assuming node a is the slow node (longest bit time) and node b is the fast node (shortest bit time): where: t bit(n) = bit time of node ?n? t sjw(n) = sjw of node ?n? figure 6: maximum time between synchronization edges example 1: find minimum sjw given: nominal bit time = 1 s oscillator tolerance = 1.25% note: #tq per bit = 8 find sjw minimum: t bit(a) = 1.01200 s t bit(b) = 0.98875 s tq (a) = 126.563 ns tq (b) = 123.438 ns using equation above: t sjw(b) > 10t bit(a) - 10t bit(b) = 0.250 s #tq sjw > t sjw(b) / tq (b) = 250 ns / 123.44 ns = 2.025 #tq sjw = 3 table 1: can bit rate vs. bus length bit rate (kb/s) bus length (m) 1000 30 500 100 250 250 125 500 62.5 1000 10t bit a () 10t bit b () t sjw b () + > synchronization edge bit time
AN754 ds00754a-page 8 ? 2001 microchip technology inc. alternatively, the following equation can be used to maintain synchronization during normal bus operation: solving for oscillator tolerance ( ? f) configuring the bit in general, the longer the bus, the slower the maximum data rate due to propagation delays on the line. increasing the oscillator tolerances between nodes can greatly amplify the relationship. can system designers must take this relationship into consideration when defining the network. the following examples demonstrate bit timings for achieving maxi- mum oscillator tolerance or maximum bit rate. example 2: maximum oscillator tolerance the maximum oscillator tolerance for a maximum data rate is achieved when the phase segments 1 and 2 are equal to the maximum synchronization jump width (4tq). also, the propagation segment is minimum, indi- cating a short bus and fast transceiver. as indicated earlier, the propagation delay is twice the delays of the bus, the receiver circuitry, and the driver. given: t bus = 50 m @ 5.5 ns/m = 275 ns t cmp = 40 ns t drv = 60 ns t prop = 2(t bus +t cmp +t drv ) = 750 ns since the propagation segment is used to compensate for propagation delays and must be set to the minimum 1tq, the implied time quantum = t prop = 750 ns. figure 7 shows the bit timing. figure 7: bit timing for maximum oscillator tolerance sjw 2 ? f () 10nbt () > ? fsjw20nbt ? < t prop 2t bus t cmp t drv ++ () = syncseg propseg phaseseg1 (ps1) phaseseg2 (ps2) nominal bit time (nbt), t bit tq tq = t prop = 750 ns syncseg = 1tq propseg = t prop = 1tq ps1 = sjw max = 4tq ps2 = sjw max = 4tq sjw max = 0.4nbt = 4tq t bit = 10tq = 7.5 s 133.3 kb/s
? 2001 microchip technology inc. ds00754a-page 9 AN754 example 3: maximum bit rate the previous example showed that for a given bus length, the maximum data rate is inversely affected, due to oscillator tolerance (as oscillator tolerance goes up, the data rate goes down). to achieve the maximum bit rate for a given bus length, the emphasis is placed on configuring the bit time for the propagation delays (i.e., adjusting propseg to maximum). the oscillator tolerance must be minimized. given the same delays as the previous example: t bus = 50 m @ 5.5 ns/m = 275 ns t cmp = 40 ns t drv = 60 ns t prop = 2(t bus +t cmp +t drv ) = 750 ns since the oscillator tolerance is minimum, the phase segments and sjw can be set to the minimum. assum- ing the bit time is 10tq total, the propseg can be set to 6tq which sets tq = 125 ns. figure 8 shows the bit timing for maximum bit rate. figure 8: bit timing for maximum bit rate references mcp2510 data sheet , ds21291, microchip technol- ogy, inc. lawrenz, wolfhard, ? can system engineering from theory to practical applications ?, springer, 1997 ?can specification?, version 2.0, parts a and b , robert bosch gmbh, 1991 ?iso11898 ?, international standards organization, 1993 controller area network (can) basics , ds00713 pic18c reference manual , ds39500 pic18c58 datasheet , ds30475 conclusion setting up can bit timing is not an arbitrary process. the system designer must be aware of the compo- nents that affect bit timing and compensate to get opti- mal performance across the network. for example, if the desired system uses oscillators with the maximum tolerance, the maximum bus length is reduced. like- wise, if maximum bus length is desired, the oscillator tolerances must be minimized. can data rates must also be considered because the data rate is a third vari- able that determines maximum length and maximum oscillator tolerances. this application note should help assist system engi- neers design a controller area network for optimal per- formance based on requirements of the system. syncseg propseg ps1 ps2 nominal bit time (nbt), t bit tq tq = t prop / 6 = 125 ns syncseg = 1tq propseg = t prop = 6tq ps1 = 1tq ps2 = 2tq sjw max = 1tq t bit = 10tq = 1.25 s 800 kb/s
AN754 ds00754a-page 10 ? 2001 microchip technology inc. definition of terms dominant bit - logic 0, overrides a recessive bit during arbitration. recessive bit - logic 1. can node - a point in the network where can commu- nications is connected. nominal bit time (nbt) - the length of a transmitted bit by an ideal transmitter with no resynchronization. can - controller area network. nominal bit rate (nbr) - the number of bits per sec- ond transmitted by an ideal transmitter. propagation delay - signals round trip time on the physical bus. hard synchronization - resets the receiving nodes bit timers. occurs only at start of frame (sof). resynchronization - maintains synchronization by adjusting the bits as needed. information processing time (ipt) - the time required to determine the bit level. begins at the sample point. start of frame (sof) - the first dominate bit during bus idle. indicates a start of frame. sample point - position within the bit where the logic level is sampled.
? 2001 microchip technology inc. ds00754a-page 11 AN754 notes:
? 2001 microchip technology inc. ds00754a-page 11 AN754 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are reg- istered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filter- lab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picc, picdem, picdem.net, icepic, migratable memory, fansense, economonitor, select mode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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