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| z8 m icrocontroller u ser s m anual um001600-z8x0599
ii um001600-z8x0599 ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. u ser s m anual t able of c ontents chapter title and subsections page um001600-z8x0599 iii chapter 1. z8 mcu product overview z8 mcu family overview key product line features .................................................................................................. 1- 1 product development support ............................................................................................. 1-3 chapter 2. address space introduction .................................................................................................................. ............... 2-1 z8 mcu standard register file ................................................................................................. .2-1 general-purpose registers ................................................................................................. 2-2 ram protect ................................................................................................................... ...... 2-2 working register groups ..................................................................................................... 2 -2 error conditions .............................................................................................................. ..... 2-4 z8 expanded register file .................................................................................................... ... 2-5 z8 control and peripheral registers .......................................................................................... 2-8 standard z8 registers ......................................................................................................... 2-8 expanded z8 registers ....................................................................................................... 2 -8 program memory ................................................................................................................ ...... 2-10 z8 external memory ............................................................................................................ ..... 2-11 external data memory ....................................................................................................... 2- 11 z8 stacks ..................................................................................................................... ......... 2-12 chapter 3. clock clock ......................................................................................................................... .................. 3-1 frequency control ............................................................................................................. .. 3-1 clock control ................................................................................................................. ............. 3-1 sclk/tclk divide-by-16 select (d0) ................................................................................. 3-2 external clock divide-by-two (d1) ..................................................................................... 3-2 oscillator control ............................................................................................................ ............ 3-2 z8 microcontrollers table of contents zilog chapter title and subsections page iv um001600-z8x0599 chapter 3. clock (continued) oscillator operation .......................................................................................................... .......... 3-3 layout ........................................................................................................................ .......... 3-3 indications of an unreliable design ..................................................................................... 3-3 circuit board design rules .................................................................................................. 3 -4 crystals and resonators ...................................................................................................... 3-5 lc oscillator ................................................................................................................. .............. 3-6 rc oscillator ................................................................................................................. ............. 3-6 chapter 4. reset?watch-dog timer reset ......................................................................................................................... ................. 4-1 reset pin, internal por operation ............................................................................................ 4-1 watch-dog timer (wdt) ......................................................................................................... ... 4-7 power-on-reset (por) .......................................................................................................... .... 4-8 chapter 5. i/o ports i/o ports ..................................................................................................................... ................ 5-1 mode registers ................................................................................................................ .... 5-1 input and output registers .................................................................................................. 5 -1 port 0 ........................................................................................................................ .................. 5-2 general i/o mode .............................................................................................................. .. 5-3 read/write operations ........................................................................................................ 5-4 handshake operation .......................................................................................................... 5-4 port 1 ........................................................................................................................ .................. 5-5 general i/o mode .............................................................................................................. .. 5-5 read/write operations ........................................................................................................ 5-8 handshake operations ........................................................................................................ 5 -8 port 2 ........................................................................................................................ ............... 5-9 general port i/o .............................................................................................................. ..... 5-9 read/write operations ...................................................................................................... 5- 12 handshake operation ........................................................................................................ 5- 12 port 3 ........................................................................................................................ ............. 5-13 general port i/o .............................................................................................................. ... 5-13 read/write operations ...................................................................................................... 5- 18 special functions ............................................................................................................. .. 5-18 port handshake ................................................................................................................ ........ 5-19 i/o port reset conditions ..................................................................................................... .... 5-24 full reset .................................................................................................................... ....... 5-24 chapter 5. i/o ports analog comparators ............................................................................................................ ..... 5-26 z8 microcontrollers zilog table of contents chapter title and subsection page um001600-z8x0599 v comparator description ..................................................................................................... 5- 26 comparator programming ................................................................................................. 5-28 comparator operation ....................................................................................................... 5- 29 interrupts .................................................................................................................... ........ 5-29 comparator definitions ...................................................................................................... 5 -29 run mode ...................................................................................................................... ... 5-29 halt mode ..................................................................................................................... ... 5-29 stop mode ..................................................................................................................... .. 5-29 open-drain configuration ...................................................................................................... ... 5-30 low emi emission .............................................................................................................. ...... 5-30 input protection .............................................................................................................. .......... 5-31 cmos z8 auto latches .......................................................................................................... .. 5-32 chapter 6. counter/timers introduction .................................................................................................................. ............... 6-1 prescalers and counter/timers ................................................................................................. . 6-2 counter/timer operation ....................................................................................................... ..... 6-3 load and enable count bits ................................................................................................ 6-3 prescaler operations .......................................................................................................... . 6-4 t out modes ........................................................................................................................ ....... 6-5 t in modes ........................................................................................................................ ........... 6-7 external clock input mode ................................................................................................... 6 -8 gated internal clock mode .................................................................................................. 6- 9 triggered input mode ......................................................................................................... 6-10 retriggerable input mode .................................................................................................. 6-1 1 cascading counter/timers ...................................................................................................... . 6-11 reset conditions .............................................................................................................. ........ 6-12 chapter 7. interrupts introduction .................................................................................................................. ............... 7-1 interrupt sources ............................................................................................................. ........... 7-2 external interrupt sources ................................................................................................... 7-2 internal interrupt sources .................................................................................................... 7-3 interrupt request (irq) register logic and timing ................................................................... 7-4 interrupt initialization ...................................................................................................... ............ 7-5 interrupt priority register (ipr) initialization ........................................................................ 7-5 interrupt mask register (imr) initialization .......................................................................... 7-6 interrupt request (irq) register initialization ..................................................................... 7-7 irq software interrupt generation ............................................................................................. 7-9 chapter 7. interrupts (continued) z8 microcontrollers table of contents zilog chapter title and subsections page vi um001600-z8x0599 vectored processing ........................................................................................................... ....... 7-9 vectored interrupt cycle timing ........................................................................................ 7-11 nesting of vectored interrupts ........................................................................................... 7-12 polled processing ............................................................................................................. ........ 7-12 reset conditions .............................................................................................................. ........ 7-12 chapter 8. power-down modes introduction .................................................................................................................. ............... 8-1 halt mode operation ........................................................................................................... ..... 8-1 stop mode operation ........................................................................................................... .... 8-2 stop-mode recovery register (smr) ...................................................................................... 8-3 chapter 9. serial i/o uart introduction ............................................................................................................. ......... 9-1 uart bit-rate generation ...................................................................................................... ... 9-2 uart receiver operation ....................................................................................................... ... 9-4 receiver shift register 9-4 overwrites .................................................................................................................... ........ 9-5 framing errors ................................................................................................................ ..... 9-5 parity ........................................................................................................................ ............ 9-5 transmitter operation ......................................................................................................... ........ 9-6 overwrites .................................................................................................................... ........ 9-6 parity ........................................................................................................................ ............ 9-6 uart reset conditions ......................................................................................................... .... 9-7 serial peripheral interface (spi) ............................................................................................. .... 9-8 spi operation ................................................................................................................. ............ 9-9 spi compare ................................................................................................................... ........... 9-9 spi clock ..................................................................................................................... ............... 9-9 receive character available and overrun ............................................................................... 9-11 chapter 10. external interface introduction .................................................................................................................. ............. 10-1 pin descriptions .............................................................................................................. .......... 10-2 as ............................................................................................................................... ....... 10-2 ds ............................................................................................................................... ....... 10-2 r/w ............................................................................................................................... ..... 10-2 dm ............................................................................................................................ ......... 10-2 p07 - p00 ..................................................................................................................... ...... 10-2 p17 - p10 ..................................................................................................................... ..... 10-2 reset ............................................................................................................................... 10-2 xtal1, xtal2 .................................................................................................................. . 10-2 z8 microcontrollers zilog table of contents chapter title and subsection page um001600-z8x0599 vii external addressing configuration ........................................................................................... 1 0-3 external stacks ............................................................................................................... .......... 10-4 data memory ................................................................................................................... ......... 10-4 bus operation ................................................................................................................. .......... 10-5 address strobe ................................................................................................................ .. 10-6 data strobe ................................................................................................................... ..... 10-6 extended bus timing ........................................................................................................... .... 10-7 instruction timing ............................................................................................................ ......... 10-9 z8 reset conditions ........................................................................................................... .... 10-10 chapter 11. addressing modes introduction .................................................................................................................. ............. 11-1 z8 addressing modes ........................................................................................................ 11 -1 z8 register addressing (r) .................................................................................................... .. 11-2 z8 indirect register addressing (ir) ........................................................................................ 1 1-3 z8 indexed addressing (x) ..................................................................................................... .. 11-5 z8 direct addressing (da) ..................................................................................................... ... 11-6 z8 relative addressing (ra) ................................................................................................... . 11-7 z8 immediate data addressing (im) ......................................................................................... 11- 8 chapter 12. instruction set z8 functional summary ......................................................................................................... .. 12-1 processor flags................................................................................................................ ..........12-2 condition codes ................................................................................................................ .........12-5 notation and binary coding..................................................................................................... ...12-6 z8 instruction summary ......................................................................................................... ....12-8 instruction description and formats.........................................................................................12- 11 viii um001600-z8x0599 u ser s m anual l ist of f igures figure title page um001600-z8x0599 ix chapter 1. z8 mcu product overview z8 mcu block diagram .......................................................................................................... .....1-2 chap[ter 2. address space 16-bit register addressing .................................................................................................... ..... 2-2 accessing individual bits (example) ........................................................................................... .2-2 working register addressing examples .....................................................................................2-3 register pointer .............................................................................................................. .............2-4 expanded register file architecture ........................................................................................... 2-5 register pointer (fdh) example ................................................................................................ .2-6 z8 program memory map ......................................................................................................... .2-10 external memory map ........................................................................................................... ....2-11 stack pointer ................................................................................................................. ............2-12 stack operations .............................................................................................................. .........2-12 chapter 3. clock z8 clock circuit .............................................................................................................. .............3-1 stop-mode recovery register (write-only except d7, which is read-only) ...................................................................3-1 external clock circuit ........................................................................................................ ..........3-2 port configuration register (pcon) (write-only) .......................................................................3-2 pierce oscillator with internal feedback circuit ..........................................................................3-3 circuit board design rules .................................................................................................... .....3-4 crystal/ceramic resonator oscillator .........................................................................................3 -5 lc clock ...................................................................................................................... ................3-5 chapter 3. clock (continued) external clock ................................................................................................................ .............3-5 z8 microcontrollers list of figures zilog figure title page x um001600-z8x0599 rc clock ...................................................................................................................... ...............3-6 chapter 4. reset?watch-dog timer reset timing .................................................................................................................. .............4-2 example of external power-on reset circuit ..............................................................................4-3 example of z8 reset with /reset pin, wdt, smr, and por ..................................................4-5 example of z8 reset with wdt, smr, and por ........................................................................4-6 example of z8 watch-dog timer mode register (write-only) ...................................................4-7 example of z8 with simple smr and por .................................................................................4-8 chapter 5. i/o ports i/o ports and mode registers .................................................................................................. ...5-1 ports 0, 1, 2 generic block diagram .......................................................................................... 5-2 port 0 configuration with open-drain capability, auto latch, and schmitt-trigger ..........................................................................................................5 -3 port 0 configuration with ttl level shifter .......................................................5-4 port 0 i/o operation .......................................................................................................... ..........5-5 port 0 handshake operation .................................................................................................... ...5-5 port 1 configuration with open-drain capability, auto latch, and schmitt-trigger ..........................................................................................................5 -6 port 1 configuration with ttl level shifter .................................................................................5- 7 port 1 i/o operation .......................................................................................................... ..........5-8 handshake operation ........................................................................................................... .......5-8 port 2 i/o mode configuration ................................................................................................. ....5-9 port 2 configuration with open-drain capability, auto latch, and schmitt-trigger ..........................................................................................................5 -9 port 2 configuration with ttl level shifter ...............................................................................5-10 port 2 configuration with open-drain capability, auto latch, schmitt-trigger and spi ..................................................................................................5-11 port 2 handshake configuration 5 .............................................................................................. -12 port 2 handshaking ............................................................................................................ .......5-12 port 3 block diagram .......................................................................................................... .......5-13 port 3 configuration with comparator, auto latch, and schmitt-trigger ..................................5-14 port 3 configuration with comparator .......................................................................................5-1 5 chapter 5. i/o ports (continued) port 3 configuration with spi and comparator outputs using p34 and p35 .........................................................................................................5-16 port 3 configuration with ttl level shifter and auto latch ......................................................5-17 port 3 mode register configuration ..........................................................................................5- 18 z8 input handshake ............................................................................................................ ......5-20 z8 microcontrollers zilog list of figures figure title page um001600-z8x0599 xi z8 output handshake ........................................................................................................... ....5-21 output strobed handshake on port 2 .......................................................................................5-23 input strobed handshake on port 2 ..........................................................................................5-2 3 port 0/1 reset ................................................................................................................ ............5-24 port 2 reset .................................................................................................................. .............5-25 port 3 mode reset ............................................................................................................. ........5-25 port 3 input analog selection ................................................................................................. ...5-26 port 3 comparator output selection .........................................................................................5-2 6 port configuration of comparator inputs on p31, p32, and p33 ...............................................5-27 port 3 configuration .......................................................................................................... .........5-28 port 2 configuration .......................................................................................................... .........5-30 port configuration register (pcon) (write-only) .....................................................................5-30 diode input protection ........................................................................................................ .......5-31 otp diode input protection .................................................................................................... ...5-31 simplified cmos z8 i/o circuit ................................................................................................ .5-32 auto latch equivalent circuit ...........................................................................5-33 effect of pulldown resistors on auto latches ...........................................................................5-33 chapter 6. counter/timers counter/timer block diagram ................................................................................................... ..6-1 counter/timer register map .................................................................................................... ...6-2 prescaler 0 register .......................................................................................................... ..........6-2 prescaler 1 register .......................................................................................................... ..........6-2 counter / timer 0 and 1 registers ............................................................................................. .6-2 timer mode register ........................................................................................................... ........6-3 starting the count ............................................................................................................ ..........6-3 counting modes ................................................................................................................ ..........6-3 timer mode register (t out operation) .......................................................................................6-5 port 3 mode register (t out operation) .......................................................................................6-5 t0 and t1 output through t out .................................................................................................6-6 chapter 6. counter/timers (continued) internal clock output through t out ........................................................................................... 6-6 timer mode register (t in operation) ..........................................................................................6-7 prescaler 1 register (t in operation) ...........................................................................................6-7 external clock input mode ..................................................................................................... .....6-8 gated clock input mode ........................................................................................................ ......6-9 triggered clock mode .......................................................................................................... .....6-10 cascaded counter/timers ....................................................................................................... ..6-11 counter/timer reset ........................................................................................................... ......6-12 prescaler 1 register reset .................................................................................................... ....6-12 z8 microcontrollers list of figures zilog figure title page xii um001600-z8x0599 prescaler 0 reset ............................................................................................................. .........6-12 timer mode register reset ..................................................................................................... ..6-12 chapter 7. interrupts interrupt control registers ................................................................................................... .......7-1 interrupt block diagram ....................................................................................................... ........7-1 interrupt sources irq0-irq2 block diagram ..............................................................................7-2 interrupt source irq3 block diagram .........................................................................................7- 3 irq register logic ............................................................................................................ ..........7-4 interrupt request timing ...................................................................................................... .......7-4 interrupt priority register ...................................................................................7-5 interrupt mask register ....................................................................................................... ........7-6 interrupt request register .................................................................................................... ......7-7 irq reset functional logic diagram ..........................................................................................7- 8 effects of an interrupt on the stack .......................................................................................... 7-9 interrupt vectoring ........................................................................................................... ..........7-10 z8 interrupt acknowledge timing .............................................................................................7 -11 chapter 8. power-down modes stop-mode recovery register (write-only except bit d7, which is read-only) ..............................................................8-3 stop-mode recovery source ....................................................................................................8 -4 chapter 9. serial i/o uart block diagram ............................................................................................................ ......9-1 port 3 mode register (p3m) and bit-rate generation ................................................................9-2 bit rate divide chain .........................................................................................9-2 prescaler 0 register (pre0) bit-rate generation ......................................................................9-3 timer mode register (tmr) bit rate generation .......................................................................9-4 receiver timing ............................................................................................................... ............9-4 receiver data formats ......................................................................................9-5 port 3 mode register (p3m) parity ............................................................................................. .9-5 transmitter data formats ...................................................................................................... ......9-6 sio register reset ............................................................................................................ ..........9-7 p3m register reset ............................................................................................................ ........9-7 spi control register (scon) ................................................................................................... ...9-8 spi system configuration ...................................................................................................... ...9-10 spi timing .................................................................................................................... .............9-11 spi logic ..................................................................................................................... ..............9-12 spi data in/out configuration ................................................................................................. ..9-13 spi clock / spi slave select output configuration ...................................................................9-14 z8 microcontrollers zilog list of figures figure title page um001600-z8x0599 xiii chapter 10. external interface z8 external interface pins .................................................................................................... .....10-1 external address configuration ................................................................................................ .10-3 z8 stack selection ............................................................................................................ .........10-4 port 3 data memory operation .................................................................................................. 10-4 external instruction fetch or memory read cycle ....................................................................10-5 external memory write cycle ................................................................................................... .10-6 extended external instruction fetch or memory read cycle ....................................................10-7 extended external memory write cycle ....................................................................................10-8 extended bus timing ........................................................................................................... .....10-8 instruction cycle timing (one-byte instructions) ......................................................................10-9 instruction cycle timing (two and three byte instructions) ...................................................10-10 chapter 11. addressing modes 8-bit register addressing ..................................................................................................... .....11-2 4-bit register addressing ..................................................................................................... .....11-2 4-bit register addressing ..................................................................................................... .....11-3 indirect register addressing to program or data memory ........................................................11-4 indexed register addressing ................................................................................................... .11-5 direct addressing ............................................................................................................. .........11-6 relative addressing ........................................................................................................... ........11-7 immediate data addressing ..................................................................................................... .11-8 z8 microcontrollers list of figures zilog figure title page xiv um001600-z8x0599 u ser s m anual l ist of t ables table title page um001600-z8x0599 xv chapter 1. z8 mcu product overview zilog general-purpose microcontroller product family ........................................................... 1-3 chapter 2. address space z8 standard register file ..................................................................................................... ...... 2-1 working register groups ....................................................................................................... .... 2-3 erf bank address .............................................................................................................. ....... 2-6 z8 expanded register file bank layout .................................................................................... 2-7 expanded register file register bank c, wr group 0 ............................................................. 2-8 expanded register file bank 0, wr group 0 ............................................................................ 2-9 expanded register file bank f, wr group 0 ............................................................................ 2-9 chapter 4. reset?watch-dog timer sample control and peripheral register reset values (erf bank 0) ....................................... 4-2 expanded register file bank 0 reset values at reset ........................................................... 4-3 sample expanded register file bank c reset values .............................................................. 4-4 sample expanded register file bank f reset values .............................................................. 4-4 time-out period of the wdt .................................................................................................... .. 4-7 chapter 5. i/o ports port 3 line functions ......................................................................................................... ....... 5-19 chapter 7. interrupts interrupt types, sources, and vectors ....................................................................................... 7 -2 interrupt priority ............................................................................................................ .............. 7-5 interrupt group priority ...................................................................................................... ......... 7-6 irq register configuration .................................................................................................... .... 7-8 z8 microcontrollers list of tables zilog table title page xvi um001600-z8x0599 chapter 8. power-down modes stop-mode recovery source ................................................................................................... 8 -4 chaper 9. serial i/o uart register map ............................................................................................................. ...... 9-2 bit rates ..................................................................................................................... ................ 9-3 spi pin configuration ......................................................................................................... ........ 9-8 um001600-z8x0599 1-1 u ser s m anual c hapter 1 z8 mcu p roduct o verview 1.1 z8 mcu family overview the zilog z8 microcontroller (mcu) product line contin- ues to expand with new product introductions. zilog mcu products are targeted for cost-sensitive, high-volume appli- cations including consumer, automotive, security, and hvac. it includes rom-based products geared for high- volume production (where software is stable) and one-time programmable (otp) equivalents for prototyping as well as volume production where time to market or code flexi- bility is critical (table 1-1). a variety of packaging options are available including plastic dip, soic, plcc, and qfp. a generalized z8 mcu ? block diagram is shown in figure 1-1. the same on-chip peripherals are used across the mcu product line with the primary differences being the amount of rom/ram, number of i/o lines present, and packaging/temperature ranges available. this allows code written for one mcu device to be easily ported to another family member. 1.1.1 key product line features general-purpose register (gpr) file: every ram register acts like an accumulator, speeding instruction execution and maximizing coding efficiency. working register groups allow fast context switching. flexible i/o: i/o byte, nibble, and/or bit programmable as inputs or outputs. outputs are software programmable as open-drain or push-pull on a port basis. inputs are schmitt-triggered with auto latches to hold unused inputs at a known voltage state. analog inputs: three input pins are software programmable as digital or analog inputs. when in the analog mode, two comparator inputs are provided with a common reference input. these inputs are ideal for a variety of common functions, including threshold level detection, analog-to-digital conversion, and short circuit detection. each analog input provides a unique maskable interrupt input. timer/counter(t/c): the t/c consists of a programmable 6-bit prescaler and 8-bit downcounter, with maskable interrupt upon end-of-count. software controls t/c load/start/stop, countdown read (at any time on the fly), and maskable end-of-count interrupt. special functions available include t in (external counter input, external gate input, or external trigger input) and t out (external access to timer output or the internal system clock.) these special functions allow accurate hardware input pulse measurement and output waveform generation. interrupts: there are six vectored interrupt sources with software-programmable enable and priority for each of the six sources. watch-dog timer (wdt): an internal wdt circuit is included as a fail-safe mechanism so that if software strays outside the bounds of normal operation, the wdt will timeout and reset the mcu. to maximize circuit robustness and reliability, the default wdt clock source is an internal rc circuit (isolated from the device clock source). auto reset/low-voltage protection: all family devices have internal power-on reset. rom devices add low-voltage protection. low-voltage protection ensures the mcu is in a known state at all times (in active run mode or reset) without external hardware (or a device reset pin). low-emi operation: mode is programmable via software or as a mask option. this new option provides for reduced radiated emission via clock and output drive circuit changes. z8 microcontrollers z8 mcu product overview zilog 1-2 um001600-z8x0599 1.1 z8 mcu family overview (continued) low-power: cmos with two standby modes; stop and halt. full z8 instruction set: forty-eight basic instructions, supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and words. figure 1-1. z8 mcu block diagram port 3 counter/ timers (2) interrupt control analog comparators (2) output input alu flag register pointer register file 256 x 8-bit machine timing & instruction control reset, wdt, por prg. memory 512/k x 8-bit program counter vcc gnd xtal address or i/o (nibble programmable) port 2 port 0 port 1 /as /ds r//w /reset 44 8 address/data or i/o (byte programmable) i/o (bit programmable) z8 microcontrollers zilog z8 mcu product overview um001600-z8x0599 1-3 1.1.2 product development support the z8 mcu product line is fully supported with a range of cross assemblers, c compilers, icebox emulators, single and gang otp/eprom programmers, and software simulators. the z86ccp01zem low-cost z8 ccp? real-time emula- tor/programmer kit was designed specifically to support all the products outlined in table 1-1. the z86ccp01zem kit comes with: z8 ccp evaluation board z8 ccp power cable zilog developers studio (zds) cd-rom , including windows-based 1 gui host software 1999 zilog technical library z8 ccp users manual a z8 ccp emulator accessory kit (z8ccp00zac) is also available and provides an rs-232 cable and power cable along with the 28- and 40- pin zif sockets and 28- and 40- pin target connector cables required to emulate/program 28/40 pin devices. 1. windows is a trademark of the microsoft corporation. table 1-1. zilog general-purpose microcontroller product family product rom/ram i/0 t/c an int wdt por v bo rc speed pin in (mhz) count z86c03 512/60 14 1 2 6 f y y y 8 18 z86e03 512/60 14 1 2 6 f y n y 8 18 z86c04 1k/124 14 2 2 6 f y y y 8 18 z86e04 1k/124 14 2 2 6 f y n y 8 18 z86c06 1k/124 14 2 2 6 p y y y 12 18 z86e06 1k/124 14 2 2 6 p y n y 12 18 z86c08 2k/124 14 2 2 6 f y y y 12 18 z86e08 2k/124 14 2 2 6 f y n y 12 18 z86c30 4k/236 24 2 2 6 p y y y 12 28 z86e30 4k/236 24 2 2 6 p y n y 12 28 z86c31 2k/124 24 2 2 6 p y y y 8 28 z86e31 2k/124 24 2 2 6 p y n y 8 28 z86c40 4k/236 32 2 2 6 p y y y 16 40/44 z86e40 4k/236 32 2 2 6 p y n y 16 40/44 note: z86cxx signify rom devices; 86xx signify eprom devices; f = fixed; p = programmable 1-4 um001600-z8x0599 2-1 u ser s m anual c hapter 2 a ddress s pace 2.1 introduction four address spaces are available for the z8 mcu ? : the z8 standard register file contains addresses for peripheral, control, all general-purpose, and all i/o port registers. this is the default register file specification. the z8 expanded register file (erf) contains addresses for control and data registers for additional peripherals/features. z8 external program memory contains addresses for all memory locations having executable code and/or data. z8 external data memory contains addresses for all memory locations that hold data only, whether internal or external. 2.2 z8 mcu standard register file the z8 standard register file totals up to 256 consecutive bytes (registers). the register file consists of 4 i/o ports (00h-03h), 236 general-purpose registers (04h-efh), and 16 control registers (f0h-ffh). table 2-1 shows the layout of the register file, including register names, loca- tions, and identifiers. table 2-1. z8 standard register file hex register register address description identi?er ff stack pointer low byte spl fe stack pointer high byte sph fd register pointer rp fc program control flags flags fb interrupt mask register imr fa interrupt request register irq f9 interrupt priority register ipr f8 port 0-1 mode register p01m f7 port 3 mode register p3m f6 port 2 mode register p2m f5 t0 prescaler pre0 f4 timer/counter 0 t0 f3 t1 prescaler pre1 f2 timer/counter 1 t1 f1 timer mode tmr f0 serial i/o sio ef r239 . general-purpose . . registers (gpr) . .. 04 r4 03 port 3 p3 02 port 2 p2 01 port 1 p1 00 port 0 p0 table 2-1. z8 standard register file hex register register address description identi?er z8 microcontrollers address space zilog 2-2 um001600-z8x0599 2.2 z8 mcu standard register file (continued) registers can be accessed as either 8-bit or 16-bit registers using direct, indirect, or indexed addressing. all 236 general-purpose registers can be referenced or modified by any instruction that accesses an 8-bit register, without the need for special instructions. registers accessed as 16 bits are treated as even-odd register pairs (there are 118 valid pairs). in this case, the datas most significant byte (msb) is stored in the even numbered register, while the least significant byte (lsb) goes into the next higher odd numbered register (figure 2-1). by using a logical instruction and a mask, individual bits within registers can be accessed for bit set, bit clear, bit complement, or bit test operations. for example, the in- struction and r15, mask performs a bit clear operation. figure 2-2 shows this example. when instructions are executed, registers are read when defined as sources and written when defined as destina- tions. all general-purpose registers function as accumu- lators, address pointers, index registers, stack areas, or scratch pad memory. 2.2.1 general-purpose registers general-purpose registers (gpr) are undefined after the device is powered up. the registers keep their last value after any reset, as long as the reset occurs in the v cc volt- age-specified operating range. it will not keep its last state from a v lv reset if v cc drops below 1.8v. note: registers in bank e0-ef may only be accessed through the working register and indirect addressing modes. direct access cannot be used because the 4-bit working register address mode already uses the format [e | dst], where dst represents the working register number from 0h to fh. 2.2.2 ram protect the upper portion of the register file address space 80h to efh (excluding the control registers) may be protected from reading and writing. the ram protect bit option is mask-programmable and is selected by the customer when the rom code is submitted. after the mask option is selected, the user activates this feature from the internal rom code to turn off/on the ram protect by loading either a 0 or 1 into the imr register, bit d6. a 1 in d6 enables ram protect. only devices that use registers 80h to efh offer this feature. 2.2.3 working register groups z8 instructions can access 8-bit registers and register pairs (16-bit words) using either 4-bit or 8-bit address fields. 8-bit address fields refer to the actual address of the register. for example, register 58h is accessed by calling upon its 8-bit binary equivalent, 01011000 (58h). with 4-bit addressing, the register file is logically divided into 16 working register groups of 16 registers each, as shown in table 2-2. these 16 registers are known as working registers. a register pointer (one of the control registers, fdh) contains the base address of the active working register group. the high nibble of the register pointer determines the current working register group. when accessing one of the working registers, the 4-bit address of the working register is combined within the up- per four bits (high nibble) of the register pointer, thus forming the 8-bit actual address. figure 2-3 illustrates this operation. since working registers are typically specified by short format instructions, there are fewer bytes of code needed, which reduces execution time. in addition, when processing interrupts or changing tasks, the register pointer speeds context switching. a special set register pointer (srp) instruction sets the contents of the register pointer. figure 2-1. 16-bit register addressing figure 2-2. accessing individual bits (example) msb lsb rn rn+1 n = even address 0 1 0 1 0 0 0 0 r15 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 mask r15 and r15, dfh ;clear bit 5 of working register 15 z8 microcontrollers zilog address space um001600-z8x0599 2-3 table 2-2. working register groups register pointer working actual (fdh) register group registers high nibble (hex) (hex) 1111(b) f f0Cff 1110(b) e e0Cef 1101(b) d d0Cdf 1100(b) c c0Ccf 1011(b) b b0Cbf 1010(b) a a0Caf 1001(b) 9 90C9f 1000(b) 8 80C8f 0111(b) 7 70C7f 0110(b) 6 60C6f 0101(b) 5 50C5f 0100(b) 4 40C4f 0011(b) 3 30C3f 0010(b) 2 20C2f 0001(b) 1 10C1f 0000(b) 0 00C0f figure 2-3. working register addressing examples 0 1 1 1 0 1 1 0 register pointer (fhd), standard register file 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 inc r6 (instruction, short format) actual register address (76h) z8 microcontrollers address space zilog 2-4 um001600-z8x0599 2.2 z8 mcu standard register file (continued) note: the full register file is shown. please refer to the selected device product specification for actual file size. 2.2.4 error conditions registers in the z8 standard register file must be correct- ly used because certain conditions produce inconsistent results and should be avoided. registers f3h and f5h-f9h are write-only registers. if an attempt is made to read these registers, ffh is returned. reading any write-only register will return ffh. when register fdh (register pointer) is read, the least significant four bits (lower nibble) will indicate the current expanded register file bank. (example: 0000 indicates the standard register file, while 1010 indicates expanded register file bank a.) when ports 0 and 1 are defined as address outputs, registers 00h and 01h will return 1s in each address bit location when read. writing to bits that are defined as timer output, serial output, or handshake output will have no effect. the z8 instruction djnz uses any general-purpose working register as a counter. logical instructions such as or and and require that the current contents of the operand be read. they therefore will not function properly on write-only registers. the wdtmr register must be written within the first 60 internal system clocks (sclk) of operation after a reset. figure 2-4. register pointer ff f0 r7 r6 r5 r4 r3 r2 r1 r0 specified working register group r253 i/o ports working register group 1 working register group 0 working register group f ef 80 7f 70 6f 60 5f 50 4f 40 3f 30 2f 20 1f 10 0f 00 the lower nibble of the register file address (provided by the instruction) points to the specified register. the upper nibble of the register file address, provided by the register pointer, specifies the active working-register group. (register pointer) r15 to r0 r15 to r4 r3 to r0 z8 microcontrollers zilog address space um001600-z8x0599 2-5 2.3 z8 expanded register file the standard register file of the z8 has been expanded to form 16 expanded register file (erf) banks (figure 2-5). each erf bank consists of up to 256 registers (the same amount as in the standard register file) that can then be divided into 16 working register groups. this expansion allows for access to additional feature/peripheral control and data registers. note: the fully implemented register file is shown. please refer to the specific product specification for actual register file archi tecture implemented. figure 2-5. expanded register file architecture z8 register file (f) 0f wdtmr expanded register ff 0f 7f f0 00 expanded register file bank (f) (f) 0e reserved (f) 0d reserved (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 0e reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon (0) 0f gpr expanded register file bank (0) (0) 0e gpr (0) 0d gpr (0) 0c gpr (0) 0b gpr (0) 0a gpr (0) 09 gpr (0) 08 gpr (0) 07 gpr (0) 06 gpr (0) 05 gpr (0) 04 gpr (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 (c) 0f reserved expanded register file bank (c) (c) 0e reserved (c) 0d reserved (c) 0c reserved (c) 0b reserved (c) 0a reserved (c) 09 reserved (c) 08 reserved (c) 07 reserved (c) 06 reserved (c) 05 reserved (c) 04 reserved (c) 03 reserved (c) 02 scon (c) 01 rxbuf (c) 00 scomp d7 d6 d5 d4 d3 d2 d1 d0 working register group pointer group pointer register pointer z8 microcontrollers address space zilog 2-6 um001600-z8x0599 2.3 z8 expanded register file (continued) currently, three out of the possible sixteen z8 erf banks have been implemented. erf bank 0, also known as the z8 standard register file, has all 256 bytes defined (fig- ure 2-1). only working register group 0 (register address- es 00h to 0fh) have been defined for erf bank c and erf bank f (table 2-4). all other working register groups in erf banks c and f, as well as the remaining thirteen erf banks, are not implemented. all are reserved for fu- ture use. when an erf bank is selected, register addresses 00h to 0fh access those sixteen erf bank registers C in effect replacing the first sixteen locations of the z8 standard register file. for example, if erf bank c is selected, the z8 standard registers 00h through 0fh are no longer accessible. reg- isters 00h through 0fh are now the 16 registers from erf bank c, working register group 0. no other z8 standard registers are effected since only working register group 0 is implemented in erf bank c. access to the erf is accomplished through the register pointer (fdh). the lower nibble of the register pointer de- termines the erf bank while the upper nibble determines the working register group within the register file (figure 2-6). the value of the lower nibble in the register pointer (fdh) corresponds to the erf bank identification. table 2.3 shows the lower nibble value and the register file assigned to it. figure 2-6. register pointer (fdh) example 0 1 1 1 1 1 0 0 working select erf bank c(h) register group expanded register bank working register group 7(h) table 2-3. erf bank address register pointer (fdh) low nibble hex register file 0000(b) 0 z8 standard register file * 0001(b) 1 expanded register file bank 1 0010(b) 2 expanded register file bank 2 0011(b) 3 expanded register file bank 3 0100(b) 4 expanded register file bank 4 0101(b) 5 expanded register file bank 5 0110(b) 6 expanded register file bank 6 0111(b) 7 expanded register file bank 7 1000(b) 8 expanded register file bank 8 1001(b) 9 expanded register file bank 9 1010(b) a expanded register file bank a 1011(b) b expanded register file bank b 1100(b) c expanded register file bank c 1101(b) d expanded register file bank d 1110(b) e expanded register file bank e 1111(b) f expanded register file bank f note: the z8 standard register file is equivalent to expanded register file bank 0. z8 microcontrollers zilog address space um001600-z8x0599 2-7 the upper nibble of the register pointer selects which group of 16 bytes in the register file, out of the full 256, will be accessed as working registers. for example: (see figure 2-4) since enabling an erf bank (c or f) only changes regis- ter addresses 00h to 0fh, the working register pointer can be used to access either the selected erf bank (bank c or f, working register group 0) or the z8 standard reg- ister file (erf bank 0, working register groups 1 through f). note: when an erf bank other than bank 0 is enabled, the first 16 bytes of the z8 standard register file (i/o ports 0 to 3, groups 4 to f) are no longer accessible (the selected erf bank, registers 00h to 0fh are accessed instead). it is important to re-initialize the register pointer to enable erf bank 0 when these registers are required for use. the spi register is mapped into erf bank c. access is easily done using the following example: please refer to the specific product specification to deter- mine the above registers are implemented. r253 rp = 00h ;erf bank 0, working reg. group 0. r0 = port 0 = 00h r1 = port 1 = 01h r2 = port 2 = 02h r3 = port 3 = 03h r11 = gpr 0bh r15 = gpr 0fh if: r253 rp = 0fh ;erf bank f, working reg. group 0. r0 = pcon = 00h r1 = reserved = 01h r2 = reserved = 02h r11 = smr = 0bh r15 = wdtmr = 0fh if: r253 rp = ffh ;erf bank f, working reg. group f. 00h = pcon r0 = si0 01h= reserved r1 = tmr 02h= reserved ... r2 = t1 0bh = smr ... r15 = spl 0fh = wdtmr ld rp, #0ch ;select erf bank c working ;register group 0 for access. ld r2,#xx ;access scon ld r1, #xx ;access rxbuf ld rp, #00h ;select erf bank 0 so i/o ports ;are again accessible. table 2-4. z8 expanded register file bank layout expanded register file bank erf f(h) pcon, smr, wdt, (00h, 0bh, 0fh), working register group 0 only implemented. e(h) not implemented (reserved) d(h) not implemented (reserved) c(h) spi registers: scomp, rxbuf, scon (00h, 01h, 02h), working register group 0 only implemented. b(h) not implemented (reserved) a(h) not implemented (reserved) 9(h) not implemented (reserved) 8(h) not implemented (reserved) 7(h) not implemented (reserved) 6(h) not implemented (reserved) 5(h) not implemented (reserved) 4(h) not implemented (reserved) 3(h) not implemented (reserved) 2(h) not implemented (reserved) 1(h) not implemented (reserved) 0(h) z8 ports 0, 1, 2, 3, and general-purpose registers 04h to efh, and control registers f0h to ffh. z8 microcontrollers address space zilog 2-8 um001600-z8x0599 2.4 z8 control and peripheral registers 2.4.1 standard z8 registers the standard z8 control registers govern the operation of the cpu. any instruction which references the register file can access these control registers. available control regis- ters are: interrupt priority register (ipr) interrupt mask register (imr) interrupt request register (irq) program control flags (flags) register pointer (rp) stack pointer high-byte (sph) stack pointer low-byte (spl) the z8 uses a 16-bit program counter (pc) to determine the sequence of current program instructions. the pc is not an addressable register. peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on- chip peripherals. any instruction that references the regis- ter file can access the peripheral registers. the peripheral registers are: serial i/o (sio) timer mode (tmr) timer/counter 0 (t0) t0 prescaler (pre0) timer/counter 1 (t1) t1 prescaler (pre1) port 0C1 mode (p01m) port 2 mode (p2m) port 3 mode (p3m) in addition, the four port registers (p0Cp3) are considered to be peripheral registers. 2.4.2 expanded z8 registers the expanded z8 control registers govern the operation of additional features or peripherals. any instruction which references the register file can access these registers. the erf contains the control registers for wdt, port con- trol, serial peripheral interface (spi), and the smr func- tions. figure 2-4 shows the layout of the register banks in the erf. register bank c in the erf consists of the reg- isters for the spi. table 2-5 shows the registers within erf bank c, working register group 0. table 2-5. expanded register file register bank c, wr group 0 register working register function register f reserved r15 e reserved r14 d reserved r13 c reserved r12 b reserved r11 a reserved r10 9 reserved r9 8 reserved r8 7 reserved r7 6 reserved r6 5 reserved r5 4 reserved r4 3 reserved r3 2 spi control (scon) r2 1 spi tx/rx data (roxburgh) r1 0 spi compare (scomp) r0 z8 microcontrollers zilog address space um001600-z8x0599 2-9 working register group 0 in erf bank 0 consists of the registers for z8 general-purpose registers and ports. ta- ble 2-6 shows the registers within this group. working register group 0 in erf bank f consists of the control registers for stop mode, wdt, and port control. table 2-7 shows the registers within this group. the functions and applications of the control and peripher- al registers are described in subsequent sections of this manual. table 2-6. expanded register file bank 0, wr group 0 register working register function register f general-purpose register r15 e general-purpose register r14 d general-purpose register r13 c general-purpose register r12 b general-purpose register r11 a general-purpose register r10 9 general-purpose register r9 8 general-purpose register r8 7 general-purpose register r7 6 general-purpose register r6 5 general-purpose register r5 4 general-purpose register r4 3 port 3 r3 2 port 2 r2 1 port 1 r1 0 port 0 r0 table 2-7. expanded register file bank f, wr group 0 register working register function register f wdtmr r15 e reserved r14 d reserved r13 c reserved r12 b smr r11 a reserved r10 9 reserved r9 8 reserved r8 7 reserved r7 6 reserved r6 5 reserved r5 4 reserved r4 3 reserved r3 2 reserved r2 1 reserved r1 0 pcon r0 z8 microcontrollers address space zilog 2-10 um001600-z8x0599 2.5 program memory the first 12 bytes of program memory are reserved for the interrupt vectors (figure 2-7). these locations contain six 16-bit vectors that correspond to the six available inter- rupts. address 12 up to the maximum rom address con- sists of on-chip mask-programmable rom. see the prod- uct data sheet for the exact program, data, register memory size, and address range available. at addresses outside the internal rom, the z8 executes external pro- gram memory fetches through port 0 and port 1 in ad- dress/data mode for devices with port 0 and port 1 fea- tured. otherwise, the program counter will continue to execute nops up to address ffffh, roll over to 0000h, and continue to fetch executable code (figure 2-7). the internal program memory is one-time programmable (otp) or mask programmable dependent on the specific device. a rom protect feature prevents dumping of the rom contents by inhibiting execution of the ldc, ldci, lde, and ldei instructions to program memory in all modes. rom look-up tables cannot be used with this feature. the rom protect option is mask-programmable, to be se- lected by the customer when the rom code is submitted. for the otp rom, the rom protect option is an otp pro- gramming option. figure 2-7. z8 program memory map interrupt external on - chip 65535 rom and ram rom irq 5 4096 interrupt location of irq 0 irq 0 irq 1 irq 1 irq 2 irq 2 irq 3 irq 3 irq 4 irq 4 irq 5 4095 12 1 2 3 4 5 6 7 8 9 10 11 0 first byte of instruction executed after reset vector (lower byte) vector (upper byte) z8 microcontrollers zilog address space um001600-z8x0599 2-11 2.6 z8 external memory the z8, in some cases, has the capability to access exter- nal program memory with the 16-bit program counter. to access external program memory the z8 offers multi- plexed address/data lines (ad7-ad0) on port 1 and ad- dress lines (a15-a8) on port 0. this feature only applies to devices that offer port 0 and port 1. the maximum external address is ffff. this memory interface is supported by the control lines as (address strobe), ds (data strobe), and r/w (read/write). the origin of the external program memory starts after the last address of the internal rom. figure 2-8 shows an example of external program memory for the z8. 2.6.1 external data memory (/dm) the z8, in some cases, can address up to 60 kbytes of ex- ternal data memory beginning at location 4096. external data memory may be included with, or separated from, the external program memory space. dm , an optional i/o function that can be programmed to appear on pin p34, is used to distinguish between data and program memory space. the state of the dm signal is controlled by the type of instruction being executed. an ldc opcode references program ( dm inactive) memory, and an lde instruction references data ( dm active low) memory. the user must configure port 3 mode register (p3m) bits d3 and d4 for this mode. note: for additional information on using external memory, see chapter 10 of this manual. for exact memory addressing options available, see the device product specification. figure 2-8. external memory map external 65535 memory 4096 not addressable 4095 0 z8 microcontrollers address space zilog 2-12 um001600-z8x0599 2.7 z8 stacks stack operations can occur in either the z8 mcu standard register file or external data memory. under software control, port 0C1 mode register (f8h) selects the stack lo- cation. only the general-purpose registers can be used for the stack when the internal stack is selected. the register pair feh and ffh form the 16-bit stack point- er (sp), that is used for all stack operations. the stack ad- dress is stored with the msb in feh and lsb in ffh (fig- ure 2-9). the stack address is decremented prior to a push opera- tion and incremented after a pop operation. the stack ad- dress always points to the data stored on the top of the stack. the z8 stack is a return stack for call instructions and interrupts, as well as a data stack. during a call instruction, the contents of the pc are saved on the stack. the pc is restored during a return instruction. interrupts cause the contents of the pc and flag registers to be saved on the stack. the iret instruc- tion restores them (figure 2-10). when the z8 is configured for an internal stack (using the z8 standard register file), register ffh serves as the stack pointer. the value in feh is ignored. feh can be used as a general-purpose register in this case only. an overflow or underflow can occur when the stack ad- dress is incremented or decremented during normal stack operations. the programmer must prevent this occurrence or unpredictable operation will result. figure 2-9. stack pointer upper byte lower byte stack pointer high ffh stack pointer low feh figure 2-10. stack operations pcl top of stack stack contents pch pcl pch flags after an interrupt cycle stack contents after a call instruction top of stack um001600-z8x0599 3-1 u ser s m anual c hapter 3 c lock 3.1 clock the z8 mcu ? derives its timing from on-board clock cir- cuitry connected to pins xtal1 and xtal2. the clock cir- cuitry consists of an oscillator, a divide-by-two shaping cir- cuit, and a clock buffer. figure 3-1 illustrates the clock circuitry. the oscillators input is xtal1 and its output is xtal2. the clock can be driven by a crystal, a ceramic resonator, lc clock, rc, or an external clock source. 3.1.1 frequency control in some cases, the z8 has an eprom/otp option or a mask rom option bit to bypass the divide-by-two flip flop in figure 3-1. this feature is used in conjunction with the low emi option. when low emi is selected, the device out- put drive and oscillator drive is reduced to approximately 25 percent of the standard drive and the divide-by-two flip flop is bypassed such that the xtal clock frequency is equal to the internal system clock frequency. in this mode, the maximum frequency of the xtal clock is 4 mhz. please refer to specific product specification for availability of options and output drive characteristics. 3.2 clock control in some cases, the z8 offers software control of the internal system clock via programming register bits. the bits are lo- cated in the stop-mode recovery register in expanded register file bank f, register 0bh. this register selects the clock divide value and determines the mode of stop- mode recovery (figure 3-2). please refer to the specific product specification for availability of this feature/register. figure 3-1. z8 clock circuit ? 2 osc xtal2 internal buffer xtal1 clock figure 3-2. stop-mode recovery register (write-only except d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (f) ob sclk/tclk divide by 16 0 off ** 1 on external clock divide mode by 2 0 = sclk/tclk = xtal/2* 1 = sclk/tclk = xtal * default setting after reset. **default setting after reset and stop-mode recovery. z8 microcontrollers clock zilog 3-2 um001600-z8x0599 3.2.1 sclk/tclk divide-by-16 select (d0) this bit of the smr controls a divide-by-16 prescalar of sclk/tclk. the purpose of this control is to selectively reduce device power consumption during normal proces- sor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). 3.2.2 external clock divide-by-two (d1) this bit can eliminate the oscillator divide-by-two circuitry. when this bit is 0, sclk (system clock) and tclk (timer clock) are equal to the external clock frequency divided by two. the sclk/tclk is equal to the external clock fre- quency when this bit is set (d1 = 1). using this bit, together with d7 of pcon, further helps lower emi (d7 (pcon) = 0, d1 (smr) = 1). the default setting is 0. maximum fre- quency is 4 mhz with d1=1 (figure 3-3). 3.3 oscillator control in some cases, the z8 mcu offers software control of the oscillator to select low emi drive or standard drive. the se- lection is done by programming bit d7 of the port configu- ration (pcon) register (figure 3-4). the pcon register is located in expanded register file bank f, register 00h. a 1 in bit d7 configures the oscillator with standard drive, while a 0 configures the oscillator with low emi drive. this only affects the drive capability of the oscillator and does not affect the relationship of the xtal clock frequency to the internal system clock (sclk). figure 3-3. external clock circuit ? 2 osc external clock d1 (smr) ? 16 d0 (smr) figure 3-4. port con?guration register (pcon) (write-only) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h low emi oscillator 0 low emi 1 standard z8 microcontrollers zilog clock um001600-z8x0599 3-3 3.4 oscillator operation the z8 ? mcu uses a pierce oscillator with an internal feedback (figure 3-5). the advantages of this circuit are low cost, large output signal, low-power level in the crystal, stability with respect to v cc and temperature, and low im- pedances (not disturbed by stray effects). one draw back is the need for high gain in the amplifier to compensate for feedback path losses. the oscillator am- plifies its own noise at start-up until it settles at the frequen- cy that satisfies the gain/phase requirements a x b = 1, where a = v 0 /v i is the gain of the amplifier and b = v i /v 0 is the gain of the feedback element. the total phase shift around the loop is forced to zero (360 degrees). since vin must be in phase with itself, the amplifier/inverter provides 180 degree phase shift and the feedback element is forced to provide the other 180 degrees of phase shift. r1 is a resistive component placed from output to input of the amplifier. the purpose of this feedback is to bias the amplifier in its linear region and to provide the start-up tran- sition. capacitor c 2 combined with the amplifier output resistance provides a small phase shift. it will also provide some at- tenuation of overtones. capacitor c 1 combined with the crystal resistance pro- vides additional phase shift. c 1 and c 2 can affect the start-up time if they increase dra- matically in size. as c 1 and c 2 increase, the start-up time increases until the oscillator reaches a point where it does not start up any more. it is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load ca- pacitors be sized as low as possible without resulting in overtone operation. 3.4.1 layout traces connecting crystal, caps, and the z8 oscillator pins should be as short and wide as possible. this reduces par- asitic inductance and resistance. the components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the z8. the traces from the oscillator pins of the ic and the ground side of the lead caps should be guarded from all other trac- es (clock, v cc , address/data lines, system ground) to re- duce cross talk and noise injection. this is usually accom- plished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a z8 device v ss ground ring around the traces/components. the ground side of the oscillator lead caps should be con- nected to a single trace to the z8 v ss (gnd) pin. it should not be shared with any other system ground trace or com- ponents except at the z8 device v ss pin. this is to prevent differential system ground noise injection into the oscillator (figure 3-6). 3.4.2 indications of an unreliable design there are two major indicators that are used in working de- signs to determine their reliability over full lot and temper- ature variations. they are: start-up time. if start -up time is excessive, or varies wide- ly from unit to unit, there is probably a gain problem. c1/c2 needs to be reduced; the amplifier gain is not adequate at frequency, or crystal rs is too large. output level. the signal at the amplifier output should swing from ground to v cc . this indicates there is adequate gain in the amplifier. as the oscillator starts up, the signal amplitude grows until clipping occurs, at which point the loop gain is effectively reduced to unity and constant oscil- lation is achieved. a signal of less than 2.5 volts peak-to- peak is an indication that low gain may be a problem. ei- ther c 1 or c 2 should be made smaller or a low-resistance crystal should be used. figure 3-5. pierce oscillator with internal feedback circuit xtal2 z8 v ss xtal1 c1 c2 r i v 1 a v 0 z8 microcontrollers clock zilog 3-4 um001600-z8x0599 3.4.3 circuit board design rules the following circuit board design rules are suggested: ? to prevent induced noise the crystal and load capacitors should be physically located as close to the z8? as possible. ? signal lines should not run parallel to the clock oscillator inputs. in particular, the crystal input circuitry and the internal system clock output should be separated as much as possible. ? v cc power lines should be separated from the clock oscillator input circuitry. ? resistivity between xtal1 or xtal2 and the other pins should be greater than 10 mohms. figure 3-6. circuit board design rules xtal2 v ss xtal1 board design example v ss 2 3 1 layout should avoid high lighted areas signal line 20 mm max z8 z8 z8 c1 c2 3 2 clock generator circuit signals a b signal c (connection to system group must be avoided) (parallel traces must be avoided) (top view) z8 microcontrollers zilog clock um001600-z8x0599 3-5 3.4.4 crystals and resonators crystals and ceramic resonators (figure 3-7) should have the following characteristics to ensure proper oscillator op- eration: depending on operation frequency, the oscillator may re- quire the addition of capacitors c1 and c2 (shown in fig- ures 3-7). the capacitance values are dependent on the manufacturers crystal specifications. in most cases, the r d is 0 ohms and r f is infinite. it is de- termined and specified by the crystal/ceramic resonator manufacturer. the r d can be increased to decrease the amount of drive from the oscillator output to the crystal. it can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. the r f can be used to im- prove the start-up of the crystal/ceramic resonator. the z8 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator. it is recommended in figures 3-7, 3-8, and 3-9 to connect the load capacitor ground trace directly to the v ss (gnd) pin of the z8 ? . this ensures that no system noise is inject- ed into the z8 clock. this trace should not be shared with any other components except at the v ss pin of the z8. in some cases, the z8 xtal1 pin also functions as one of the eprom high-voltage mode programming pins or as a special factory test pin. in this case, applying 2 v above v cc on the xtal1 pin will cause the device to enter one of these modes. since this pin accepts high voltages to enter these respective modes, the standard input protection di- ode to v cc is not on xtal1. it is recommended that in ap- plications where the z8 is exposed to much system noise, a diode from xtal1 to v cc be used to prevent accidental enabling of these modes. this diode will not affect the crystal/ceramic resonator operation. please note that a parallel resonant crystal or resonator data sheet will specify a load capacitor value that is the se- ries combination of c 1 and c 2 , including all parasitics (pcb and holder). crystal cut at (crystal only) mode parallel, fundamental mode crystal capacitance <7pf load capacitance 10pf < cl < 220 pf, 15 typical resistance 100 ohms max figure 3-7. crystal/ceramic resonator oscillator figure 3-8. lc clock xtal2 z8 v ss xtal1 c1 c2 r f r d xtal2 z8 v ss xtal1 c1 c2 l figure 3-9. external clock xtal2 z8 v ss xtal1 z8 microcontrollers clock zilog 3-6 um001600-z8x0599 3.5 lc oscillator the z8 oscillator can use a lc network to generate a xtal clock (figure 3-8). the frequency stays stable over v cc and temperature. the oscillation frequency is determined by the equation: where l is the total inductance including parasitics and c t is the total series capacitance including the parasitics. simple series capacitance is calculated using the following equation: sample calculation of capacitance c 1 and c 2 for 5.83 mhz frequency and inductance value of 27 uh: 3.6 rc oscillator in some cases, the z8 has a rc oscillator option. please refer to the specific product specification for availability. the rc oscillator requires a resistor across xtal1 and xtal2. an additional load capacitor is required from the xtal1 input to v ss pin (figure 3-10). 1 frequency = 2 p (lct)1/2 1 = 1 + 1 c t = c 1 c 2 if c 1 = c 2 1 = 2 c t = c 1 c 1 = 2ct 5.83 (10^6) = 1 2 p [2.7 (10 -6 ) ct] 1/2 ct = 27.6 pf thus c 1 = 55.2 pf and c 2 = 55.2 pf. figure 3-10. rc clock xtal2 z8 v ss xtal1 c1 r um001600-z8x0599 4-1 u ser s m anual c hapter 4 r eset w atch -d og t imer 4.1 reset this section describes the z8 mcu ? reset conditions, reset timing, and register initialization procedures. reset is gen- erated by power-on reset (por), reset pin, watch-dog timer (wdt), and stop-mode recovery. a system reset overrides all other operating conditions and puts the z8 into a known state. to initialize the chips inter- nal logic, the reset input must be held low for at least 21 scp or 5 xtal clock cycles. the control register and ports are reset to their default conditions after a por, a reset from the reset pin, or watch-dog timer timeout while in run mode and halt mode. the control registers and ports are not reset to their default conditions after stop- mode recovery and wdt timeout while in stop mode. while reset pin is low, as is output at the internal clock rate, ds is forced low, and r//w remains high. the pro- gram counter is loaded with 000ch. i/o ports and control registers are configured to their default reset state. resetting the z8 does not effect the contents of the general-purpose registers. 4.2 reset pin, internal por operation in some cases, the z8 hardware reset pin initializes the control and peripheral registers, as shown in tables 4-1, 4- 2, 4-3, and 4-4. specific reset values are shown by 1 or 0, while bits whose states are unknown are indicated by the letter u. the tables 4-1, 4-2, 4-3, and 4-4 show the reset conditions for the generic z8. note: the register file reset state is device dependent. please refer to the selected device product specifications for register availability and reset state. z8 microcontrollers resetwatch-dog timer zilog 4-2 um001600-z8x0599 4.2 reset pin, internal por operation (continued) program execution starts 5 to 10 clock cycles after internal reset has returned high. the initial instruction fetch is from location 000ch. figure 4-1 shows reset timing. table 4-1. sample control and peripheral register reset values (erf bank 0) register register bits (hex) name 76543210 comments f0 serial i/o uuuuuuuu f1 timer mode 00000000 counter/timers stopped f2 counter/timer1 uuuuuuuu f3 t1 prescaler uuuuuu00single-p ass count mode, external clock source f4 counter/timer0 uuuuuuuu f5 t0 prescaler uuuuuuu0single-p ass count mode f6 port 2 mode 11111111all i nputs f7 port 3 mode 00000000port 2 open-drain, p33Cp30 input, p37Cp34 output f8 port 0C1 mode 01001101internal stack, normal memory timing f9 interrupt priority uuuuuuuu fa interrupt request 00000000all interrupts cleared fb interrupt mask 0 uuuuuuuinterrupts disabled fc flags uuuuuuuu fd register pointer 00000000 fe stack pointer (high) uuuuuuuu ff stack pointer (low)uuuuuuuu figure 4-1. reset timing first machine cycle t1 clock reset as ds r/w first instruction fetch hold low for 4 sclk periods (minimum) sclk z8 microcontrollers zilog resetwatch-dog timer um001600-z8x0599 4-3 after a reset, the first routine executed should be one that initializes the control registers to the required system con- figuration. the reset pin is the input of a schmitt-triggered circuit. resetting the z8 will initialize port and control registers to their default states. to form the internal reset line, the out- put of the trigger is synchronized with the internal clock. the clock must therefore be running for reset to function. it requires 4 internal system clocks after reset is detected for the z8 to reset the internal circuitry. an internal pull-up, combined with an external capacitor of 1 uf, provides enough time to properly reset the z8 (figure 4-2). in some cases, the z8 has an internal por timer circuit that holds the z8 in reset mode for a duration (t por ) before releasing the device out of reset. on these z8 devices, the internally generated reset drives the reset pin low for the por time. any devices driving the reset line must be open-drained in order to avoid damage from possible conflict during reset conditions. this reset time allows the on-board clock oscil- lator to stabilize. to avoid asynchronous and noisy reset problems, the z8 is equipped with a reset filter of four external clocks (4tpc). if the external reset signal is less than 4tpc in du- ration, no reset occurs. on the fifth clock after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the du- ration of the external reset, whichever is longer. during the reset cycle, ds is held active low while as cycles at a rate of the internal system clock. program execution begins at location 000ch, 5-10 tpc cycles after reset is released. for the internal power-on reset, the reset output time is specified as t por . please refer to specific product specifi- cations for actual values. figure 4-2. example of external power-on reset circuit 1 m f +5v 100 k w /reset 1k to 200 k w 10 v table 4-2. expanded register file bank 0 reset values at reset register register bits (hex) name 7 6 5 4 3 2 1 0 comments 00 port 0 u u u u u u u u input mode, output set to push-pull 01 port 1 u u u u u u u u input mode, output set to push-pull 02 port 2 u u u u u u u u input mode, output set to open drain 03 port 3 1 1 1 1 u u u u standard digital input and output z86l7x family device port p34-p37 = 0 (except z86l70/71/75) all other z8 = 1 04Cef general- purpose registers 04-ef u u u u u u u u unde?ned z8 microcontrollers resetwatch-dog timer zilog 4-4 um001600-z8x0599 4.2 reset pin, internal por operation (continued) table 4-3. sample expanded register file bank c reset values register register bits (hex) name 7 6 5 4 3 2 1 0 comments 00 spi compare 0 0 0 0 0 0 0 0 (scomp) 01 receive buffer u u u u u u u u (rxbuf) 02 spi control u u u u 0 0 0 0 (scon) table 4-4. sample expanded register file bank f reset values register register bits (hex) name 7654321 0 comments 00 port con?guration 1111111 0 comparator outputs disabled on port 3 (pcon) port 0 and 1 output is push-pull port 0, 1, 2, 3, and oscillator with standard output drive 0b stop-mode recovery 0010000 0clock divide by 16 off (smr) xtal divide by 2 por and / or external reset stop delay on stop recovery level is low, stop ?ag is por 0f watch-dog timer mode (wdtmr) u u u 0 1 1 0 1 512 tpc for wdt time out, wdt runs during stop z8 microcontrollers zilog resetwatch-dog timer um001600-z8x0599 4-5 figure 4-3. example of z8 reset with reset pin, wdt, smr, and por 256 tpc 256 512 1024 4096 wdt/por counter chain por tpc tpc tpc tpc + - m wdt tap select clear 18 clock reset reset clk generator 4 clock filter ck clr rc osc. u x internal reset 2.6v operating voltage det. /reset from stop mode recovery source stop delay select (smr) /wdt . vdd xtal wdt select (wdtmr) clk source select (wdtmr) 2.6v ref z8 microcontrollers resetwatch-dog timer zilog 4-6 um001600-z8x0599 4.2 reset pin, internal por operation (continued) figure 4-4. example of z8 reset with wdt, smr, and por 5ms por 5ms 15ms 25ms 100ms wdt/por counter chain clk + - m wdt tap select 4 clock filter clr internal rc osc. u x 2v operating voltage det. from stop mode recovery source stop delay select (smr) wdt . v dd xtal wdt select (wdtmr) clk source select (wdtmr) v lv internal reset clear clk 18 clock reset generator reset z8 microcontrollers zilog resetwatch-dog timer um001600-z8x0599 4-7 4.3 watch-dog timer (wdt) the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. when operating in the run or halt modes, a wdt reset is functionally equiva- lent to a hardware por reset. the wdt is initially enabled by executing the wdt instruction and refreshed on subse- quent executions of the wdt instruction. the wdt cannot be disabled after it has been initially enabled. permanently enabled wdts are always enabled and the wdt instruc- tion is used to refresh it. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the por clock source is selected with bit 4 of the watch-dog timer mode register (wdtmr). in some cases, a z8 that offers the wdt but does not have a wdt- mr register, has a fixed wdt timeout and uses the on board rc oscillator as the only clock source. please refer to specific product specifications for selectability of time- out, wdt during halt and stop modes, source of wdt clock, and availability of the permanently-on wdt option. note: execution of the wdt instruction affects the z (zero), s (sign), and v (overflow) flags. note: the wdtmr register is accessible only during the first 60 processor cycles from the execution of the first instruction after power-on reset, watch-dog reset or a stop-mode recovery. after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr is a write-only register. the wdtmr is located in expanded register file bank f, register 0fh. the control bits are described as follows: wdt time select (d1, d0). bits 0 and 1 control a tap circuit that determines the time-out period. table 4-5 shows the different values that can be obtained. the de- fault value of d1 and d0 are 0 and 1, respectively. wdt during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. a wdt time out dur- ing halt mode will reset control register ports to their de- fault reset conditions. wdt during stop (d3). this bit determines whether or not the wdt is active during stop mode. since xtal clock is stopped during stop mode, unless as specified below, the on-board rc must be selected as the clock source to the por counter. a 1 indicates active during stop. the default is 1. if bits d3 and d4 are both set to 1, the wdt only, is driven by the external clock during stop mode. this feature makes it possible to wake up from stop mode from an internal source. please refer to spe- cific product specifications for conditions of control and port registers when the z8 comes out of stop mode. a wdt time out during stop mode will not reset all control registers. the reset conditions of the ports from stop mode due to wdt time out is the same as if recovered us- ing any of the other stop mode sources. figure 4-5. example of z8 watch-dog timer mode register (write-only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f int 00 5 128 01** 10 256 10 20 512 11 80 2048 wdt rc sys tap* osc clk wdt during stop 0 off 1 on * wdt during halt 0 off 1 on * xtal1/int rc 0 on-board rc * 1 xtal reserved (must be 0) select for wdt * must be 0 for z86c03 reserved (must be 0) ** default setting after reset table 4-5. time-out period of the wdt typical time-out of time-out of d1 d0 internal rc osc sys clock 0 0 5 ms min 256tpc 0 1 15 ms min 512tpc 1 0 25 ms min 1024tpc 1 1 100 ms min 4096tpc notes: tpc = xtal clock cycle the default on reset is, d0 = 1 and d1 = 0. the values given are for vcc = 5.0v. see the device product specification for exact wdtmr time out select options available. z8 microcontrollers resetwatch-dog timer zilog 4-8 um001600-z8x0599 clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc os- cillator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configu- ration of this bit is 0, which selects the internal rc oscilla- tor. bits 5, 6 and 7. these bits are reserved. v cc voltage comparator . an on-board voltage com- parator checks that v cc is at the required level to insure correct operation of the device. reset is globally driven if v cc is below the specified voltage. this feature is available in select rom z8 devices. see the device product specifi- cation for feature availability and operating range. 4.4 power-on-reset (por) a timer circuit clocked by a dedicated on-board rc oscil- lator is used for the power-on reset (por) timer (t por ) function. the por time allows v cc and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status (cold start). 2. stop-mode recovery (if bit 5 of smr=1). 3. wdt timeout. the por time is specified as tpor. on z8 devices that feature a stop-mode recovery register (smr), bit 5 se- lects whether the por timer is used after stop-mode re- covery or by-passed. if bit d5 = 1 then the por timer is used. if bit 5 = 0 then the por timer is by-passed. in this case, the stop-mode recovery source must be held in the recovery state for 5 t p c or 5 crystal clocks to pass the re- set signal internally. this option is used when the clock is provided with an rc/lc clock. see the device product specification for timing details. por (cold start) will always reset the z8 control and port registers to their default condition. if a z8 has a smr reg- ister, the warm start bit will be reset to a 0 to indicate por. figure 4-6. example of z8 with simple smr and por int osc chip por reset p27 (stop mode) (cold start) vbo wdt delay line t por ms 18 clk reset filter xtal osc um001600-z8x0599 5-1 u ser s m anual c hapter 5 i/o p orts 5.1 i/o ports the z8 has up to 32 lines dedicated to input and output. these lines are grouped into four 8-bit ports known as port 0, port 1, port 2, and port 3. port 0 is nibble programmable as input, output, or address. port 1 is byte configurable as input, output, or address/data. port 2 is bit programmable as either inputs or outputs, with or without handshake and spi. port 3 can be programmed to provide timing, serial and parallel input/output, or comparator input/output. all ports have push-pull cmos outputs. in addition, the push-pull outputs of port 2 can be turned off for open-drain operation. 5.1.1 mode registers each port has an associated mode register that deter- mines the ports functions and allows dynamic change in port functions during program execution. port and mode registers are mapped into the standard register file as shown in figure 5-1. because of their close association, port and mode regis- ters are treated like any other general-purpose register. there are no special instructions for port manipulation. any instruction which addresses a register can address the ports. data can be directly accessed in the port register, with no extra moves. 5.1.2 input and output registers each bit of ports 0, 1, and 2, have an input register, an out- put register, associated buffer, and control logic. since there are separate input and output registers associated with each port, writing to bits defined as inputs stores the data in the output register. this data cannot be read as long as the bits are defined as inputs. however, if the bits are reconfigured as outputs, the data stored in the output register is reflected on the output pins and can then be read. this mechanism allows the user to initialize the out- puts prior to driving their loads (figure 5-2). since port inputs are asynchronous to the z8 internal clock, a read operation could occur during an input tran- sition. in this case, the logic level might be uncertain (somewhere between a logic 1 and 0). to eliminate this meta-stable condition, the z8 latches the input data two clock periods prior to the execution of the current instruc- tion. the input register uses these two clock periods to sta- bilize to a legitimate logic level before the instruction reads the data. note: the following sections describe the generic function of the z8 ports. any additional features of the ports such as spi, c/t, and stop-mode recovery are covered in their own section. figure 5-1. i/o ports and mode registers register hex port 3 mode port 2 mode identifier f8h f7h f6h p01m p3m p2m port 3 port 0-1 mode port 2 port 1 port 0 03h 02h 01h 00h p3 p2 p1 p0 z8 microcontrollers i/o ports zilog 5-2 um001600-z8x0599 5.2 port 0 this section deals with only the i/o operation of port 0. the port's external memory interface operation is covered later in this manual. figure 5-2 shows a block diagram of port 0. this diagram also applies to ports 1 and 2. figure 5-2. ports 0, 1, 2 generic block diagram handshake logic internal timing handshake selected rdy//dav /dav/rdy port i/o lines input buffer input register handshake logic output buffer output register output enable internal bus write port read port e 8 8 8 88 8 8 z8 microcontrollers zilog i/o ports um001600-z8x0599 5-3 5.2.1 general i/o mode port 0 can be an 8-bit, bidirectional, cmos or ttl compat- ible i/o port. these eight i/o lines can be configured under software control as a nibble i/o port (p03-p00 input/output and p07-p04 input/output), or as an address port for inter- facing external memory. the input buffers can be schmitt- triggered, level shifted, or a single-trip point buffer and can be nibble programmed. either nibble output can be global- ly programmed as push-pull or open-drain. low emi out- put buffers in some cases can be globally programmed by the software, as an otp program option, or as a rom mask option. in some, the z8 has auto latches hardwired to the inputs. please refer to specific product specifications for exact input/output buffer type features that are avail- able (figures 5-3 and 5-4). figure 5-3. port 0 con?guration with open-drain capability, auto latch, and schmitt-trigger oen port 1 (i/o or ad15 - ad08) handshake controls /dav0 and rdy0 4 z8 (p32 and p35) pin out in 2.3v hysteresis open-drain 1.5 r ? 500 k w auto latch 4 z8 microcontrollers i/o ports zilog 5-4 um001600-z8x0599 5.2 port 0 (continued) 5.2.2 read/write operations in the nibble i/0 mode, port 0 is accessed as general-pur- pose register p0 (00h) with erf bank set to 0. the port is written by specifying p0 as an instruction's destination reg- ister. writing to the port causes data to be stored in the port's output register. the port is read by specifying p0 as the source register of an instruction. when an output nibble is read, data on the external pins is returned. under normal loading conditions this is equivalent to reading the output register. however, for port 0 outputs defined as openCdrain, the data returned is the value forced on the output by the external system. this may not be the same as the data in the output regis- ter. reading a nibble defined as input also returns data on the external pins. however, input bits under handshake control return data latched into the input register via the in- put strobe. the port 0C1 mode resister bits d 1 d 0 and d 7 d 6 are used to configure port 0 nibbles. the lower nibble (p0 0 Cp0 3 ) can be defined as inputs by setting bits d 1 to 0 and d 0 to 1, or as outputs by setting both d 1 and d 0 to 0. likewise, the up- per nibble (p0 4 Cp0 7 ) can be defined as inputs by setting bits d 7 to 0 and d 6 to 1, or as outputs by setting both d 6 and d 7 to 0 (figure 5-5). 5.2.3 handshake operation when used as an i/0 port, port 0 can be placed under handshake control by programming the port 3 mode regis- ter bit d 2 to 1. in this configuration, handshake control lines are dav 0 (p3 2 ) and rdy 0 (p3 5 ) when port 0 is an input port, or rdy 0 (p3 2 ) and dav 0 (p3 5 ) when port 0 is an out- put port. (see figure 5-6) handshake direction is determined by the configuration (input or output) assigned to the port 0 upper nibble, p0 4 Cp0 7 . the lower nibble must have the same i/0 config- uration as the upper nibble to be under handshake control. figure 5-3 illustrates the port 0 upper and lower nibbles and the associated handshake lines of port 3. figure 5-4. port 0 con?guration with ttl level shifter oen pin out in ttl level shifter z8 microcontrollers zilog i/o ports um001600-z8x0599 5-5 5.3 port 1 this section deals only with the i/0 operation. the port's external memory interface operation is discussed later in this manual. figure 5-2 shows a block diagram of port 1. 5.3.1 general i/o mode port 1 can be an 8-bit, bidirectional, cmos or ttl compat- ible port with multiplexed address (a7Ca0) and data (d7Cd0) ports. these eight i/o lines can be byte pro- grammed as inputs or outputs or can be configured under software control as an address/data port for interfacing to external memory. the input buffers can be schmitt-trig- gered, level- shifted, or a single-point buffer. in some cas- es, the output buffers can be globally programmed as ei- ther push-pull or open-drain. low-emi output buffers can be globally programmed by software, as an otp program option, or as a rom mask option. in some cases, the z8can have auto latches hardwired to the inputs. please refer to specific product specifications for exact input/out- put buffer-type features available (figures 5-7 and 5-8). figure 5-5. port 0 i/o operation figure 5-6. port 0 handshake operation d7 d6 d1 d0 (write-only) 01 = input 1x = a 8 - a 11 p0 0 - p0 3 mode 00 = output port 0-1 mode register (p01m) register f8h (p01m) p0 4 - p0 7 mode 00 = output 01 = input 1x = a 12 - a 15 d2 (write-only) 0 p3 2 = input p3 5 = output port 3 mode register (p3m) register f7h 1 p3 2 = dav0/rdy0 p3 5 = rdy0/dav0 z8 microcontrollers i/o ports zilog 5-6 um001600-z8x0599 5.3 port 1 (continued) figure 5-7. port 1 con?guration with open-drain capability, auto latch, and schmitt-trigger oen port 1 (i/o or ad7 - ad0) handshake controls /dav1 and rdy1 8 z8 (p33 and p34) pin out in 2.3v hysteresis open-drain 1.5 r ? 500 k w auto latch z8 microcontrollers zilog i/o ports um001600-z8x0599 5-7 figure 5-8. port 1 con?guration with ttl level shifter oen port 1 (i/o or ad7 - ad0) 8 z8 (p33 and p34) pin out in ttl level shifter handshake controls dav1 and rdy1 z8 microcontrollers i/o ports zilog 5-8 um001600-z8x0599 5.3.2 read/write operations in byte input or byte output mode, the port is accessed as general-purpose register p1 (01h). the port is written by specifying p1 as an instruction's destination register. writ- ing to the port causes data to be stored in the port's output register. the port is read by specifying p1 as the source register of an instruction. when an output is read, data on the exter- nal pins is returned. under normal loading conditions, this is equivalent to reading the output register. however, if port 1 outputs are defined as open-drain, the data returned is the value forced on the output by the external system. this may not be the same as the data in the output regis- ter. when port 1 is defined as an input, reading also re- turns data on the external pins. however, inputs under handshake control return data latched into the input regis- ter via the input strobe. using the port 0-1 mode register, port 1 is configured as an output port by setting bits d 4 and d 3 to 0, or as an input port by setting d 4 to 0 and d 3 to 1 (figure 5-8). 5.3.3 handshake operations when used as an i/o port, port 1 can be placed under handshake control by programming the port 3 mode regis- ter bits d 4 and d 3 both to 1. in this configuration, hand- shake control lines are dav 1 (p3 3 ) and rdy1 (p3 4 ) when port 1 is an input port, or rdy 1 (p3 3 ) and dav1 (p3 4 ) when port 1 is an output port. see figures 5-8 and 5-10. handshake direction is determined by the configuration (input and output) assigned to port 1. for example, if port 1 is an output port then handshake is defined as output. figure 5-9. port 1 i/o operation d4 d3 (f8, write-only) port 0-1 mode register r248 p01m 01 = byte output 10 = ad 0 -ad 7 00 = byte output p1 0 - p1 3 mode as , ds , r /w, 11 = high impedance ad 0 - ad 7 , a 8 - a 11 , a 12 - a 15 figure 5-10. handshake operation d4 d3 (f7, write-only) 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register r247 p3m 10 p33 = input p34 = dm 11 p33 = dav1 / rdy1 p34 = rdy1/ dav1 z8 microcontrollers zilog i/o ports um001600-z8x0599 5-9 5.4 port 2 port 2 is a general-purpose port. figure 5-2 shows a block diagram of port 2. each of its lines can be independently programmed as input or output via the port 2 mode regis- ter (f6h) as seen in figure 5-11. a bit set to a 1 in p2m configures the corresponding bit in port 2 as an input, while a bit set to 0 configures an output line. figure 5-11. port 2 i/o mode con?guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 1 = input port 2 mode 0 = output port 2 mode register (p2m) register f6h figure 5-12. port 2 con?guration with open-drain capability, auto latch, and schmitt-trigger p21-p26 oe pin p21-p26 out p21-p26 in 2.3v hysteresis @ v cc = 5.0v open-drain 1.5 r ? 500 k w auto latch p21-p26 z8 microcontrollers i/o ports zilog 5-10 um001600-z8x0599 5.4 port 2 (continued) figure 5-13. port 2 con?guration with ttl level shifter oen pin out in ttl level shifter open-drain z8 microcontrollers zilog i/o ports um001600-z8x0599 5-11 figure 5-14. port 2 con?guration with open-drain capability, auto latch, schmitt-trigger and spi p27 out pin spi active p27 in 0 soi d0 enable open-drain r ? 500 k w auto latch p27 p20 oe pin p20 out p20 in open-drain r ? 500 k w auto latch p20 spi en spi do p27 oe spi spi do spi standard standard 1 p27 out *spi must be enabled with d0 d2 scon or spi di z8 microcontrollers i/o ports zilog 5-12 um001600-z8x0599 5.4.2 read/write operations port 2 is accessed as general-purpose register p2 (02h). port 2 is written by specifying p2 as an instructions desti- nation register. writing to port 2 causes data to be stored in the output register of port 2, and reflected externally on any bit configured as an output. port 2 is read by specifying p2 as the source register of an instruction. when an output bit is read, data on the external pin is returned. under normal loading conditions, this is equivalent to reading the output register. however, if a bit of port 2 is defined as an open-drain output, the data re- turned is the value forced on the output pin by the external system. this may not be the same as the data in the output register. reading input bits of port 2 also returns data on the external pins. however, inputs under handshake con- trol return data latched into the input register via the input strobe. 5.4.3 handshake operation port 2 can be placed under handshake control by program- ming bit 6 in the port 3 mode register (figure 5-15). in this configuration, port 3 lines p31 and p36 are used as the handshake control lines dav2 and rdy2 for input hand- shake, or rdy2 and dav2 for output handshake. handshake direction is determined by the configuration (input or output) assigned to bit 7 of port 2. only those bits with the same configuration as p27 will be under hand- shake control. figure 5-16 illustrates bit lines of port 2 and the associated handshake lines of port 3. figure 5-15. port 2 handshake con?guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register register f7h 1 p31 = dav2 /rdy2 p36 = rdy2/ dav2 0 p31 = input (t in ) p36 = output (t out ) port 2 handshaking figure 5-16. port 2 handshaking handshake controls dav2 and rdy2 (p3 1 and p3 6 ) p2 7 port 2 (i/o) p2 0 z8 microcontrollers zilog i/o ports um001600-z8x0599 5-13 5.5 port 3 5.5.1 general port i/o port 3 differs structurally from port 0, 1, and 2. port 3 lines are fixed as four inputs (p33Cp30) and four outputs (p37Cp34) port 3 does not have an input and output reg- ister for each bit. instead, all the input lines have one input register, and all the output lines have an output register. port 3 can be a cmos- or ttl- compatible i/o port. under software control, the lines can be configured as special control lines for handshake, comparator inputs, spi con- trol, external memory status, or i/o lines for the on-board serial and timer facilities. figure 5-17 is a generic block di- agram of port 3. the inputs can be schmitt-triggered, level-shifted, or sin- gle-trip point buffered. in some cases, the z8 may have auto latches hardwired on certain port 3 inputs and low- emi capabilities on the outputs. please refer to specific product specifications for exact input/output buffer type features. please refer to the section on counter/timers, stop-mode recovery, serial i/o, comparators, and inter- rupts for more information on the relationships of port 3 to that feature. figure 5-17. port 3 block diagram input buffer input register output buffer output register output register write port read port 4 4 4 4 4 4 4 4 internal bus from timer, handshake logic, or serial i/o to interrupt timer, handshake logic, or serial i/o port output lines p3 4 - p3 7 port input lines p3 0 - p3 3 read port input buffer output buffer output register output buffer data return z8 microcontrollers i/o ports zilog 5-14 um001600-z8x0599 5.5 port 3 (continued) figure 5-18. port 3 con?guration with comparator, auto latch, and schmitt-trigger p31 (an1) r247 = p3m + - irq2, t in , p31 data latch p30 + - 1 = analog 0 = digital d1 r ? 500 k w auto latch port 3 (i/o or control) p30 data latch irq3 z8 p34 p35 p37 p36 p30 p31 p32 p33 irq0, p32 data latch irq1, p33 data latch p32 (an2) p33 (ref) from stop-mode recovery source dig. an. z8 microcontrollers zilog i/o ports um001600-z8x0599 5-15 figure 5-19. port 3 con?guration with comparator pin p37 0 p34, p37 standard output 1 p34, p37 comparator output d0 p37 out pcon p32 ref (p33) + - pin p34 p37 out p32 ref (p33) + - z8 microcontrollers i/o ports zilog 5-16 um001600-z8x0599 5.5 port 3 (continued) figure 5-20. port 3 con?guration with spi and comparator outputs using p34 and p35 spi mstr pin p31 + spi en p34 sk in spi mstr pin p35 spi en ref ss 0 p34, p35 standard output 1 p34, p35 comparator output d0 p34 out pcon p31 ref + - p34 out - spi en sk out mux z8 microcontrollers zilog i/o ports um001600-z8x0599 5-17 5.5.2 read/write operations port 3 is accessed as a general-purpose register p3 (03h). port 3 is written by specifying p3 as an instructions destination register. however, port 3 outputs cannot be written to if they are used for special functions. when writ- ing to port 3, data is stored in the output register. port 3 is read by specifying p3 as the source register of an instruction. when reading from port 3, the data returned is both the data on the input pins and in the output register. 5.5.3 special functions special functions for port 3 are defined by programming the port 3 mode register. by writing 0s in bit 6 through bit 1, lines p37Cp30 are configured as input/output pairs (fig- ure 5-22). table 5-1 shows available functions for port 3. the special functions indicated in the figure are discussed in detail in their corresponding sections in this manual. port 3 input lines p33Cp30 always function as interrupt re- quests regardless of the configuration specified in the port 3 mode register. figure 5-21. port 3 con?guration with ttl level shifter and auto latch pin pin out r ? 500 k w auto latch in ttl level shifter port 3 output configuration port 3 input configuration z8 microcontrollers i/o ports zilog 5-18 um001600-z8x0599 figure 5-22. port 3 mode register con?guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input p35 = output 0 port 2 open-drain 1 port 2 push-pull 00 p33 = input p34 = output 01 p33 = input p34 = /dm port 3 mode register register f7h 10 p33 = input p34 = /dm 0 p31 = input p36 = output 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 party on 1 party off table 5-1. port 3 line functions function line signal inputs p30 input p31 input p32 input p33 input outputs p34 output p35 output p36 output p37 output port 0 handshake input p32 dav0 /rdy0 port 1 handshake input p33 dav1 /rdy1 port 2 handshake input p31 dav2 /rdy2 port 0 handshake output p35 rdy0/ dav0 port 1 handshake output p34 rdy1/ dav1 port 2 handshake output p36 rdy2/ dav2 analog comparator input p31 an1 p32 an2 p33 ref analog comparator output p34 an1-out p35 an2-out p37 an2-out interrupt requests p30 irq3 p31 irq2 p32 irq0 p33 irq1 serial input (uart) p30 di serial output (uart) p37 do spi slave select p35 ss spi clock p34 sk counter/timer p31 t in p36 t out external memory status p34 dm table 5-1. port 3 line functions function line signal z8 microcontrollers zilog i/o ports um001600-z8x0599 5-19 5.6 port handshake when ports 0, 1, and 2 are configured for handshake op- eration, a pair of lines from port 3 are used for handshake controls. the handshake controls are interlocked to prop- erly time asynchronous data transfers between the z8? and a peripheral. one control line (/dav) functions as a strobe from the sender to indicate to the receiver that data is available. the second control line (rdy) acknowledges receipt of the senders data, and indicates when the receiv- er is ready to accept another data transfer. in the input mode, data is latched into the ports input reg- ister by the first /dav signal, and is protected from being overwritten if additional pulses occur on the /dav line. this overwrite protection is maintained until the port data is read. in the output mode, data written to the port is not pro- tected and can be overwritten by the z8 during the hand- shake sequence. to avoid losing data, the software must not overwrite the port until the corresponding interrupt re- quest indicates that the external device has latched the da- ta. the software can always read port 3 output and input handshake lines, but cannot write to the output handshake line. the following is the recommended setup sequence when configuring a port for handshake operation for the first time after a reset: ? load p01m or p2m to configure the port for input/output. ? load p3 to set the output handshake bit to a logic 1. ? load p3m to select the handshake mode for the port. once a data transfer begins, the configuration of the hand- shake lines should not be changed until the handshake is completed. figures 5-23 and 5-24 show detailed operation for the handshake sequence. z8 microcontrollers i/o ports zilog 5-20 um001600-z8x0599 5.6 port handshake (continued) figure 5-23. z8 input handshake valid data (input to z8) state 1. 2 13 45 /dav (output from z8) rdy (input to z8) data on port port 3 output is high, indicating that the i/o device is ready to accept data. state 2. the i/o device puts data on the port and then activates the dav input. this causes the data to be latched . state 3. the z8 forces the ready (rdy) output low, signaling to the i/o device that the data has been latched. state 4. the i/o device returns the dav line high in response to rdy going low. state 5. the z8 rr software must respond to the interrupt request and read the contents of the port in order for the into the port input register and generates an interrupt request. handshake sequence to be completed. the rdy line goes high if and only if the port has been read and dav is high. this returns the interface to its initial state. z8 microcontrollers i/o ports zilog 5-21 um001600-z8x0599 5.6 port handshake (continued) figure 5-24. z8 output handshake valid data (input to z8) state 1. 2 13 45 rdy (output from z8) dav (output from z8) data on port rdy input is high indicating that the i/o device is ready to accept data. state 2. the z8 writes to the port register to initiate a data transfer. writing to the port outputs new data and forces dav low if and only if rdy is high. state 3. the i/o device forces rdy low after latching the data. rdy low causes an interrupt request to be generated. the z8 can write new data responses to rdy going low; however, the data is not output until state 5. state 4. the dav output from the z8 is driven high in response to rdy going low. state 5. the dav goes high, the i/o device is free to raise rdy high thus returning the interface to its initial state. z8 microcontrollers i/o ports zilog 5-22 um001600-z8x0599 in applications requiring a strobed signal instead of the in- terlocked handshake, the z8 mcu can satisfy this require- ment as follows: ? in the strobed input mode, data can be latched in the port input register using the dav input. the data transfer rate must allow enough time for the software to read the port before strobing in the next character. the rdy output is ignored. ? in the strobed output mode, the rdy input should be tied to the dav output. figures 5-25 and 5-26 illustrate the strobed handshake connections. figure 5-25. output strobed handshake on port 2 p3 6 z8 p2 0 - p2 7 p3 1 i/o device dav rdy figure 5-26. input strobed handshake on port 2 z8 p2 0 - p2 7 p3 1 i/o device dav z8 microcontrollers zilog i/o ports um001600-z8x0599 5-23 5.7 i/o port reset conditions 5.7.1 full reset after a hardware reset, watch-dog timer (wdt) reset, or a power-on reset (por), port mode registers p01m, p2m, and p3m are set as shown in figures 5-27 through 5-22. port 2 is configured for input operation on all bits and is set for open-drain (figure 5-29). if push-pull outputs are desired for port 2 outputs, remember to configure them us- ing p3m. please note that a wdt time-out from stop- mode recovery does not do a full reset. certain registers that are not reset after stop-mode recovery will not be re- set. for the condition of the ports after stop-mode recovery, please refer to specific device product specifications. in some cases, the z8 has the p01m, p2m, and p3m control register set back to the default condition after reset while others do not. all special i/o functions of port 3 are inactive, with p33Cp30 set as inputs and p37Cp34 set as outputs (fig- ure 5-29). note: because the types and amounts of i/o vary greatly among the z8 family devices, the user is advised to review the selected device's product specifications for the register default state after reset. figure 5-27. port 0/1 reset 0 1 0 0 1 1 0 1 (write-only) 01 = input 1x = a 8 - a 11 stack selection 0 = external p0 0 - p0 3 mode 00 = output port 0-1 mode register (p01m) register f8h 01 = byte output 1 = internal external memory timing normal = 0 extended = 1 p0 4 - p0 7 mode output = 00 input = 01 a 12 - a 15 = 1x 10 = ad 0 - ad 7 00 = byte output p 10 - p 17 mode a 8 - a 15 , as , ds , r /w 11 = high impedance ad 0 - ad 7, z8 microcontrollers i/o ports zilog 5-24 um001600-z8x0599 figure 5-28. port 2 reset 1 1 1 1 1 1 1 1 (write-only) 1 = input port 2 mode 0 = output port 2 mode register (p2m) register f6h figure 5-29. port 3 mode reset 0 0 0 0 0 0 0 0 (write-only) 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input p35 = output 1 p32 = dav0 /rdy0 p35 = rdy0/ dav0 0 port 2 open-drain 1 port 2 push-pull 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register (p3m) register f7h 10 p33 = input p34 = dm 11 p33 = dav1 /rdy1 p34 = rdy1/ dav1 0 p31 = input p36 = output 1 p32 = dav2/ rdy2 p36 = rdy2/ dav2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 parity off 1 parity on z8 microcontrollers i/o ports zilog 5-25 um001600-z8x0599 5.8 analog comparators (continued) 5.8 analog comparators select z8 devices include two independent on-chip analog comparators. see the device product specification for fea- ture availability and use. port 3, pins p31 and p32 each have a comparator front end. the comparator reference voltage, pin p33, is common to both comparators. in ana- log mode, the p31 and p32 are the positive inputs to the comparators and p33 is the reference voltage supplied to both comparators. in digital mode, pin p33 can be used as a p33 register input or irq1 source. p34, p35, or p37 may output the comparator outputs by software-programming the pcon register bit d0 to 1. 5.8.1 comparator description two on-board comparators can process analog signals on p31 and p32 with reference to the voltage on p33. the an- alog function is enabled by programming the port 3 mode register (p3m bit 1). for interrupt functions during analog mode, p31 and p32 can be programmable as rising, fall- ing, or both edge triggered interrupts (irq register bits 6 and bit 7). note: p33 cannot generate an external interrupt while in this mode. p33 can only generate interrupts in the digital mode. note: port 3 inputs must be in digital mode if port 3 is a stop-mode recovery source. the analog comparator is disabled in stop mode. p31 can be used as t in in analog or digital modes, but it must be referenced to p33, when in analog mode. figure 5-30. port 3 input analog selection d1 (write-only) 0 = digital mode p31, p32, p33 1 = analog mode p31, p32, p33 port 3 mode register (p3m) register f7h figure 5-31. port 3 comparator output selection d0 (write-only) 0 = p34, p35, or p37 standard outputs 1 = p34, p35, or p37 comparator outputs port configuration register (pcon) register 00h erf bank f z8 microcontrollers i/o ports zilog 5-26 um001600-z8x0599 figure 5-32. port con?guration of comparator inputs on p31, p32, and p33 p31 (an1) r247 = p3m + - irq2, t in , p31 data latch p30 + - 1 = analog 0 = digital d1 r ? 500 k w auto latch port 3 (i/o or control) p30 data latch irq3 z8 p34 p35 p37 p36 p30 p31 p32 p33 irq0, p32 data latch irq1, p33 data latch p32 (an2) p33 (ref) from stop-mode recovery source dig. an. z8 microcontrollers zilog i/o ports um001600-z8x0599 5-27 5.8.2 comparator programming example of enabling analog comparator mode. note: x = any binary number example of enabling analog comparator output. figure 5-33. port 3 con?guration pin p37 0 p34, p37 standard output 1 p34, p37 comparator output d0 p37 out pcon p32 ref (p33) + - pin p34 p34 out p31 ref (p33) + - ld p3m, #xxxx xx1xb ld rp, #%0fh ;sets register pointer to ;working register group 0 ;and expanded register ;file bank f. ld r0, #xxxx xxx1b ;enables comparator ;outputs using pcon ;register programming. z8 microcontrollers i/o ports zilog 5-28 um001600-z8x0599 5.8.3 comparator operation after enabling the analog comparator mode, p33 be- comes a common reference input for both comparators. the p33 (ref) is hard wired to the reference inputs to both comparators and cannot be separated. p31 and p32 are always connected to the positive inputs to the compara- tors. p31 is the positive input to comparator an1 while p32 is the positive input to comparator an2. the outputs to comparators an1 and an2 are an1-out and an2-out, re- spectively. the comparator output reflects the relationship between the positive input to the reference input. example: if the voltage on an1 is higher than the voltage on ref then an1-out will be at a high state. if voltage on an2 is lower than the voltage on ref then an2-out will be at a low state. in this example, when the port 3 register is read, bits d1 = 1 and d2 = 0. if the comparator outputs are enabled to come out on p34 and p37, then p34 = 1 and p37 = 0. please note that the previous data stored in p34 and p37 is not disturbed. once the comparator outputs are de-selected the stored values in the p34 and p37 register bits will be reflected on these pins again. 5.8.4 interrupts in the example from section 5.8.3, p32 (an2) will generate an interrupt based on the result of the comparison being low and the interrupt request register (irq fah) having bits d7=0 and d6=0. if irq d7=1 and d6=0 then both p31 and p32 would generate interrupts. 5.8.5 comparator definitions 5.8.5.1 v icr the usable voltage range for both positive inputs and the reference input is called the common mode voltage range (v icr ). the comparator is not guaranteed to work if the in- puts are outside of the v icr range. 5.8.5.2 v offset the absolute value of the voltage between the positive in- put and the reference input required to make the compar- ator output voltage switch is the input offset voltage (v off- set ). if an1 is 3.000v and ref is 3.001v when the comparator output switches states then the voffset = 1mv. 5.8.5.3 i io for cmos voltage comparator inputs, the input offset cur- rent (i io ) is the leakage current of the cmos input gate. 5.8.6 run mode p33 is not available as an interrupt input during analog mode. p31 and p32 are valid interrupt inputs in conjunc- tion with p33 (ref) when in the analog mode. p31 can still be used as t in when the analog mode is se- lected. if comparator outputs are desired to be outputted on the port 3 outputs, please refer to specific products specification for priority of mixing when other special fea- tures are sharing those same port 3 pins. 5.8.7 halt mode the analog comparators are functional during halt mode if the analog mode has been enabled. p31 and p32, in conjunction with p33 (ref) will be able to generate inter- rupts. only p33 cannot generate an interrupt since the p33 input goes directly to the ref input of the comparators and is disconnected from the interrupt sensing circuits. 5.8.8 stop mode the analog comparators are disabled during stop mode so it does not use any current at that time. if p31, p32, or p33 are used as a source for stop-mode recovery, the port 3 digital mode must be selected by setting bit d1=0 in the port 3 mode register. otherwise in stop mode, the p31, p32, and p33 cannot be sensed. if the analog mode was selected when entering stop mode, it will still be en- abled after a valid smr triggered reset. z8 microcontrollers zilog i/o ports um001600-z8x0599 5-29 5.9 open-drain configuration all z8s can configure port 2 to provide open-drain outputs by programming the port 3 mode register (p3m) bit d0=0. other z8s that have a port configuration register (pcon) that can configure port 0 and port 1 to provide open-drain outputs. the pcon register is located in expanded reg- ister file (erf) bank f, register 00h. see figure 5-35. port 1 open-drain (d1). port 1 can be configured as open- drain by resetting this bit (d1=0) or configured as push-pull active by setting this bit (d1=1). the default value is 1. port 0 open drain (d2). port 0 can be configured as open- drain by resetting this bit (d2=0) or configured as push-pull active by setting this bit (d2=1). the default value is 1. 5.10 low emi emission some z8s can be programmed to operate in a low emi emission mode using the port configuration register (pcon). the pcon register allows the oscillator and all i/o ports to be programmed in the low-emi mode inde- pendently. other z8s may offer a rom mask or otp pro- gramming option to configure the z8 ports and oscillator globally to a low-emi mode (where the xtal frequency is set equal to the internal system clock frequency. use of the low emi feature results in: ? the output pre-drivers slew rate reduced to 10 ns (typical). ? low emi output drivers have resistance of 200 ohms (typical). ? low emi oscillator. ? all output drivers are approximately 25 percent of the standard drive. ? internal sclk/tclk = xtal operation limited to a maximum of 4 mhz - 250 ns cycle time, when low emi oscillator is selected and system clock (sclk=xtal, smr reg. bit d1=1). figure 5-34. port 2 con?guration figure 5-35. port con?guration register (pcon) (write-only) d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0= pull-ups active port 2 configuration 1= pull-ups open-drain port 3 mode register register f7h d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h 0 port 1 open drain 1 port 1 push-pull active * 0 p34, p37 standard output* 1 p34, p37 comparator output comparator output port 3 low emi oscillator 0 port 0 open drain 1 port 0 push-pull active * 0 port 0 low emi 1 port 0 standard * 0 port 1 low emi 1 port 1 standard * 0 port 2 low emi 1 port 2 standard * 0 low emi 1 standard * 0 port 3 low emi 1 port 3 standard * * default setting after reset z8 microcontrollers i/o ports zilog 5-30 um001600-z8x0599 for z8s having the pcon register feature, the following bits control the low emi options: ? low emi port 0 (d3). port 0 can be configured as a low emi port by resetting this bit (d3=0) or configured as a standard port by setting this bit (d3=1). the default value is 1. ? low emi port 1 (d4) . port 1 can be configured as a low emi port by resetting this bit (d4=0) or configured as a standard port by setting this bit (d4=1). the default value is 1. ? low emi port 2 (d5). port 2 can be configured as a low emi port by resetting this bit (d5=0) or configured as a standard port by setting this bit (d5=1). the default value is 1. ? low emi port 3 (d6). port 3 can be configured as a low emi port by resetting this bit (d6=0) or configured as a standard port by setting this bit (d6=1). the default value is 1. ? low emi osc (d7). this bit of the pcon register controls the low emi oscillator. a 1 in this location configures the oscillator with standard drive, while a 0 configures the oscillator with low noise drive. the low- emi mode will reduce the drive of the oscillator (osc). the default value is 1. xtal/2 mode is not effected by this bit. note: the maximum external clock frequency is 4 mhz when running in the low emi oscillator mode. please refer to the selected device product specification for availability of the low emi feature and programming options. 5.11 input protection all cmos rom z8s have i/o pins with diode input protec- tion. there is a diode from the i/o pad to v cc and to v ss . see figure 5-36. on cmos otp eprom z8s, the port 3 inputs p31, p32, p33 and the xtal 1 pin have only the input protection di- ode from pad to v ss . see figure 5-37. the high-side input protection diodes were removed on these pins to allow the application of +12.5v during the various otp programming modes. for better noise immunity in applications that are exposed to system emi, a clamping diode to v cc from these pins may be required to prevent entering the otp programming mode or to prevent high voltage from damaging these pins. figure 5-36. diode input protection pin v cc v ss figure 5-37. otp diode input protection pin v ss z8 microcontrollers zilog i/o ports um001600-z8x0599 5-31 5.12 z8 cmos auto latches i/o port bits that are configurable as inputs are protected against open circuit conditions using auto latches. an auto latch is a circuit which, in the event of an open circuit condition, latches the input at a valid cmos level. this in- hibits the tendency of the input transistors to self-bias in the forward active region, thus drawing excessive supply current. a simplified schematic of the cmos z8 i/o circuit is shown in figure 5-38. the operation of the auto latch circuit is straight-forward. assume the input pad is latched at +5v (logic 1). the in- verter g1 inverts the bit, turning the p-channel fet on and the n-channel fet off. the output of the circuit is ef- fectively shorted to v dd , returning +5v to the input. if the pad is then disconnected from the +5v source, the auto latch will hold the input at the previous state. if the device is powered up with the input floating, the state of the auto latch will be at either supply, but which state is unpredict- able. there are four operating conditions which will activate the auto latches. the first, which occurs when the input pin is physically disconnected from any source, is the most obvi- ous. the second occurs when the input is connected to the output of a device with tri-state capability. the auto latch will also activate when the input voltage at the pin is not within 200 microvolts or so of either supply rail. in this case, the circuit will draw current, which is not significant compared to the icc operating current of the de- vice, but will increase i cc2 stop mode current of the de- vice dramatically. the fourth condition occurs when the i/o bit is configured as an output. referring to the output section of figure 5- 38, there are two ways of tri-stating the port pin. the first is by configuring the port as an input, which disables the oe signal turning both transistors off. the second can be achieved in output mode by writing a 1 to the output port, then activating the open drain mode. both transistors are again off, and the port bit is in a high impedance state. the auto latches then pull the input section toward v dd . figure 5-38. simpli?ed cmos z8 i/o circuit open-drain pin v dd oe data out data in auto latch g1 n p v dd n p z8 microcontrollers i/o ports zilog 5-32 um001600-z8x0599 auto latch model: the auto latchs equivalent circuit is shown in figure 5-39. when the input is high, the circuit consists of a resistance rp from v dd (the p-channel transistor in its on state) and a much greater resistance rh to g nd . current iao flows from v dd to the output. when the input is low, the circuit may be modeled as a resistance rp from g nd (the n-chan- nel transistor in the on state) and a much greater resis- tance rh to v dd . current iao now flows from the input to ground. the auto latch is characterized with respect to iao, so the equivalent resistance rp is calculated accord- ing to r p = (v dd -vin)/i ao . the worst case equivalent resis- tance rp (min) may be calculated at the worst case input voltage, v i = v ih (min). design considerations: for circuits in which the auto latch is active, consideration should be given to the loading constraints of the auto latches. for example, with weak values of v in , close to vih (min) or vil (max), pullup or pull-down resistances must be calculated using ref = r/rp. for best case stop mode operation, the inputs should be within 200 mv of the supply rails. in output mode, if a port bit is forced into a tri-state condi- tion, the auto latches will force the pad to v dd . if there is an external pulldown resistor on the pin, the voltage at the pin may not switch to gnd due to the auto latch. as shown in figure 5-40, the equivalent resistance of the auto latch and the external pulldown form a voltage divider, and if the external resistor is large, the voltage developed across it will exceed vil(max). for worst case: v il (max > v dd [rext/(rext+rp)] rext(max) = [(vil(max)/v dd )rp]/[1-(vil(max)/v dd )] for v dd = 5.0v and iao = 5 ua we have vih(max) =0.8v: r ext (max) = (0.16/1m)/(1C0.16) = 190 k ohms. rp increases rapidly with v dd , so increased v dd will relax the requirement on rext. in summary, the cmos z8 auto latch inhibits excessive current drain in z8 devices by latching an open input to ei- ther v dd or gnd. the effect of the auto latch on the i/o characteristics of the device may be modeled by a current iao and a resistor rp, whose value is v dd /iao. figure 5-39. auto latch equivalent circuit v dd data in pin logic 1 a0 pin v dd r p r h r h r p data in logic 0 a0 figure 5-40. effect of pulldown resistors on auto latches v lo v ih (min.) r p r ext um001600-z8x0599 6-1 u ser s m anual c hapter 6 c ounter /t imers 6.1 introduction the z8 mcu ? provides up to two 8-bit counter/timers, t0 and t1, each driven by its own 6-bit prescaler, pre0 and pre1 (figure 6-1). both counter/timers are independent of the processor instruction sequence, that relieves software from time-critical operations such as interval timing or event counting. some mcus offer clock scaling using the smr register. see the device product specification for clock available options. the following description is typical. each counter/timer operates in either single-pass or con- tinuous mode. at the end-of-count, counting either stops or the initial value is reloaded and counting continues. under software control, new values are loaded immediately or when the end-of-count is reached. software also controls the counting mode, how a counter/timer is started or stopped, and its use of i/o lines. both the counter and prescaler registers can be altered while the counter/timer is running. figure 6-1. counter/timer block diagram ? 2 osc d1 (smr) ? 16 d0 (smr) clock ? 4 logic internal clock external clock internal clock gated clock triggered clock t in p31 ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register write read write write read write 6-bit down counter 8-bit down counter pre0 initial value register t0 initial value register t0 current value register ? 2 internal data bus internal data bus t out irq 4 p36 irq 5 z8 microcontrollers counter/timers zilog 6-2 um001600-z8x0599 counter/timers 0 and 1 are driven by a timer clock gener- ated by dividing the internal clock by four. the divide-by- four stage, the 6-bit prescaler, and the 8-bit counter/timer form a synchronous 16-bit divide chain. counter/timer 1 can also be driven by a external input (t in ) using p31. port 3 line p36 can serve as a timer output (t out ) through which t0, t1, or the internal clock can be output. the timer output will toggle at the end-of-count. the counter/timer, prescaler, and associated mode regis- ters are mapped into the register file as shown in figure 6- 2. this allows the software to treat the counter/timers as general-purpose registers, and eliminates the need for special instructions. 6.2 prescalers and counter/timers the prescalers, pre0 (f5h) and pre1 (f3h), each con- sist of an 8-bit register and a 6-bit down-counter as shown in figure 6-1. the prescaler registers are write-only regis- ters. reading the prescalers returns the value ffh. fig- ures 6-3 and 6-4 show the prescaler registers. the six most significant bits (d2-d7) of pre0 or pre1 hold the prescalers count modulo, a value from 1 to 64 decimal. the prescaler registers also contain control bits that specify t0 and t1 counting modes. these bits also in- dicate whether the clock source for t 1 is internal or exter- nal. these control bits will be discussed in detail through- out this chapter. the counter/timer registers, t0 (f4h) and t1 (f2h), each consist of an 8-bit down-counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value (figure 6-1). the initial value can range from 1 to 256 decimal (01h,02h,..,00h). figure 6-5 illustrates the counter/timer registers. figure 6-2. counter/timer register map hex identifiers t0 prescaler f7 timer/counter0 port 3 mode t1 prescaler time/counter1 timer mode f5 f4 f3 f2 f1 dec 247 245 244 243 242 241 figure 6-3. prescaler 0 register figure 6-4. prescaler 1 register figure 6-5. counter / timer 0 and 1 registers d7 d6 d5 d4 d3 d2 d1 d0 (%f5; write-only) 1 = t 0 modulo-n count mode 0 = t 0 single pass prescaler 0 register r245 pre0 01-00 hex) prescaler modulo (range: 1-64 decimal reserved (must be 0) u u u u u u 0 0 (%f3; write-only) 1 = t 1 modulo-n count mode 0 = t 1 single pass prescaler 1 register r243 pre1 01-00 hex) prescaler modulo (range: 1-64 decimal clock source 0 = t 1 external (t in ) 1 = t 1 internal d7 d6 d5 d4 d3 d2 d1 d0 (%f4; write/read only) current value when read initial value when written (range 1-256 decimal, 01-00 hex) counter/timer 0 register r244 t0 (%f2; write/read only) counter/timer 1 register r242 t1 z8 microcontrollers zilog counter/timers um001600-z8x0599 6-3 6.3 counter/timer operation under software control, counter/timers are started and stopped via the timer mode register (tmr,f1h) bits d 0 - d 3 (figure 6-6). each counter/timer is associated with a load bit and an enable count bit. 6.3.1 load and enable count bits setting the load bit (d 0 for t0 and d 2 for t1) transfers the initial value in the prescaler and the counter/timer registers into their respective down-counters. the next internal clock resets bits d 0 and d 2 to 0, readying the load bit for the next load operation. new values may be loaded into the down-counters at any time. if the counter/timer is run- ning, it continues to do so and starts the count over with the new value. therefore, the load bit actually functions as a software re-trigger. the counter timers remain at rest as long as the enable count bits are 0. to enable counting, the enable count bit (d 1 for t0 and d 3 for t1) must be set to 1. counting actu- ally starts when the enable count bit is written by an in- struction. the first decrement occurs four internal clock pe- riods after the enable count bit has been set. if t1 is configured to use an external clock, the first decrement be- gins on the next clock period. the load and enable count bits can be set at the same time. for example, using the instruction: or tmr,#03h sets both d0 and d1 of the tmr. this loads the initial val- ues of pre0 and t0 into their respective counters and starts the count after the m2t2 machine state after the op- erand is fetched (figure 6-7). figure 6-6. timer mode register d3 d2 d1 d0 (% f1; read/write) 0 = disable t 0 count 0 = no function 1 = load t 0 timer mode register r241 tmr 1 = enable t 0 count 0 = no function 1 = load t 1 0 = disable t 1 count 1 = enable t 1 count figure 6-7. starting the count d0 (% f5; write-only) count mode prescaler 0 register r245 pre0 (% f3; write-only) prescaler 1 register r243 pre1 0 = t 1 single pass 1 = t 1 modulo-n figure 6-8. counting modes t1 t2 t3 t1 t2 t3 t1 t2 t3 t1 t2 t3 tmr is written, counter/timer first decrement occurs four clock periods later is loaded #03h is fetched m3 m1 m2 mn z8 microcontrollers counter/timers zilog 6-4 um001600-z8x0599 6.3.2 prescaler operations during counting, the programmed clock source drives the 6-bit prescaler counter. the counter is counted down from the value specified by bits of the corresponding prescaler register, pre0 (bit 7 to bit 2) or pre1 (bit 7 to bit 2). (fig- ures 6-3, 6-4). when the prescaler counter reaches its end-of-count, the initial value is reloaded and counting continues. the prescaler never actually reaches 0. for ex- ample, if the prescaler is set to divide-by-three, the count sequence is: each time the prescaler reaches its end of count a carry is generated, that allows the counter/timer to decrement by one on the next timer clock input. when the counter/timer and the prescaler both reach the end-of-count, an interrupt request is generated (irq4 for t0, irq5 for t1). depend- ing on the counting mode selected, the counter/timer will either come to rest with its value at 00h (single-pass mode) or the initial value will be automatically reloaded and counting will continue (continuous mode). the count- ing modes are controlled by bit 0 of pre0 and bit 0 of pre1. (figure 6-8). a 0, written to this bit configures the counter for single-pass counting mode, while a 1 written to this bit configures the counter for continuous mode. the counter/timer can be stopped at any time by setting the enable count bit to 0, and restarted by setting it back to 1. the counter/timer will continue its count value at the time it was stopped. the current value in the counter/tim- er can be read at any time without affecting the counting operation. note: the prescaler registers are write-only and cannot be read. new initial values can be written to the prescaler or the counter/timer registers at any time. these values will be transferred to their respective down counters on the next load operation. if the counter/timer mode is continuous, the next load occurs on the timer clock following an end-of- count. new initial values should be written before the de- sired load operation, since the prescalers always effective- ly operate in continuous count mode. the time interval (i) until end-of-count, is given by the equation: the internal clock frequency defaults to the external clock source (xtal, ceramic resonator, and others) divided by 2. some z8 microcontrollers allow this divisor to be changed via the stop-mode recovery register. see the product data sheet for available clock divisor options. note that t is equal to eight divided-by-xtal frequency of the external clock source for t1 (external clock mode only). p = the prescaler value (1 C 63) for t 0 and t 1 . the minimum prescaler count of 1 is achieved by loading 000001xx. the maximum prescaler count of 63 is achieved by loading 111111xx. v = the counter/timer value (1-256) minimum duration is achieved by loading 01h (1 prescaler output count), maximum duration is achieved by loading 00h (256 prescaler outputs counts). the prescaler and counter/timer are true divide-by-n counters. 3C2C1C3C2C1C3C2C1C3... i = t x p x v in which: t = four times the internal clock period. z8 microcontrollers zilog counter/timers um001600-z8x0599 6-5 6.4 t out modes the timer mode register tmr (f1h) (figure 6-9), is used in conjunction with the port 3 mode register p3m (f7h) (figure 6-10) to configure p36 for t out operation for t0 and t1. in order for t out to function, p36 must be defined as an output line by setting p3m bit 5 to 0. output is con- trolled by one of the counter/timers (t0 or t1) or the inter- nal clock. figure 6-9. timer mode register (t out operation) d7 d6 d3 d0 (read/write) 0 = no function 1 = load t 0 timer mode register (tmr) register f1hr t out modes: 0 = disable t 1 count 1 = enable t 1 count t out off = 00 t 0 out = 01 t 1 out = 10 internal clock out = 11 figure 6-10. port 3 mode register (t out operation) d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register (p3m) register f7h 0 p31 = input (t in ) p36 = output (t out ) 1 p31 = dav2 /rdy2 p36 = rdy2/ dav2 z8 microcontrollers counter/timers zilog 6-6 um001600-z8x0599 6.4 t out modes (continued) the counter/timer to be output is selected by tmr bit 7 and bit 6. t0 is selected to drive the t out line by setting bit 7 to 0 and bit 6 to 1. likewise, t1 is selected by setting bit 7 and bit 6 to 1 and 0, respectively. the counter/timer t out mode is turned off by setting tmr bit and bit 6 both to 0, freeing p36 to be a data output line. t out is initialized to a logic 1 whenever the tmr load bit (bit 0 for t0 or bit 1 for t2) is set to 1. the t out configura- tion timer load, and timer enable count bits for the counter/timer driving the t out pin can be set at the same time. for example, using the instruction: or tmr,#43h ? configures t0 to drive the t out pin (p36). ? sets the p36 t out pin to a logic 1 level. ? loads the initial pre0 and t0 levels into their respective counters and starts the counter after the m2t2 machine state after the operand is fetched. at end-of-count, the interrupt request line (irq4 or irq5), clocks a toggle flip-flop. the output of this flip-flop drives the t out line, p36. in all cases, when the selected counter/timer reaches its end-of-count, t out toggles to its opposite state (figure 6-11). if, for example, the counter/timer is in continuous counting mode, tout will have a 50 percent duty cycle output. this duty cycle can easily be controlled by varying the initial values after each end-of-count. the internal clock can be selected as output instead of t0 or t1 by setting tmr bit 7 and bit 6 both to 1. the internal clock (xtal frequency/2) is then directly output on p36 (figure 6-12). while programmed as t out , p36 cannot be modified by a write to port register p3. however, the z8 ? software can examine the p36 current output by reading the port regis- ter. figure 6-11. t0 and t1 output through t out ? 2 p3 6 t out tmr d 7 - d 6 = 01 irq 4 (t0 end-of-count) irq 5 (t1 end-of-count) tmr d 7 - d 6 = 10 figure 6-12. internal clock output through t out osc ? 2 p3 6 t out internal tmr d 6 clock tmr d 7 z8 microcontrollers zilog counter/timers um001600-z8x0599 6-7 6.5 t in modes the timer mode register tmr (f1h) (figure 6-13) is used in conjunction with the prescaler register pre1 (f3h) (figure 6-14) to configure p31 as t in . t in is used in con- junction with t1 in one of four modes: ? external clock input ? gated internal clock ? triggered internal clock ? retriggerable internal clock note: the t in mode is restricted for use with timer 1 only. to enable the t in mode selected (via tmr bits 4- 5), bit 1 of pre1 must be set to 0. the counter/timer clock source must be configured for ex- ternal by setting the pre1 register bit 2 to 1. the timer mode register bit 5 and bit 4 can then be used to select the desired t in operation. for t1 to start counting as a result of a t in input, the en- able count bit (bit 3 in tmr) must be set to 1. when using t in as an external clock or a gate input, the initial values must be loaded into the down counters by setting the load bit (bit 2 in tmr) to a 1 before counting begins. in the de- scriptions of t in that follow, it is assumed the programmer has performed these operations. initial values are auto- matically loaded in trigger and retrigger modes so soft- ware loading is unnecessary. figure 6-13. timer mode register (t in operation) d5 d4 (read/write) timer mode register (tmr) register f1h (retriggerable) (non-retriggerable) trigger input = 10 t in = modes: external clock input = 00 gate input = 01 trigger input = 11 figure 6-14. prescaler 1 register (t in operation) d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 1 = t 1 internal disable t in mode clock source 0 = t 1 external enable t in mode prescaler 1 register (pre1) register f3h z8 microcontrollers counter/timers zilog 6-8 um001600-z8x0599 it is suggested that p31 be configured as an input line by setting p3m register bit 5 to 0, although t in is still function- al if p31 is configured as a handshake input. each high-to-low transition on t in generates an interrupt request irq2, regardless of the selected t in mode or the enabled/disabled state of t1. irq2 must therefore be masked or enabled according to the needs of the applica- tion. 6.5.1 external clock input mode the t in external clock input mode (tmr bit 5 and bit 4 both set to 0) supports counting of external events, where an event is considered to be a high-to-low transition on t in (figure 6-15). note: see the product data sheet for the minimum allowed t in external clock input period (t p t in ). figure 6-15. external clock input mode d p3 1 internal irq 2 tmr t in clock d pre1 t1 irq 5 d 5 - d 4 = 00 clock z8 microcontrollers zilog counter/timers um001600-z8x0599 6-9 6.5.2 gated internal clock mode the t in gated internal clock mode (tmr bit 5 and bit 4 set to 0 and 1 respectively) measures the duration of an exter- nal event. in this mode, the t1 prescaler is driven by the internal timer clock, gated by a high level on t in (figure 6- 16). t1 counts while t in is high and stops counting while t in is low. interrupt request irq2 is generated on the high-to-low transition of t in signalling the end of the gate input. interrupt request irq5 is generated if t1 reaches its end-of-count. figure 6-16. gated clock input mode osc ? 2 ? 4 d d pre1 p3 1 t1 irq 2 t in irq 5 gate internal tmr d 5 - d 4 = 01 clock z8 microcontrollers counter/timers zilog 6-10 um001600-z8x0599 6.5.3 triggered input mode the t in triggered input mode (tmr bits 5 and 4 are set to 1 and 0, respectively) causes t1 to start counting as the result of an external event (figure 6-17). t1 is then loaded and clocked by the internal timer clock following the first high-to-low transition on the t in input. subsequent t in transitions do not affect t1. in the single-pass mode, the enable bit is reset whenever t1 reaches its end-of-count. further t in transitions will have no effect on t1 until soft- ware sets the enable count bit again. in continuous mode, once t1 is triggered counting continues until software re- sets the enable count bit. interrupt request irq5 is gener- ated when t1 reaches its end-of-count. figure 6-17. triggered clock mode osc ? 2 ? 4 d d pre1 tmr p3 1 t1 irq 2 t in irq 5 trigger d 5 - d 4 = 11 internal tmr d 5 = 1 clock edge trigger z8 microcontrollers zilog counter/timers um001600-z8x0599 6-11 6.5.4 retriggerable input mode the t in retriggerable input mode (tmr bits 5 and 4 are set to 1) causes t1 to load and start counting on every oc- currence of a high-to-low transition on t in (figure 6-17). interrupt request irq5 will be generated if the pro- grammed time interval (determined by t1 prescaler and counter/timer register initial values) has elapsed since the last high-to-low transition on t in . in single-pass mode, the end-of-count resets the enable count bit. subsequent t in transitions will not cause t1 to load and start counting until software sets the enable count bit again. in continu- ous mode, counting continues once t1 is triggered until software resets the enable count bit. when enabled, each high-to-low t in transition causes t1 to reload and restart counting. interrupt request irq5 is generated on every end-of-count. 6.6 cascading counter/timers for some applications, it may be necessary to measure a time interval greater than a single counter/timer can mea- sure. in this case, t in and t out can be used to cascade t0 and t1 as a single unit (figure 6-18). t0 should be config- ured to operate in continuous mode and to drive t out . t in should be configured as an external clock input to t1 and wired back to t out . on every other t0 end-of-count, t out undergoes a high-to-low transition that causes t1 to count. t1 can operate in either single-pass or continuous mode. when the t1 end-of-count is reached, interrupt request irq5 is generated. interrupt requests irq2 (t in high-to- low transitions) and irq4 (t0 end-of-count) are also gen- erated but are most likely of no importance in this configu- ration and should be disabled. figure 6-18. cascaded counter / timers osc ? 2 ? 4 pre0 t0 ? 2 pre1 irq 2 p3 1 p3 6 t1 irq 4 t out t in irq 5 z8 microcontrollers counter/timers zilog 6-12 um001600-z8x0599 6.7 reset conditions after a hardware reset, the counter/timers are disabled and the contents of the counter/timer and prescaler regis- ters are undefined. however, the counting modes are con- figured for single-pass and the t1 clock source is set for external. t in is set for external clock mode, and the t out mode is off. figures 6-19 through 6-22 show the binary reset values of the prescaler, counter/timer, and timer mode registers. figure 6-19. counter / timer reset figure 6-20. prescaler 1 register reset u u u u u u u u (%f4; write/read only) current value when read initial value when written (range 1-256 decimal, 01-00 hex) counter/timer 0 register r244 t0 (%f2; write/read only) counter/timer 1 register r242 t1 u u u u u u 0 0 (%f3; write-only) 1 = t 1 modulo-n count mode 0 = t 1 single pass prescaler 1 register r243 pre1 01-00 hex) prescaler modulo (range: 1-64 decimal clock source 0 = t 1 external (t in ) 1 = t 1 internal figure 6-21. prescaler 0 reset figure 6-22. timer mode register reset u u u u u u u 0 (%f5; write-only) 1 = t 0 modulo-n count mode 0 = t 0 single pass prescaler 0 register r245 pre0 01-00 hex) prescaler modulo (range: 1-64 decimal reserved (must be 0) 0 0 0 0 0 0 0 0 (% f1; read/write) 0 = disable t 0 count 0 = no function 1 = load t 0 timer mode register r241 tmr 1 = enable t 0 count (retriggerable) t out modes: (non-retriggerable) trigger input = 10 t in = modes: external clock input = 00 gate input = 01 0 = no function 1 = load t 1 0 = disable t 1 count 1 = enable t 1 count t out off = 00 t 0 out = 01 t 1 out = 10 internal clock out = 11 trigger input = 11 um001600-z8x0599 7-1 u ser s m anual c hapter 7 i nterrupts 7.1 introduction the z8 mcu ? allows 6 different interrupts from a variety of sources; up to four external inputs, the on-chip counter/timer(s), software, and serial i/o peripherals. these interrupts can be masked and their priorities set by using the interrupt mask and the interrupt priority regis- ters. all six interrupts can be globally disabled by resetting the master interrupt enable, bit 7 in the interrupt mask register, with a disable interrupt (di) instruction. interrupts are globally enabled by setting bit 7 with an enable inter- rupt (ei) instruction. there are three interrupt control registers: the interrupt re- quest register (irq), the interrupt mask register (imr), and the interrupt priority register (ipr). figure 7-1 shows addresses and identifiers for the interrupt control registers. figure 7-2 is a block diagram showing the interrupt mask and interrupt priority logic. the z8 mcu family supports both vectored and polled in- terrupt handling. details on vectored and polled interrupts can be found later in this chapter. note: see the selected z8 mcu's product specification for the exact interrupt sources supported. figure 7-1. interrupt control registers register hex interrupt mask interrupt request interrupt priority identifier fbh fah f9h imr irq ipr figure 7-2. interrupt block diagram irq irq 0 - irq 5 vector select interrupt request imr ipr priority logic 6 global interrupt enable 6 z8 microcontrollers interrupts zilog 7-2 um001600-z8x0599 7.2 interrupt sources table 7-1 presents the interrupt types, sources, and vectors available in the z8 family of processors. 7.2.1 external interrupt sources external sources involve interrupt request lines irq0- irq3. irq0, irq1, and irq2 can be generated by a tran- sition on the corresponding port 3 pin (p32, p33, and p31 correspond to irq0, irq1, and irq2, respectively). figure 7-3 is a block diagram for interrupt sources irq0, irq1, and irq2. note: the interrupt sources and trigger conditions are device dependent. see the device product specification to determine available sources (internal and external), triggering edge options, and exact programming details. table 7-1. interrupt types, sources, and vectors * name sources vector location comments irq 0 dav 0 , irq 0 , comparator 0,1 external (p3 2 ), edge triggered; internal irq 1 dav 1 , irq 1 2,3 external (p3 3 ), edge triggered; internal irq 2 dav 2 , irq 2 , tin, comparator 4,5 external (p3 1 ), edge triggered; internal irq 3 6,7 external (p3 0 ) or (p3 2 ), edge triggered; internal serial in 6,7 internal t 0 8,9 internal serial out 8,9 internal irq 5 t 1 10,11 internal figure 7-3. interrupt sources irq0-irq2 block diagram p3 n irq m system clock multiple input n = 2, 3, 1 and signal q s r conditioning circuitry m = 0,1,2 (internal) q d q d z8 microcontrollers zilog interrupts um001600-z8x0599 7-3 when the port 3 pin (p31, p32, or p33) transitions, the first flip-flop is set. the next two flip-flops synchronize the re- quest to the internal clock and delay it by two internal clock periods. the output of the last flip-flop (irq0, irq1, or irq2) goes to the corresponding interrupt request regis- ter. irq3 can be generated from an external source only if se- rial in is not enabled. otherwise, its source is internal. the external request is generated by a low edge signal on p30 as shown in figure 7-4. again, the external request is syn- chronized and delayed before reaching irq3. some z8 products replace p30 with p32 as the external source for irq3. in this case, irq3 interrupt generation follows the logic as illustrated in figure 7-3. note: although interrupts are edge triggered, minimum interrupt request low and high times must be observed for proper operation. see the device product specification for exact timing requirements on external interrupt requests (t w il, t w ih). 7.2.2 internal interrupt sources internal sources involve interrupt requests irq0, irq2, irq3, irq4, and irq5. internal sources are ored with the external sources, so either an internal or external source can trigger the interrupt. internal interrupt sources and trig- ger conditions are device dependent. see the device product specification to determine avail- able sources, triggering edge options, and exact program- ming details. for more details on the internal interrupt sources, refer to the chapters describing the counter/tim- er, i/o ports, and serial i/o. figure 7-4. interrupt source irq3 block diagram q pin d serial receiver p3m 6 irq 3 clock irq 3 irq 3 external source (irq 3 serial in) internal source d q z8 microcontrollers interrupts zilog 7-4 um001600-z8x0599 7.3 interrupt request register logic and timing figure 7-5 shows the logic diagram for the interrupt re- quest (irq) register. the leading edge of the request will set the first flip-flop, that will remain set until interrupt re- quests are sampled. requests are sampled internally during the last clock cycle before an opcode fetch (figure 7-6). external requests are sampled two internal clocks earlier, due to the synchroniz- ing flip-flops shown in figures 7-3 and 7-4. at sample time the request is transferred to the second flip- flop in figure 7-5, that drives the interrupt mask and priority logic. when an interrupt cycle occurs, this flip-flop will be reset only for the highest priority level that is enabled. the user has direct access to the second flip-flop by read- ing and writing the irq register. irq is read by specifying it as the source register of an instruction and written by specifying it as the destination register. figure 7-5. irq register logic q s from to mask irq 0 - irq 5 r q r priority logic and priority logic sample clock figure 7-6. interrupt request timing t1 t2 t3 t1 t2 t3 t1 t2 t3 external interrupt interrupt request sampled internally request sampled mn m1 m2 z8 microcontrollers zilog interrupts um001600-z8x0599 7-5 7.4 interrupt initialization after reset, all interrupts are disabled and must be initial- ized before vectored or polled interrupt processing can be- gin. the interrupt priority register (ipr), interrupt mask register (imr), and interrupt request register (irq) must be initialized, in that order, to start the interrupt process. 7.4.1 interrupt priority register (ipr) initial- ization ipr (figure 7-7) is a write-only register that sets priorities for the vectored interrupts in order to resolve simultaneous interrupt requests. (there are 48 sequence possibilities for interrupts.) the six interrupt levels irq0-irq5 are divided into three groups of two interrupt requests each. one group contains irq3 and irq5. the second group con- tains irq0 and irq2, while the third group contains irq1 and irq4. priorities can be set both within and between groups as shown in tables 7-2 and 7-3. bits 1, 2, and 5 define the pri- ority of the individual members within the three groups. bits 0, 3, and 4 are encoded to define six priority orders be- tween the three groups. bits 6 and 7 are reserved. figure 7-7. interrupt priority register d7 d6 d5 d4 d3 d2 d1 d0 (write-only) interrupt priority register (ipr) register f9h interrupt group priority bits priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved 0 = irq1 > irq4 1 = irq4 > irq1 group c (irq1 and irq4 priority) reserved (must be 0) 0 = irq2 > irq0 1 = irq0 > irq2 group b (irq0 and irq2 priority) 0 = irq5 > irq3 1 = irq3 > irq5 group a (irq3 and irq5 priority) table 7-2. interrupt priority priority group bit value highest lowest c bit 1 0 irq1 irq4 1 irq4 irq1 b bit 2 0 irq2 irq0 1 irq0 irq2 a bit 5 0 irq5 irq3 1 irq3 irq5 table 7-3. interrupt group priority bit pattern group priority bit 4 bit 3 bit 0 high medium low 0 0 0 not used 00 1c a b 01 0a b c 01 1a c b 10 0b c a 10 1c b a 11 0b a c 1 1 1 not used z8 microcontrollers interrupts zilog 7-6 um001600-z8x0599 7.4 interrupt initialization (continued) 7.4.2 interrupt mask register (imr) initialization imr individually or globally enables or disables the six in- terrupt requests (figure 7-8). when bit 0 to bit 5 are set to 1, the corresponding interrupt requests are enabled. bit 7 is the master enable and must be set before any of the in- dividual interrupt requests can be recognized. resetting bit 7 globally disables all the interrupt requests. bit 7 is set and reset by the ei and di instructions. it is automatically reset during an interrupt service routine and set following the execution of an interrupt return (iret) instruction. note: bit 7 must be reset by the di instruction before the contents of the interrupt mask register or the interrupt priority register are changed except: ? immediately after a hardware reset. ? immediately after executing an interrupt service routine and before imr bit 7 has been set by any instruction. note: the ram protect option is selected at rom mask submission time or at eprom program time. if not selected or not an available option, this bit is reserved and must be 0. figure 7-8. interrupt mask register d7 d6 d5 d4 d3 d2 d1 d0 (read/write) interrupt request register (imr) register fbh 0 = disables irq0 1 = enables irq0 0 = disables irq1 1 = enables irq1 0 = disables irq2 1 = enables irq2 0 = disables irq3 1 = enables irq3 0 = disables irq4 1 = enables irq4 0 = disables irq5 1 = enables irq5 0 = disables ram protect 1 = enables ram protect 0 = disables interrupt 1 = enables interrupt z8 microcontrollers zilog interrupts um001600-z8x0599 7-7 7.4.3 interrupt request (irq) register initialization irq (figure 7-9) is a read/write register that stores the in- terrupt requests for both vectored and polled interrupts. when an interrupt is made on any of the six, the corre- sponding bit position in the register is set to 1. bit 0 to bit 5 are assigned to interrupt requests irq0 to irq5, respec- tively. whenever power-on reset (por) is executed, the irq resister is reset to 00h and disabled. before the irq reg- ister will accept requests, it must be enabled by executing an enable interrupts (ei) instruction. note: setting the global interrupt enable bit in the interrupt mask register (imr, bit 7) will not enable the irq. execution of the ei instruction is required (figure 7- 10). for polled processing, irq must still be initialized by an ei instruction. to properly initialize the irq register, the following code is provided: note: irq is always cleared to 00hex and is read only until the 1st ei instruction which enables the irq to be read/write. clr imr //make sure disabled vectored interrupts ei //enable irq register otherwise read only. //not needed if interrupts were previously enabled. di //disable interrupt heading. figure 7-9. interrupt request register d7 d6 d5 d4 d3 d2 d1 d0 (read/write) reserved /int edge select interrupt request register (irq) register fah 0 = irq0 reset 1 = irq0 set 0 = irq1 reset 1 = irq1 set 0 = irq2 reset 1 = irq2 set 0 = irq3 reset 1 = irq3 set 0 = irq4 reset 1 = irq4 set 0 = irq5 reset 1 = irq5 set z8 microcontrollers interrupts zilog 7-8 um001600-z8x0599 7.4 interrupt initialization (continued) imr is cleared before the irq enabling sequence to insure no unexpected interrupts occur when ei is executed. this code sequence should be executed prior to programming the application required values for ipr and imr. note: irq bits 6 and 7 are device dependent. when reserved, the bits are not used and will return a 0 when read. when used as the interrupt edge select bits, the configuration options are as show in table 7-4. the proper sequence for programming the interrupt edge select bits is (assumes ipr and imr have been previously initialized): table 7-4. irq register con?guration irq interrupt edge d7 d6 p31 p32 00ff 01fr 10rf 11r/fr/f notes: f = falling edge r = rising edge di ;inhibit all interrupts until input edges are con?gured or irq,#xx 000000b ;con?gure interrupt do not disturb edges as needed - irq 0-5. ei ;re-enable interrupts. figure 7-10. irq reset functional logic diagram s interrupt request register (irq, fah) reset el instruction por r z8 microcontrollers zilog interrupts um001600-z8x0599 7-9 7.5 irq software interrupt generation irq can be used to generate software interrupts by spec- ifying irq as the destination of any instruction referencing the z8 standard register file. these software interrupts (swi) are controlled in the same manner as hardware gen- erated requests (in other words, the ipr and the imr con- trol the priority and enabling of each swi level). to generate a swi, the desired request bit in the irq is set as follows: where the immediate data, number, has a 1 in the bit po- sition corresponding to the level of the swi desired. for example, if an swi is desired on irq5, number would have a 1 in bit 5: with this instruction, if the interrupt system is globally en- abled, irq5 is enabled, and there are no higher priority pending requests, control is transferred to the service rou- tine pointed to by the irq5 vector. 7.6 vectored processing each z8 interrupt level has its own vector. when an inter- rupt occurs, control passes to the service routine pointed to by the interrupts vector location in program memory. the sequence of events for vectored interrupts is as fol- lows: ? push pc low byte on stack ? push pc high byte on stack ? push flags on stack ? fetch high byte of vector ? fetch low byte of vector ? branch to service routine specified by vector figures 7-11 and 7-12 show the vectored interrupt opera- tion. orirq, #number or irq, #00100000b figure 7-11. effects of an interrupt on the stack sp top of stack pc low byte pc high byte flags sp and stack after an interrupt sp sp and stack before an interrupt z8 microcontrollers interrupts zilog 7-10 um001600-z8x0599 7.6 vectored processing (continued) figure 7-12. interrupt vectoring pc high byte flags vector selected 000ch program memory interrupt service routine by priority logic interrupt vector table 0000h xxffh z8 microcontrollers zilog interrupts um001600-z8x0599 7-11 7.6.1 vectored interrupt cycle timing the interrupt acknowledge cycle time is 24 internal clock cycles and is shown in figure 7-13. in addition, two internal clock cycles are required for the synchronizing flip-flops. the maximum interrupt recognition time is equal to the number of clock cycles required for the longest executing instruction present in the user program (assumes worst case condition of interrupt sampling, figure 7-6, just prior to the interrupt occurrence). to calculate the worst case in- terrupt latency (maximum time required from interrupt gen- eration to fetch of the first instruction of the interrupt ser- vice routine), sum these components: worst case interrupt latency ? 24 int clk (interrupt ac- knowledge time) + # t p c of longest instruction present in the user's application program + 2t p c (internal synchroni- zation time). figure 7-13. z8 interrupt acknowledge timing pc for stack external only pc+1 pc pcl sp-1 sp-2 pch sp-3 flags vect vect+1 even vector address odd vector address op code (discarded) vecth vectl first instruction of interrupt service routine for stack external only a0-a7 in internal clock /as /ds a0-a7 out m3 m1 m2 m1 m2 stack push fetch vector high fetch vector low stack push stack push r/w z8 microcontrollers interrupts zilog 7-12 um001600-z8x0599 7.6.2 nesting of vectored interrupts nesting of vectored interrupts allows higher priority re- quests to interrupt a lower priority request. to initiate vec- tored interrupt nesting, do the following during the interrupt service routine: ? push the old imr on the stack. ? load imr with a new mask to disable lower priority interrupts. ? execute ei instruction. ? proceed with interrupt processing. ? after processing is complete, execute di instruction. ? restore the imr to its original value by returning the previous mask from the stack. ? execute iret. depending on the application, some simplification of the above procedure may be possible. 7.7 polled processing polled interrupt processing is supported by masking off the irq to be polled. this is accomplished by clearing the cor- responding bits in the imr. to enable any interrupt, first the interrupt mechanism must be engaged with an ei instruction. if only polled interrupts are to be serviced, execute: ei ;enable interrupt mechanism di ;disable vectored interrupts. to initiate polled processing, check the bits of interest in the irq using the test under mask (tm) instruction. if the bit is set, call or branch to the service routine. the service routine services the request, resets its request bit in the irq, and branches or returns back to the main program. an example of a polling routine is as follows: in this example, if irq2 is being polled, maska will be 00000100b and maskb will be 11111011b. 7.8 reset conditions upon reset, all bits in ipr are undefined. in imr, bit 7 is 0 and bits 0-6 are undefined. the irq reg- ister is reset and held in that state until an enable interrupt (ei) instruction is executed. tm irq, #maska ;test for request jr z, next ;if no request go to next call service ;if request is there, then ;service it next: . . . service: ;process request . . . and irq, #maskb ;clear request bit ret ;return to next um001600-z8x0599 8-1 u ser s m anual c hapter 8 p ower -d own m odes 8.1 introduction in addition to the standard run mode, the z8 mcu ? sup- ports two power-down modes to minimize device current consumption. the two modes supported are halt and stop. 8.2 halt mode operation the halt mode suspends instruction execution and turns off the internal cpu clock. the on-chip oscillator circuit re- mains active so the internal clock continues to run and is applied to the counter/timer(s) and interrupt logic. to enter the halt mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid- instruction. to do this, the application program must exe- cute a nop instruction (opcode = ffh) immediately before the halt instruction (opcode 7fh), that is, the halt mode is exited by interrupts, either externally or internally generated. upon completion of the interrupt ser- vice routine, the user program continues from the instruc- tion after halt. the halt mode may also be exited via a por/reset ac- tivation or a watch-dog timer (wdt) timeout. (see the product data sheet for wdt availability). in this case, pro- gram execution will restart at the reset restart address 000ch. to further reduce power consumption in the halt mode, some z8 family devices allow dynamic internal clock scal- ing. clock scaling may be accomplished on the fly by re- programming bit 0 and/or bit1 of the stop-mode recov- ery register (smr). see figure 8-1. note: internal clock scaling directly effects counter/timer operation adjustment of the prescaler and downcounter values may be required. to determine the actual halt mode current (i cc1 ) value for the various optional modes available, see the related z8 devices product specification. ff nop ;clear the instruction pipeline 7f halt ;enter halt mode z8 microcontrollers power-down modes zilog 8-2 um001600-z8x0599 8.3 stop mode operation the stop mode provides the lowest possible device standby current. this instruction turns off the on-chip oscil- lator and internal system clock. to enter the stop mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid- instruction. to do this, the application program must exe- cute a nop instruction (opcode=ffh) immediately before the stop instruction (opcode=6fh), that is, the stop mode is exited by any one of the following re- sets: power-on reset activation, wdt time out (if avail- able), or a stop-mode recovery source. upon reset gen- eration, the processor will always restart the application program at address 000ch. por/reset activation is present on all z8 devices and is implemented as a reset pin and/or an on-chip power on re- set circuit. some z8 devices allow for the on-chip wdt to run in the stop mode. if so activated, the wdt timeout will gener- ate a reset some fixed time period after entering the stop mode. note: stop-mode recovery by the wdt will increase the stop mode standby current (i cc2 ). this is due to the wdt clock and divider circuitry that is now enabled and running to support this recovery mode. see the product data sheet for actual i cc2 values. all z8 devices provide some form of dedicated stop- mode recovery (smr) circuitry. two smr methods are implemented a single fixed input pin or a flexible, pro- grammable set of inputs. the selected z8 device product specification should be reviewed to determine the smr options available for use. note: for devices that support spi, the slave mode compare feature also serves as a smr source. in the simple case, a low level applied to input pin p27 will trigger a smr. to use this mode, pin p27 (i/o port 2, bit 7) must be configured as an input before the stop mode is entered. the low level on p27 must meet a minimum pulse width t wsm . (see the product data sheet) to trigger the de- vice reset mode). some z8 devices provide multiple smr input sources. the desired smr source is selected via the smr register. note: use of specialized smr modes (p2.7 input or smr register based) or the wdt timeout (only when in the stop mode) provide a unique reset operation. some control registers are initialized differently for a smr/wdt triggered por than a standard reset operation. see the product specification (register file map) for exact details. to determine the actual stop mode current (i cc2 ) value for the optional smr modes available, see the selected z8 devices product data sheet. note: the stop mode current (i cc2 ) will be minimized when: ? v cc is at the low end of the devices operating range. ? wdt is off in the stop mode. ? output current sourcing is minimized. ? all inputs (digital and analog) are at the low or high rail voltages. ff nop ;clear the instruction pipeline 6f stop ;enter stop mode z8 microcontrollers zilog power-down modes um001600-z8x0599 8-3 8.4 stop-mode recovery register this register selects the clock divide value and determines the mode of stop-mode recovery (figure 8-1). all bits are write-only, except bit 7, that is read-only. bit 7 is a flag bit that is hardware set on the condition of stop re- covery and reset by a power-on cycle. bit 6 controls wheth- er a low level or a high level is required from the recovery source. bit 5 controls the reset delay after recovery. bits 2, 3, and 4, of the smr register, specify the source of the stop-mode recovery signal. bits 0 and 1 control internal clock divider circuitry. the smr is located in bank f of the expanded register file at address 0bh. note: the smr register is available in select z8 mcu products. refer to the device product specification to determine smr options available. sclk/tclk divide-by-16 select (do). this bit of the smr controls a divide-by-16 prescaler of sclk/tclk. the purpose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). external clock divide-by-two (d1). this bit can eliminate the oscillator divide-by-two circuitry. when this bit is 0, the system clock (sclk) and timer clock (tclk) are equal to the external clock frequency divided by two. the sclk/tclk is equal to the external clock frequency when this bit is set (d1=1). using this bit together with d7 of pcon helps further lower emi (d7 (pcon) =0, d1 (smr) =1). the default setting is zero. figure 8-1. stop-mode recovery register (write-only except bit d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b stop-mode recovery source 000 por only and/or external reset 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 0 off ** 1 on sclk/tclk divide-by-16 0 off 1 on* stop delay 0 por* 1 stop recovery stop flag (read only) 0 sclk/tclk = xtal/2* external clock divide by 2 0 low* 1 high stop recovery level 1 sclk/tclk = xtal * default setting after reset. ** default setting after reset and stop-mode recovery. z8 microcontrollers power-down modes zilog 8-4 um001600-z8x0599 8.4 stop-mode recovery register (continued) stop-mode recovery source (d2, d3, and d4). these three bits of the smr specify the wake-up source of the stop recovery and (table 8-1 and figures 8-2). stop-mode recovery delay select (d5). this bit, if high, enables the t por /reset delay after stop-mode recovery. the default configuration of this bit is 1. if the fast wake up is selected, the stop-mode recovery source is kept active for at least 5 tpc. stop-mode recovery edge select (d6). a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the z8 from stop mode. a 0 in- dicates low-level recovery. the default is 0 on por (figure 8-2). cold or warm start (d7). this bit is set by the device upon entering stop mode. a 0 in this bit (cold) indicates that the device reset by por/wdt reset. a 1 in this bit (warm) indicates that the device awakens by a smr source. note: if p31, p32, or p33 are to be used for a smr source, the digital mode of operation must be selected prior to entering the stop mode. table 8-1. stop-mode recovery source smr: 432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 p30 transition 0 1 0 p31 transition (not in analog mode) 0 1 1 p32 transition (not in analog mode) 1 0 0 p33 transition (not in analog mode) 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 figure 8-2. stop-mode recovery source smr d4 d3 d2 0 0 0 smr d4 d3 d2 0 0 1 0 1 0 0 1 1 smr d4 d3 d2 1 0 0 smr d4 d3 d2 1 0 1 smr d4 d3 d2 1 1 0 smr d4 d3 d2 1 1 0 v dd p20 p23 p20 p27 p30 p33 p27 p31 p32 mux to por reset to p33 data latch and irq 1 stop mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) um001600-z8x0599 9-1 u ser s m anual c hapter 9 s erial i/o 9.1 uart introduction select z8 mcu ? microcontrollers contain an on-board full- duplex universal asynchronous receiver/transmitter (uart) for data communications. the uart consists of a serial i/o register (sio) located at address f0h, and its associated control logic (figure 9-1). the sio is actually two registers, the receiver buffer and the transmitter buffer, which are used in conjunction with counter/timer t0 and port 3 i/o lines p30 (input) and p37 (output). counter/tim- er t0 provides the clock input for control of the data rates. figure 9-1. uart block diagram stop bit detect transmitter shift register ? 6 parity gan serial out char detect receiver buffer receiver shift register serial in start bit detect clock control parity check shift clock shift clock ? 16 transfer stop start write foh reset read foh mark serial i/o clock (from t0) irq 4 internal data bus irq 3 p3 7 p3 0 z8 microcontrollers serial i/o zilog 9-2 um001600-z8x0599 configuration of the uart is controlled by the port 3 mode register (p3m) located at address f7h. the z8 always transmits eight bits between the start and stop bits (eight data bits or seven data bits and one parity bit). odd parity generation and detection is supported. the sio register and its associated mode control regis- ters are mapped into the standard z8 register file as shown in table 9-1. the organization allows the software to access the uart as general-purpose registers, elimi- nating the need for special instructions. 9.2 uart bit-rate generation when port 3 mode register bit 6 is set to 1, the uart is enabled and t0 automatically becomes the bit rate gener- ator (figure 9-2). the end-of-count signal of t0 no longer generates interrupt request irq4. instead, the signal is used as the input to the divide-by-16 counters (one each for the receiver and the transmitter) that clock the data stream. the divide chain that generates the bit rate is shown in fig- ure 9-3. the bit rate is given by the following equation: bit rate = xtal frequency/(2 x 4 x p x t x 16) where p and t are the initial values in prescaler0 and counter/timer0, respectively. the final divide-by-16 is re- quired since t0 runs at 16 times the bit rate in order to syn- chronize on the incoming data. to configure the z8 for a specific bit rate, appropriate val- ues as determined by the above equation must be loaded into registers pre0 (f5h) and t0 (f4h). pre0 also controls the counting mode for t0 and should therefore be set to the continuous mode (d0 = 1). table 9-1. uart register map register hex name identi?er address port 3 mode p3m f7 t0 prescaler pre0 f5 timer/counter0 t0 f4 timer mode tmr f1 uart sio f0 figure 9-2. port 3 mode register (p3m) and bit-rate generation d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register (p3m) register f7h 0 p30 input and p37 = output 1 p30 serial in and p37 = serial out figure 9-3. bit rate divide chain p t ? 16 bit rate ? 4 ? 2 clock pre0 t0 f xtal z8 microcontrollers zilog serial i/o um001600-z8x0599 9-3 for example, given an input clock frequency (xtal) of 11.9808 mhz and a selected bit rate of 1200 bits per sec- ond, the equation is satisfied by p = 39 and t = 2. counter/timer t0 should be set to 02h. with t0 in contin- uous mode, the value of pre0 becomes 9dh (figure 9-4). table 9-2 lists several commonly used bit rates and the values of xtal, p, and t required to derive them. this list is presented for convenience and is not intended to be ex- haustive. table 9-2. bit rates bit 7,3728 7,9872 9,8304 11,0592 11,6736 11,9808 12,2880 rate p t p t p t p t p t p t p t 19200 3 1 C C 4 1 C C C C C C 5 1 9600 3 2 C C 4 2 9 1 C C C C 5 2 4800 3 4 13 1 4 4 9 2 19 1 C C 5 4 2400 3 8 13 2 4 8 9 4 19 2 39 1 5 8 1200 3 16 13 4 4 16 9 8 19 4 39 2 5 16 600 3 32 13 8 4 32 9 16 19 8 39 4 5 32 300 3 64 13 16 4 64 9 32 19 16 39 8 5 64 150 3 128 13 32 4 128 9 64 19 32 39 16 5 128 110 3 175 3 189 4 175 5 157 4 207 17 50 8 109 figure 9-4. prescaler 0 register (pre0) bit-rate generation d7 d6 d5 d4 d3 d2 d1 d0 (write-only) prescalar 0 register (pre0) register f5h count mode 0 = t 0 single pass (range: 1-64 decimal, 01h-00h) (range: 1-64) 1 = t 0 modulo-n z8 microcontrollers serial i/o zilog 9-4 um001600-z8x0599 the bit rate generator is started by setting the timer mode register (tmr) (f1h) bit 1 and bit 0 both to 1 (figure 9-5). this transfers the contents of the prescaler 0 register and counter/timer0 register to their corresponding down counters. in addition, counting is enabled so that uart operations begin. 9.3 uart receiver operation the receiver consists of a receiver buffer (sio register [f0h]), a serial-in, parallel-out shift register, parity check- ing, and data synchronizing logic. the receiver block dia- gram is shown as part of figure 9-1. 9.3.1 receiver shift register after a hardware reset or after a character has been re- ceived, the receiver shift register is initialized to all 1s and the shift clock is stopped. serial data, input through port 3 bit 0, is synchronized to the internal clock by two d- type flip-flops before being input to the shift register and the start bit detection circuitry. the start bit detection circuitry monitors the incoming data stream, looking for a start bit (a high-to-low input transi- tion). when a start bit is detected, the shift clock logic is en- abled. the t0 input is divided-by-16 and, when the count equals eight, the divider outputs a shift clock. this clock shifts the start bit into the receiver shift register at the center of the bit time. before the shift actually occurs, the input is rechecked to ensure that the start bit is valid. if the detected start bit is false, the receiver is reset and the pro- cess of looking for a start bit is repeated. if the start bit is valid, the data is shifted into the shift register every six- teen counts until a full character is assembled (figure 9-6). figure 9-5. timer mode register (tmr) bit rate generation d7 d6 d5 d4 d3 d2 d1 d0 (read/write) 0 = no function 1 = load t 0 timer mode register (tmr) register f1h 0 = disable t 0 count 1 = enable t 0 count figure 9-6. receiver timing shift register contents (r) shift rcvr start bit transition detected eight t0 counts later shifting starts stop bit one or more transferred to receive buffer and irq3 is generated rcvr data clock irq3 z8 microcontrollers zilog serial i/o um001600-z8x0599 9-5 after a full character has been assembled in the receivers buffer, sio register (f0h), interrupt request irq3 is gen- erated. the shift clock is stopped and the shift register re- set to all 1s. the start bit detection circuitry begins moni- toring the data input for the next start bit. this cycle allows the receiver to synchronize on the center of the bit time for each incoming character. 9.3.2 overwrites although the receiver is single buffered, it is not protected from being overwritten, so the software must read the sio register (f0h) within one character time after the interrupt request (irq3). the z8 does not have a flag to indicate this overrun condition. if polling is used, the irq3 bit in the interrupt request register must be reset by software. 9.3.3 framing errors framing error detection is not supported by the receiver hardware, but by responding to the interrupt request within one character bit time, the software can test for a stop bit on p30. port 3 bits are always readable, which facilitates break detection. for example, if a null character is re- ceived, testing p30 results in a 0 being read. 9.3.4 parity the data format supported by the receiver must have a start bit, eight data bits, and at least one stop bit. if parity is on, bit 7 of the data received will be replaced by a parity error flag. a parity error sets bit 7 to 1, otherwise, bit d7 is set to 0. figure 9-7 shows these data formats. the z8 hardware supports odd parity only, that is enabled by setting the port 3 mode register bit 7 to 1 (figure 9-8). if even parity is required, the parity mode should be dis- abled (p3m bit 7 set to 0), and software must calculate the received datas parity. figure 9-7. receiver data formats sp d7 d6 d5 d4 d3 d2 d1 d0 st eight data bits start bit start bit seven data bits one stop bit sp p d6 d5 d4 d3 d2 d1 d0 st parity error flag one stop bit received data (no parity) received data (with parity) figure 9-8. port 3 mode register (p3m) parity d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0 = parity off 1 = parity on port 3 mode register (p3m) register f7h z8 microcontrollers serial i/o zilog 9-6 um001600-z8x0599 9.4 transmitter operation the transmitter consists of a transmitter buffer (sio reg- ister [f0h]), a parity generator, and associated control log- ic. the transmitter block diagram is shown as part of fig- ure 9-1. after a hardware reset or after a character has been trans- mitted, the transmitter is forced to a marking state (output always high) until a character is loaded into the transmitter buffer, sio register (f0h). the transmitter is loaded by specifying the sio register as the destination register of any instruction. t0s output drives a divide-by-16 counter that in turn gen- erates a shift clock every 16 counts. this counter is reset when the transmitter buffer is written by an instruction. this reset synchronizes the shift clock to the software. the transmitter then outputs one bit per shift clock, through port 3 bit 7, until a start bit, the character written to the buff- er, and two stop bits have been transmitted. after the sec- ond stop bit has been transmitted, the output is again forced to a marking state. interrupt request irq4 is gener- ated at this time to notify the processor that the transmitter is ready to accept another character. 9.4.1 overwrites the user is not protected from overwriting the transmitter, so it is up to the software to respond to irq4 appropriately. if polling is used, the irq4 bit in the interrupt request reg- ister must be reset. 9.4.2 parity the data format supported by the transmitter has a start bit, eight data bits, and at least two stop bits. if parity is on, bit 7 of the data transmitted will be replaced by an odd par- ity bit. figure 9-9 shows the transmitter data formats. parity is enabled by setting port 3 mode register bit 7 to 1. if even parity is required, the parity mode should be dis- abled (p3m bit 7 reset to 0), and software must modify the data to include even parity. since the transmitter can be overwritten, the user is able to generate a break signal. this is done by writing null characters to the transmitter buffer (sio register [f0h]) at a rate that does not allow the stop bits to be output. each time the sio register is loaded, the divide-by-16 counter is resynchronized and a new start bit is output followed by data. figure 9-9. transmitter data formats sp sp d7 d6 d5 d4 d3 d2 d1 d0 st eight data bits start bit start bit seven data bits two stop bit sp sp p d6 d5 d4 d3 d2 d1 d0 st odd parity two stop bit transmitted data (no parity) transmitted data (with parity) z8 microcontrollers zilog serial i/o um001600-z8x0599 9-7 9.5 uart reset conditions after a hardware reset, the sio register contents are un- defined, and serial mode and parity are disabled. figures 9-10 and 9-11 show the binary reset values of the sio register and its associated mode register p3m. figure 9-10. sio register reset u u u u u u u u (read/write) serial data (d 0 = lsb) serial i/o register (sio) register rf0h figure 9-11. p3m register reset 0 0 0 0 0 0 0 0 (write-only) 0 p32 = input p35 = output 1 p32 = dav0 /rdy0 p35 = rdy0/ dav0 0 port 2 pull-ups open-drain 1 port 2 pull-ups active 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register (p3m) register f7h 10 p33 = input p34 = dm 11 p33 = dav1/ rdy1 p34 = rdy1/ dav1 0 p31 = input (t in ) p36 = output (t out ) 1 p32 = dav2 /rdy2 p36 = rdy2/ dav2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 parity on 1 parity off z8 microcontrollers serial i/o zilog 9-8 um001600-z8x0599 9.6 serial peripheral interface (spi) select z8 microcontrollers incorporate a serial peripheral interface (spi) for communication with other microcontrol- lers and peripherals. the spi includes features such as stop-mode recovery, master/slave selection, and com- pare mode. table 9-3 contains the pin configuration for the spi feature when it is enabled. the spi consists of four registers: spi control register (scon), spi compare register (scomp), spi receive/buffer register (rxbuf), and spi shift register. scon is located in bank (c) of the expanded register file at address 02. the spi control register (scon) (figure 9-12), is a read/write register that controls master/slave selection, in- terrupts, clock source and phase selection, and error flag. bit 0 enables/disables the spi with the default being spi disabled. a 1 in this location will enable the spi, and a 0 will disable the spi. bits 1 and 2 of the scon register in master mode select the clock rate. the user may choose whether internal clock is divide-by-2, 4, 8, or 16. in slave mode, bit 1 of this register flags the user if an overrun of the rxbuf register has occurred. the rxcharoverrun flag is only reset by writing a 0 to this bit. in slave mode, bit 2 of the control register disables the data-out i/o function. if a 1 is written to this bit, the data-out pin is released to its original port configuration. if a 0 is written to this bit, the spi shifts out one bit for each bit received. bit 3 of the scon register enables the compare feature of the spi, with the default being disabled. when the compare feature is enabled, a comparison of the value in the scomp reg- ister is made with the value in the rxbuf register. bit 4 signals that a receive character is available in the rxbuf register. if the associated irq3 is enabled, an interrupt is generat- ed. bit 5 controls the clock phase of the spi. a 1 in bit 5 allows for receiving data on the clocks falling edge and transmitting data on the clocks rising edge. a 0 allows re- ceiving data on the clocks rising edge and transmitting on the clocks falling edge. the spi clock source is defined in bit 6. a 1 uses timer0 output for the spi clock, and a 0 uses tclk for clocking the spi. finally, bit 7 determines whether the spi is used as a master or a slave. a 1 puts the spi into master mode and a 0 puts the spi into slave mode. table 9-3. spi pin configuration name function pin location di data-in p20 do data-out p27 ss slave select p35 sk spi clock p34 figure 9-12. spi control register (scon) d7 d6 d5 d4 d3 d2 d1 d0 scon (c) 02 clk divide (m) 00 tclk/2 01 tclk/4 10 tclk/8 11 tclk/16 do spi port enable (s) 0 spi do port enable 1 do port to i/o 0 disable * 1 enable spi enable 0 enable 1 disable * compare enable 0 trans/fall 1 trans/rise clock phase 0 reset rxcharoverrun (s) 0 reset 1 char. avail rxcharavail 1 overrun (m) used with bit d7 equal to 1 * default setting after reset 0 tclk 1 timer 0 output clk source 0 slave 1 master master slave (s) used with bit d7 equal to 0 z8 microcontrollers zilog serial i/o um001600-z8x0599 9-9 9.7 spi operation the spi is used in one of two modes: either as system slave, or as system master. several of the possible system configurations are shown in figure 9-13. in the slave mode, data transfer starts when the slave select (ss) pin goes active. data is transferred into the slaves spi shift register through the di pin, which has the same address as the rxbuf register. after a byte of data has been re- ceived by the spi shift register, a receive character available (rca/irq3) flag and interrupt is generated. the next byte of data will be received at this time. the rxbuf register must be cleared, or a receive character overrun (rxcharoverrun) flag will be set in the scon register, and the data in the rxbuf register will be overwritten. when the communication between the master and slave is complete, the ss goes inactive.when the spi is activated as a slave, it operates in all system modes: stop, halt, and run. unless disconnected, for every bit that is transferred into the slave through the di pin, a bit is transferred out through the d0 pin on the opposite clock edge. during slave oper- ation, the spi clock pin (sk) is an input. in master mode, the cpu must first activate a ss through one of its i/o ports. next, data is transferred through the masters d0 pin one bit per master clock cycle. loading data into the shift register initiates the transfer. in master mode, the masters clock will drive the slaves clock. at the conclusion of a transfer, a receive character available (rca/irq3) flag and interrupt is generated. before data is transferred via the d0 pin, the spi enable bit in the scon register must be enabled. 9.8 spi compare when the spi compare enable bit, d3 of the scon reg- ister is set to 1, the spi compare feature is enabled. the compare feature is only valid for slave mode. a compare transaction begins when the (ss) line goes active. data is received as if it were a normal transaction, but there is no data transmitted to avoid bus contention with other slave devices. when the compare byte is received, irq3 is not generated. instead, the data is compared with the contents of the scomp register. if the data does not match, do re- mains inactive and the slave ignores all data until the (ss) signal is reset. if the data received matches the data in the scomp register, then a smr signal is generated. do is activated if it is not tri-stated by d2 in the scon register, and data is received the same as any other spi slave transaction. slaves not comparing remain in their current mode, whereas slaves comparing wake from a stop mode by means of an smr 9.9 spi clock the spi clock maybe driven by three sources: timer0, a division of the internal system clock, or the external master when in slave mode. bit d6 of the scon register controls what source drives the spi clock. a 0 in bit d6 of the scon register determines the division of the internal system clock if this is used as the spi clock source. divide by 2, 4, 8, or 16 is chosen as the scaler. z8 microcontrollers serial i/o zilog 9-10 um001600-z8x0599 figure 9-13. spi system con?guration ss sk do di slave multiple slaves may have the same address ss1 ss4 do ss2 ss3 sk di master three wire compare setup ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master ss sk do di slave setup for compare ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master up to 256 slaves per ss line (1) (2) (255) (256) ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di slave standard parallel setup ss sk do di slave standard serial setup ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master z8 microcontrollers zilog serial i/o um001600-z8x0599 9-11 9.10 receive character available and overrun when a complete data stream is received, an interrupt is generated and the rxcharavail bit in the scon register is set. bit 4 in the scon register is for enabling or dis- abling the rxcharavail interrupt. the rxcharavail bit is available for interrupt polling purposes and is reset when the rxbuf register is read. rxcharavail is generated in both master and slave modes. while in slave mode, if the rxbuf is not read before the next data stream is received and loaded into the rxbuf register, receive character overrun (rxcharoverrun) occurs. since there is no need for clock control in slave mode, bit d1 in the spi control register is used to log any rxcharoverrun (figure 9-14 and figure 9-15). no parameter min units 1 di to sk setup 10 ns 2 sk to d0 valid 15 ns 3 ss to sk setup .5 tsk ns 4 ss to d0 valid 15 ns 5 sk to di hold time 10 ns figure 9-14. spi timing tsk ss sk d0 di 1 2 3 4 5 z8 microcontrollers serial i/o zilog 9-12 um001600-z8x0599 9.10 receive character available and overrun (continued) figure 9-15. spi logic spi compare register (scomp) ss d0 di sk port tclk smr bit control spi control spi receive buffer (rxbuf) spi shift register /interrupt control irq 3 sclk + n spi clock control z8 microcontrollers zilog serial i/o um001600-z8x0599 9-13 figure 9-16. spi data in/out con?guration p27 out pin spi active p27 in 0 soi d0 enable open-drain auto latch p27 p20 oe pin p20 in open-drain r ? 500 k w auto latch p20 spi en spi do p27 oe spi spi do spi standard standard 1 p27 out *spi must be enabled with d0 d2 scon or spi di r ? 500 k w z8 microcontrollers serial i/o zilog 9-14 um001600-z8x0599 9.10 receive character available and overrun (continued) figure 9-17. spi clock / spi slave select output con?guration spi mstr pin p31 + spi en p34 sk in spi mstr pin p35 spi en ref ss 0 p34, p35 standard output 1 p34, p35 comparator output d0 p35 out pcon p32 ref + - p34 out - spi en sk out mux z8 microcontrollers zilog serial i/o um001600-z8x0599 9-15 z8 microcontrollers serial i/o zilog 9-16 um001600-z8x0599 um001600-z8x0599 10-1 u ser s m anual c hapter 10 e xternal i nterface 10.1 introduction the z8 can be a microcontroller with 20 pins for external memory interfacing. the external memory interface on the z8 is generally for either ram or rom. this is only avail- able for devices featuring port 0, port 1, r/ w , dm , as , and ds . please refer to specific product specifications for avail- ability of these features. the z8 has a multiplexed external memory interface. in the multiplexed mode, eight pins from port 1 form an ad- dress/data bus (ad7-ad0), eight pins from port 0 form a high address bus (a15-a8). three additional pins provide the address strobe, data strobe, and the read/write sig- nal. figure 10-1 shows the z8 external interface pins. figure 10-1. z8 external interface pins external z8 mcu program/data 64 kbytes each (port 1) ad7 - ad0 (port 0) ad15 - ad8 /as /ds r//w /dm z8 microcontrollers external interface zilog 10-2 um001600-z8x0599 10.2 pin descriptions the following sections briefly describe the pins associated with the z8 mcu ? external memory interface. 10.2.1 /as address strobe (output, active low). address strobe is pulsed low once at the beginning of each machine cycle. the rising edge of as indicates the address, read/write (r/ w ), and data memory ( dm ) signals are valid for pro- gram or data memory transfers. in some cases, the z8 ad- dress strobe is pulsed low regardless of accessing exter- nal or internal memory. please refer to specific product specifications for as operation. 10.2.2 ds data strobe (output, active low) . data strobe provides the timing for data movement to or from the address/data bus for each external memory transfer. during a write cy- cle, data out is valid at the leading edge of the ds . during a read cycle, data in must be valid prior to the trailing edge of the ds . 10.2.3 r/ w read/write (output). read/write determines the direction of data transfer for memory transactions. r/ w is low when writing to program or data memory, and high for all other transactions. 10.2.4 dm data memory (output) . data memory provides a signal to separate external program memory from external data memory. it is a programmable function on pin p34. data memory is active low for external data memory accesses and high for external program memory accesses. 10.2.5 p07 - p00 high address lines a15 -a8 (outputs can be cmos- or ttl- compatible. please refer to product specifications for actual type). a15-a8 provide the high address lines for the memory interface. port 0 - 1 mode register must have bits d7 = 1 and d1 = 1 to configure port 0 as a15 - a8 (figure 10-2). 10.2.6 p17 - p10 address/data lines ad7 - ad0 (inputs/outputs, ttl-com- patible). ad7-ad0 is a multiplexed address/data memory interface. the lower eight address lines (a7-a0) are multi- plexed with data lines (d7-d0). port 0 - 1 mode register must have bits d4 = 1 and d3 = 0 to configure port 1 as ad7 - ad0 (figure 10-2). 10.2.7 /reset reset (input, active low). reset initializes the z8. when reset is deactivated, program execution begins from program location 000ch. if held low, reset acts as a register file protect during power-down and power-up sequences. to avoid asynchronous and noisy reset problems, the z8 is equipped with a reset filter of four external clocks (4t p c). if the external reset signal is less than 4t p c in duration, no reset will occur. on the fifth clock after the reset is detected, an internal reset signal is latched and held for an internal register count of 18 or more external clocks, or for the duration of the external reset , whichever is longer. please refer to specific product specifications for length of reset delay time. 10.2.8 xtal1, xtal2. crystal1, crystal2 (oscillator input and output). these pins connect a parallel-resonant crystal, ceramic resonator, lc, rc network, or external single-phase clock to the on-chip oscillator input. please refer to the device product specifi- cations for information on availability of rc oscillator fea- tures. z8 microcontrollers zilog external interface um001600-z8x0599 10-3 10.3 external addressing configuration the minimum bus configuration uses port 1 as a multi- plexed address/data port (ad7 - ad0), allowing access to 256 bytes of external memory. in this configuration, the eight low-order bits (a0 - a7) are multiplexed with the data (d7 - d0). port 0 can be programmed to provide either four additional address lines (a11- a8), which increases the addressable memory to 4k bytes, or eight additional address lines (a15 - a8), which increases the addressable external memory up to 64k bytes. it is required to add a nop after configur- ing port 0 / port 1 for external addressing before jumping to external memory execution. figure 10-2. external address configuration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 01 = input 1x = a 8 - a 11 p0 0 - p0 7 mode 00 = output port 0-1 mode register (p01m) register f8h (p01m) 01 = byte output p0 4 - p0 7 mode 00 = output 01 = input 1x = a 12 - a 15 10 = ad 0 -ad 7 00 = byte output p 10 - p 17 mode a 8 - a 15 , as , ds , r/ w 11 = high impedance ad 0 - ad 7 , z8 microcontrollers external interface zilog 10-4 um001600-z8x0599 10.4 external stacks the z8 architecture supports stack operations in either the z8 standard register file or external data memory. a stacks location is determined by bit 2 in the port 0-1 mode register (f8h). if bit 2 is set to 0, the stack is in external data memory. (figure 10-3). the instruction used to change the stack selection bit should not be immediately followed by the instructions ret or iret, because this will cause indeterminate pro- gram flow. after a reset , the internal stack is selected. please note that if port 0 is configured as a15 - a8 and the stack is selected as internal, any stack operation will cause the contents in register feh to be displayed on port 0. 10.5 data memory the two z8 external memory spaces, data and program, are addressed as two separate spaces of up to 64 kbytes each. external program memory and external data mem- ory are logically selected by the data memory select out- put ( dm ). dm is made available on port 3, bit 4 (p34) by setting bit 4 and bit 3 in the port 3 mode register (f7h) to 10 or 01 (figure 10-4). dm is active low during the execu- tion of the lde, ldei instructions, and high for the execu- tion of program instructions. dm is also active low during the execution of call, pop, push, ret and iret in- structions if the stack resides in external data memory. af- ter a reset , dm is not selected. figure 10-3. z8 stack selection d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 0-1 register register f8h (p01m) z8 stack selection 0 = external 1 = internal figure 10-4. port 3 data memory operation d7 d6 d5 d4 d3 d2 d1 d0 (write-only) bits configuration 00 p33 = input p34 = output 01 p33 = input p34 = /dm port 3 mode register register f7h (p3m) 10 p33 = input p34 = /dm 11 p33 = /dav1/rdy1 p34 = rdy1//dav1 z8 microcontrollers zilog external interface um001600-z8x0599 10-5 10.6 bus operation typical data transfers between the z8 mcu and external memory are illustrated in figures 10-5 and 10-6. machine cycles can vary from six to 12 clock periods depending on the operation being performed. the notations used to de- scribe the basic timing periods of the z8 are machine cy- cles (mn), timing states (tn), and clock periods. all timing references are made with respect to the output signals as and ds . the clock is shown for clarity only and does not have a specific timing relationship with other signals. figure 10-5. external instruction fetch or memory read cycle machine cycle t1 t2* t3 clock a15-a8 ad7-ad0 /as /ds r/w /dm read cycle a8-a15 a7-a0 d7-d0 in *port inputs are strobed during t2, which is two internal systems clocks before the execution cycle of the current instruction. z8 microcontrollers external interface zilog 10-6 um001600-z8x0599 10.6 bus operation (continued) 10.6.1 address strobe ( as ) all transactions start with as driven low and then raised high by the z8 mcu. the rising edge of as indicates that r/ w , dm (if used), and the address outputs are valid. the address outputs (ad7-ad0), remain valid only during mnt1 and typically need to be latched using as . address outputs (a15-a8) remain stable throughout the machine cycle, regardless of the addressing mode. 10.6.2 data strobe (/ds) the z8 uses ds to time the actual data transfer. for write operations (r/ w = low), a low on ds indicates that valid data is on the ad7-ad0 lines. for read operations (r/w = high), the bus is placed in a high-impedance state before driving ds low, so the addressed device can put its data on the bus. the z8 samples this data prior to raising ds high. figure 10-6. external memory write cycle machine cycle t1 t2 t3 clock a15-a8 ad7-ad0 /as /ds r/w /dm write cycle a8-a15 a7-a0 d7-d0 out z8 microcontrollers zilog external interface um001600-z8x0599 10-7 10.7 extended bus timing some products can accommodate slow memory access time by automatically inserting an additional software con- trolled state time (tx). this stretches the ds timing by two clock periods. figures 10-7 and 10-8 illustrate extended external memory read and write cycles. figure 10-7. extended external instruction fetch or memory read cycle machine cycle t2* tx t3 clock a15-a8 ad7-ad0 /as /ds r/w /dm read cycle a15-a8 a7-a0 d7-d0 in t1 *port inputs are strobed during t2, which is two internal system clocks before the execution of the current instruction. z8 microcontrollers external interface zilog 10-8 um001600-z8x0599 timing is extended by setting bit d5 in the port 0-1 mode register (f8h) to 1 (figure 10-9). after a reset , this bit is set to 0. figure 10-8. extended external memory write cycle machine cycle t2 tx t3 clock a15-a8 ad7-ad0 as ds r/w dm write cycle a15-a8 a7-a0 d7-d0 out t1 figure 10-9. extended bus timing d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 0-1 register register f8h (p01m) external memory timing 0 = normal 1 = extended z8 microcontrollers zilog external interface um001600-z8x0599 10-9 10.8 instruction timing the high throughput of the z8 is due, in part, to the use of an instruction pipeline, in which the instruction fetch and execution cycles are overlapped. during the execution of the current instruction, the opcode of the next instruction is fetched. instruction pipelining is illustrated in figure 10-10. figures 10-10 and 10-11 show typical instruction cycle tim- ing for instructions fetched from memory. for those in- structions that require execution time longer than that of the overlapped fetch, or reference program or data mem- ory as part of their execution, the pipe must be flushed. figures 10-10 and 10-11 assume the xtal/2 clock mode is selected. figure 10-10. instruction cycle timing (one-byte instructions) t1 t2 t3 t3 t1 /ds /as r/w t1 t2 t2 fetch 1st byte t3 m1 m2 m3 a15-a8 a15-a8 a15-a8 a7-a0 a7-a0 a7-a0 a7-a0 a7-a0 fetch 1st byte of next instruction * port inputs are strobed during t2, which is two internal system clocks before the execution cycle of the current installation clock z8 microcontrollers external interface zilog 10-10 um001600-z8x0599 10.9 z8 reset conditions after a hardware reset, extended timing is set to accom- modate slow memory access during the configuration rou- tine, dm is inactive, the stack resides in the register file. port 0, 1, and 2 are reset to input mode. port 2 is set to open-drain mode. figure 10-11. instruction cycle timing (2- and 3-byte instructions) t1 t2 t3 t3 t1 ds as r/w t1 t2 t2 fetch 1st byte t3 m1 m2 m3 a15-a8 a15-a8 a15-a8 a7-a0 a7-a0 a7-a0 a7-a0 a7-a0 fetch 2nd byte fetch 3rd byte fetch 1st byte (1- or 2-byte instruction ) (3-byte instruction) a15-a8 a7-a0 a7-a0 clock *port inputs are strobed during t2, which is two internal system clocks before the execution cycle of the current instruction. um001600-z8x0599 11-1 u ser s m anual c hapter 11 a ddressing m odes 11.1 introduction 11.1.1 z8 addressing modes the z8 microcontroller provides six addressing modes: ? register (r) ? indirect register (ir) ? indexed (x) ? direct (d) ? relative (ra) ? immediate (im) with the exception of immediate data and condition codes, all operands are expressed as register file, program mem- ory, or data memory addresses. registers are accessed using 8-bit addresses in the range of 00h-ffh. the pro- gram memory or data memory is accessed using 16-bit addresses (register pairs) in the range of 0000h-ffffh. working registers are accessed using 4-bit addresses in the range of 0-15 (0h-fh). the address of the register be- ing accessed is formed by the combination of the upper four bits in the register pointer (r253) and the 4-bit work- ing register address supplied by the instruction. registers can be used in pairs to designate 16-bit values or memory addresses. a register pair must be specified as an even-numbered address in the range of 0, 2,...., 14 for working registers, or 4, 6,....238 for actual registers. in the following definitions of z8 addressing modes, the use of'register' can also imply register pair, working regis- ter, or working register pair, depending on the context. note: see the product data sheet for exact program, data, and register memory types and address ranges available. z8 microcontrollers addressing modes zilog 11-2 um001600-z8x0599 11.2 z8 register addressing (r) in 8-bit register addressing mode, the operand value is equivalent to the contents of the specified register or reg- ister pair. in the register addressing (figure 11-1), the destination and/or source address specified corresponds to the actual register in the register file. in 4-bit register addressing (figure 11-2), the destination and/or source addresses point to the working register within the current working register group. this 4-bit address is combined with the upper four bits of the register pointer to form the actual 8-bit address of the affected register. figure 11-1. 8-bit register addressing opcode one operand register file operand program memory points to dst 8-bit register one register in the register file instruction (example) file address figure 11-2. 4-bit register addressing op code two operand register file operand program memory points to src 4-bit working one register in the register file instruction (example) registers operand rp dst points to origin of working register group z8 microcontrollers zilog addressing modes um001600-z8x0599 11-3 11.3 z8 indirect register addressing (ir) in the indirect register addressing mode, the contents of the specified register are equivalent to the address of the operand (figures 11-3 and 11-4). depending upon the instruction selected, the specified register contents points to a register, program memory, or an external data memory location. when accessing program memory or external data mem- ory, register pairs or working register pairs are used to hold the 16-bit addresses. figure 11-3. 4-bit register addressing op code one operand register file operand program memory points to one 8-bit register value used in address of operand instruction (example) file address address dst points to register of operand register in register file instruction execution used by instruction z8 microcontrollers addressing modes zilog 11-4 um001600-z8x0599 11.3 z8 indirect register addressing (ir) (continued) figure 11-4. indirect register addressing to program or data memory op code instruction example program or register file program memory points to src 4-bit working points to origin registers address register dst rp operand pair lsb register pair msb data memory working register pair (even address) of working register group 16-bit address points to program or data memory references either program memory or data memory value used in instruction z8 microcontrollers zilog addressing modes um001600-z8x0599 11-5 11.4 z8 indexed addressing (x) the indexed addressing mode is used only by the load (ld) instruction. an indexed address consists of a register address offset by the contents of a designated working register (the index). this offset is added to the register ad- dress to obtain the address of the operand. figure 11-5 il- lustrates this addressing convention. figure 11-5. indexed register addressing op code register file program memory points to src two operand points to origin instruction dst/ rp operand offset working register offset address of working register group value used in instruction address x z8 microcontrollers addressing modes zilog 11-6 um001600-z8x0599 11.5 z8 direct addressing (da) the direct addressing mode, as shown in figure 11-6, specifies the address of the next instruction to be execut- ed. only the conditional jump (jp) and call (call) in- structions use this addressing mode. figure 11-6. direct addressing op code upper addr. byte lower addr. byte program memory program memory address used z8 microcontrollers zilog addressing modes um001600-z8x0599 11-7 11.6 z8 relative addressing (ra) in the relative addressing mode, illustrated in figure 11- 7, the instruction specifies a twos-complement signed dis- placement in the range of C128 to +127. this is added to the contents of the pc to obtain the address of the next in- struction to be executed. the pc (prior to the add) consists of the address of the instruction following the jump rela- tive (jr) or decrement and jump if non-zero (djnz) in- struction. jr and djnz are the only instructions which use this addressing mode. figure 11-7. relative addressing opcode displacement next opcode current jr or djnz program memory program memory address used pc value z8 microcontrollers addressing modes zilog 11-8 um001600-z8x0599 11.7 z8 immediate data addressing (im) immediate data is considered an addressing mode for the purposes of this discussion. it is the only addressing mode that does not indicate a register or memory address as the source operand. the operand value used by the in- struction is the value supplied in the operand field itself. because an immediate operand is part of the instruction, it is always located in the program memory address space (figure 11-8). figure 11-8. immediate data addressing opcode immediate data program memory the operand value is in the instruction um001600-z8x0599 12-1 u ser s m anual c hapter 12 i nstruction s et 12.1 z8 functional summary z8 instructions can be divided functionally into the follow- ing eight groups: ? load ? bit manipulation ? arithmetic ? block transfer ? logical ? rotate and shift ? program control ? cpu control the following summary shows the instructions belonging to each group and the number of operands required for each. the source operand is src, the destination operand is dst, and a condition code is cc. table 12-1. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant lde dst, src load external pop dst pop push src push table 12-2. arithmetic instructions mnemonic operands instruction adc dst, src add with carry add dst, src add cp dst, src compare da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word sbc dst, src subtract with carry sub dst, src subtract table 12-3. logical instructions mnemonic operands instruction and dst, src logical and com dst complement or dst, src logical or xor dst, src logical exclusive or table 12-4. program control instructions mnemonic operands instruction call dst call procedure djnz dst, src decrement and jump non-zero iret interrupt return jp cc, dst jump jr cc, dst jump relative ret return z8 microcontrollers instruction set zilog 12-2 um001600-z8x0599 12.2 processor flags the flag register (fch) informs the user of the current status of the z8. the flags and their bit positions in the flag register are shown in figure 12-1. the z8 flag register contains six bits of status information which are set or cleared by cpu operations. four of the bits (c, v, z and s) can be tested for use with conditional jump instructions. two flags (h and d) cannot be tested and are used for bcd arithmetic. the two remaining bits in the flag register (f1 and f2) are available to the user, but they must be set or cleared by instructions and are not us- able with conditional jumps. as with bits in the other control registers, the flag register bits can be set or reset by instructions; however, only those instructions that do not affect the flags as an out- come of the execution should be used (load immediate). note: the watch-dog timer (wdt) instruction effects the flags accordingly: z=1, s=0, v=0. table 12-5. bit manipulation instructions mnemonic operands instruction tcm dst, src test complement under mask tm dst, src test under mask and dst, src bit clear or dst, src bit set xor dst, src bit complement table 12-6. block transfer instructions mnemonic operands instruction ldci dst, src load constant auto increment ldei dst, src load external auto increment table 12-7. rotate and shift instructions mnemoni c operands instruction rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles table 12-8. cpu control instructions mnemoni c operands instruction ccf complement carry flag di disable interrupts ei enable interrupts halt halt nop no operation rcf reset carry flag scf set carry flag srp src set register pointer stop stop wdh wdt enable during halt wdt wdt enable or refresh z8 microcontrollers zilog instruction set um001600-z8x0599 12-3 figure 12-1. z8 flag register d7 d6 d5 d4 d3 d2 d1 d0 flag register (read/write) half carry flag (h) user flag (f1) user flag (f2) register fch (flags) overflow flag (v) carry flag (c) decimal adjust flag (d) zero flag (z) sign flag (s) z8 microcontrollers instruction set zilog 12-4 um001600-z8x0599 12.2.1 carry flag (c) the carry flag is set to 1 whenever the result of an arith- metic operation generates a carry or a borrow the high or- der bit 7. otherwise, the carry flag is cleared to 0. following rotate and shift instructions, the carry flag contains the last value shifted out of the specified register. an instruction can set, reset, or complement the carry flag. iret may change the value of the carry flag when the flag register, saved in the stack, is restored. 12.2.2 zero flag (z) for arithmetic and logical operations, the zero flag is set to 1 if the result is zero. otherwise, the zero flag is cleared to 0. if the result of testing bits in a register is 00h, the zero flag is set to 1. otherwise the zero flag is cleared to 0. if the result of a rotate or shift operation is 00h, the zero flag is set to 1. otherwise, the zero flag is cleared to 0. iret changes the value of the zero flag when the flag register saved in the stack is restored. the wdt instruc- tion sets the zero flag to a 1. 12.2.3 sign flag (s) the sign flag stores the value of the most significant bit of a result following an arithmetic, logical, rotate, or shift op- eration. when performing arithmetic operations on signed num- bers, binary twos-complement notation is used to repre- sent and process information. a positive number is identi- fied by a 0 in the most significant bit position (bit 7); therefore, the sign flag is also 0. a negative number is identified by a 1 in the most signifi- cant bit position (bit 7); therefore, the sign flag is also 1. iret changes the value of the sign flag when the flag register saved in the stack is restored. 12.2.4 overflow flag (v) for signed arithmetic, rotate, and shift operations, the overflow flag is set to 1 when the result is greater than the maximum possible number (>127) or less than the mini- mum possible number ( z8 microcontrollers instruction set zilog 12-6 um001600-z8x0599 12.4 notation and binary encoding in the detailed instruction descriptions that make up the rest of this chapter, operands and status flags are repre- sented by a notational shorthand. operands, condition codes, address modes, and their notations are as follows (table 12-12): table 12-12. notational shorthand notation address mode operand range * cc condition code see condition codes r working register rn n = 0 C 15 r register reg reg. represents a number in the range of 00h to ffh or working register rn n = 0 C 15 rr register pair reg reg. represents an even number in the range of 00h to feh or working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 ir indirect working register @rn n = 0 C15 ir indirect register @reg reg. represents a number in the range of 00h to ffh or indirect working register @rn n = 0C 15 irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to ffh or working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 x indexed reg (rn) reg. represents a number in the range of 00h to ffh and n = 0 C 15 da direct address addrs addrs. represents a number in the range of 00h to ffh ra relative address addrs addrs. represents a number in the range of +127 to C128 which is an offset relative to the address of the next instruction im immediate #data data is a number between 00h to ffh *see the device product specification to determine the exact register file range available. the register file size varies by th e device type. z8 microcontrollers zilog instruction set um001600-z8x0599 12-7 additional symbols used are: assignment of a value is indicated by the symbol . for example, dst dst + src indicates the source data is added to the destination data and the result is stored in the destination location. the notation 'addr(n)' is used to refer to bit'n' of a given lo- cation. for example, dst (7) refers to bit 7 of the destination operand. 12.4.1 assembly language syntax for proper instruction execution, z8 assembly language syntax requires dst, src be specified, in that order. the fol- lowing instruction descriptions show the format of the ob- ject code produced by the assembler. this binary format should be followed by users who prefer manual program coding or who intend to implement their own assembler. example : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: in general, whenever an instruction format requires an 8- bit register address, that address can specify any register location in the range 0 - 255 or a working register r0 - r15. if, in the above example, register 08h is a working register, the assembly syntax and resulting object code would be: note: see the device product specification to determine the exact register file range available. the register file size varies by device type table 12-13. additional symbols symbol de?nition dst destination operand src source operand @ indirect address pre?x sp stack pointer pc program counter flags flag register (fch) rp register pointer (fdh) imr interrupt mask register (fbh) # immediate operand pre?x % hexadecimal number pre?x h hexadecimal number suf?x b binary number suf?x opc opcode asm: add 43h, 08h (add dst, src) obj: 04 08 43 (opc src, dst) asm: add 43h, 08h (add dst, src) obj: 04 08 43 (opc src, dst) z8 microcontrollers instruction set zilog 12-8 um001600-z8x0599 12.5 z8 instruction summary instruction and operation address mode op code byte (hex) flags affected dst src c z s v d h adc dst, src dst ? dst + src +c ? 1[ ] [[[ [ 0 [ add dst, src dst ? dst + src ? 0[ ] [[[ [ 0 [ and dst, src dst ? dst and src ? 5[ ] C [[ 0CC call dst da d6 C C C C C C sp ? sp C 2 irr d4 and pc ? dst or @ sp ? pc ccf ef [ CC CCC c ? not c clr dst r b0 C C C C C C dst ? 0ir b1 com dst r 60 C [[ 0CC dst ? not dst ir 61 cp dst, src ? a[ ] [[[ [ CC dst - src da dst r 40 [[[ xCC dst ? da dst ir 41 dec dst r 00 C [[ [ CC dst ? dst C 1 ir 01 decw dst r r 80 C [[ [ CC dst ? dst C 1 ir 81 di dst 8 f C C C C C C imr(7) ? 0 djnz r, dst ra ra C C C C C C r ? r C 1 r=0-f if r 1 0 pc ? pc + dst range:+127, -128 ei 9 f C C C C C C imr(7) ? 1 halt 7 f C C C C C C inc dst dst ? dst + 1 rreC [[ [ CC r=0-f r20 ir 21 incw dst rr a0 C [[ [ CC dst ? dst + 1 ir a1 instruction and operation address mode op code byte (hex) flags affected dst src c z s v d h iret b f [[[ [[[ flags ? @sp; sp ? sp + 1 pc ? @sp; sp ? sp + 2; and imr(7) C 1 jp cc, dst da cd C C C C C C if cc is true, c = 0 C f then pc ? dst irr 30 jr cc, dst ra cb C C C C C C if cc is true, c = 0 C f pc ? pc + dst range: +127, C128 ld dst, src r im r c C C C C C C dst ? src r r r 8 r r r 9 r = 0 C f rx c 7 xr d 7 rir e 3 ir r f 3 rr e 4 rir e 5 rim e 6 ir im e 7 ir r f 5 ldc dst, src r irr c 2 C C C C C C dst ? src lrr r d 2 ldci dst, src ir irr c 3 C C C C C C dst ? src lrr r d 3 r ? r + 1 or rr ? rr + 1 lde dst, src r irr 82 C C C C C C dst ? src lrr r 92 ldei dst, src r irr c 2 C C C C C C dst ? src and lrr r d 2 r ? r + 1 or rr ? rr + 1 nop ff C C C C C C or dst, src ? 4[ ] C [[ 0CC dst ? dst or src z8 microcontrollers zilog instruction set um001600-z8x0599 12-9 instruction address mode op code byte flags affected and operation dst src (hex) c z s v d h pop dst r 50 CCC CCC dst ? @sp ir 51 and sp ? sp + 1 push src r 70 C C C C C C sp ? sp C 1 ir 71 and @sp ? src rcf c f 0CC CCC c ? 0 ret a f CCC CCC pc ? @sp; sp ? sp + 2 rl dst r ir 90 91 [[[ [ CC rlc dst r ir 10 11 [[[ [ CC rr dst r ir e 0 e 1 [[[ [ CC rrc dst r c 0 [[[ [ CC ir c 1 sbc dst, src ? 3[ ] [[[ [ 1 [ dst ? dst C src C c scf d f 1CC CCC c ? 1 sra dst r d 0 [[[ 0CC ir d 1 srp dst im 31 CCC CCC rp ? src stop 6 f CCC CCC sub dst, src ? 2[ ] [[[ [ 1 [ dst ? dst C src swap dst r ir f0 f1 x [[ xCC c 7 0 c 7 0 c 7 0 c 7 0 c 7 0 7 4 3 0 instruction address mode opcode byte flags affected and operation dst src (hex) c z s v d h tcm dst, src ? 6[ ] C [[ 0CC (not dst) and src tm dst, src ? 7[ ] C [[ 0CC dst and src wdh 4 f C x x x C C wdt 5 f C x x x C C xor dst, src ? 7[ ] C [[ 0CC dst and src xor src note: ? these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is ex- pressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the ad- dressing modes r (destination) and ir (source) is 13. address mode lower dst src op code nibble r r [2] rir [3] r r [4] rir [5] rim [6] ir im [7] z8 microcontrollers instruction set zilog 12-10 um001600-z8x0599 12.5.1 op code map 10.5 cp r , r1 6.5 dec r1 6.5 dec ir1 6.5 add r1, r2 6.5 add r1, ir2 10.5 add r2, r1 10.5 add ir2, r1 10.5 add r1, im 10.5 add ir1, im 0123456789a bcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) bytes per instruction 2 32 31 6.5 rlc r1 6.5 rlc ir1 6.5 adc r1, r2 6.5 adc r1, ir2 10.5 adc r2, r1 10.5 adc ir2, r1 10.5 adc r1, im 10.5 adc ir1, im 6.5 inc r1 6.5 inc ir1 6.5 sub r1, r2 6.5 sub r1, ir2 10.5 sub r2, r1 10.5 sub ir2, r1 10.5 sub r1, im 10.5 sub ir1, im 10.5 decw rr1 10.5 decw ir1 6.5 rl r1 6.5 rl ir1 10.5 incw rr1 10.5 incw ir1 6.5 cp r1, r2 6.5 cp r1, ir2 10.5 cp r2, r1 10.5 cp ir2, r1 10.5 cp r1, im 10.5 cp ir1, im 6.5 clr r1 6.5 clr ir1 6.5 xor r1, r2 6.5 xor r1, ir2 10.5 xor r2, r1 10.5 xor ir2, r1 10.5 xor r1, im 10.5 xor ir1, im 6.5 rrc r1 6.5 rrc ir1 12.0 ldc r1, irr2 18.0 ldci ir1, irr2 10.5 ld r1,x,r2 6.5 sra r1 6.5 sra ir1 20.0 call* irr1 20.0 call da 10.5 ld r2,x,r1 6.5 rr r1 6.5 rr ir1 6.5 ld r1, ir2 10.5 ld r2, r1 10.5 ld ir2, r1 10.5 ld r1, im 10.5 ld ir1, im 8.5 swap r1 8.5 swap ir1 6.5 ld ir1, r2 10.5 ld r2, ir1 6.5 ld r1, r2 6.5 ld r2, r1 12/10.5 djnz r1, ra 12/10.0 jr cc, ra 6.5 ld r1, im 12.10.0 jp cc, da 6.5 inc r1 6.0 stop 7.0 halt 6.1 di 6.1 ei 14.0 ret 16.0 iret 6.5 rcf 6.5 scf 6.5 ccf 6.0 nop 2 4 a lower op code nibble pipeline cycles mnemonic second operand fetch cycles upper op code nibble first operand legend: r = 8-bit address r = 4-bit address r1 or r1 = dst address r2 or r2 = src address sequence: opcode, first operand, second operand note: blank areas are reserved. * 2-byte instruction appears as a 3-byte instruction 8.0 jp irr1 6.1 srp im 6.5 sbc r1, r2 6.5 sbc r1, ir2 10.5 sbc r2, r1 10.5 sbc ir2, r1 10.5 sbc r1, im 10.5 sbc ir1, im 8.5 da r1 8.5 da ir1 6.5 or r1, r2 6.5 or r1, ir2 10.5 or r2, r1 10.5 or ir2, r1 10.5 or r1, im 10.5 or ir1, im 10.5 pop r1 10.5 pop ir1 6.5 and r1, r2 6.5 and r1, ir2 10.5 and r2, r1 10.5 and ir2, r1 10.5 and r1, im 10.5 and ir1, im 6.5 com r1 6.5 com ir1 6.5 tcm r1, r2 6.5 tcm r1, ir2 10.5 tcm r2, r1 10.5 tcm ir2, r1 10.5 tcm r1, im 10.5 tcm ir1, im 10/12.1 push r2 12/14.1 push ir2 6.5 tm r1, r2 6.5 tm r1, ir2 10.5 tm r2, r1 10.5 tm ir2, r1 10.5 tm r1, im 10.5 tm ir1, im 6.0 wdt 6.0 wdh upper nibble (hex) 12.0 ldc lrr1, r2 18.0 ldci lrr1, ir2 12.0 lde r1, lrr2 18.0 ldei lr1, lrr2 12.0 lde r2, lrr1 18.0 ldei lr2, lrr1 z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-11 12.6 instruction description and formats adc add with carry adc add with carry adc dst, src instruction format: operation: dst < dst + src + c the source operand, along with the setting of the carry (c) flag, is added to the destination operand. twos complement addition is performed. the sum is stored in the destination operand. the contents of the source operand are not affected. in multiple precision arithmetic, this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r3 contains 16h, the c flag is set to 1, and working register r11 contains 20h, the statement: adc r3, r11 op code: 12 3b leaves the value 37h in working register r3. the c, z, s, v, d, and h flags are all cleared. flags: c: set if there is a carry from the most signi?cant bit of the result; cleared otherwise. z: set if the result is zero; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if an arithmetic over?ow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared. h: set if there is a carry from the most signi?cant bit of the low order four bits of the result; cleared otherwise. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 12 r r 613 r ir 10 14 r r 10 15 r ir 10 16 r im 10 17 ir im esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-12 um001600-z8x0599 adc add with carry example: if working register r16 contains 16h, the c flag is not set, working register r10 contains 20h, and register 20h contains 11h, the statement: adc r16, @r10 op code: 13 fa leaves the value 27h in working register r16. the c, z, s, v, d, and h flags are all cleared. example if register 34h contains 2eh, the c flag is set, and register 12h contains 1bh, the statement: adc 34h, 12h op code: 14 12 34 leaves the value 4ah in register 34h. the h flag is set, and the c, z, s, v, and d flags are cleared. example: if register 4bh contains 82h, the c flag is set, working register r3 contains 10h, and register 10h contains 01h, the statement: adc 4bh, @r3 op code: 15 e3 4b leaves the value 84h in register 4bh. the s flag is set, and the c, z, v, d, and h flags are cleared. example: if register 6ch contains 2ah, and the c flag is not set, the statement: adc 6ch, #03h op code: 16 6c 03 leaves the value 2dh in register 6ch. the c, z, s, v, d, and h flags are all cleared. example: if register d4h contains 5fh, register 5fh contains 4ch, and the c flag is set, the statement: adc @d4h, #02h op code: 17 d4 02 leaves the value 4fh in register 5fh. the c, z, s, v, d, and h flags are all cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-13 add add add add add dst, src instruction format: operation: dst < dst + src the source operand is added to the destination operand. twos complement addition is performed. the sum is stored in the destination operand. the contents of the source operand are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r3 contains 16h and working register r11 contains 20h, the statement: dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 02 r r 603 r ir 10 04 r r 10 05 r ir 10 06 r im 10 07 ir im flags : c: set if there is a carry from the most signi?cant bit of the result; cleared otherwise. z: set if the result is zero; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if an arithmetic over?ow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared. h: set if there is a carry from the most signi?cant bit of the low order four bits of the result; cleared otherwise. esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-14 um001600-z8x0599 add add add add add dst, src instruction format: operation: dst < dst + src the source operand is added to the destination operand. twos complement addition is performed. the sum is stored in the destination operand. the contents of the source operand are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the opcode. example: if working register r3 contains 16h and working register r11 contains 20h, the statement: add r3, r11 opcode: 02 3b leaves the value 36h in working register r3. the c, z, s, v, d, and h flags are all cleared. flags : c: set if there is a carry from the most signi?cant bit of the result; cleared otherwise. z: set if the result is zero; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if an arithmetic over?ow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared. h: set if there is a carry from the most signi?cant bit of the low order four bits of the result; cleared otherwise. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 02 r r 603 r ir 10 04 r r 10 05 r ir 10 06 r im 10 07 ir im esrc e dst or z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-15 add add example: if working register r16 contains 16h, working register r10 contains 20h, and register 20h contains 11h, the statement: add r16, @r10 op code: 03 fa leaves the value 27h in working register r16. the c, z, s, v, d, and h flags are all cleared. example: if register 34h contains 2eh and register 12h contains 1bh, the statement: add 34h, 12h op code: 04 12 34 leaves the value 49h in register 34h. the h flag is set, and the c, z, s, v, and d flags are cleared. example if register 4bh contains 82h, working register r3 contains 10h, and register 10h contains 01h, the statement: add 3eh, @r3 op code: 05 e3 4b leaves the value 83h in register 4bh. the s flag is set, and the c, z, v, d, and h flags are cleared. example: if register 6ch contains 2ah, the statement: add 6ch, #03h op code: 06 6c 03 leaves the value 2dh in register 6ch. the c, z, s, v, d, and h flags are all cleared. example: if register d4h contains 5fh and register 5fh contains 4ch, the statement: add @d4h, #02h op code: 07 d4 02 leaves the value 4eh in register 5fh. the c, z, s, v, d, and h flags are all cleared. z8 microcontrollers instruction descriptions and formats zilog 12-16 um001600-z8x0599 and logical and and logical and and dst, src instruction format: operation: dst < dst and src the source operand is logically anded with the destination operand. the and operation results in a 1 being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored. the result is stored in the destination operand. the contents of the source bit are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r1 contains 34h (00111000b) and working register r14 contains 4dh (10001101), the statement: and r1, r14 op code: 52 1e dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 52 r r 653 r ir 10 54 r r 10 55 r ir 10 56 r im 10 57 ir im flags : c: unaffected z: set if the result is zero; cleared otherwise s: set if the result of bit 7 is set; cleared otherwise v: always reset to 0 d: unaffected h: unaffected esrc e dst or z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-17 add add add add: add dst, src: instruction format: operation: dst < dst + src the source operand is added to the destination operand. twos complement addition is performed. the sum is stored in the destination operand. the contents of the source operand are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the opcode. example: if working register r3 contains 16h and working register r11 contains 20h, the statement: add r3, r11 opcode: 02 3b leaves the value 36h in working register r3. the c, z, s, v, d, and h flags are all cleared. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 02 r r 603 r ir 10 04 r r 10 05 r ir 10 06 r im 10 07 ir im flags : c: set if there is a carry from the most signi?cant bit of the result; cleared otherwise. z: set if the result is zero; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if an arithmetic over?ow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared. h: set if there is a carry from the most signi?cant bit of the low order four bits of the result; cleared otherwise. esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-18 um001600-z8x0599 and logical and example: if working register r4 contains f9h (11111001b), working register r13 contains 7bh, and register 7bh contains 6ah (01101010b), the statement: and r4, @r13 op code: 53 4d leaves the value 68h (01101000b) in working register r4. the z, v, and s flags are cleared. example: if register 3ah contains the value f5h (11110101b) and register 42h contains the value 0ah (00001010), the statement: and 3ah, 42h op code: 54 42 3a leaves the value 00h (00000000b) in register 3ah. the z flag is set, and the v and s flags are cleared. example: if working register r5 contains f0h (11110000b), register 45h contains 3ah, and register 3ah contains 7fh (01111111b), the statement: and r5, @45h op code: 55 45 e5 leaves the value 70h (01110000b) in working register r5. the z, v, and s flags are cleared. example: if register 7ah contains the value f7h (11110111b), the statement: and 7ah, #f0h op code: 56 7a f0 leaves the value f0h (11110000b) in register 7ah. the s flag is set, and the z and v flags are cleared. example: if working register r3 contains the value 3eh and register 3eh contains the value ech (11101100b), the statement: and @r3, #05h op code: 57 e3 05 leaves the value 04h (00000100b) in register 3eh. the z, v, and s flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-19 call call procedure call call procedure call dst instruction format: operation: sp < sp - 2 @sp < pc pc < dst the stack pointer is decremented by two, the current contents of the program counter (pc) (address of the first instruction following the call instruction) are pushed onto the top of the stack, and the specified destination address is then loaded into the pc. the pc now points to the first instruction of the procedure. at the end of the procedure a ret (return) instruction can be used to return to the original program flow. ret will pop the top of the stack and replace the original value into the pc. note: address mode irr can be used to specify a 4-bit working register pair. in this format, the destination working register pair operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register pair rr12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. dst opc opc dst 20 cycles opc (hex) address mode dst d6 da 20 d4 irr flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-20 um001600-z8x0599 call call procedure example: if the contents of the pc are 1a47h and the contents of the sp (registers feh and ffh) are 3002h, the statement: call 3521h op code: d6 35 21 causes the sp to be decremented to 3000h, 1a4ah (the address following the call instruction) to be stored in external data memory 3000 and 3001h, and the pc to be loaded with 3521h. the pc now points to the address of the first statement in the procedure to be executed. example: if the contents of the pc are 1a47h, the contents of the sp (register ffh) are 72h, the contents of register a4h are 34h, and the contents of register pair 34h are 3521h, the statement: call @a4h op code: d4 a4 causes the sp to be decremented to 70h, 1a4ah (the address following the call instruction) to be stored in r70h and 71h, and the pc to be loaded with 3521h. the pc now points to the address of the first statement in the procedure to be executed. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-21 ccf complement carry flag ccf complement carry flag ccf instruction format: operation: c < not c the c flag is complemented. if c = 1, then it is changed to c = 0; or, if c = 0, then it is changed to c = 1. example: if the c flag contains a 0, the statement: ccf op code: ef will change the c flag from c = 0 to c = 1. opc 6 cycles opc (hex) ef flags : c: complemented z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-22 um001600-z8x0599 clr clear clr clear clr dst instruction format: operation: dst < 0 the destination operand is cleared to 00h. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r6 contains afh, the statement: clr r6 op code: b0 e6 will leave the value 00h in working register r6. if register a5h contains the value 23h, and register 23h contains the value fch, the statement: clr @a5h op code: b1 a5 will leave the value 00h in register 23h. opc dst 6 cycles opc (hex) address mode dst b0 r 6b1 ir flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-23 com complement com complement com dst instruction format: operation: dst < not dst the contents of the destination operand are complemented (ones complement). all 1 bits are changed to 0, and all 0 bits are changed to 1. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if register 08h contains 24h (00100100b), the statement: com 08h op code: 60 08 leaves the value dbh (11011011) in register 08h. the s flag is set, and the z and v flags are cleared. example: if register 08h contains 24h, and register 24h contains ffh (11111111b), the statement: com @08h op code: 61 08 leaves the value 00h (00000000b) in register 24h. the z flag is set, and the v and s flags are cleared. opc dst 6 cycles opc (hex) address mode dst 60 r 661 ir flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: always reset to 0. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-24 um001600-z8x0599 cp compare cp compare cp dst, src instruction format: operation: dst - src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r3 contains 16h and working register r11 contains 20h, the statement: cp r3, r11 op code: a2 3b sets the c and s flags, and the z and v flags are cleared. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src a2 r r 6a3 r ir 10 a4 r r 10 a5 r ir 10 a6 r im 10 a7 ir im flags: c: cleared if there is a carry from the most signi?cant bit of the result. set otherwise indicating a borrow. z: set if the result is zero; cleared otherwise. s: set if result bit 7 is set (negative); cleared otherwise. v: set if arithmetic over?ow occurs; cleared otherwise. d: unaffected h: unaffected esrc e dst or z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-25 cp compare example: if working register r15 contains 16h, working register r10 contains 20h, and register 20h contains 11h, the statement: cp r16, @r10 op code: a3 fa clears the c, z, s, and v flags. example: if register 34h contains 2eh and register 12h contains 1bh, the statement: cp 34h,12h op code: a4 12 34 clears the c, z, s, and v flags. example: if register 4bh contains 82h, working register r3 contains 10h, and register 10h contains 01h, the statement: cp 4bh, @r3 op code: a5 e3 4b sets the s flag, and clears the c, z, and v flags. example: if register 6ch contains 2ah, the statement: cp 6ch, #2ah op code: a6 6c 2a sets the z flag, and the c, s, and v flags are all cleared. example: if register d4h contains fch, and register fch contains 8fh, the statement: cp @d4h, 7fh op code: a7 d4 ff sets the v flag, and the c, z, and s flags are all cleared. z8 microcontrollers instruction descriptions and formats zilog 12-26 um001600-z8x0599 da decimal adjust da decimal adjust da dst instruction format: operation: dst < da dst the destination operand is adjusted to form two 4-bit bcd digits following a binary addition or subtraction operation on bcd encoded bytes. for addition (add and adc) or subtraction (sub and sbc), the following table indicates the operation performed. if the destination operand is not the result of a valid addition or subtraction of bcd digits, the operation is undefined. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for carry bits 7-4 h flag bits 3-0 number carry instruction before value before value added to after da (hex) da (hex) byte da 0 0-9 0 0-9 00 0 0 0-8 0 a-f 06 0 0 0-9 1 0-3 06 0 add 0 a-f 0 0-9 60 1 adc 0 9-f 0 a-f 66 1 0 a-f 1 0-3 66 1 1 0-2 0 0-9 60 1 1 0-2 0 a-f 66 1 1 0-3 1 0-3 66 1 0 0-9 0 0-9 00 0 sub 0 0-8 1 6-f fa 0 sbc 1 7-f 0 0-9 a0 1 1 6-f 1 6-f 9a 1 flags: c: set if there is a carry from the most signi?cant bit; cleared otherwise (see table above). z: set if the result is zero; cleared otherwise. s: set if result bit 7 is set (negative); cleared otherwise. d unaffected h: unaffected opc dst 8 cycles opc (hex) address mode dst 40 r 841 ir z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-27 example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if addition is performed using the bcd value 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic. if the result of the addition is stored in register 5fh, the statement: da 5fh op code: 40 5f adjusts this result so the correct bcd representation is obtained. register 5f now contains the value 42h. the c, z, and s flags are cleared, and v is undefined. example: if addition is performed using the bcd value 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic. register 45f contains the value 5fh, and the result of the addition is stored in register 5fh, the statement: da @45h op code: 40 45 adjusts this result so the correct bcd representation is obtained. register 5f now contains the value 42h. the c, z, and s flags are cleared, and v is undefined. e dst 0001 0101 = 15h +0010 0111 = 27h 0011 1100 = 3ch 0011 1100 = 3ch 0000 0110 = 06h 0100 0010 = 42h 0001 0101 = 15h + 0010 0111 = 27h 0011 1100 = 3ch 0011 1100 = 3ch 0000 0110 = 06h 0100 0010 = 42h z8 microcontrollers instruction descriptions and formats zilog 12-28 um001600-z8x0599 dec decrement dec decrement dec dst instruction format: operation: dst < dst - 1 the contents of the destination operand are decremented by one. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r10 contains 2a%, the statement: dec r10 op code: 00 ea leaves the value 29h in working register r10. the z, v, and s flags are cleared. example: if register b3h contains cbh, and register cbh contains 01h, the statement: dec @b3h op code: 01 b3 leaves the value 00h in register cbh. the z flag is set, and the v and s flags are cleared. opc dst 6 cycles opc (hex) address mode dst 00 r 601 ir flags: c: unaffected z: set if the result is zero; cleared otherwise s: set if the result of bit 7 is set (negative); cleared otherwise v: set if arithmetic over?ow occurs; cleared otherwise d: unaffected h: unaffected e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-29 decw decrement word decw decrement word decw dst instruction format: operation: dst < dst - 1 the contents of the destination (which must be an even address) operand are decremented by one. the destination operand can be a register pair or a working register pair. note: address modes rr or ir can be used to specify a 4-bit working register pair. in this format, the destination working register pair operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register pair r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if register pair 30h and 31h contain the value 0af2h, the statement: decw 30h op code: 80 30 leaves the value 0af1h in register pair 30h and 31h. the z, v, and s flags are cleared. example: if working register r0 contains 30h and register pairs 30h and 31h contain the value faf3h, the statement: decw @r0 op code: 81 e0 leaves the value faf2h in register pair 30h and 31h. the s flag is set, and the z and v flags are cleared. opc dst 10 cycles opc (hex) address mode dst 80 rr 10 81 ir flags: c: unaffected z: set if the result is zero; cleared otherwise s: set if the result of bit 7 is set (negative); cleared otherwise v: set if arithmetic over?ow occurs; cleared otherwise d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-30 um001600-z8x0599 di disable interrupts di disable interrupts dl instruction format: operation: imr (7) < 0 bit 7 of control register fbh (the interrupt mask register) is reset to 0. all interrupts are disabled, although they remain potentially enabled. (for instance, the global interrupt enable is cleared, but not the individual interrupt level enables.) example: if control register fbh contains 8ah (10001010) (interrupts irq1 and irq3 are enabled), the statement: di op code: 8f sets control register fbh to 0ah (00001010b) and disables these interrupts. opc 6 cycles opc (hex) 8f flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-31 djnz decrement and jump if non-zero djnz decrement and jump if non-zero djnz r, dst instruction format: operation: r < r - 1; if r <> 0, pc < pc + dst the specified working register being used as a counter is decremented. if the contents of the specified working register are not zero after decrementing, then the relative address is added to the program counter (pc) and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to C128. the original value of the pc is the address of the instruction byte following the djnz statement. when the specified working register counter reaches zero, control falls through to the statement following the djnz instruction. note: the working register being used as a counter must be one of the registers from 04h to efh. use of one of the i/o ports, control or peripheral registers will have undefined results. example: djnz is typically used to control a loop of instructions. in this example, 12 bytes are moved from one buffer area in the register file to another. the steps involved are: ? load 12 into the counter (working register r6). ? set up the loop to perform the moves. ? end the loop with djnz. the assembly listing required for this routine is as follows: r dst 12 if jump taken cycles opc (hex) address mode dst ra ra 10 if jump not taken (r = 0 to f) opc flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected ld r6, 12 ;load counter loop : ld r9, @r6 ;move one byte to ld @r6, r9 ;new location djnz r6, loop ;decrement and loop until counter = 0 z8 microcontrollers instruction descriptions and formats zilog 12-32 um001600-z8x0599 ei enable interrupts ei enable interrupts ei instruction format: operation: imr (7) < 0 bit 7 of control register fbh (the interrupt mask register) is set to 1. this allows potentially enabled interrupts to become enabled. example: if control register fbh contains 0ah (00001010) (interrupts irq1 and irq3 are selected), the statement: ei op code: 9f sets control register fbh to 8ah (10001010b) and enables irq1 and irq3. opc 6 cycles opc (hex) 9f flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-33 halt halt halt halt halt instruction format: operation: the halt instruction turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and the external interrupts irq1, irq2, and irq3 remain active. the devices are recovered by interrupts, either externally or internally generated. note: in order to enter halt mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. the user must execute a nop immediately before the execution of the halt instruction. example: assuming the z8 is in normal operation, the statements: nop halt op codes: ff 7f place the z8 into halt mode. opc 6 cycles opc (hex) 7f flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-34 um001600-z8x0599 inc increment inc increment instruction format: operation: dst < dst + 1 the contents of the destination operand are incremented by one. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r10 contains 2ah, the statement: inc r10 op code: ae leaves the value 2bh in working register r10. the z, v, and s flags are cleared. example: if register b3h contains cbh, the statement: inc b3h op code: 20 b3 leaves the value cch in register cbh. the s flag is set, and the z and v flags are cleared. example: if register b3h contains cbh and register bch contains ffh, the statement: inc @b3h op code: 21 b3 leaves the value 00h in register cbh. the z flag is set, and the v and s flags are cleared. dst opc opc dst 6 cycles opc (hex) address mode dst re r 620 r 621 ir flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result of bit 7 is set (negative); cleared otherwise. v: set if arithmetic over?ow occurs; cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-35 incw increment word incw increment word incw dst instruction format: operation: dst < dst - 1 the contents of the destination (which must be an even address) operand is decremented by one. the destination operand can be a register pair or a working register pair. note: address modes rr or ir can be used to specify a 4-bit working register pair. in this format, the destination working register pair operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register pair r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code example: if register pairs 30h and 31h contain the value 0af2h, the statement: incw 30h op code: a0 30 leaves the value 0af3h in register pair 30h and 31h. the z, v, and s flags are cleared. example: if working register r0 contains 30h, and register pairs 30h and 31h contain the value faf3h, the statement: incw @r0 op code: a1 e0 leaves the value faf4h in register pair 30h and 31h. the s flag is set, and the z and v flags are cleared. opc dst cycles opc address mode (hex) dst 10 10 10 a0 a1 a0 rr ir r flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result of bit 7 is set (negative); cleared otherwise. v: set if arithmetic over?ow occurs; cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-36 um001600-z8x0599 iret interrupt return iret interrupt return iret instruction format: operation: flags < @sp sp < sp + 1 pc < @sp sp < sp + 2 imr (7) < 1 this instruction is issued at the end of an interrupt service routine. it restores the flag register (control register fch) and the pc. it also re-enables any interrupts that are potentially enabled. example: if stack pointer low register ffh currently contains the value 45h, register 45h contains the value 00h, register 46h contains 6fh, and register 47 contains e4h, the statement: iret op code: bf restores the flag register fch with the value 00h, restores the pc with the value 6fe4h, re-enables the interrupts, and sets the stack pointer low to 48h. the next instruction to be executed will be at location 6fe4h. opc 16 cycles opc (hex) bf flags: c: restored to original setting before the interrupt occurred. z: restored to original setting before the interrupt occurred. s: restored to original setting before the interrupt occurred. v: restored to original setting before the interrupt occurred. d: restored to original setting before the interrupt occurred. h: restored to original setting before the interrupt occurred. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-37 jp jump jp jump jp cc, dst instruction format: operation: if cc (condition code) is true, then pc < dst a conditional jump transfers program control to the destination address if the condition specified by cc (condition code) is true. otherwise, the instruction following the jp instruction is executed. see section 12.3 for a list of condition codes. the unconditional jump simply replaces the contents of the program counter with the contents of the register pair specified by the destination operand. program control then passes to the instruction addressed by the pc. note: address mode irr can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if the carry flag is set, the statement: jp c, 1520h op code: 7d 15 20 replaces the contents of the program counter with 1520h and transfers program control to that location. if the carry flag had not been set, control would have fallen through to the statement following the jp instruction. example: if working register pair rr2 contains the value 3f45h, the statement: jp @rr2 op code: 30 e2 replaces the contents of the pc with the value 3f45h and transfers program control to that location. dst opc opc dst cycles 12 if jump taken 8 10 if not taken opc (hex) address mode dst ccd da 30 irr cc = 0 to f cc flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-38 um001600-z8x0599 jr jump relative jr jump relative jr cc, dst instruction format: operation: if cc is true, pc < pc + dst if the condition specified by the cc is true, the relative address is added to the pc and control passes to the instruction located at the address specified by the pc (see section 12.3 for a list of condition codes). otherwise, the instruction following the jr instruction is executed. the range of the relative address is +127 to C128, and the original value of the pc is taken to be the address of the first instruction byte following the jr instruction. example: if the result of the last arithmetic operation executed is negative, the next four statements (which occupy a total of seven bytes) are skipped with the statement: jr ml, #9 op code: 5b 09 if the result was not negative, execution would have continued with the instruction following the jr instruction. example: a short form of a jump C45 is: jr #C45 op code: 8b d3 the condition code is blank in this case, and is assumed to be always true. dst cycles opc address mode (hex) dst 12 if jump taken 10 if jump not taken ccb cc = 0 to f rr cc opc flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-39 ld load ld load ld dst, src instruction format: operation: dst < src the contents of the source operand are loaded into the destination operand. the contents of the source operand are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. dst opc src 6 cycles opc (hex) address mode dst src rc r im 6 r8 rr opc dst 6 r9 r* r r = 0 to f 6e3 r ir 6f3 ir r opc opc src dst dst src 10 e4 r r 10 e5 r ir 10 e6 r im 10 e7 ir im opc opc src dst src opc dst src opc dst src dst x src x 10 f5 ir r 10 r x 10 d7 x r * in this instance, only a full 8-bit register can be used. c7 flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-40 um001600-z8x0599 ld load example: the statement: ld r15, #34h op code: fc 34 loads the value 34h into working register r15. example: if register 34h contains the value fch, the statement: ld r14, 34h op code: f8 34 loads the value fch into working register r15. the contents of register 34h are not affected. example: if working register r14 contains the value 45h, the statement: ld 34h, r14 op code: e9 34 loads the value 45h into register 34h. the contents of working register r14 are not affected. example: if working register r12 contains the value 34h, and register 34h contains the value ffh, the statement: ld r13, @r12 op code: e3 dc loads the value ffh into working register r13. the contents of working register r12 and register r34 are not affected. example: if working register r13 contains the value 45h, and working register r12 contains the value 00h the statement: ld @r13, r12 op code: f3 dc loads the value 00h into register 45h. the contents of working register r12 and working register r13 are not affected. example: if register 45h contains the value cfh, the statement: ld 34h, 45h op code: e4 45 34 loads the value cfh into register 34h. the contents of register 45h are not affected. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-41 ld load example: if register 45h contains the value cfh and register cfh contains the value ffh, the statement: ld 34h, @45h op code: e5 45 34 loads the value ffh into register 34h. the contents of register 45h and register cfh are not affected. example: the statement: ld 34h, #a4h op code: e6 34 a4 loads the value a4h into register 34h. example: if working register r14 contains the value 7fh, the statement: ld @r14, #fch op code: e7 ee fc loads the value fch into register 7fh. the contents of working register r14 are not affected. example: if register 34h contains the value cfh and register 45h contains the value ffh, the statement: ld @34h, 45h op code: f5 45 34 loads the value ffh into register cfh. the contents of register 34h and register 45h are not affected. example: iif working register r0 contains the value 08h and register 2ch (24h + 08h = 2ch) contains the value 4fh, the statement: ld r10, 24h(r0) op code: c7 a0 24 loads working register r10 with the value 4fh. the contents of working register r0 and register 2ch are not affected. example: if working register r0 contains the value 0bh and working register r10 contains 83h the statement: ld f0h(r0), r10 op code: d7 a0 f0 loads the value 83h into register fbh (f0h + 0bh = fbh). since this is the interrupt mask register, the load statement has the effect of enabling irq0 and irq1. the contents of working registers r0 and r10 are unaffected by the load. z8 microcontrollers instruction descriptions and formats zilog 12-42 um001600-z8x0599 ldc load constant ldc load constant ldc dst, src instruction format: operation: dst < src this instruction is used to load a byte constant from program memory into a working register, or vice versa. the address of the program memory location is specified by a working register pair. the contents of the source operand are not affected. example: if working register pair r6 and r7 contain the value 30a2h and program memory location 30a2h contains the value 22h, the statement: ldc r2, @rr6 op code: c2 26 loads the value 22h into working register r2. the value of program memory location 30a2h is unchanged by the load. example: if working register r2 contains the value 22h, and working register pair r6 and r7 contains the value 10a2h, the statement: ldc @rr6, r2 op code: d2 26 loads the value 22h into program memory location 10a2h. the value of working register r2 is unchanged by the load. note: this instruction format is valid only for mcus which can address external program memory. 12 cycles opc (hex) address mode src dst c2 r irr 12 d2 irr r dst src opc opc dst src flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-43 ldci load constant auto-increment ldci load constant auto-increment ldci dst, src instruction format: operation: dst < src r < r + 1 rr < rr + 1 this instruction is used for block transfers of data between program memory and the register file. the address of the program memory location is specified by a working register pair, and the address of the register file location is specified by working register. the contents of the source location are loaded into the destination location. both addresses in the working registers are then incremented automatically. the contents of the source operand are not affected. example: if working register pair r6-r7 contains 30a2h, program memory location 30a2h and 30a3h contain 22h and bch respectively, and working register r2 contains 20h, the statement: ldci @r2, @rr6 op code: c3 26 loads the value 22h into register 20h. working register pair rr6 is incremented to 30a3h and working register r2 is incremented to 21h. a second ldci @r2, @rr6 op code: c3 26 loads the value bch into register 21h. working register pair rr6 is incremented to 30a4h and working register r2 is incremented to 22h. 18 cycles opc (hex) address mode src dst c3 ir irr 18 d3 irr ir dst src opc opc dst src flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-44 um001600-z8x0599 ldci load constant auto-increment example: if working register r2 contains 20h, register 20h contains 22h, register 21h contains bch, and working register pair r6-r7 contains 30a2h, the statement: ldci @rr6, @r2 op code: d3 26 loads the value 22h into program memory location 30a2h. working register r2 is incremented to 21h and working register pair r6-r7 is incremented to 30a3h. a second ldci @rr6, @r2 op code: d3 26 loads the value bch into program memory location 30a3h. working register r2 is incremented to 22h and working register pair r6-r7 is incremented to 30a4h. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-45 lde load external data lde load external data lde dst, src instruction format: operation: dst < src this instruction is used to load a byte from external data memory into a working register or vice versa. the address of the external data memory location is specified by a working register pair. the contents of the source operand are not affected. example: if working register pair r6 and r7 contain the value 40a2h and external data memory location 40a2h contains the value 22h, the statement: lde r2, @rr6 op code: 82 26 loads the value 22h into working register r2. the value of external data memory location 40a2h is unchanged by the load. example: if working register pair r6 and r7 contain the value 404ah and working register r2 contains the value 22h, the statement: lde @rr6, r2 op code: 92 26 loads the value 22h into external data memory location 404ah note: this instruction format is valid only for mcus which can address external data memory. 12 cycles opc (hex) address mode src dst 82 r irr 12 92 irr r dst src opc opc dst src flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-46 um001600-z8x0599 ldei load external data auto-increment ldei load external data auto-increment ldei dst, src instruction format: operation: dst < src r < r + 1 rr < rr + 1 this instruction is used for block transfers of data between external data memory and the register file. the address of the external data memory location is specified by a working register pair, and the address of the register file location is specified by a working register. the contents of the source location are loaded into the destination location. both addresses in the working registers are then incremented automatically. the contents of the source are not affected. example: if working register pair r6 and r7 contains 404ah, external data memory location 404ah and 404bh contain abh and c3h respectively, and working register r2 contains 22h, the statement: ldei @r2, @rr6 op code: 83 26 loads the value abh into register 22h. working register pair rr6 is incremented to 404bh and working register r2 is incremented to 23h. a second ldei @r2, @rr6 op code: 83 26 loads the value c3h into register 23h. working register pair rr6 is incremented to 404ch and working register r2 is incremented to 24h. 18 cycles opc (hex) address mode src dst 83 ir irr 18 93 irr ir dst src opc opc dst src flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-47 ldei load external data auto-increment example: if working register r2 contains 22h, register 22h contains abh, register 23h contains c3h, and working register pair r6 and r7 contains 404ah, the statement: ldei @rr6, @r2 op code: 93 26 loads the value abh into external data memory location 404ah. working register r2 is incremented to 23h and working register pair rr6 is incremented to 404bh. a second ldei @rr6, @r2 op code: 93 26 loads the value c3h into external data memory location 404bh. working register r2 is incremented to 24h and working register pair rr6 is incremented to 404ch. note: this instruction format is valid only for mcus which can address external data memory. z8 microcontrollers instruction descriptions and formats zilog 12-48 um001600-z8x0599 nop no operation nop no operation nop instruction format: operation no action is performed by this instruction. it is typically used for timing delays or clearing the pipeline. opc 6 cycles opc (hex) ff flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-49 or logical or or logical or or dst, src instruction format: operation: dst < dst or src the source operand is logically ored with the destination operand and the result is stored in the destination operand. the contents of the source operand are not affected. the or operation results in a one bit being stored whenever either of the corresponding bits in the two operands is a one. otherwise, a zero bit is stored. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r1 contains 34h (00111000b) and working register r14 contains 4dh (10001101), the statement: or r1, r14 op code: 42 1e leaves the value bdh (10111101b) in working register r1. the s flag is set, and the z and v flags are cleared. dst src opc opc opc src dst dst src 6 cycles opc (hex) address mode dst src 42 r r 643r ir 10 44 r r 10 45 r ir 10 46 r im 10 47 ir im flags: c: unaffected z: set if the result is zero; cleared otherwise s: set if the result of bit 7 is set; cleared otherwise v: always reset to 0 d: unaffected h: unaffected esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-50 um001600-z8x0599 or logical or example: if working register r4 contains f9h (11111001b), working register r13 contains 7bh, and register 7b contains 6ah (01101010b), the statement: or r4, @r13 op code: 43 4d leaves the value fbh (11111011b) in working register r4. the s flag is set, and the z and v flags are cleared. example: if register 3ah contains the value f5h (11110101b) and register 42h contains the value 0ah (00001010), the statement: or 3ah, 42h op code: 44 42 3a leaves the value ffh (11111111b) in register 3ah. the s flag is set, and the z and v flags are cleared. example: if working register r5 contains 70h (01110000b), register 45h contains 3ah, and register 3ah contains 7fh (01111111b), the statement: or r5, @45h op code: 45 45 e5 leaves the value 7fh (01111111b) in working register r5. the z, v, and s flags are cleared. example: if register 7ah contains the value f3h (11110111b), the statement: or 7ah, #f0h op code: 46 7a f0 leaves the value f3h (11110111b) in register 7ah. the s flag is set, and the z and v flags are cleared. example: if working register r3 contains the value 3eh and register 3eh contains the value 0ch (00001100b), the statement: or @r3, #05h op code: 57 e3 05 leaves the value 0dh (00001101b) in register 3eh. the z, v, and s flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-51 pop pop pop pop pop dst instruction format: operation: dst < @sp sp < sp + 1 the contents of the location specified by the sp (stack pointer) are loaded into the destination operand. the sp is then incremented automatically. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if the sp (control registers feh and ffh) contains the value 70h and register 70h contains 44h, the statement: pop 34h op code: 50 34 loads the value 44h into register 34h. after the pop operation, the sp contains 71h. the contents of register 70 are not affected. example: if the sp (control registers feh and ffh) contains the value 1000h, external data memory location 1000h contains 55h, and working register r6 contains 22h, the statement: pop @r6 op code: 51 e6 loads the value 55h into register 22h. after the pop operation, the sp contains 1001h. the contents of working register r6 are not affected. opc dst 10 cycles opc (hex) address mode dst 50 r 10 51 ir flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-52 um001600-z8x0599 push push push push push src instruction format: operation: sp < sp - 1 @sp < src the contents of the sp (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented sp, thus adding a new element to the stack. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if the sp contains 1001h, the statement: push fch op code: 70 fc stores the contents of register fch (the flag register) in location 1000h. after the push operation, the sp contains 1000h. example: if the sp contains 61h and working register r4 contains fch, the statement: push @r4 op code: 71 e4 stores the contents of register fch (the flag register) in location 60h. after the push operation, the sp contains 60h. opc src cycles opc (hex) address mode dst r ir 10 internal stack 12 external stack 10 internal stack 10 external stack 70 71 flags : c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-53 rcf reset carry flag rcf reset carry flag rcf instruction format: operation: c < 0 the c flag is reset to 0, regardless of its previous value. example: if the c flag is currently set, the statement: rcf op code: cf resets the carry flag to 0. opc 6 cycles opc (hex) cf flags: c: reset to 0 z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-54 um001600-z8x0599 ret return ret return ret instruction format: operation: pc < @sp sp < sp + 2 this instruction is normally used to return from a procedure entered by a call instruction. the contents of the location addressed by the sp are popped into the pc. the next statement executed is the one addressed by the new contents of the pc. the stack pointer is also incremented by two. note: each push instruction executed within the subroutine should be countered with a pop instruction in order to guarantee the sp is at the correct location when the ret instruction is executed. otherwise the wrong address will be loaded into the pc and the program will not operate as desired. example: if sp contains 2000h, external data memory location 2000h contains 18h, and location 2001h contains b5h, the statement: ret op code: af leaves the value 2002h in the sp, and the pc contains 18b5h, the address of the next instruction to be executed. opc 14 cycles opc (hex) af flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-55 rl rotate left rl rotate left rl dst instruction format: operation: c < dst(7) dst(0) < dst(7) dst(1) < dst(0) dst(2) < dst(1) dst(3) < dst(2) dst(4) < dst(3) dst(5) < dst(4) dst(6) < dst(5) dst(7) < dst(6) the contents of the destination operand are rotated left by one bit position. the initial value of bit 7 is moved to the bit 0 position and also into the carry flag. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. opc dst 6 cycles opc (hex) address mode dst 90 r 691 ir d7 d6 d5 d4 d3 d2 d1 d0 c flags: c: set if the bit rotated from the most signi?cant bit position was 1 ( i.e., bit 7 was 1). z: set if the result is zero; cleared otherwise. s: set if the result in bit 7 is set; cleared otherwise. v: set if arithmetic over?ow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-56 um001600-z8x0599 rl rotate left example: if the contents of register c6h are 88h (10001000b), the statement: rl c6h op code: 80 c6 leaves the value 11h (00010001b) in register c6h. the c and v flags are set, and the s and z flags are cleared. example: if the contents of register c6h are 88h, and the contents of register 88h are 44h (01000100b), the statement: rl @c6h op code: 81 c6 leaves the value 88h in register 88h (10001000b). the s and v flags are set, and the c and z flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-57 rlc rotate left through carry rlc rotate left through carry rlc dst instruction format: operation: c< dst(7) dst(0) < c dst(1) < dst(0) dst(2) < dst(1) dst(3) < dst(2) dst(4) < dst(3) dst(5) < dst(4) dst(6) < dst(5) dst(7) < dst(6) the contents of the destination operand along with the c flag are rotated left by one bit position. the initial value of bit 7 replaces the c flag and the initial value of the c flag replaces bit 0. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. opc dst 6 cycles opc (hex) address mode dst 10 r 611 ir d7 d6 d5 d4 d3 d2 d1 d0 c flags: c: set if the bit rotated from the most signi?cant bit position was 1 (i.e., bit 7 was 1). z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic over?ow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-58 um001600-z8x0599 rlc rotate left through carry example: if the c flag is reset and register c6 contains 8f (10001111b), the statement: rlc c6 op code: 10 c6 leaves register c6 with the value 1eh (00011110b). the c and v flags are set, and s and z flags are cleared. example: if the c flag is reset, working register r4 contains c6h, and register c6 contains 8f (10001111b), the statement: rlc @r4 op code: 11 e4 leaves register c6 with the value 1eh (00011110b). the c and v flags are set, and s and z flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-59 rr rotate right rr rotate right rr dst instruction format: operation: c < dst(0) dst(0) < dst(1) dst(1) < dst(2) dst(2) < dst(3) dst(3) < dst(4) dst(4) < dst(5) dst(5) < dst(6) dst(6) < dst(7) dst(7) < dst(0) the contents of the destination operand are rotated to the right by one bit position. the initial value of bit 0 is moved to bit 7 and also into the c flag. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. opc dst 6 cycles opc (hex) address mode dst e0 r 6e1 ir d7 d6 d5 d4 d3 d2 d1 d0 c flags: c: set if the bit rotated from the least signi?cant bit position was 1 ( i.e., bit 0 was 1). z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic over?ow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-60 um001600-z8x0599 rr rotate right example: if the contents of working register r6 are 31h (00110001b), the statement: rr r6 op code: e0 e6 leaves the value 98h (10011000) in working register r6. the c, v, and s flags are set, and the z flag is cleared. example: if the contents of register c6 are 31h and the contents of register 31h are 7eh (01111110b), the statement: rr @c6 op code: e1 c6 leaves the value 4fh (00111111) in register 31h. the c, z, v, and s flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-61 rrc rotate right through carry rrc rotate right through carry rrc dst instruction format: operation: c < dst(0) dst(0) < dst(1) dst(1) < dst(2) dst(2) < dst(3) dst(3) < dst(4) dst(4) < dst(5) dst(5) < dst(6) dst(6) < dst(7) dst(7) < c the contents of the destination operand with the c flag are rotated right by one bit position. the initial value of bit 0 replaces the c flag and the initial value of the c flag replaces bit 7. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. opc dst 6 cycles opc (hex) address mode dst c0 r 6c1 ir d7 d6 d5 d4 d3 d2 d1 d0 c flags: c: set if the bit rotated from the least signi?cant bit position was 1 (i.e., bit 0 was 1). z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic over?ow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d: unaffected h: unaffected e dst z8 microcontrollers instruction descriptions and formats zilog 12-62 um001600-z8x0599 rrc rotate right through carry example: if the contents of register c6h are ddh (11011101b) and the c flag is reset, the statement: rrc c6h op code: c0 c6 leaves the value 6eh (01101110b) in register c6h. the c and v flags are set, and the z and s flags are cleared. example: if the contents of register 2c are edh, the contents of register edh is 00h (00000000b), and the c flag is reset, the statement: rrc @2ch op code: c1 2c leaves the value 02h (00000010b) in register edh. the c, z, s, and v flags are reset. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-63 sbc subtract with carry sbc subtract with carry sbc dst, src instruction format: operation: dst < dst - src - c the source operand, along with the setting of the c flag, is subtracted from the destination operand and the result is stored in the destination operand. the contents of the source operand are not affected. subtraction is performed by adding the twos complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry (borrow) from the subtraction of low order operands to be subtracted from the subtraction of high order operands. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 32 r r 633 r ir 10 34 r r 10 35 r ir 10 36 r im 10 37 ir im flags: c: cleared if there is a carry from the most signi?cant bit of the result; set otherwise, indicating a borrow. z: set if the result is 0; cleared otherwise. v: set if arithmetic over?ow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. s: set if the result is negative; cleared otherwise. h: cleared if there is a carry from the most signi?cant bit of the low order four bits of the result; set otherwise indicating a borrow. d: always set to 1. esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-64 um001600-z8x0599 sbc subtract with carry example: working register r3 contains 16h, the c flag is set to 1, and working register r11 contains 20h, the statement: sbc r3, r11 op code: 32 3b leaves the value f5h in working register r3. the c, s, and d flags are set, and the z, v, and h flags are all cleared. example: if working register r15 contains 16h, the c flag is not set, working register r10 contains 20h, and register 20h contains 11h, the statement: sbc r16, @r10 op code: 33 fa leaves the value 05h in working register r15. the d flag is set, and the c, z, s, v, and h flags are cleared. example :if register 34h contains 2eh, the c flag is set, and register 12h contains 1bh, the statement: sbc 34h, 12h op code: 34 12 34 leaves the value 13h in register 34h. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register 4bh contains 82h, the c flag is set, working register r3 contains 10h, and register 10h contains 01h, the statement: sbc 4bh, @r3 op code: 35 e3 4b leaves the value 80h in register 4bh. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register 6ch contains 2ah, and the c flag is not set, the statement: sbc 6ch, #03h op code: 36 6c 03 leaves the value 27h in register 6ch. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register d4h contains 5fh, register 5fh contains 4ch, and the c flag is set, the statement: sbc @d4h, #02h op code: 37 d4 02 leaves the value 4ah in register 5fh. the d flag is set, and the c, z, s, v, and h flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-65 scf set carry flag scf set carry flag src instruction format: operation: c < 1 the c flag is set to 1, regardless of its previous value. example: if the c flag is currently reset, the statement: scf op code: df sets the carry flag to 1. opc 6 cycles opc (hex) df flags: c: set to 1 z unaffected s unaffected v unaffected d unaffected h unaffected z8 microcontrollers instruction descriptions and formats zilog 12-66 um001600-z8x0599 sra shift right arithmetic sra shift right arithmetic sra dst instruction format: operation: c < dst(0) dst(0) < dst(1) dst(1) < dst(2) dst(2) < dst(3) dst(3) < dst(4) dst(4) < dst(5) dst(5) < dst(6) dst(6) < dst(7) dst(7) < dst(7) an arithmetic shift right by one bit position is performed on the destination operand. bit 0 replaces the c flag. bit 7 (the sign bit) is unchanged and its value is shifted into bit 6. note: address modes r or ir can be used to specify a 4-bit working register. in this format, destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. opc dst 6 cycles opc (hex) address mode dst d0 r 6d1 ir d7 d6 d5 d4 d3 d2 d1 d0 c flags: c: set if the bit rotated from the least signi?cant bit position was 1 (i.e., bit 0 was 1). z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to 0. d: unaffected h: unaffected e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-67 sra shift right arithmetic example: if the contents of working register r6 are 31h (00110001b), the statement: sra r6 op code: d0 e6 leaves the value 98h (00011000) in working register r6. the c flag is set, and the z, v, and s flags are cleared. example: if register c6 contains the value dfh, and register dfh contains the value b8h (10111000b), the statement: sra @c6 op code: d1 c6 leaves the value dch (11011100b) in register dfh. the c, z, and v flags are reset, and the s flag is set. z8 microcontrollers instruction descriptions and formats zilog 12-68 um001600-z8x0599 srp set register pointer srp set register pointer srp src instruction format: operation: rp < src the specified value is loaded into the register pointer (rp) (control register fdh). bits 7-4 determine the working register group. bits 3-0 selects the expanded register bank. addressing of un- implemented working register group, while using expanded register banks, will point to bank 0. example: srp td addresses working register group 7 of bank 0. opc src 6 cycles opc (hex) address mode dst 31 im register pointer working actual (fdh) register group registers contents (bin) (hex) (hex) 1111 0000 f f0-ff 1110 0000 e e0-ef 1101 0000 d d0-df 1100 0000 c c0-cf 1011 0000 b b0-bf 1010 0000 a a0-af 1001 0000 9 90-9f 1000 0000 8 80-8f 0111 0000 7 70-7f 0110 0000 6 60-6f 0101 0000 5 50-5f 0100 0000 4 40-4f 0011 0000 3 30-3f 0010 0000 2 20-2f 0001 0000 1 10-1f 0000 0000 0 00-0f z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-69 srp set register pointer note: when an expanded register bank , other than bank 0 is selected, access to the z8 standard register file is possible except for the port register and general purpose registers 04h to 0fh. fpr register addresses 0h to fh. example: the statement: srp f0h op code: 31 f0 sets the register pointer to access expanded register bank 0 and working register group f in the z8 standard register file. all references to working registers now affect this group of 16 registers. registers f0h to ffh can be accessed as working registers r0 to r15 example: the statement: srp 0fh op code: 31 0f sets the register pointer to access expanded register bank f, reg 00h to reg 0fh, as the current working registers. all references to working registers now affect this group of 16 registers. these registers are now accessed as working registers r0 to r15. port registers are now not accessable. register pointer expanded working (fdh) register bank registers contents (hex) (hex) (dec) xxxx 1111 f r0-r15 xxxx 1110 e r0-r15 xxxx 1101 d r0-r15 xxxx 1100 c r0-r15 xxxx 1011 b r0-r15 xxxx 1010 a r0-r15 xxxx 1001 9 r0-r15 xxxx 1000 8 r0-r15 xxxx 0111 7 r0-r15 xxxx 0110 6 r0-r15 xxxx 0101 5 r0-r15 xxxx 0100 4 r0-r15 xxxx 0011 3 r0-r15 xxxx 0010 2 r0-r15 xxxx 0001 1 r0-r15 xxxx 0000 0 r0-r15 flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-70 um001600-z8x0599 srp set register pointer example: assume the rp currently addresses the control and peripheral working register group and the program has just entered an interrupt service routine. the statement: srp 70h op code: 31 70 retains the contents of the control and peripheral registers by setting the rp to 70h (01110000b). any reference to working registers in the interrupt routine will point to registers 70h to 7fh. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-71 stop stop stop stop stop instruction format: operation: this instruction turns off the internal system clock (sclk) and external crystal (xtal) oscillation, and reduces the standby current. the stop mode is terminated by a reset which causes the processor to restart the application program at address 000ch. note: in order to enter stop mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. the user must execute a nop immediately before the execution of the stop instruction. example: the statements: nop stop op codes: ff 6f place the z8 into stop mode. opc 6 cycles opc (hex) 6f flags: c: unaffected z: unaffected s: unaffected v: unaffected d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-72 um001600-z8x0599 sub subtract sub subtract sub dst, src instruction format: operation: dst < dst - src the source operand is subtracted from the destination operand and the result is stored in the destination operand. the contents of the source operand are not affected. subtraction is performed by adding the twos complement of the source operand to the destination operand. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: ]if working register r3 contains 16h, and working register r11 contains 20h, the statement: sub r3, r11 op code: 22 3b leaves the value f6h in working register r3. the c, s, and d flags are set, and the z, v, and h flags are cleared. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 22 r r 623 r ir 10 24 r r 10 25 r ir 10 26 r im 10 27 ir im flags: c: cleared if there is a carry from the most signi?cant bit of the result; set otherwise, indicating a borrow. z: set if the result is 0; cleared otherwise. v: set if arithmetic over?ow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. s: set if the result is negative; cleared otherwise. h: cleared if there is a carry from the most signi?cant bit of the low order four bits of the result; set otherwise indicating a borrow. d: always set to 1. esrc e dst or z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-73 sub subtract example: if working register r15 contains 16h, working register r10 contains 20h, and register 20h contains 11h, the statement: sub r16, @r10 op code: 23 fa leaves the value 05h in working register r15. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register 34h contains 2eh, and register 12h contains 1bh, the statement: sub 34h, 12h op code: 24 12 34 leaves the value 13h in register 34h. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register 4bh contains 82h, working register r3 contains 10h, and register 10h contains 01h, the statement: sub 4bh, @r3 op code: 25 e3 4b leaves the value 81h in register 4bh. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register 6ch contains 2ah, the statement: sub 6ch, #03h op code: 26 6c 03 leaves the value 27h in register 6ch. the d flag is set, and the c, z, s, v, and h flags are cleared. example: if register d4h contains 5fh, register 5fh contains 4ch, the statement: sub @d4h, #02h op code: 17 d4 02 leaves the value 4ah in register 5fh. the d flag is set, and the c, z, s, v, and h flags are cleared. z8 microcontrollers instruction descriptions and formats zilog 12-74 um001600-z8x0599 swap swap nibbles swap swap nibbles swap dst instruction format: operation: dst(7-4) <> dst(3-0) the contents of the lower four bits and upper four bits of the destination operand are swapped. note: address modes r or ir can be used to specify a 4-bit working register. in this format, destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if register bch contains b3h (10110011b), the statement: swap b3h op code: f0 b3 will leave the value 3bh (00111011b) in register bch. the z and s flags are cleared. example: if working register r5 contains bch and register bch contains b3h (10110011b), the statement: swap @r5h op code: f1 e5 will leave the value 3bh (00111011b) in register bch. the z and s flags are cleared. flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: unde?ned d: unaffected h: unaffected opc dst 6 cycles opc (hex) address mode dst f0 r 6f1 ir e dst z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-75 tcm test complement under mask tcm test complement under mask tcm dst, src instruction format: operation: (not dst) and src this instruction tests selected bits in the destination operand for a logical 1 value. the bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). the tcm instruction complements the destination operand, and then ands it with the source mask (operand). the zero (z) flag can then be checked to determine the result. if the z flag is set, then the tested bits were 1. when the tcm operation is complete, the destination and source operands still contain their original values. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 62 r r 663 r ir 10 64 r r 10 65 r ir 10 66 r im 10 67 ir im flags : c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to 0. d: unaffected h: unaffected esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-76 um001600-z8x0599 tcm test complement under mask example: if working register r3 contains 45h (01000101b) and working register r7 contains the value 01h (00000001b) (bit 0 is being tested if it is 1), the statement: tcm r3, r7 op code: 62 37 will set the z flag indicating bit 0 in the destination operand is 1. the v and s flags are cleared. example: if working register r14 contains the value f3h (11110011b), working register r5 contains cbh, and register cbh contains 88h (10001000b) (bit 7 and bit 3 are being tested if they are 1), the statement: tcm r14, @r5 op code: 63 e5 will reset the z flag, because bit 3 in the destination operand is not a 1. the v and s flags are also cleared. example: if register d4h contains the value 04h (000001000b), and working register r0 contains the value 80h (10000000b) (bit 7 is being tested if it is 1), the statement: tcm d4h, r0 op code: 64 e0 d4 will reset the z flag, because bit 7 in the destination operand is not a 1. the s flag will be set, and the v flag will be cleared. example: if register dfh contains the value ffh (11111111b), register 07h contains the value 1fh, and register 1fh contains the value bdh (10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 1), the statement: tcm dfh, @07h op code: 65 07 df will set the z flag indicating the tested bits in the destination operand are 1. the s and v flags are cleared. example: if working register r13 contains the value f2h (11110010b), the statement: tcm r13, #02h op code: 66 ed, 02 tests bit 1 of the destination operand for 1. the z flag will be set indicating bit 1 in the destination operand was 1. the s and v flags are cleared. example: if register 5dh contains a0h, and register a0h contains 0fh (00001111b), the statement: tcm @5d, #10h op code: 67 5d 10 tests bit 4 of the register a0h for 1. the z flag will be reset indicating bit 1 in the destination operand was not 1. the s and v flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-77 tm test under mask tm test under mask tm dst, src instruction format: operation: dst and src this instruction tests selected bits in the destination operand for a 0 logical value. the bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). the tm instruction ands the destination operand with the source operand (the mask). the zero (z) flag can then be checked to determine the result. if the z flag is set, then the tested bits were 0. when the tm operation is complete, the destination and source operands still contain their original values. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r3 contains 45h (01000101b) and working register r7 contains the value 02h (00000010b) (bit 1 is being tested if it is 0), the statement: tm r3, r7 op code: 72 37 will set the z flag indicating bit 1 in the destination operand is 0. the v and s flags are cleared. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src 72 r r 673 r ir 10 74 r r 10 75 r ir 10 76 r im 10 77 ir im flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to 0. d: unaffected h: unaffected esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-78 um001600-z8x0599 tm test under mask example working register r14 contains the value f3h (11110011b), working register r5 contains cbh, and register cbh contains 88h (10001000b) (bit 7 a bit 3 are being tested if they are 0), the statement: tm r14, @r5 op code: 73 e5 will reset the z flag, because bit 7 iin the destination operand is not a 0. the s flag will be set, and the v flag is cleared. example: if register d4h contains the value 08h (00001000b), and working register r0 contains the value 04h (00000100b) (bit 2 is being tested if it is 0), the statement: tm d4h, r0 op code: 74 e0 d4 will set the z flag, because bit 2 in the destination operand is a 0. the s and v flags will be cleared. example: if register dfh contains the value 00h (00000000b), register 07h contains the value 1fh, and register 1fh contains the value bdh (10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 0), the statement: tm dfh, @07h op code: 75 07 df will set the z flag indicating the tested bits in the destination operand are 0. the s is set, and the v flag is cleared. example: if working register r13 contains the value f1h (11110001b), the statement: tm r13, #02h op code: 76 ed, 02 tests bit 1 of the destination operand for 0. the z flag will be set indicating bit 1 in the destination operand was 0. the s and v flags are cleared. example: if register 5dh contains a0h, and register a0h contains 0fh (00001111b), the statement: tm @5d, #10h op code: 77 5d 10 tests bit 4 of the register a0h for 0. the z flag will be set indicating bit 4 in the destination operand was 0. the s and v flags are cleared. z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-79 wdh watch-dog timer enable during halt mode wdh watch-dog timer enable during halt mode wdh instruction format: operation: when this instruction is executed it will enable the wdt (watch-dog timer) during halt mode. if this instruction is not executed the wdt will stop when entering halt mode. this instruction does not clear the counter, it just makes it possible to have the wdt function running during halt mode. a wdh instruction executed without executing wdt (5fh) has no effect. note: the wdh instruction should not be used following any instruction in which the condition of the flags is important. example: if the wdt is enabled, the statement: wdh op code: .byte 4fh will enable the wdt in halt mode. note: this instruction format is valid only for the z86c04/c08 and z86e04/e07/e08. opc 6 cycles opc (hex) 4f flags: c: unaffected z: unde?ned s: unde?ned v: unde?ned d: unaffected h: unaffected z8 microcontrollers instruction descriptions and formats zilog 12-80 um001600-z8x0599 wdt watch-dog timer wdt watch-dog timer wdt instruction format: operation: the wdt (watch-dog timer) is a retriggerable one shot timer that will reset the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction. each subsequent execution of the wdt instruction refreshes the timer and prevents the wdt from timing out. note: the wdt instruction should not be used following any instruction in which the condition of the flags is important. example: if the wdt is enabled, the statement: wdt op code: .byte 5fh refreshes the watch-dog timer. example: the first execution of the statement: wdt op code: .byte 5fh enables the watch-dog timer. opc 6 cycles opc (hex) 5f flags : c: unaffected z: unde?ned s: unde?ned v: unde?ned d: unaffected h: unaffected z8 microcontrollers zilog instruction descriptions and formats um001600-z8x0599 12-81 xor logical exclusive or xor logical exclusive or xor dst, src instruction format: operation: dst < dst xor src the source operand is logically exclusive ored with the destination operand. the xor operation results in a 1 being stored in the destination operand whenever the corresponding bits in the two operands are different, otherwise a 0 is stored. the contents of the source operand are not affected. note: address modes r or ir can be used to specify a 4-bit working register. in this format, the source or destination working register operand is specified by adding 1110b (eh) to the high nibble of the operand. for example, if working register r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example: if working register r1 contains 34h (00111000b) and working register r14 contains 4dh (10001101b), the statement: xor r1, r14 op code: b2 1e leaves the value bdh (10111101b) in working register r1. the z, and v flags are cleared, and the s flag is set. dst src opc opc opc src dst dst src 6 cycles opc (hex) address dst mode src b2 r r 6b3 r ir 10 b4 r r 10 b5 r ir 10 b6 r im 10 b7 ir im flags: c: unaffected z: set if the result is zero; cleared otherwise. s: set if the result of bit 7 is set; cleared otherwise. v: always reset to 0 d: unaffected h: unaffected esrc e dst or z8 microcontrollers instruction descriptions and formats zilog 12-82 um001600-z8x0599 xor logical exclusive or example if working register r4 contains f9h (11111001b), working register r13 contains 7bh, and register 7b contains 6ah (01101010b), the statement: xor r4, @r13 op code: b3 4d leaves the value 93h (10010011b) in working register r4. the s flag is set, and the z, and v flags are cleared. example: if register 3ah contains the value f5h (11110101b) and register 42h contains the value 0ah (00001010b), the statement: xor 3ah, 42h op code: b4 42 3a leaves the value ffh (11111111b) in register 3ah. the s flag is set, and the c and v flags are cleared. example: if working register r5 contains f0h (11110000b), register 45h contains 3ah, and register 3a contains 7f (01111111b), the statement: xor r5, @45h op code: b5 45 e5 leaves the value 8fh (10001111b) in working register r5. the s flag is set, and the c and v flags are cleared. example: if register 7ah contains the value f7h (11110111b), the statement: xor 7ah, #f0h op code: b6 7a f0 leaves the value 07h (00000111b) in register 7ah. the z, v and s flags are cleared. example: if working register r3 contains the value 3eh and register 3eh contains the value 6ch (01101100b), the statement: xor @r3, #05h op code: b7 e3 05 leaves the value 69h (01101001b) in register 3eh. the z, v, and s flags are cleared. |
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