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| never stop thinking. hyb18t512400af hyb18t512800af hyb18t512160af 512-mbit ddr2 sdram ddr2 sdram rohs compliant products data sheet, rev. 1.3, jan. 2005 memory products
edition 2005-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. never stop thinking. hyb18t512400af hyb18t512800af hyb18t512160af 512-mbit ddr2 sdram ddr2 sdram rohs compliant products data sheet, rev. 1.3, jan. 2005 memory products template: mp_a4_s_rev300 / 2004-11-30 hyb18t512[40/80/16]0af?[3/3s/3.7/5] revision history: 2005-01 rev. 1.3 previous version: 2004-09 (rev. 1.2) page subjects (major changes since last revision) 113 added t ds1 , t dh1 derating for single-ended dqs for ddr2-400 and ddr2-533 all added 50 ohm support all document contains green products only chapter 8 pull-up and pull-down driver characteristics have been updated we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 5 rev. 1.3, 2005-01 09112003-sdm9-iq3p 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 pin configuration and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 tfbga ball out diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 512 mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 programming the mode register and extended mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5 ddr2 sdram mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6 ddr2 sdram extended mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.8 output disable (qoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9 single-ended and differential data strobe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.10 extended mode register emr(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 extended mode register emr(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.12 off-chip driver (ocd) impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.13 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14 bank activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.15 read and write commands and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 3.16 posted cas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.17 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.18 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.19 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.20 write data mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.21 burst interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.22 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.22.1 read followed by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.22.2 write followed by precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.23 auto-precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.23.1 read with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.23.2 write with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.23.3 read or write to precharge command spacing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.23.4 concurrent auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.24 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.24.1 auto-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.24.2 self-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.25 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.26 other commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.26.1 no operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.26.2 deselect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.27 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.28 asynchronous cke low reset event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5 ac & dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table of contents hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 6 rev. 1.3, 2005-01 09112003-sdm9-iq3p 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5 full strength output v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.1 calibrated output driver v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6 reduced output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.7 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.8 power & ground clamp v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6 currents measurement specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.1.1 on die termination (odt) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.1 speed grade defenitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8 ac timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.1 reference load for timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.2 slew rate measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.2.1 output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.2.2 input slew rate - differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.3 input and data setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.3.1 definition for input setup ( t is ) and hold time ( t ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes . . . . . . . . . . . . . . . 106 8.3.3 definition data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes . . . . . . . . . . . . . . 107 8.3.4 slew rate definition for input and data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 product namenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table of contents hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 7 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 1 high performance ddr667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 high performance for ddr2?400b and ddr2?533c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7 512 mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8 mode register definition (ba[2:0] = 000b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9 extended mode register definition (ba[2:0] = 001b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 single-ended and differential data strobe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . 34 table 12 emr(3) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . 35 table 13 off chip driver program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14 off-chip-driver adjust program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17 bank selection for precharge by address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 18 minimum command delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 19 command delay table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 20 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 21 clock enable (cke) truth table for synchronous transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 22 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 23 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 24 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 25 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 26 odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 27 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 28 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 29 single-ended ac input test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 30 differential dc and ac input and output logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 31 sstl_18 output dc current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 32 sstl_18 output ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 33 ocd default characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 34 full strength default pull-up driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 35 full strength default pull?down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36 full strength calibrated pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 37 full strength calibrated pull-up driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 38 reduced strength default pull-up driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 table 39 reduced strength default pull?down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 40 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 41 power & ground clamp v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 42 ac overshoot / undershoot specification for address and control pins . . . . . . . . . . . . . . . . . . . . 89 table 43 ac overshoot / undershoot specification for clock, data, strobe and mask pins . . . . . . . . . . . . 90 table 44 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 45 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 46 i dd specification for ddr2?667c and ddr2-667d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 47 i dd specification for ddr2?533c and ddr2?400b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 48 i dd measurement test conditions for ddr2?667c and ddr2?667d . . . . . . . . . . . . . . . . . . . . . . 95 table 49 i dd measurement test condition for ddr2?533c and ddr2?400b . . . . . . . . . . . . . . . . . . . . . . . 96 table 50 odt current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 51 speed grade definition speed bins for ddr667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 table 52 speed grade definition speed bins for ddr533 and ddr400 . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 53 timing parameter by speed grade - ddr2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 list of tables hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 8 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 54 timing parameter by speed grade - ddr2-400b & ddr2-533c . . . . . . . . . . . . . . . . . . . . . . . 101 table 55 odt ac electrical characteristics and operating conditions for ddr2-667 . . . . . . . . . . . . . . . 104 table 56 odt ac electrical characteristics and op erating conditions for ddr2-533 and ddr2-400 . . . 104 table 57 derating values for input setup and hold time (ddr2-667). . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 58 derating values for input setup and hold time (ddr2-400 & ddr2-533) . . . . . . . . . . . . . . . . . 111 table 59 derating values for data setup and hold time of differential dqs (ddr2-667) . . . . . . . . . . . . 112 table 60 derating values for data setup and hold time of differential dqs (ddr2-400 & -533). . . . . . . 112 table 61 derating values for data setup and hold ti me of single-ended dqs (ddr2-400 & -533). . . . . 113 table 62 nomenclature fields and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 63 ddr2 memory components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 list of tables hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 9 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 1 pin configuration for 4 components, p-tfbga-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 2 pin configuration for 8 components, p-tfbga-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3 pin configuration for 16 components, p-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4 block diagram 32 mbit 4 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5 block diagram 16 mbit 8 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6 block diagram 8 mbit 16 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8 initialization sequence after power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9 ocd impedance adjustment flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10 timing diagram adjust mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11 timing diagram drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12 functional representation of odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13 odt timing for active and standby (idle) modes (synchronous odt timings). . . . . . . . . . . . . . . 41 figure 14 odt timing for precharge power-down and active power-down mode. . . . . . . . . . . . . . . . . . . . 42 figure 15 odt mode entry timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16 odt mode exit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17 bank activate command cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18 read timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19 activate to read timing example: read followed by a write to the same bank . . . . . . . . . . . . . . 47 figure 20 read to write timing example: read followed by a write to the same bank . . . . . . . . . . . . . . . . 47 figure 21 read to write timing example: read followed by a write to the same bank . . . . . . . . . . . . . . . . 48 figure 22 read to write timing example: read followed by a write to the same bank . . . . . . . . . . . . . . . . 48 figure 23 write to read timing example: write followed by a read to the same bank . . . . . . . . . . . . . . . . . 48 figure 24 basic read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25 read operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 26 read operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27 read followed by write example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28 seamless read operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 29 seamless read operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30 basic write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 31 write operation example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 32 write operation example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 33 write followed by read example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 34 seamless write operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 35 seamless write operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 36 write data mask timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 37 write operation with data mask example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 38 read interrupt timing example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 39 write interrupt timing example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 40 read operation followed by precharge example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 41 read operation followed by precharge example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 42 read operation followed by precharge example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 43 read operation followed by precharge example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 44 read operation followed by precharge example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 45 write followed by precharge example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 46 write followed by precharge example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 47 read with auto-precharge example 1, followed by an activation to the same bank ( t rc limit) . . 63 figure 48 read with auto-precharge example 2, followed by an activation to the same bank ( t ras limit) . 63 figure 49 read with auto-precharge example 3, followed by an activation to the same bank . . . . . . . . . . 64 figure 50 read with auto-precharge example 4, followed by an activation to the same bank, . . . . . . . . . . 64 figure 51 write with auto-precharge example 1 ( t rc limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 52 write with auto-precharge example 2 (wr + t rp limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 53 auto refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 list of figures hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram data sheet 10 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 54 self refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 55 active power-down mode entry and exit after an activate command . . . . . . . . . . . . . . . . . . . . . 70 figure 56 active power-down mode entry and exit example after a read command . . . . . . . . . . . . . . . . . 71 figure 57 active power-down mode entry and exit example after a write command . . . . . . . . . . . . . . . . . 71 figure 58 active power-down mode entry and exit example after a write command with ap . . . . . . . . . . 72 figure 59 precharge power down mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 60 auto-refresh command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 61 mrs, emrs command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 figure 62 input frequency change example during precharge power-down mode . . . . . . . . . . . . . . . . . . . 74 figure 63 asynchronous low reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 64 single-ended ac input test conditions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 65 differential dc and ac input and output logic levels diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 66 full strength default pull-up driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 67 full strength default pull?down driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 68 reduced strength default pull-up driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 69 reduced strength default pull?down driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 figure 70 ac overshoot / undershoot diagram for address and control pins . . . . . . . . . . . . . . . . . . . . . . . 90 figure 71 ac overshoot / undershoot diagram for clock, data , strobe and mask pins . . . . . . . . . . . . . . . . 90 figure 72 reference load for timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 73 input setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 74 data setup and hold time (differential data strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 figure 75 data setup and hold time (single ended data strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 76 slew rate definition nominal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 77 slew rate definition tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 78 package pinout pg-tfbga-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 79 package pinout pg-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 list of figures data sheet 11 rev. 1.3, 2005-01 09112003-sdm9-iq3p 512-mbit ddr2 sdram ddr2 sdram hyb18t512400af hyb18t512800af hyb18t512160af 1 overview this chapter gives an overview of the 512-mbit ddr2 sdram product family and describes its main characteristics. 1.1 features the 512-mbit ddr2 sdram offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o ? dram organisations with 4, 8 and 16 data in/outputs ? double data rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation ?cas latency: (2), 3, 4 and 5 ? burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differential data strobes (dqs and dqs ) are transmitted / received with data. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power-down modes ? average refresh period 7.8 s ? full and reduced strength data-output drivers ? 1k page size for 4 & 8, 2k page size for 16 ? packages: p-tfbga-60 for 4 & 8 components p-tfbga-84 for 16 components ? rohs compliant products 1) 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. table 1 high performance ddr667 product type speed code ?3 ?3s unit speed grade ddr2?667c 4?4?4 ddr2?667d 5?5?5 ? max. clock frequency @cl5 f ck5 333 333 mhz @cl4 f ck4 333 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12 15 ns min. row precharge time t rp 12 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57 60 ns hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram overview data sheet 12 rev. 1.3, 2005-01 09112003-sdm9-iq3p 1.2 description the 512-mb ddr2 dram is a high-speed double- data-rate-2 cmos synchronous dram device containing 536,870,912 bits and internally configured as a quad-bank dram. the 512-mb device is organized as either 32 mbit 4i/o 4 banks, 16 mbit 8 i/o 4 banks or 8 mbit 16 i/o 4 banks chip. these synchronous devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 3 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. off-chip driver (ocd) impedance adjustment 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 16-bit address bus for 4 and 8 organised components and a 15-bit address bus for 16 components is used to convey row, column and bank address information in a ras -cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in p-tfbga package. table 2 high performance for ddr2?400b and ddr2?533c product type speed code ?3.7 ?5 unit speed grade ddr2?533c 4?4?4 ddr2?400b 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 40 ns min. row cycle time t rc 60 55 ns data sheet 13 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram overview 1.3 ordering information note: for product nomenclature see chapter 10 of this data sheet table 3 ordering information for rohs compliant products part number org. speed cas 1) rcd 2) rp 3) latencies 1) cas: column adress strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) cas 1) rcd 2) rp 3) latencies clock (mhz) package hyb18t512400af?5 4 ddr2?400 3?3?3 200 ? ? p-tfbga-60 hyb18t512800af?5 8 hyb18t512160af?5 16 p-tfbga-84 hyb18t512400af?3.7 4 ddr2?533 4?4?4 266 3?3?3 200 p-tfbga-60 hyb18t512800af?3.7 8 hyb18t512160af?3.7 16 p-tfbga-84 hyb18t512400af?3 4 ddr2?667 4?4?4 333 3?3?3 200 p-tfbga-60 hyb18t512800af?3 8 hyb18t512160af?3 16 p-tfbga-84 hyb18t512400af?3s 4 5?5?5 333 4?4?4 266 p-tfbga-60 hyb18t512800af?3s 8 hyb18t512160af?3s 16 p-tfbga-84 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 14 rev. 1.3, 2005-01 09112003-sdm9-iq3p 2 pin configuration and block diagrams the pin configuration of a ddr2 sdram is listed by function in table 4 . the abbreviations used in the pin#/buffer type columns are explained in table 5 and table 6 respectively. the pin numbering for the fbga package is depicted in figure 1 for 4, figure 2 for 8 and figure 3 for 16 . table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function clock signals 4/ 8 organizations e8 ck i sstl clock signal ck, complementary clock signal ck note: ck and ck are differential system clock inputs. all address and control inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both direction of crossing) f8 ck isstl f2 cke i sstl clock enable note: cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power- down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entry. input buffers excluding cke are disabled during self-refresh. cke is used asynchronously to detect self-refresh exit condition. self-refresh termination itself is synchronous. after v ref has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck k8 ck isstl k2 cke i sstl clock enable control signals 4/ 8 organizations f7 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) note: ras , cas and we (along with cs ) define the command being entered. g7 cas isstl f3 we isstl g8 cs isstl chip select note: all command are masked when cs is registered high. cs provides for external rank selection on systems with multiple memory ranks. cs is considered part of the command code. data sheet 15 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams control signals 16 organization k7 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas isstl k3 we isstl l8 cs isstl chip select address signals 4/ 8 organizations g2 ba0 i sstl bank address bus 1:0 note: ba[1:0] define to which bank an activate, read, write or precharge command is being applied. ba[1:0] also determines if the mode register or extended mode register is to be accessed during a mrs or emrs(1) cycle g3 ba1 i sstl h8 a0 i sstl address signal 12:0, address signal 10/autoprecharge note: address signal 10/autoprecharge provides the row address for activate commands and the column address and auto- precharge bit a10 (=ap) for read/write commands to select one location out of the memory array in the respective bank. a10(=ap) is sampled during a precharge command to determine whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be precharged, the bank is selected by ba[1:0]. the address inputs also provide the op-code during mode register set commands. h3 a1 i sstl h7 a2 i sstl j2 a3 i sstl j8 a4 i sstl j3 a5 i sstl j7 a6 i sstl k2 a7 i sstl k8 a8 i sstl k3 a9 i sstl h2 a10 i sstl ap i sstl k7 a11 i sstl l2 a12 i sstl l8 a13 i sstl address signal 13 note: 512 mbit components nc ? ? note: 256 mbit components address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ? table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 16 rev. 1.3, 2005-01 09112003-sdm9-iq3p m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals 4/ 8 organizations c8 dq0 i/o sstl data signal 3:0 note: bi-directional data bus. dq[3:0] for 4 components, dq[7:0] for 8 components c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl data signals 8 organization d1 dq4 i/o sstl data signal 7:4 d9 dq5 i/o sstl b1 dq6 i/o sstl b9 dq7 i/o sstl data signals 16 organization table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function data sheet 17 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams g8 dq0 i/o sstl data signal 15:0 note: bi-directional data bus. dq[15:0] for 16 components g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 4 / 8 organisations b7 dqs i/o sstl data strobe note: output with read data, input with write data. edge aligned with read data, centered with write data. for the 16, ldqs corresponds to the data on dq[7:0]; udqs corresponds to the data on dq[15:8]. the datastrobes dqs, ldqs, udqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , udqs and rdqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals a8 dqs i/o sstl data strobe 8 organisations b3 rdqs i sstl read data strobe a2 rdqs isstl read data strobe data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 4 / 8 organizations table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 18 rev. 1.3, 2005-01 09112003-sdm9-iq3p b3 dm i sstl data mask note: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ldm and udm are the input mask signals for 16 components and control the lower or upper bytes. for 8 components the data mask function is disabled, when rdqs/rdqs are enabled by emrs(1) command. data mask 16 organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte power supplies 4/ 8 / 16 organizations a9,c1,c3,c7, c9 v ddq pwr ? i/o driver power supply a1 v dd pwr ? power supply a7,b2,b8,d2, d8 v ssq pwr ? power supply a3,e3 v ss pwr ? power supply power supplies 4/ 8 organizations e2 v ref ai ? i/o reference voltage e1 v ddl pwr ? power supply e9,h9,l1 v dd pwr ? power supply e7 v ssdl pwr ? power supply j1,k9 v ss pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected 4/ 8 organizations g1, l3,l7, l8 nc nc ? not connected note: no internal electrical connection is present not connected 4 organization a2, b1, b9, d1, d9 nc nc ? not connected table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function data sheet 19 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins 4/ 8 organizations f9 odt i sstl on-die termination control note: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs and dm signal for 4 and dq, dqs, dqs , rdqs, rdqs and dm for 8 configurations. for 16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the extended mode register (emrs(1)) is programmed to disable odt. other pins 16 organization k9 odt i sstl on-die termination control table 5 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 6 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 4 pin configur ation of ddr sdram ball#/pin# name pin type buffer type function hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 20 rev. 1.3, 2005-01 09112003-sdm9-iq3p 2.1 tfbga ball out diagrams figure 1 pin configuration for 4 components, p-tfbga-60 (top view) note: 1. v ddl and v ssdl are power and ground for the dll.they are isolated on the device from v dd , v ddq , v ss , and v ssq 2. ball position l8 is a13 for 512-mbit and is not connected on 256-mbit - 0 0 4 # 3 " ! . # . # 6 2 % & ! ! 0 . # ! ! ! ! ! ! . # $ 1 $ - 3 3 6 ! ! ! $ 1 $ 1 3 6 3 3 $ , 6 3 3 1 6 $ $ 1 6 3 3 1 ! . # ! 6 $ $ 1 . # $ 1 . # ! " # $ & ' ( * % , + 6 $ $ 3 3 1 6 6 $ $ 1 $ 1 6 $ $ 1 3 3 1 6 6 $ $ , 3 3 6 7 % # + % # + " ! . # 3 3 6 6 $ $ $ 1 3 # ! 3 6 $ $ 1 6 3 3 1 # + 6 $ $ 2 ! 3 / $ 4 6 $ $ ! 6 . # ! 3 3 data sheet 21 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams figure 2 pin configuration for 8 components, p-tfbga-60 (top view) note: 1. rdqs / rdqs are enabled by emrs(1) command. 2. if rdqs / rdqs is enabled, the dm function is disabled 3. when enabled, rdqs & rdqs are used as strobe signals during reads. 4. v ddl and v ssdl are power and ground for the dll. they are isolated on the device from v dd , v ddq , v ss and v ssq . 5. ball position l8 is a13 for 512-mbit and is not connected on 256-mbit. - 0 0 4 # 3 $ 1 $ 1 " ! 6 . # 2 % & ! ! 0 2 $ 1 3 ! ! ! ! ! ! . # $ 1 $ - 2 $ 1 3 3 3 6 ! ! ! $ 1 $ 1 3 6 3 3 $ , 6 3 3 1 6 $ $ 1 6 3 3 1 ! . # ! 6 $ $ 1 $ 1 $ 1 $ 1 ! " # $ & ' ( * % , + 6 $ $ 3 3 1 6 6 $ $ 1 $ 1 6 $ $ 1 3 3 1 6 6 $ $ , 3 3 6 7 % # + % # + " ! . # 3 3 6 6 $ $ $ 1 3 # ! 3 6 $ $ 1 6 3 3 1 # + 6 $ $ 2 ! 3 / $ 4 6 $ $ ! 6 . # ! 3 3 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 22 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 3 pin configuration for 16 components, p-tfbga-84 (top view) note: 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ddsl are power and ground for the dll. they are isolated on the device from v dd , v ddq , v ss and v ssq . - 0 0 4 6 $ $ . # ! 6 3 3 1 . # 6 3 3 # + % # + 6 3 3 5 $ - $ 1 6 $ $ 1 $ 1 $ 1 6 3 3 6 $ $ , ! 6 3 3 1 $ 1 , $ 1 3 2 ! 3 6 $ $ ! " # $ & ' ( * % , - + . $ 1 6 $ $ " ! " ! ! ! 0 ! 6 3 3 6 $ $ 1 $ 1 $ 1 6 3 3 $ , ! ! ! $ 1 . # 6 $ $ . # 0 2 ! ! ! ! . # 6 3 3 $ 1 6 $ $ 1 6 3 3 1 $ 1 , $ - 6 $ $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 2 % & 7 % . # ! ! 5 $ 1 3 5 $ 1 3 $ 1 6 $ $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 3 3 1 6 $ $ 1 , $ 1 3 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 # + 6 $ $ / $ 4 # ! 3 # 3 6 3 3 1 6 3 3 1 data sheet 23 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams 2.2 512 mbit ddr2 addressing table 7 512 mbit ddr2 addressing configuration 128 mb x 4 64 mb x 8 32 mb x 16 note bank address ba[1:0] ba[1:0] ba[1:0] number of banks 4 4 4 auto-precharge a10 / ap a10 / ap a10 / ap row address a[13:0] a[13:0] a[12:0] column address a11, a[9:0] a[9:0] a[9:0] number of column address bits 11 10 10 1) 1) refered to as ?colbits? number of i/os 4 8 16 2) 2) refered to as ?org? page size [bytes] 1024 (1k) 1024 (1k) 2048 (2k) 3) 3) pagesize = 2 colbits org/8 [bytes hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 24 rev. 1.3, 2005-01 09112003-sdm9-iq3p 2.3 block diagrams figure 4 block diagram 32 mbit 4 i/o 4 internal memory banks note: 1. 128mb 4 organisation with 14 row, 2 bank and 11 column external adresses 2. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 3. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. - 0 " 4 # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o n t r o l , o g i c 2 o w ! d d r e s s - 5 8 ) / ' a t i n g $ - - a s k , o g i c 2 e f r e s h # o u n t e r # o l u m n ! d d r e s s # o u n t e r , a t c h # / , ! d d r e s s 2 e g i s t e r - o d e 2 e g i s t e r s # o m m a n d $ e c o d e 2 ! 3 # ! 3 7 % # 3 # + # + # + % ! ! " ! " ! $ a t a - a s k 7 r i t e & ) & / $ r i v e r s # / , # + # + 2 e c e i v e r s ) n p u t 2 e g i s t e r - 5 8 # / , $ 1 3 ' e n e r a t o r $ r i v e r s $ a t a $ 1 3 $ 1 3 2 e a d , a t c h $ , , # + # + $ 1 3 $ 1 3 $ 1 $ 1 / $ 4 # o n t r o l $ - / $ 4 " a n k " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k " a n k x " a n k " a n k " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r " a n k " a n k # o n t r o l , o g i c data sheet 25 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams figure 5 block diagram 16 mbit 8 i/o 4 internal memory banks note: 1. 64mb 8 organisation with 14 row, 2 bank and 10 column external adresses 2. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 3. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. - 0 " 4 # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o n t r o l , o g i c 2 o w ! d d r e s s - 5 8 ) / ' a t i n g $ - - a s k , o g i c 2 e f r e s h # o u n t e r # o l u m n ! d d r e s s # o u n t e r , a t c h # / , ! d d r e s s 2 e g i s t e r - o d e 2 e g i s t e r s # o m m a n d $ e c o d e 2 ! 3 # ! 3 7 % # 3 # + # + # + % ! ! " ! " ! $ a t a - a s k 7 r i t e & ) & / $ r i v e r s # / , # + # + 2 e c e i v e r s ) n p u t 2 e g i s t e r - 5 8 # / , $ 1 3 ' e n e r a t o r $ r i v e r s $ a t a $ 1 3 $ 1 3 2 e a d , a t c h $ , , # + # + $ 1 3 $ 1 3 $ 1 $ 1 / $ 4 # o n t r o l $ - 2 $ 1 3 2 $ 1 3 / $ 4 " a n k " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k " a n k x " a n k " a n k " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r " a n k " a n k # o n t r o l , o g i c hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram pin configuration and block diagrams data sheet 26 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 6 block diagram 8 mbit 16 i/o 4 internal memory banks note: 1. 32mb 16 organisation with 13 row, 2 bank and 10 column external adresses 2. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 3. ldm, udm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional ldqs and udqs signals. - 0 " 4 # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o n t r o l , o g i c 2 o w ! d d r e s s - 5 8 ) / ' a t i n g $ - - a s k , o g i c 2 e f r e s h # o u n t e r # o l u m n ! d d r e s s # o u n t e r , a t c h # / , ! d d r e s s 2 e g i s t e r - o d e 2 e g i s t e r s # o m m a n d $ e c o d e 2 ! 3 # ! 3 7 % # 3 # + # + # + % ! ! " ! " ! $ a t a - a s k 7 r i t e & ) & / $ r i v e r s # / , # + # + 2 e c e i v e r s ) n p u t 2 e g i s t e r - 5 8 # / , $ 1 3 ' e n e r a t o r $ r i v e r s $ a t a $ 1 3 $ 1 3 2 e a d , a t c h $ , , # + # + 5 $ 1 3 5 $ 1 3 $ 1 $ 1 / $ 4 # o n t r o l 5 $ - , $ - , $ 1 3 , $ 1 3 / $ 4 " a n k " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k " a n k x " a n k " a n k " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r " a n k " a n k # o n t r o l , o g i c data sheet 27 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3 functional description 3.1 simplified state diagram figure 7 simplified state diagram note: this simplified state diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. in particular situations involving more than one bank, enabling / disabling on-die termination, power-down entry / exit, timing restrictions during state transitions - among other things - are not captured in full detail. - 0 & 4 ! u t o m a t i c 3 e q u e n c e # o m m a n d 3 e q u e n c e 0 r e c h a r g i n g 7 r i t i n g w i t h ! 0 0 r e c h a r g e 0 o w e r $ o w n / # $ c a l i b r a t i o n 2 e a d i n g w i t h ! 0 7 2 ! 2 $ ! 7 2 ! 2 $ ! 2 e a d 7 r i t e 0 2 0 2 ! 0 2 0 2 ! 0 2 0 2 ! 2 $ ! 2 e a d 7 r i t e 7 r i t i n g 2 e a d i n g 7 r i t e 2 e a d ! c t i v e 0 o w e r $ o w n " a n k ! c t i v e # + % , # + % ( ! c t i v a t i n g # + % , # + % , % - 2 3 3 e t t i n g - 2 3 o r % - 2 3 ! # 4 0 2 # + % , 3 e l f 2 e f r e s h 3 2 & # + % ( 2 % & # + % , 2 e f r e s h i n g # + % , ) d l e ! l l b a n k s p r e c h a r g e d # + % , # + % ( ) n i t i a l i z a t i o n 3 e q u e n c e hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 28 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.2 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command description and device operation. 3.3 power on and initialization ddr2 sdram?s must be powered up and initialized in a predefined manner. operatio nal procedures other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 v ddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. maximum power up interval for v dd / v ddq is specified as 20.0 ms. the power interval is defined as the amount of time it takes for v dd / v ddq to power-up from 0 v to 1.8 v 100 mv. at least one of these two sets of conditions must be met: ? v dd , v ddl and v ddq are driven from a single power converter output, and ? v tt is limited to 0.95 v max, and ? v ref tracks v ddq /2 or ? apply v dd before or at the same time as v ddl. ? apply v ddl before or at the same time as v ddq. ? apply v ddq before or at the same time as v tt & v ref . 2. start clock (ck, ck ) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands and take cke high. 4. continue nop or deselect commands for 400 ns, then issue a precharge all command. 5. issue emrs(2) command. 6. issue emrs(3) command. 7. issue emrs(1) command to enable dll. 8. issue a mrs command for ?dll reset?. 9. issue precharge-all command. 10. issue 2 or more auto-refresh commands. 11. issue the final mrs command to turn the dll on and to set the necessary operating parameter. 12. at least 200 clocks after step 8, issue emrs(1) commands to either execute the ocd calibration or select the ocd default. issue the final emrs(1) command to exit ocd calibration mode and set the necessary operating parameters. 13. the ddr2 sdram is now ready for normal operation. figure 8 initialization sequence after power up 1st auto refresh ck, ck mrs pre all emrs(3) trp tmrs tmrs cke 400 ns nop odt "low" emrs(2) tmrs emrs(1) tmrs pre all trp trfc 2nd auto refresh trfc extended mode register(1) set with dll enable mode register set with dll reset min. 200 cycles to lock the dll mrs tmrs follow ocd flowchart emrs(1) ocd emrs(1) ocd any command ocd drive(1) or ocd default ocd calibration mode exit mode register set w/o dll reset tmrs data sheet 29 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.4 programming the mode register and extended mode registers for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time (wr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, on die termination (odt), single-ended strobe and off chip driver impedance adjustment (ocd) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) or extended mode registers (emr(1, 2, 3)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mr or emr variables, all variables must be redefined when the mrs or emrs commands are issued. after initial power up, all mrs and emrs commands must be issued before read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. either mrs or emrs commands are activated by the low signals of cs , ras , cas and we at the positive edge of the clock. when both bank addresses ba[1:0] are 0, the ddr2 sdram enables the mrs command. when the bank addresses ba0 is 1 and ba1is 0, the ddr2 sdram enables the emrs(1) command. the address input data during this cycle defines the parameters to be set as shown in the mrs and emrs tables. a new command may be issued after the mode register set command cycle time (t mrd ). mrs, emrs and dll reset do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. 3.5 ddr2 sdram mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs cas latency, burst length, burst sequence, test mode, dll reset, write recovery (wr) and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba[1:0], while controlling the state of address pins a[13:0]. the ddr2 sdram should be in all bank precharged (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time (tmrd) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. the mode register is divided into various fields depending on functionality. burst length is defined by a[2:0] with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a[6:4]. a7 is used for test mode and must be set to 0 for normal dram operation. a8 is used for dll reset. a[11:9] are used for write recovery time (wr) definition for auto-precharge mode. with address bit a12 two power-down modes can be selected, a ?standard mode? and a ?low-power? power-down mode, where the dll is disabled. address bit a13 and all ?higher? address bits have to be set to 0 for compatibility with other ddr2 memory products with higher memory densities. hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 30 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 8 mode register definition (ba[2:0] = 000b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address a13 13 address bus[13] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 , address bit 13 pd 12 w active power-down mode select 0 b pd , fast exit 1 b pd , slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr , 2 010 b wr , 3 011 b wr , 4 100 b wr , 5 110 b wr , 6 dll 8 w dll reset 0 b dll , no 1 b dll , yes tm 7 w test mode 0 b tm , normal mode 1 b tm , vendor specific test mode cl [6:4] w cas latency note: all other bit combinations are illegal. 010 b cl , 2 011 b cl , 3 100 b cl , 4 101 b cl , 5 011 b cl , 6 - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 0 $ 7 2 " , r e g a d d r w w w w w w $ , , 4 - # , " 4 w data sheet 31 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.6 ddr2 sdram extended mode register set (mrs) the extended mode register emr(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register emr(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. the extended mode register is written by asserting low on cs, ras, cas, we, ba1 and high on ba0, while controlling the state of the address pins bt 3 w burst type 0 b bt , sequential 1 b bt , interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl , 4 011 b bl , 8 1) w = write only register bits 2) number of clock cycles for write recovery during auto-precharge. wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . table 8 mode register definition (ba[2:0] = 000b) field bits type 1) description table 9 extended mode register definition (ba[2:0] = 001b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 1 o f f 2 $ 1 3 $ 1 3 / # $ 0 r o g r a m 2 t t ! , 2 t t $ ) # $ , , r e g a d d r w w w w w w w w hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 32 rev. 1.3, 2005-01 09112003-sdm9-iq3p a13 13 w address bus[13] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 , address bit 13 qoff 12 output disable 0 b qoff , output buffers enabled 1 b qoff , output buffers disabled rdqs 11 read data strobe output (rdqs, rdqs) 0 b rdqs , disable 1 b rdqs , enable dqs 10 complement data strobe (dqs output) 0 b dqs , enable 1 b dqs , disable ocd program [9:7] off-chip driver calibration program 000 b ocd , ocd calibration mode exit, maintain setting 001 b ocd , drive (1) 010 b ocd , drive (0) 100 b ocd , adjust mode 111 b ocd , ocd calibration default al [5:3] additive latency note: all other bit combinations are illegal. 000 b al , 0 001 b al , 1 010 b al , 2 011 b al , 3 100 b al , 4 101 b al , 5 r tt 2,6 nominal termination resistance of odt 00 b rtt , (odt disabled) 01 b rtt , 75 ohm 10 b rtt , 150 ohm 11 b rtt , 50 ohm 2) dic 1 off-chip driver impedance control 0 b dic , full (driver size = 100%) 1 b dic , reduced dll 0 dll enable 0 b dll , enable 1 b dll , disable 1) w = write only register bits 2) optional for ddr2-400/533 & 667 table 9 extended mode register definition (ba[2:0] = 001b) field bits type 1) description data sheet 33 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description a0 is used for dll enable or disable. a1 is used for enabling half-strength data-output driver. a2 and a6 enables on-die termination (odt) and sets the rtt value. a[5:3] are used for additive latency settings and a[9:7] enables the ocd impedance adjustment mode. a10 enables or disables the differential dqs and rdqs signals, a11 disables or enables rdqs. address bit a12 have to be set to 0 for normal operation. with a12 set to 1 the sdram outputs are disabled and in hi-z. 1 on ba0 and 0 for ba1 have to be set to access the emrs(1). a13 and all ?higher? address bits have to be set to 0 for compatibility with other ddr2 memory products with higher memory densities. refer to extended mode register definition. 3.7 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self-refresh operation and is automatically re- enabled and reset upon exit of self-refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. 3.8 output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data (qoff bit in the emr(1) is set to 0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure i dd currents during read operations, without including the output buffer current and external load currents. 3.9 single-ended and differential data strobe signals table 10 lists all possible combinations for dqs, dqs , rdqs, rqds which can be programmed by a[11:10] address bits in emrs. rdqs and rdqs are available in 8 components only. if rdqs is enabled in 8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes. table 10 single-ended and differential data strobe signals emrs(1) strobe function matrix signaling a11 (rdqs enable) a10 (dqs enable) rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs rdqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 34 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.10 extended mode register emr(2) the extended mode registers emr(2) and emr(3) are reserved for future use and must be programmed when setting the mode register during initialization.the extended mode register emr(2) is written by asserting low on cs , ras , cas , we , ba0 and high on ba1, while controlling the states of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the emr(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. table 11 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 reg.addr bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba1 15 bank adress[1] 1 b ba1 , bank address ba0 14 bank adress[0] 0 b ba0 , bank address a [13:0] w address bus[13:0] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:0] , address bits - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! r e g a d d r data sheet 35 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.11 extended mode register emr(3) the extended mode register emr(3) is reserved for future use and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. the emrs(3) is written by asserting low on cs, ras, cas, we, ba2 and high on ba0 and ba1, while controlling the state of the address pins. table 12 emr(3) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 reg.addr bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba1 15 bank adress[1] 1 b ba1 , bank address ba0 14 bank adress[0] 1 b ba0 , bank address a [13:0] w address bus[13:0] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:0] , address bits - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! r e g a d d r hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 36 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.12 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) should be carefully controlled depending on system environment. ocd impedance adjustment flow chart figure 9 ocd impedance adjustment flow chart note: mr should be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment - 0 & 4 3 t a r t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t . e e d # a l i b r a t i o n % - 2 3 % n t e r ! d j u s t - o d e " , c o d e i n p u t t o a l l $ 1 s ) n c $ e c o r . / 0 % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 $ r i v e $ 1 $ 1 3 ( i g h $ 1 3 , o w ! , , / + % - 2 3 $ r i v e $ 1 $ 1 3 , o w $ 1 3 ( i g h 4 e s t 4 e s t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 % n t e r ! d j u s t - o d e " , c o d e i n p u t t o a l l $ 1 s ) n c $ e c o r . / 0 . e e d # a l i b r a t i o n % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % n d ! , , / + data sheet 37 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs(1) mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emr(1) bit enabling rdqs operation. in drive(1)mode, all dq, dqs (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. indrive(0) mode, all dq, dqs (and rdqs ) signals are driven low and all dqs (and rdqs) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emr(1) and if half strength is set, ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a[9:7] as?000? in order to maintain the default or calibrated value. ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs(1) command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 in the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maximum step count range. when adjust mode command is issued, al from previously set value must be applied. table 13 off chip driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdq s) high and dqs (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs (rdqs ) high 1 0 0 adjust mode 1 1 1 ocd calibration default table 14 off-chip-driver adjust program 4 bit burst code inputs to all dqs operation dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength 0 000nop (no operation) nop (no operation) 0 001increase by 1 step nop 0 010decrease by 1 step nop 0 100nop increase by 1 step 1 000nop decrease by 1 step 0 101increase by 1 step increase by 1 step 0 110decrease by 1 step increase by 1 step 1 001increase by 1 step decrease by 1 step 1 010decrease by 1 step decrease by 1 step other combinations illegal hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 38 rev. 1.3, 2005-01 09112003-sdm9-iq3p for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds / t dh should be met as shown in figure 10 . input data pattern for adjustment, dt[0:3] is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). burst length of 4 have to be programmed in the mrs for ocd impedance adjustment. figure 10 timing diagram adjust mode drive mode both drive(1) and drive(0) are used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command. see figure 11 . figure 11 timing diagram drive mode nop nop nop nop nop emrs(1) cmd dq_in nop twr dqs_in ck, ck wl emrs(1) nop dm dqs ocd adjust mode ocd calibration mode exit tds tdh dt0 dt1 dt2 dt3 ocd1 nop nop nop nop emrs(1) cmd dq_in nop dqs_in ck, ck emrs(1) nop enter drive mode ocd calibration mode exit nop dqs high & dqs low for drive(1), dqs low & dqs high for drive 0 dqs high for drive(0) dqs high for drive(1) toit toit data sheet 39 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.13 on-die termination (odt) on-die termination (odt) is a new feature on ddr2 components that allows a dram to turn on/off termi- nation resistance for each dq, dqs, dqs , dm for 4 and dq, dqs, dqs , dm, rdqs (dm/rdqs share the same pin) and rdqs for 8 configuration via the odt control pin. dqs and rdqs are only terminated when enabled by emr(1). for 16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resis- tance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self-refresh mode. figure 12 functional representation of odt switch sw1, sw2 or sw3 are enabled by the odt pin. selection between sw1, sw2 or sw3 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target: rval1 = rval2 = rval3 = 2 rtt the odt pin will be ignored if the extended mode register (emrs(1)) is programmed to disable odt. e le a s e c o dram input buffer input pin rval2 rval2 sw2 sw2 vddq vssq rval3 rval3 sw3 sw3 vddq vssq rval1 rval1 sw1 sw1 vddq vssq odt_funct2 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 40 rev. 1.3, 2005-01 09112003-sdm9-iq3p odt truth tables the odt truth table shows which of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs(1) for all three device organisations ( 4, 8 and 16). to activate termination of any of these pins, the odt function has to be enabled in the emrs(1) by address bits a6 and a2. note: x = don?t care; 0 = bit set to low; 1 = bit set to high table 15 odt truth table input pin emrs(1) address bit a10 emrs(1) address bit a11 x4 components dq[3:0] x dqs x dqs 0x dm x x8 components dq[7:0] x dqs x dqs 0x rdqs x 1 rdqs 01 dm x 0 x16 components dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x data sheet 41 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description odt timing modes depending on the operating mode asynchronous or synchronous odt timings apply. asynchronous odt timings ( t aofpd , t aonpd ) apply when the on-die dll is disabled. these modes are: ? slow exit active power down mode (with mrs bit a12 is set to ?1?) ? precharge power down mode synchronous odt timings ( t aond , t aofd , t aon , t aof ) apply for all other modes. figure 13 odt timing for active and standb y (idle) modes (synchronous odt timings) note: 1. synchronous odt timings apply for active mode and standby mode with cke high and for the ?fast exit? active power down mode (mrs bit a12 set to ?0?). in all these modes the on-die dll is enabled. 2. odt turn-on time ( t aon.min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. ( t aon.max ) is when the odt resistance is fully on. both are measured from t aond . 3. odt turn off time min. ( t aof.min ) is when the device starts to turn off the odt resistance.odt turn off time max. ( t aof.max ) is when the bus is in high impedance. both are measured from t aofd . cke dq odt01 odt ck, ck rtt taon(min) taon(max) taof(max) taof(min) taond (2 tck) taofd (2.5 tck) t is t is t0 t1 t2 t3 t4 t5 t6 t7 t8 is t hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 42 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 14 odt timing for precharge power-down and active power-down mode note: asynchronous odt timings apply for precharge power-down mode and ?slow exit? active power down mode (mrs bit a12 set to ?1?), where the on-die dll is disabled in this mode of operation. odt timing mode switch when entering the power down modes ?slow exit? active power down and precharge power down two additional timing parameters ( t anpd and t axpd ) define if synchronous or asynchronous odt timings have to be applied. mode entry as long as the timing parameter t anpd.min is satisfied when odt is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. if t anpd.min is not satisfied, asynchronous timing parameters apply. taofpdmax cke dq odt odt02 ck, ck "low" t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t is t is rtt taonpd,min taofpdmin taonpd,max data sheet 43 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 15 odt mode entry timing diagram cke ck, ck tanpd (3 tck) t0 t1 t2 t-1 t-2 t-3 t-4 t-5 t is odt03 odt turn-off, tanpd >= 3 tck : odt turn-off, tanpd <3 tck : taofd rtt odt t is rtt t is odt taond rtt taonpdmax odt odt turn-on, tanpd >= 3 tck : synchronous timings apply synchronous timings apply asynchronous timings apply taofpdmax odt rtt asynchronous timings apply odt turn-on, tanpd < 3 tck : t is hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 44 rev. 1.3, 2005-01 09112003-sdm9-iq3p mode exit as long as the timing parameter t axpd.min is satisfied when odt is turned on or off after exiting these power- down modes, synchronous timing parameters can be applied. if t axpd.min is not satisfied, asynchronous timing parameters apply. figure 16 odt mode exit timing diagram cke taxpd odt04 odt turn-off, taxpd >= taxpdmin: rtt rtt taonpdmax t0 t1 t5 t6 t7 t8 t is synchronous timings apply t9 odt turn-off, taxpd < taxpdmin: asynchronous timings apply odt taofd rtt odt taofpdmax rtt odt turn-on, taxpd >= taxpdmin: synchronous timings apply taond t is t is odt t is odt t is odt turn-on, taxpd < taxpdmin: asynchronous timings apply t10 ck, ck data sheet 45 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.14 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba[1:0] are used to select the desired bank. the row addresses a0 through a13 are used to determine which row to activate in the selected bank for 4 and 8 organized components. for 16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd.min specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcd.min is satisfied. additive latencies of 0, 1, 2, 3, 4 and 5 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined by t rc . the minimum time interval between bank active commands to different banks is t rrd . figure 17 bank activate command cycle t rcd = 3, al = 2, t rp = 3, t rrd = 2 address nop command t0 t2 t1 t3 t4 col. addr. bank a row addr. bank b col. addr. bank b internal ras-cas delay trcdmin. bank a to bank b delay trrd. activate bank b read a posted cas activate bank a read b posted cas read a begins row addr. bank a addr. bank a precharge bank a nop addr. bank b precharge bank b row addr. bank a activate bank a trp row precharge time (bank a) trc row cycle time (bank a) tn tn+1 tn+2 tn+3 act tras row active time (bank a) additive latency al=2 ck, ck tccd hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 46 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.15 read and write commands and access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles at data rates of up to 533 mb/sec/pin for main memory. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 32 mbit 4 i/o 4 bank chip has a page length of 2048 bits (defined by ca[11, 9:0]). in case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely addressable segments (4-bits 4 i/o each). the 4-bit burst operation will occur entirely within one of the 512 segments (defined by ca[8:0]) starting with the column address supplied to the device during the read or write command (ca[11, 9:0]). the second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. in case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely addressable segments (8-bits 4 i/o each). the 8-bit burst operation will occur entirely within one of the 256 segments (defined by ca[7:0]) beginning with the column address supplied to the device during the read or write command (ca[11, 9:0]). a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay ( t ccd ) is a minimum of 2 clocks for read or write cycles. for 8 bit burst operation (bl = 8) the minimum cas to cas delay ( t ccd ) is 4 clocks for read or write cycles. burst interruption is allowed with 8 bit burst operation. for details see chapter 3.20. figure 18 read timing example cl = 3, al = 0, rl = 3, bl = 4 nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t12 cmd dq rb dq s, dq s read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout c0 dout c1 dout c2 dout c3 nop read c tccd tccd ck, ck data sheet 47 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.16 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immediately after the bank activate command (or any time during the ras to cas delay time, t rcd period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the t rcd.min , then al greater than 0 must be written into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcd.min period, the read latency is also defined as rl = al + cl. figure 19 activate to read timing example: read followed by a write to the same bank activate to read delay < t rcd.min : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 figure 20 read to write timing example: read followed by a write to the same bank activate to read delay < t rcd.min : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 8 activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 dout0 dout1 dout2dout3 din0 din1 din2 din3 bank a read write bank a activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas3 cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 bank a read write bank a din0 din1 din2 din3 dout0 dout1dout2 dout3 dout4 dout5 dout6 dout7 12 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 48 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 21 read to write timing example: read followed by a write to the same bank activate to read delay = t rcd.min : al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 figure 22 read to write timing example: read followed by a write to the same bank activate to read delay > t rcd.min : al = 1, cl = 3, rl = 4, wl = 3, bl = 4 figure 23 write to read timing example: write followed by a read to the same bank al = 2, cl = 3, rl = 5, wl = 4, t wtr = 2, bl = 4 activate bank a bank a write trcd cl = 3 al = 0 rl = al + cl = 3 wl = rl -1 = 2 postcas2 bank a cmd dq dqs, dqs ck, ck 02345 1 67891011 read dout0 dout1 dout2 dout3 din0 din1 din2 din3 activate bank a trcd > trcdmin. rl = 4 wl = 3 postcas5 cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 bank a read dout0 dout1 dout2 dout3 din0 din1 din2 din3 write bank a 12 13 activate bank a trcd > trcdmin. rl = 4 wl = 3 postcas5 cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 bank a read dout0 dout1 dout2 dout3 din0 din1 din2 din3 write bank a 12 13 data sheet 49 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.17 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a[2:0] of the mr. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mr. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see chapter 3.21 . a burst stop command is not supported on ddr2 sdram devices. note: 1. pagesize and length is a function of i/o organization: 128mb x 4 organization (ca[9:0], ca11); page size = 1 kbyte; page length = 2048 64mb x 8 organization (ca[9:0]); page size = 1 kbyte; page length = 1024 32mb x 16 organization (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components table 16 burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 50 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.18 read command the read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs(1)). figure 24 basic read timing diagram figure 25 read operation example 1 rl = 5 (al = 2, cl = 3, bl = 4) dqs, dqs dq dqs dqs t rpre t dqsqmax t rpst t dqsck t ac dout dout dout dout clk, clk clk clk t ch t cl t ck do-read t qh dqsqmax t qh t t lz t hz nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= t dqsck cmd dq bread523 dqs, dqs posted cas ck, ck data sheet 51 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 26 read operation example 2 rl = 3 (al = 0, cl = 3, bl = 8) figure 27 read followed by write example rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the read command to the write command is defined by a read-to-write turn-around time, which is bl/2 + 2 clocks. cmd nop nop nop nop nop nop dq's nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= tdqsck bread303 dq s, dq s dout a4 dout a5 dout a6 dout a7 ck, ck nop posted cas write a nop nop nop nop nop read a posted cas t0 t1 dout a0 dout a1 dout a2 dout a3 rl = 5 nop cmd dq brbw514 t3 t4 t5 t6 t7 t8 t9 din a0 din a1 din a2 din a3 dq s, dq s wl = rl - 1 = 4 bl/2 + 2 ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 52 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 28 seamless read operation example 1 rl = 5, al = 2, cl = 3, bl = 4 the seamless read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. figure 29 seamless read operation example 2 rl = 3, al = 0, cl = 3, bl = 8 (non interrupting) the seamless, non interrupting 8-bit read operation is supported by enabling a read command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. nop nop nop nop nop nop nop read a posted cas read b posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dqs, dqs ck, ck nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 rl = 3 cl = 3 sbr_bl8 cmd dq dqs, dqs read b posted cas dout b0 dout b1 dout b2 dout b3 dout b4 nop nop nop nop nop t9 ck, ck data sheet 53 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.19 write command the write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl ? 1). a data strobe signal (dqs) has to be driven low (preamble) a time t wpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is named ?write recovery time? ( t wr ) and is the time needed to store the write data into the memory array. t wr is an analog timing parameter (see chapter 5 ) and is not the programmed value for wr in the mrs. figure 30 basic write timing figure 31 write operation example 1 rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 dqs, dqs dqs dqs t dqsh t dqsl t wpre wpst t din din din din t ds t dh nop nop nop nop nop precharge nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= t dqss twr completion of the burst write dqs, dqs ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 54 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 32 write operation example 2 rl = 3 (al = 0, cl = 3), wl = 2, bl = 4 figure 33 write followed by read example rl = 5 (al = 2, cl = 3), wl = 4, t wtr = 2, bl = 4 the minimum number of clocks from the write command to the read command is (cl - 1) +bl/2 + t wtr , where t wtr is the write-to-read turn-around time t wtr expressed in clock cycles. the t wtr is not a write recovery time ( t wr ) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 bw322 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write <= t dqss precharge bank a activate trp dqs, dqs ck, ck nop nop nop nop nop read a posted cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop twtr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 write to read = (cl - 1)+ bl/2 +twtr(2) = 6 dqs, dqs wl = rl - 1 = 4 rl=5 ck, ck data sheet 55 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 34 seamless write operation example 1 rl = 5, wl = 4, bl = 4 the seamless write operation is supported by enabling a write command every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. figure 35 seamless write operation example 2 rl = 3, wl = 2, bl = 8, non interrupting the seamless non interrupting 8-bit write operation is supported by enabling a write command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a posted cas wl = rl - 1 = 4 write b posted cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dqs, dqs ck, ck nop nop nop nop nop nop nop write a wl = rl - 1 = 2 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbw_bl8 dqs, dqs write b din a0 din a1 din a2 din a3 din a4 din a5 din a5 din a7 din b0 din b1 din b2 din b3 din b4 din b5 di n ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 56 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.20 write data mask one write data mask input (dm) for 4 and 8 components and two write data mask inputs (ldm, udm) for 16 components are supported on ddr2 sdram?s, consistent with the implementation on ddr sdram?s. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, the write data bit is not written to the memory. for 8 components the dm function is disabled, when rdqs / rdqs are enabled by emrs(1). figure 36 write data mask timing figure 37 write operation with data mask example rl = 3 (al = 0, cl = 3), wl = 2, t wr = 3, bl = 4 - 0 4 4 $ 1 3 $ 1 3 t $ 1 3 ( t $ 1 3 , t 7 0 2 % 7 0 3 4 t $ 1 $ i n $ i n $ i n $ i n t $ 3 $ ( t $ - d o n g t c a r e - 0 4 4 # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 0 r e c h a r g e $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 4 4 7 , 2 , . / 0 " a n k ! ! c t i v a t e . / 0 7 r i t e ! . / 0 t $ 1 3 3 t 7 2 t 2 0 $ - 4 data sheet 57 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.21 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not from the end of the actual burst end. figure 38 read interrupt timing example 1 cl = 3, al = 0, rl = 3, bl = 8 figure 39 write interrupt timing example 2 cl = 3, al = 0, wl = 2, bl = 8 nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b7 nop ck, ck nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dq s, dq s nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 nop write b ck, ck nop hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 58 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.22 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre-charge command can be used to precharge each bank independently or all banks simultaneously. 3 address bits a10, ba[1:0] are used to define which bank to precharge when the command is issued. note: the bank address assignment is the same for activating and precharging a specific bank. 3.22.1 read followed by a precharge the following rules apply as long as the t rtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 mhz (ddr2 400 and 533 speed sorts). minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read command, as long as the minimum t ras timing is satisfied. the term (t rtp - 2 t ck ) is 0 clocks for operating frequencies less or equal 266 mhz (ddr2-400 and ddr2-533 product speed sorts). the term (t rtp - 2 t ck ) is one clock for frequencies higher then 266 mhz (ddr2-667 speed sort). a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the precharge begins. 2. the ras cycle time ( t rc.min ) from the previous bank activation has been satisfied. figure 40 read operation followed by precharge example 1 rl = 4 (al = 1, cl = 3), bl = 4, t rtp 2cks table 17 bank selection for precharge by address bits a10 ba1 ba0 precharge bank(s) 0 0 0 bank 0 only 0 0 1 bank 1 only 0 1 0 bank 2 only 0 1 1 bank 3 only 1 don?t care don?t care all banks nop precharge nop bank a activate nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp ck, ck data sheet 59 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 41 read operation followed by precharge example 2 rl = 4 (al = 1, cl = 3), bl = 8, t rtp 2cks figure 42 read operation followed by precharge example 3 rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2cks nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413(8) nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a activate first 4-bit prefetch second 4-bit prefetch ck, ck nop nop nop bank a activate nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p523 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 3 rl = 5 >=tras cl = 3 trp precharge dqs, dqs >=trc >=trtp ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 60 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 43 read operation followed by precharge example 4 rl=6,(al=2,cl=4),bl=4, t rtp 2cks figure 44 read operation followed by precharge example 5 rl=4,(al=0,cl=4),bl=8, t rtp > 2cks 3.22.2 write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time ( t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see chapter 7 ) and is not the programmed value wr in the mr. nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p624 nop al + bl/2 clocks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 4 rl = 6 >=tras cl = 4 trp precharge a bank a activate dqs, dqs nop nop >=trc >=trtp ck, ck p r e -r e le a nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p404(8) nop a l + b l/2 clks + 1 dout a0 dout a1 dout a2 dout a3 cl = 4 rl = 4 >=tras tr p dqs, dqs nop >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a a ctivate first 4-bit prefetch second 4-bit p refetch ck, ck data sheet 61 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 45 write followed by precharge example 1 wl=(rl-1)=3, bl=4, t wr =3 figure 46 write followed by precharge example 2 wl=(rl -1)=4,bl=4, t wr =3 nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 wl = 3 bw-p3 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 62 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.23 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto- precharge function is enabled. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto- precharge is also implemented for write commands. the precharge operation engaged by the auto- precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge command may be issued with any read or write command. 3.23.1 read with auto-precharge if a10 is 1 when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras.min and t rtp are satisfied. if t ras.min is not satisfied at the edge, the start point of auto-precharge operation will be delayed until t ras.min is satisfied. if t rtp.min is not satisfied at the edge, the start point of auto-precharge operation will be delayed until t rtp.min is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + t rtp + t rp . note that ( t rtp + t rp ) has to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the auto-precharge begins. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. data sheet 63 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 47 read with auto-precharge example 1, followed by an activation to the same bank ( t rc limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 cks figure 48 read with auto-precharge example 2, followed by an activation to the same bank ( t ras limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 cks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dq s, dq s tras trcmin. nop al + bl/2 ck, ck nop nop nop nop b ank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dq s, dq s trc tras(min) nop ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 64 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 49 read with auto-precharge example 3, followed by an activation to the same bank rl = 4 (al = 1, cl = 3), bl = 8, t rtp 2 cks figure 50 read with auto-precharge example 4, followed by an activation to the same bank, rl = 5 (al = 1, cl = 4), bl = 4, t rtp = 3 cks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dq s, dq s nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck p r e -r e l e a nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 1 cl = 4 nop cmd dq br-ap4133 a10 ="high" auto-precharge begins dqs, dqs nop first 4-bit prefetch trtp al + trtp + trp trp ck, ck t8 data sheet 65 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.23.2 write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. 1. the last data-in to bank activate delay time ( t dal = wr + t rp ) has been satisfied. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. in ddr2 sdram?s the write recovery time delay (wr) has to be programmed into the mrs mode register. as long as the analog t wr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + t dal . figure 51 write with auto-precharge example 1 ( t rc limit) wl = 2, t dal = 6 (wr = 3, t rp = 3), bl = 4 figure 52 write with auto-precharge example 2 (wr + t rp limit) wl = 4, t dal = 6 (wr = 3, t rp = 3), bl = 4 nop nop nop nop nop bank a a ctivate nop write w /a p t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dq s, dq s completion of the burst write tdal >=trasmin. ck, ck nop nop nop nop nop bank a a ctivate nop write w/ap posted cas t0 t3 t4 t5 t6 t7 t12 nop cmd dq bw-ap423 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 4 wr >=trc t9 t8 completion of the burst write dq s, dq s tdal >=tras ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 66 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.23.3 read or write to precharge command spacing summary the following table summarizes the minimum command delays between read, read w/ap, write, write w/ap to the precharge commands to the same banks and precharge-all commands. table 18 minimum command delays from command to command minimum delay between ?from command? to ?to command? unit note read precharge (to same banks as read) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) 1) ru{ t rtp (ns) / t ck (ns)} must be used, where ru stands for ?round up? 2) for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-all, issued to that bank. the precharge period is satisfied after t rp,all depending on the latest precharge command issued to that bank precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) read w/ap precharge (to same banks as read w/ap) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) write precharge (to same banks as write) wl + bl/2 + t wr t ck 2) precharge-all wl + bl/2 + t wr t ck 2) write w/ap precharge (to same banks as write w/ap) wl + bl/2 + wr t ck 2) precharge-all wl + bl/2 + wr t ck 2) precharge precharge (to same banks as precharge) 1 t ck 2) precharge-all 1 t ck 2) precharge-all precharge 1 t ck 2) precharge-all 1 t ck 2) data sheet 67 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description 3.23.4 concurrent auto-precharge ddr2 devices support the ?concurrent auto- precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus). the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in the command delay table. as defined, the wl = rl - 1 for ddr2 devices which allows the command gap and corresponding data gaps to be minimized. 3.24 refresh ddr2 sdram requires a refresh of all rows in any rolling 64 ms interval. the necessary refresh can be generated in one of two ways: by explicit auto-refresh commands or by an internally timed self-refresh mode. 3.24.1 auto-refresh command auto-refresh is used during normal operation of the ddr2 sdram?s. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of t refi.max . when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time ( t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto- refresh cycle time ( t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 t refi . table 19 command delay table from command to command (different bank, non-interrupting command) minimum delay with concurrent auto- precharge support unit note write w/ap read or read w/ap (cl -1) + (bl/2) + t wtr t ck write or write w/ap bl/2 t ck precharge or activate 1 t ck 1) 1) this rule only applies to a selective precharge command to another bank, a precharge-all command is illegal read w/ap read or read w/ap bl/2 t ck write or write w/ap bl/2 + 2 t ck precharge or activate 1 t ck 1) hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 68 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 53 auto refresh timing 3.24.2 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self- refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. the device must be in idle state and odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs(1) command. once the command is registered, cke must be held low to keep the device in self-refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self-refresh mode all of the external control signals, except cke, are ?don?t care?. the dram initiates a minimum of one auto refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during self-refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self-refresh exit command is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self-refresh exit period t xsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after t xsnr expires. nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval t xsnr . odt should be turned off during t xsnr . the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop a u to refresh any nop > = t rfc > = t rfc a u to refresh nop nop nop cke "high" data sheet 69 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 54 self refresh timing note: 1. device must be in the ?all banks idle? state before entering self refresh mode. 2. t xsrd ( 200 t ck ) has to be satisfied for a read or a read with auto-precharge command. 3. t xsnr has to be satisfied for any command except a read or a read with auto-precharge command 4. since cke is an sstl input, v ref must be maintained during self refresh. 3.25 power-down power-down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge, auto-precharge or auto-refresh is in progress, but power-down i dd specification will not be applied until finishing those operations. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with any cke intensive operations as long as dram controller complies with dram specifications. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the t xard timing parameter can be used. when a12 is set to high this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-down, but the dll is kept enabled during fast exit active power-down. in power- down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down duration is limited by 9 times t refi of the device. ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr tn tr tm t5 t4 trp tis taofd cmd self refresh entry nop non-read command read command t0 tis tis odt tcke hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 70 rev. 1.3, 2005-01 09112003-sdm9-iq3p power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power- mode after an auto-refresh command or mrs / emrs(1) command when t mrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active power- down mode entry is allowed when wl + bl/2 + t wtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is wl + bl/2 + wr starting from the write with auto- precharge command. in this case the ddr2 sdram enters the precharge power-down mode. power-down exit the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defined in chapter 7.2 . figure 55 active power-down mode entry and exit after an activate command note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. example : active power-down mode entry and exit after read command : rl = 4 (al = 1, cl =3), bl = 4 nop nop activate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit v alid command txard or txards *) ck, ck data sheet 71 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 56 active power-down mode entry and exit example after a read command note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. figure 57 active power-down mode entry and exit example after a write command wl = 2, t wtr =2,bl= 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. c op y nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck read w/ap r e -r e l e a txp nop nop precharge *) t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop tis tn+2 tis precharge power-down exit v alid command trp nop t3 ck, ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 72 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 58 active power-down mode entry and exit example after a write command with ap wl = 2, wr = 3, bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. wr is the programmed value in the mrs mode register. figure 59 precharge power down mode entry and exit note: "precharge" may be an external command or an internal precharge following write with ap. c op y nop nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 wl + bl/2 + wr nop nop act.pd 3 wr tis tn+2 tis valid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 active power-down entry txp nop nop precharge t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop tis tn+2 tis precharge power-down exit valid command trp nop t3 ck, ck data sheet 73 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description figure 60 auto-refresh command to power-down entry figure 61 mrs, emrs command to power-down entry 3.26 other commands 3.26.1 no operation command the no operation command (nop) should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 3.26.2 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. t0 t2 t1 t3 t4 tn cmd cke ck, ck auto refresh arpd trfc tis txp valid command cke can go low one clock after an auto-refresh command when trfc expires the dram is in precharge power-down mode t0 t2 t1 t3 t4 t5 t6 t7 cmd cke ck, ck mrs or emrs mrs_pd t mrd enters precharge power-down mode hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram functional description data sheet 74 rev. 1.3, 2005-01 09112003-sdm9-iq3p 3.27 input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: ? during self-refresh operation ? dram is in precharge power-down mode and odt is completely turned off. in the precharge power-down mode the ddr2- sdram has to be in precharged power-down mode and idle. odt must be already turned off and cke must be at a logic low state. after a minimum of two clock cycles after t rp and t aofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a high logic level again. after t xp has been satisfied a dll reset command via emrs(1) has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll- re-lock period the dram is ready to operate with the new clock frequency. figure 62 input frequency change example during precharge power-down mode 3.28 asynchronous cke low reset event in a given system, asynchronous reset event can occur at any time without prior knowledge. in this situation, memory controller is forced to drop cke asynchronously low, immediately interrupting any valid operation. dram requires cke to be maintained high for all valid operations as defined in this data sheet. if cke asynchronously drops low during any valid operation, the dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised high again. the dram must be fully re-initialized as described the initialization sequence (power on and initialization, step 4 through 13). dram is ready for normal operation after the initialization sequence. see chapter 7 for t delay specification. figure 63 asynchronous low reset event nop nop t0 t2 t1 t3 t4 tx tx+1 ty cmd nop nop nop nop nop dll reset ty+2 ty+3 cke frequency change occurs here nop nop frequ.ch. tz txp stable new clock before power-down exit ck, ck trp taofd minimum 2 clocks required before changing the frequency ty+1 nop v alid command 200 clocks odt is off during dll reset cke cke drops low due to an asynchronous reset event clocks can be turned off after this point tdelay ck, ck stable clocks data sheet 75 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram truth tables 4 truth tables table 20 command truth table function cke cs ras cas we ba0 ba1 a[12:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. previous cycle current cycle (extended) mode register set hhllllbaop code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas, and cke at the rising edge of the clock. 5) bank addresses (bax) determine which bank is to be operated upon. for (e)mrs ba[1:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. see chapter 3.21 for details. write with auto- precharge h h l h l l ba column h column 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto- precharge h h l h l h ba column h column 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements outlined in chapter 3.24 lh h h power down exit l h h x x x x x x x 4)9) lh h h hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram truth tables data sheet 76 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 21 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2) 3) ras , cas , we 2) command (n) is the command registered at clock edge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see chapter 3.24.2 . action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; cke (n-1) was the state of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refresh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) valid commands for power-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 t cke + t ih . self refresh l l x maintain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refresh exit are nop and deselct only. bank(s) active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, precharge or refresh operations are in progress. see chapter 3.25 and chapter 3.24 for a detailed list of restrictions. all banks idle h l deselect or nop precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be entered from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. table 22 data mask (dm) truth table name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1) data sheet 77 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions 5 ac & dc operating conditions 5.1 absolute maximum ratings table 23 absolute maximum ratings symbol parameter rating unit note v dd voltage on v dd pin relative to v ss ?1.0 to +2.3 v 1)2) 1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) v dd , v ddq and v ddl must be within 300 mv of each other at all times, and v ref must not be greater than 0.6 x v ddq . however when v dd , v ddq and v ddl are less than 500 mv, v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 to +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 to +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 to +2.3 v 1) t stg storage temperature ?55 to +100 c 1)3) 3) storage temperature is the case surface temperature on the center/top side of the dram. table 24 dram component operating temperature range symbol parameter rating unit note t oper operating temperature 0 to 95 c 1)2)3)4) 1) operating temperature is the case surface temperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dram case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) self-refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the dram is below 85 c case temperature before initiating self-refresh operation. hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 78 rev. 1.3, 2005-01 09112003-sdm9-iq3p 5.2 dc characteristics table 25 recommended dc operating conditions (sstl_18) symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . table 26 odt dc electrical characteristics parameter / condition symbol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i ( v ihac ) and i ( v ilac ) respectively. rtt(eff) = ( v ih(ac) ? v il(ac) ) /( i ( v ihac ) ? i ( v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage ( v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m / v ddq ) ? 1) x 100% table 27 input and output leakage currents symbol parameter / condition min. max. unit note iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off data sheet 79 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. figure 64 single-ended ac input test conditions diagram table 28 dc & ac logic input levels symbol parameter ddr2-400, ddr2-533 ddr2-667 min. max. min. max. unit v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v ref + 0.200 ? v v il(ac) ac input low ? v ref ? 0.250 ? v ref ? 0.200 v table 29 single-ended ac input test conditions symbol condition value unit note v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 64 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions. v ddq v ih (ac) .min v ih (dc) .min v ref v il (dc) .max v il (ac) .max v ss v swing.max delta tr delta tf start of falling edge input timing start of rising edge input timing v ref - v il (ac).max delta tf falling slew = rising slew = v ih(ac).min - delta tr ref v hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 80 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 65 differential dc and ac input and output logic levels diagram table 30 differential dc and ac input and output logic levels symbol parameter min. max. unit note v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential input signals must cross. crossing point vddq vssq vid vix or vox vtr vcp sstl18_3 data sheet 81 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions 5.4 output buffer characteristics table 31 sstl_18 output dc current drive symbol parameter sstl_18 unit note i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 1.7 v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in 1) and 3) . they are used to test drive current capability to ensure v ih.min . plus a noise margin and v il.max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 2)3) 3) v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. table 32 sstl_18 output ac test conditions symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and vol is different from the referenced load described in chapter 8.1 . the sstl_18 test load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectively 25 ohm termination resistor (13.4 ma 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates into a minimum requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v 1) v otr output timing measurement reference level 0.5 v ddq v table 33 ocd default characteristics symbol description min. nominal max. unit note ? output impedance 12.6 18 23.4 ohms 1)2) 1) absolute specifications ( t oper ; v dd = 1.8 v 0.1 v; v ddq = 1.8 v 0.1 v), altering ocd from default state no longer requires dram to meet timing, voltage and slew rate specifications on i/o?s. 2) impedance measurement condition for output source dc current: v ddq = 1.7 v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement condition for output sink dc current: v ddq = 1.7 v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 ohms 1)2)3) 3) mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 ohms 4) 4) this represents the step size when the ocd is near 18 ohms at nominal conditions across all process parameters and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 1)5)6)7)8) 5) slew rates according to chapter 8.2.1 v il(ac) to v ih(ac) with the load specified in figure 72 . 6) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is verified by design and characterization but not subject to production test. 7) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification. 8) dram output slew rate specification applies to 400, 533 and 667 mhz speed bins. hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 82 rev. 1.3, 2005-01 09112003-sdm9-iq3p 5.5 full strength output v-i characteristics ddr2 sdram output driver characteristics are defined for full strength default operation as selected by the emrs(1) bits a[9:7] =?111?. figure 66 and figure 67 show the driver characteristics graphically and the tables show the same data suitable for input into simulation tools. table 34 full strength default pull-up driver characteristics voltage (v) pull-up driver current [ma] min. 1) 1) the driver characteristics evaluation conditions are minimum 95 c ( t case ), v ddq = 1.7 v, slow?slow process ibis target low 2) 2) the driver characteristics evaluation conditions are nominal default 25 c ( t case ), v ddq = 1.8 v, typical process ibis target high 2) max. 3) 3) the driver characteristics evaluation conditions are maximum 0 c ( t case ). v ddq = 1.9 v, fast?fast process 0.0 0.00 0.00 0.00 0.00 0.1 ?4.30 ?5.55 ?5.90 ?7.95 0.2 ?8.6 ?11.10 ?11.8 ?15.90 0.3 ?12.9 ?16.0 ?17.0 ?23.85 0.4 ?16.9 ?20.3 ?22.2 ?31.80 0.5 ?20.05 ?24.0 ?27.5 ?39.75 0.6 ?22.10 ?27.2 ?32.4 ?47.70 0.7 ?23.27 ?29.8 ?36.9 ?55.55 0.8 ?24.10 ?31.9 ?40.8 ?62.95 0.9 ?24.73 ?33.4 ?44.5 ?69.55 1.0 ?25.23 ?34.6 ?47.7 ?75.35 1.1 ?25.65 ?35.5 ?50.4 ?80.35 1.2 ?26.02 ?36.2 ?52.5 ?84.55 1.3 ?26.35 ?36.8 ?54.2 ?87.95 1.4 ?26.65 ?37.2 ?55.9 ?90.70 1.5 ?26.93 ?37.7 ?57.1 ?93.00 1.6 ?27.20 ?38.0 ?58.4 ?95.05 1.7 ?27.46 ?38.4 ?59.6 ?97.05 1.8 ? ?38.6 ?60.8 ?99.05 1.9 ? ? ? ?101.05 data sheet 83 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions figure 66 full strength default pull-up driver diagram table 35 full strength default pull?down driver characteristics voltage (v) pull-down driver current [ma] min. 1) 1) the driver characteristics evaluation conditions are minimum 95 c ( t case ), v ddq = 1.7 v, slow-slow process nominal default low 2) 2) the driver characteristics evaluation conditions are nominal default 25 c ( t case ), v ddq = 1.8 v, typical process nominal default high 2) max. 3) 3) the driver characteristics evaluation conditions are maximum 0 c ( t case ). v ddq = 1.9 v, fast-fast process 0.0 0.00 0.00 0.00 0.00 0.1 4.30 5.65 5.90 7.95 0.2 8.60 11.30 11.80 15.90 0.3 12.90 16.50 16.80 23.85 0.4 16.90 21.20 22.10 31.80 0.5 20.05 25.00 27.60 39.75 0.6 22.10 28.30 32.40 47.70 0.7 23.27 30.90 36.90 55.05 0.8 24.10 33.00 40.90 62.95 0.9 24.73 34.50 44.60 69.55 1.0 25.23 35.50 47.70 75.35 1.1 25.65 36.10 50.40 80.35 1.2 26.02 36.60 52.60 84.55 1.3 26.35 36.90 54.20 87.95 1.4 26.65 37.10 55.90 90.70 1.5 26.93 37.40 57.10 93.00 1.6 27.20 37.60 58.40 95.05 1.7 27.46 37.70 59.60 97.05 1.8 ? 37.90 60.90 99.05 1.9 ? ? ? 101.05 e c op y 9 ' ' 4 w r 9 2 8 7 9 $ p w q h u u x f s x o o x 3 0 l q l p x p , % , 6 7 d u j h w / r z , % , 6 7 d u j h w + l j k 0 d [ l p x p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 84 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 67 full strength default pull?down driver diagram 5.5.1 calibrated output driver v-i characteristics ddr2 sdram output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the off-chip driver (ocd) impedance adjustment. the table 36 and table 37 show the data in tabular format suitable for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves are represented here or in supplier ibis models need to be adjusted to a wider range as a result of any system calibration error. since this is a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the dram portion of uncertainty while looking at one dq only. if the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters in the specification cannot be guaranteed. it is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. if this can?t be guaranteed by the system calibration procedure, re- calibration policy and uncertainty with dq to dq variation, it is recommended that only the default values to be used. the nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. e c op y 9 2 8 7 w r 9 6 6 4 9 $ p w q h u u x f q z r g o o x 3 0 l q l p x p , % , 6 7 d u j h w / r z , % , 6 7 d u j h w + l j k 0 d [ l p x p data sheet 85 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions table 36 full strength calibrated pull-down driver characteristics voltage (v) calibrated pull-down driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8v, any process nominal 3) (18 ohms) 3) the driver characteristics evaluation conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 table 37 full strength calibrated pull-up driver characteristics voltage (v) calibrated pull-up driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8v, any process nominal (18 ohms) 3) 3) the driver characteristics evaluation conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 86 rev. 1.3, 2005-01 09112003-sdm9-iq3p 5.6 reduced output drive characteristics a driver mode with reduced output drive characteristics can be selected by setting address bit a1 in the emrs(1) extended mode register to 1. table 38 reduced strength default pull-up driver characteristics voltage (v) pull-up driver current [ma] min. 1) 1) the driver characteristics evaluation conditions are minimum 95 c ( t case ), v ddq = 1.7 v, slow?slow process ibis target low 2) 2) the driver characteristics evaluation conditions are nominal default 25 c ( t case ), v ddq = 1.8 v, typical process ibis target high 2) max. 3) 3) the driver characteristics evaluation conditions are maximum 0 c ( t case ). v ddq = 1.9 v, fast?fast process 0.0 0.00 0.00 0.00 0.00 0.1 ?1.72 ?3.20 ?3.70 ?4.77 0.2 ?3.44 ?6.20 ?7.22 ?9.54 0.3 ?5.16 ?9.04 ?10.56 ?14.31 0.4 ?6.76 ?11.69 ?13.75 ?19.08 0.5 ?8.02 ?14.11 ?16.78 ?23.85 0.6 ?8.84 ?16.27 ?19.61 ?28.62 0.7 ?9.31 ?18.16 ?22.20 ?33.33 0.8 ?9.64 ?19.77 ?24.50 ?37.77 0.9 ?9.89 ?21.10 ?26.46 ?41.73 1.0 ?10.09 ?22.15 ?28.07 ?45.21 1.1 ?10.26 ?22.96 ?29.36 ?48.21 1.2 ?10.41 ?23.61 ?30.40 ?50.73 1.3 ?10.54 ?24.61 ?31.24 ?52.77 1.4 ?10.66 ?24.64 ?31.93 ?54.42 1.5 ?10.77 ?25.07 ?32.51 ?55.80 1.6 ?10.88 ?25.47 ?33.01 ?57.03 1.7 ?10.98 ?25.85 ?33.46 ?58.23 1.8 ? ?26.21 ?33.89 ?59.43 1.9 ? ? ? ?60.63 data sheet 87 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions figure 68 reduced strength default pull-up driver diagram table 39 reduced strength default pull?down driver characteristics voltage (v) pull-down driver current [ma] min. 1) 1) the driver characteristics evaluation conditions are minimum 95 c ( t case ), v ddq = 1.7 v, slow-slow process ibis target low 2) 2) the driver characteristics evaluation conditions are nominal default 25 c ( t case ), v ddq = 1.8 v, typical process ibis target high 2) max. 3) 3) the driver characteristics evaluation conditions are maximum 0 c ( t case ). v ddq = 1.9 v, fast-fast process 0.0 0.00 0.00 0.00 0.00 0.1 1.72 3.24 4.11 4.77 0.2 3.44 6.25 8.01 9.54 0.3 5.16 9.03 11.67 14.31 0.4 6.76 11.52 15.03 19.08 0.5 8.02 13.66 18.03 23.85 0.6 8.84 15.41 20.61 28.62 0.7 9.31 16.77 22.71 33.33 0.8 9.64 17.74 24.35 37.77 0.9 9.89 18.83 25.56 41.73 1.0 10.09 18.80 26.38 45.21 1.1 10.26 19.06 26.90 48.21 1.2 10.41 19.23 27.24 50.73 1.3 10.54 19.35 27.47 52.77 1.4 10.66 19.46 27.64 54.42 1.5 10.77 19.56 27.78 55.80 1.6 10.88 19.65 27.89 57.03 1.7 10.98 19.73 27.97 58.23 1.8 ? 19.80 28.02 59.43 1.9 ? ? ? 60.63 s e c op y -80,00 -60,00 -40,00 -20,00 0,00 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vddq to vout (v) pull-up current (ma) minimum ibis target low ibis target high maximum hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 88 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 69 reduced strength default pull?down driver diagram 5.7 input / output capacitance table 40 input / output capacitance symbol parameter ddr2-400 & ddr-2-533 ddr2-667 unit min. max. min. max. cck input capacitance, ck and ck 1.0 2.0 1.0 2.0 pf cdck input capacitance delta, ck and ck ? 0.25 ? 0.25 pf ci input capacitance, all other input-only pins 1.0 2.0 1.0 2.0 pf cdi input capacitance delta, all other input-only pins ? 0.25 ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 4.0 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?0.5 ?0.5 pf s e c op y 0 10 20 30 40 50 60 70 80 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vout to vssq (v) pull - down current (ma) minimum nominal default low no maximum 0 10 20 30 40 50 60 70 80 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vout to vssq (v) pull-down current (ma) minimum ibis target low ibis target high maximum data sheet 89 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions 5.8 power & ground clamp v-i characteristics power and ground clamps are provided on address (a[13:0], ba[11:0]), ras , cas , cs , we , and odt pins. the v-i characteristics for pins with clamps is shown in table 41 . 5.9 overshoot and undershoot specification table 41 power & ground clamp v-i characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 table 42 ac overshoot / undershoot specification for address and control pins parameter ddr2-400 ddr2-533 dd2-667 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v dd 1.33 1.00 0.80 v.ns maximum undershoot area below v ss 1.33 1.00 0.80 v.ns hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac & dc operating conditions data sheet 90 rev. 1.3, 2005-01 09112003-sdm9-iq3p figure 70 ac overshoot / undershoot diagram for address and control pins figure 71 ac overshoot / undershoot diagram for clock, data, strobe and mask pins table 43 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2-400 ddr2-533 dd2-667 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.28 0.23 v.ns maximum undershoot area below v ssq 0.38 0.28 0.23 v.ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) data sheet 91 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions 6 currents measurement specifications and conditions table 44 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd0 1)2)3)4)5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4)5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs are stable; data bus inputs are floating . i dd2p 1)2)3)4)5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4)5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4)5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4)5)6) operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4)5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4)5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b 1)2)3)4)5)6) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4)5)6) hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions data sheet 92 rev. 1.3, 2005-01 09112003-sdm9-iq3p self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 1)2)3)4)5)6) operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. 2. timing pattern: ddr2-400-333: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d (11 clocks) ddr2-533-333: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d (15 clocks) ddr2-533-444: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d (16 clocks) ddr2-667-444: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d (19 clocks) ddr2-667-555: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d (20 clocks) i dd7 1)2)3)4)5)6)7) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : see table 2 6) timing parameter minimum and maximum values for i dd current measurements are defined in chapter 7.. 7) a = activate, ra = read with auto-precharge, d=deselect table 45 definition for i dd parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes table 44 i dd measurement conditions parameter symbol note data sheet 93 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions table 46 i dd specification for ddr2?667c and ddr2-667d product type speed code ?3 ?3s unit note speed grade ddr2?667c ddr2?667d symbol max. max. i dd0 75 71 ma 4/ 8 95 90 16 i dd1 90 85 ma 4/ 8 110 104 16 i dd2n 50 50 ma i dd2p 55ma i dd2q 40 40 ma i dd3n 50 50 ma i dd3p 19 19 ma 1) 4/ 8 1) mrs(12)=0 66ma 2) 16 2) mrs(12)=1 i dd4r 130 130 ma 4/ 8 150 150 ma 16 i dd4w 140 140 ma 4/ 8 170 170 ma 16 i dd5b 140 140 ma 3) 3) 0 t case 85 c i dd5d 66ma 3) i dd6 55ma 3)4) 4) standard products i dd7 155 147 ma 4/ 8 240 228 ma 16 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions data sheet 94 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 47 i dd specification for ddr2?533c and ddr2?400b product type speed code ?3.7 ?5 unit note speed grade ddr2?533c ddr2?400b symbol max. max. i dd0 65 55 ma 4/ 8 80 70 ma 16 i dd1 75 60 ma 4/ 8 90 75 ma 16 i dd2n 40 32 ma i dd2p 44ma i dd2q 30 25 ma i dd3n 40 35 ma i dd3p 16 13 ma 1) 4/ 8 1) mrs(12)=0 55ma 2) 16 2) mrs(12)=1 i dd4r 90 70 ma 4/ 8 100 85 ma 16 i dd4w 95 75 ma 4/ 8 110 90 ma 16 i dd5b 130 120 ma 3) 3) 0 t case 85 c i dd5d 66ma 3) i dd6 44ma 3)4) 4) standard products i dd7 140 130 ma 4/ 8 220 210 ma 16 data sheet 95 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions 6.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: table 48 i dd measurement test conditions for ddr2?667c and ddr2?667d parameter symbol ?3 ?3s unit note ddr2?667c 4?4?4 ddr2?667d 5?5?5 cas latency cl (idd) 45 t ck clock cycle time t ck(idd) 33 ns active to read or write delay t rcd(idd) 12 15 ns active to active / auto-refresh command period t rc(idd) 57 60 ns active bank a to active bank b command delay t rrd(idd) 7.5 7.5 ns 1) 1) 4 & 8 (1 kb page size) t rrd(idd) 10 10 ns 2) 2) 16 (2 kb page size); not on 256m component active to precharge command t ras.min(idd) 45 45 ns t ras.max(idd) 70000 70000 ns precharge command period t rp(idd) 12 15 ns auto-refresh to active / auto-refresh command period t rfc(idd) 75 75 ns auto-refresh to active / auto-refresh command period t rfc(idd) 105 105 ns average periodic refresh interval t refi 7.8 7.8 s table 49 i dd measurement test condition for ddr2?533c and ddr2?400b parameter symbol ?3.7 ?5 unit note ddr2?533c 4?4?4 ddr2?400b 3?3?3 cas latency cl (idd) 43 t ck clock cycle time t ck(idd) 3.75 5 ns active to read or write delay t rcd(idd) 15 15 ns active to active / auto-refresh command period t rc(idd) 60 55 ns active bank a to active bank b command delay t rrd(idd) 7.5 7.5 ns 1) 1) 4 & 8 (1 kb page size) 10 10 ns 2) 2) 16 (2 kb page size); not on 256m component active to precharge command t ras.min(idd) 45 40 ns t ras.max(idd) 70000 70000 ns precharge command period t rp(idd) 15 15 ns auto-refresh to active / auto- refresh command period t rfc(idd) 105 105 ns average periodic refresh interval t refi 7.8 7.8 s hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram currents measurement specifications and conditions data sheet 96 rev. 1.3, 2005-01 09112003-sdm9-iq3p 6.1.1 on die termination (odt) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a full or reduced termination can be selected. the current consumption for any terminated input pin depends on whether the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time.. see table 50 note: for power consumption calculations the odt duty cycle has to be taken into account table 50 odt current per terminated input pin odt current emrs(1) state min. typ. max. unit enabled odt current per dq added i ddq current for odt enabled; odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq a6 = 1, a2 = 1 7.5 9 11.25 ma/dq active odt current per dq added i ddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq a6 = 1, a2 = 0 15 18 22.5 ma/dq data sheet 97 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics 7 electrical characteristics 7.1 speed grade defenitions table 51 speed grade definition speed bins for ddr667 speed grade ddr2?667c ddr2?667d unit note ifx sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements? according to chapter 8.1 only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs/dqs , rdqs/rdqs is defined in chapter 8.3. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . see section 8 for the reference load for timing measurements. @ cl = 4 t ck 383.758ns 1)2)3)4) @ cl = 5 t ck 3838ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? ns 1)2)3)4) table 52 speed grade definition speed bins for ddr533 and ddr400 speed grade ddr2?533c ddr2?400b unit note ifx sort name ?3.7 ?5 cas-rcd-rp latencies 4?4?4 3?3?3 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) @ cl = 4 t ck 3.75 8 5 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 5 8 ns 1)2)3)4) row active time t ras 45 70000 40 70000 ns 1)2)3)4)5) row cycle time t rc 60 ? 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 15 ? 15 ? ns 1)2)3)4) hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics data sheet 98 rev. 1.3, 2005-01 09112003-sdm9-iq3p 7.2 ac timing parameters 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements? according to chapter 8.1 only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs/dqs , rdqs/rdqs is defined in chapter 8.3. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . see section 8 for the reference load for timing measurements. 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . table 53 timing parameter by speed grade - ddr2-667 parameter symbol ddr2-667 unit note 1)2)3)4)5)6) min. max. dq output access time from ck / ck t ac ?450 +450 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh (base) 175 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?400 + 400 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq 240 ? ps 10) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ps 12) address and control input hold time t ih (base) 275 ? ps 9) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 200 ? ps 9) dq low-impedance time from ck / ck t lz(dq) 2 x t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data sheet 99 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs 340 ? ps average periodic refresh interval t refi ?7.8 s 13)14) ?3.9 s 13)15) auto-refresh to active/auto-refresh command period t rfc 105 ? ns 1) read preamble t rpre 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 7.5 ? ns 16)17) 10 ? ns 17)18) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.35 ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto-precharge t wr 15 ? ns write recovery time for write with auto-precharge wr t wr / t ck t ck internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) v ddq = 1.8v 0.1v; v dd = 1.8 v 0.1 v. see notes 3)4)5)6) 2) timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8 of this data sheet. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the reference load for timing measurements according to chapter 8.1 only. 4) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs/dqs , rdqs/rdqs is defined in chapter 8.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 8 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required as describes in chapter 2.12. 9) for timing definition, slew rate and slew rate derating see chapter 8.3 10) consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs/dqs and associated dq in any given cycle. table 53 timing parameter by speed grade - ddr2-667 parameter symbol ddr2-667 unit note 1)2)3)4)5)6) min. max. hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics data sheet 100 rev. 1.3, 2005-01 09112003-sdm9-iq3p 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz , t rpst ), or begins driving ( t lz , t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters are verified by design and characterization, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 t case 85 c 15) 85 c < t case 95 c 16) x4 & x8 (1k page size) 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1.5 18) x16 (2k page size), not on 256mbit component 19) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. data sheet 101 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics table 54 timing parameter by speed grade - ddr2-400b & ddr2-533c parameter symbol ddr2?533c ddr2?400b unit note 1)2)3)4)5) 6) min. max. min. max. dq output access time from ck / ck t ac ?500 +500 ?600 + 600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?ns 8) dq and dm input hold time (differential data strobe) t dh (base) 225 ?? 275 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? 25 ? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ?500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ? 350 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? 150 ? ps 9) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? 25 ? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 12) address and control input hold time t ih (base) 375 ? 475 ? ps 9) address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics data sheet 102 rev. 1.3, 2005-01 09112003-sdm9-iq3p address and control input setup time t is (base) 250 ? 350 ? ps 9) dq low-impedance time from ck / ck t lz(dq) 2 x t ac.min t ac.max 2 x t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 012012ns data output hold time from dqs t qh t hp ? t qhs ? t hpq ? t qhs ? data hold skew factor t qhs ? 400 ? 450 ps average periodic refresh interval t refi ? 7.8 ? 7.8 s 13)14) ? 3.9 ? 3.9 s 13)15) auto-refresh to active/auto- refresh command period t rfc 105 ? 105 ? ns 1) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 7.5 ? 7.5 ? ns 16)17) 10 ? 10 ? ns 18)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.35x t ck ? 0.35x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 19) write recovery time for write without auto-precharge t wr 15 ? 15 ? ns write recovery time for write with auto-precharge wr t wr / t ck t wr / t ck t ck internal write to read command delay t wtr 7.5 ? 10 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? 6 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 3)4)5)6) table 54 timing parameter by speed grade - ddr2-400b & ddr2-533c (cont?d) parameter symbol ddr2?533c ddr2?400b unit note 1)2)3)4)5) 6) min. max. min. max. data sheet 103 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics 2) timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8 of this data sheet. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the reference load for timing measurements according to chapter 8.1 only. 4) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs/dqs , rdqs/rdqs is defined in chapter 8.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 8 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required as describes in chapter 2.12. 9) for timing definition, slew rate and slew rate derating see chapter 8.3 10) consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs/dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz , t rpst ), or begins driving ( t lz , t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters are verified by design and characterization, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 t case 85 c 15) 85 c < t case 95 c 16) x4 & x8 (1k page size) 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1.5 18) x16 (2k page size), not on 256 mbit component 19) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram electrical characteristics data sheet 104 rev. 1.3, 2005-01 09112003-sdm9-iq3p 7.3 odt ac electrical characteristics table 55 odt ac electrical characteristics and operating conditions for ddr2-667 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max +0.7ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min +2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max +0.6ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck table 56 odt ac electrical characteristics and operating conditions for ddr2-533 and ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck data sheet 105 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions 8 ac timing measurement conditions 8.1 reference load for timing measurements figure 72 represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. this reference load is also used for output slew rate characterization. the output timing reference voltage level for single ended signals is the crosspoint with v tt . the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. figure 72 reference load for timing measurements 8.2 slew rate measurement conditions 8.2.1 output slew rate for dq and single ended dqs signals output slew rate for falling and rising edges is measured between v tt ? 250 mv and v tt + 250 mv. for differential signals (dqs / dqs ) output slew rate is measured between dqs - dqs = ?500 mv and dqs ? dqs = + 500 mv. output slew rate is defined with the reference load according to figure 72 and verified by design and characterization, but not subject to production test. 8.2.2 input slew rate - differential signals input slew rate for differential signals (ck / ck , dqs / dqs , rdqs / rdqs ) for rising edges are measured from ck - ck = ?250 mv to ck ? ck = +500 mv and from ck ? ck = +250 mv to ck ? ck = ?500mv for falling edges. 25 ohm v tt = v ddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions data sheet 106 rev. 1.3, 2005-01 09112003-sdm9-iq3p 8.3 input and data setup and hold time 8.3.1 definition for input setup ( t is ) and hold time ( t ih ) address and control input setup time ( t is ) is referenced from the input signal crossing at the v ih(ac) level for a rising signal and v il(ac) for a falling signal applied to the device under test. address and control input hold time ( t ih ) is referenced from the input signal crossing at the v il(dc) level for a rising signal and v ih(dc) for a falling signal applied to the device under test. figure 73 input setup and hold time 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes data input setup time ( t ds ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs/dqs signals must be monotonic between v il(dc).max and v ih(dc).min . data input hold time ( t dh ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v il(dc) level to the differential data strobe crosspoint for a rising signal and v ih(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs/dqs signals must be monotonic between v il(dc).max and v ih(dc).min . figure 74 data setup and hold time (differential data strobes) v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t is t ih t is t ih ck ck v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t ds t dh t ds t dh dqs dqs data sheet 107 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions 8.3.3 definition data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes data input setup time ( t ds1 ) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(ac) level to the single- ended data strobe crossing v ih/l(dc) at the start of its transition for a rising signal, and from the input signal crossing at the v il(ac) level to the single-ended data strobe crossing v ih/l(dc) at the start of its transition for a falling signal applied to the device under test. data input hold time ( t dh1 ) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(dc) level to the single- ended data strobe crossing v ih/l(ac) at the end of its transition for a rising signal and from the input signal crossing at the v il(dc) level to the single-ended data strobe crossing v ih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between v il(dc.max and v ih(dc).min . figure 75 data setup and hold time (single ended data strobes) t ds t dh t ds t dh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss dqs dq hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions data sheet 108 rev. 1.3, 2005-01 09112003-sdm9-iq3p 8.3.4 slew rate definition for input and data setup and hold times setup ( t is & t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac).min . setup ( t is & t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac).max . if the actual signal is always earlier than the nominal slew rate line between shaded ? v ref(dc) to ac region?, use nominal slew rate for derating value (see figure 76 ). if the actual signal is later than the nominal slew rate line anywhere between shaded ? v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(see figure 77 ) hold ( t ih & t dh ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc).max and the first crossing of v ref(dc) . hold ( t ih & t dh ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc).min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref region?, use nominal slew rate for derating value (see figure 76 ). if the actual signal is earlier than the actual signal from the dc level to v ref level is used for derating value (see figure 77 ) figure 76 slew rate definition nominal 3 e t u p 3 l e w 2 a t e 6 2 % & d c 6 ) , a c m a x $ e l t a 4 & 3 f a l l i n g s i g n a l 3 e t u p 3 l e w 2 a t e 6 ) ( a c m i n 6 2 % & d c $ e l t a 4 2 3 r i s i n g s i g n a l ( o l d 3 l e w 2 a t e 6 2 % & d c 6 ) , d c m a x $ e l t a 4 2 ( r i s i n g s i g n a l ( o l d 3 l e w 2 a t e 6 ) ( d c m i n 6 2 % & d c $ e l t a 4 & ( f a l l i n g s i g n a l 6 3 3 6 ) , a c m a x 6 ) , d c m a x 6 2 % & 6 ) ( d c m i n 6 $ $ 1 6 ) ( a c m i n $ e l t a 4 & 3 $ e l t a 4 2 ( $ e l t a 4 & ( $ e l t a 4 2 3 d c t o 6 2 % & r e g i o n 6 2 % & t o a c r e g i o n d c t o 6 2 % & r e g i o n 6 2 % & t o a c r e g i o n # + # + f o r t ) 3 a n d t ) ( $ 1 3 $ 1 3 f o r t $ 3 a n d t $ ( t ) 3 t $ 3 t ) ( t $ ( t ) 3 t $ 3 t ) ( t $ ( data sheet 109 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions figure 77 slew rate definition tangent 6 3 3 6 ) , a c m a x 6 ) , d c m a x 6 2 % & 6 ) ( d c m i n 6 $ $ 1 6 ) ( a c m i n $ e l t a 4 & 3 $ e l t a 4 2 ( $ e l t a 4 & ( $ e l t a 4 2 3 d c t o 6 r e f r e g i o n d c t o 6 r e f r e g i o n 6 2 % & t o a c r e g i o n 6 2 % & t o a c r e g i o n t a n g e n t l i n e n o m i n a l l i n e # + # + f o r t ) 3 a n d t ) ( $ 1 3 $ 1 3 f o r t $ 3 a n d t $ ( t ) 3 t $ 3 t ) ( t $ ( t ) 3 t $ 3 t ) ( t $ ( 3 e t u p 3 l e w 2 a t e t a n g e n t l i n e ; 6 2 % & d c 6 ) , a c m a x = $ e l t a 4 & 3 3 e t u p 3 l e w 2 a t e t a n g e n t l i n e ; 6 ) ( a c m i n 6 2 % & d c = $ e l t a 4 2 3 ( o l d 3 l e w 2 a t e t a n g e n t l i n e ; 6 2 % & d c 6 ) , d c m a x = $ e l t a 4 2 ( ( o l d 3 l e w 2 a t e t a n g e n t l i n e ; 6 ) ( d c m i n 6 2 % & d c = $ e l t a 4 & ( f a l l i n g s i g n a l f a l l i n g s i g n a l r i s i n g s i g n a l r i s i n g s i g n a l hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions data sheet 110 rev. 1.3, 2005-01 09112003-sdm9-iq3p 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables 1. for all input signals the total input setup time and input hold time required is calculated by adding the data sheet value to the derating value respectively. example: t is (total setup tine) = t is (base) + ? t is 2. for slow slew rate the total setup time might be negative (i.e. a valid input signal will not have reached v ih(ac) / v il(ac) at the time of the rising clock) a valid input signal is still required to complete the transition and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterization. table 57 derating values for input setup and hold time (ddr2-667) command / address slew rate (v/ns) ck, ck differential slew rate unit note 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih 4.0 +150 +94 +180 +124 +210 +154 ps 1)2) 1) for all input signals t is (total) = t is (base) + ? t is and t ih (total) = t ih (base) + ? t ih 2) for slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached v ih(ac) / v il(ac) at the time of the rising clock) a valid signal is still required to complete the transistion and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterisation. 3.5 +143 +89 +173 +119 +203 +149 ps 1) 3.0 +133 +83 +163 +113 +193 +143 ps 1) 2.5 +120 +75 +150 +105 +180 +135 ps 1) 2.0 +100 +45 +130 +75 +160 +105 ps 1) 1.5 +67 +21 +97 +51 +127 +81 ps 1) 1.0 0 0 +30 +30 +60 +60 ps 1) 0.9 ?5 ?14 +25 +16 +55 +46 ps 1) 0.8 ?13 ?31 +17 ?1 +47 +29 ps 1) 0.7 ?22 ?54 +8 ?24 +38 +6 ps 1) 0.6 ?34 ?83 ?4 ?53 +26 ?23 ps 1) 0.5 ?60 ?125 ?30 ?95 0 ?65 ps 1) 0.4 ?100 ?188 ?70 ?158 ?40 ?128 ps 1) 0.3 ?168 ?292 ?138 ?262 ?108 ?232 ps 1) 0.25 ?200 ?375 ?170 ?345 ?140 ?315 ps 1) 0.2 ?325 ?500 ?295 ?470 ?265 ?440 ps 1) 0.15 ?517 ?708 ?487 ?678 ?457 ?648 ps 1) 0.1 ?1000 ?1125 ?970 ?1095 ?940 ?1065 ps 1) data sheet 111 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions table 58 derating values for input setup and hold time (ddr2-400 & ddr2-533) command / address slew rate (v/ns) ck, ck differential slew rate unit note 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih 4.0 +187 +94 +217 +124 +247 +154 ps 1)2) 1) for all input signals t is (total) = t is (base) + ? t is and t ih (total) = t ih (base) + ? t ih 2) for slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached v ih(ac) / v il(ac) at the time of the rising clock) a valid signal is still required to complete the transistion and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterisation. 3.5 +179 +89 +209 +119 +239 +149 ps 1) 3.0 +167 +83 +197 +113 +227 +143 ps 1) 2.5 +150 +75 +180 +105 +210 +135 ps 1) 2.0 +125 +45 +155 +75 +185 +105 ps 1) 1.5 +83 +21 +113 +51 +143 +81 ps 1) 1.0 0 0 +30 +30 +60 +60 ps 1) 0.9 ?11 ?14 +19 +16 +49 +46 ps 1) 0.8 ?25 ?31 +5 ?1 +35 +29 ps 1) 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 1) 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 1) 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 1) 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 1) 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 1) 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 1) 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 1) 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 1) 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps 1) hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions data sheet 112 rev. 1.3, 2005-01 09112003-sdm9-iq3p table 59 derating values for data setup and hold time of differential dqs (ddr2-667) dq slew rate (v/ns) dqs, dqs differential slew rate 1)2) 1) all units in ps. 2) for all input signals t ds (total) = t ds (base) + ? t ds and t dh (total) = t dh (base) + ? t dh 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0+100+45+100+45+100+45???????????? 1.5+67+21+67+21+67+21+97+33?????????? 1.00 00 00 0+12+12+24+24???????? 0.9???5?14?5?14+7?2+19+10+31+22?????? 0.8?????13?31?1?19+11?7+23+5+35+17???? 0.7 ? ? ? ? ? ? ?10 ?42 +2 ?30 +14 ?18 +26 ?6 +38 +6 ? ? 0.6 ? ? ? ? ? ? ? ? ?10 ?59 +2 ?47 +14 ?35 +26 ?23 +538 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?24 ?89 ?12 ?77 0 ?65 +12 ?53 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ?52 ?140 ?20 ?28 ?28 ?116 table 60 derating values for data setup and ho ld time of differential dqs (ddr2-400 & -533) dq slew rate (v/ns) dqs, dqs differential slew rate 1)2) 1) all units in ps. 2) for all input signals t ds (total) = t ds (base) + ? t ds and t dh (total) = t dh (base) + ? t dh 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0+125+45+125+45+125+45???????????? 1.5+83+21+83+21+83+21+95+33?????????? 1.00 00 00 0+12+12+24+24???????? 0.9???11?14?11?14+1?2+13+10+25+22?????? 0.8?????25?31?13?19?1?7+11+5+23+17???? 0.7 ? ? ? ? ? ? ?31 ?42 ?19 ?30 ?7 ?18 +5 ?6 +17 +6 ? ? 0.6 ? ? ? ? ? ? ? ? ?43 ?59 ?31 ?47 ?19 ?35 ?7 ?23 +5 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?74 ?89 ?62 ?77 ?50 ?65 ?38 ?53 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ?127 ?140 ?115 ?128 ?103 ?116 data sheet 113 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram ac timing measurement conditions table 61 derating values for data setup and ho ld time of single-ended dqs (ddr2-400 & -533) dq slew rate (v/ns) dqs, dqs single-ended slew rate 1)2) 1) all units in ps. 2) for all input signals t ds1 (total) = t ds1 (base) + ? t ds1 and t dh1 (total) = t dh1 (base) + ? t dh1 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 2.0+188+188+167+146+125+63????? ? ? ? ? ? ? ? 1.5 +146 +167 +125 +125 +83 +42 +81 +43 ? ? ? ? ? ? ? ? ? ? 1.0+63+125+42+830 0 -2+1-7-13???????? 0.9 ? ? +31 +69 -11 -14 -13 -13 -18 -27 -29 -45 ? ? ? ? ? ? 0.8????-25-31-27-30-32-44-43-62-60?86???? 0.7??????-45-53-50-67-61-85-78-109-108-152?? 0.6????????-74-96-85-114-102-138-132-181-183-246 0.5?????? ????-128-156-145-180-175-223-226-288 0.4?????? ????? ? -210-243-240-286-291-351 hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram package dimensions data sheet 114 rev. 1.3, 2005-01 09112003-sdm9-iq3p 9 package dimensions figure 78 package pinout pg-tfbga-60 (top view) x " x ! - ) . - ! 8 ? ? x ? ? " - - ! # 3 % ! 4 ) . ' 0 , ! . % # # $ u m m y p a d s w i t h o u t b a l l 0 a c k a g e o r i e n t a t i o n m a r k ! - i d d l e o f p a c k a g e s e d g e s - ! 8 - ! 8 # " a d u n i t m a r k i n g " 5 - $ i e s o r t f i d u c i a l data sheet 115 rev. 1.3, 2005-01 09112003-sdm9-iq3p hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram package dimensions figure 79 package pinout pg-tfbga-84 (top view) x ! " ? ? ? - ? x - # ! " - ! 8 - ) . # 3 % ! 4 ) . ' 0 , ! . % - i d d l e o f p a c k a g e s e d g e s 0 a c k a g e o r i e n t a t i o n m a r k ! $ u m m y p a d s w i t h o u t b a l l x - ! 8 # # - ! 8 " a d u n i t m a r k i n g " 5 - $ i e s o r t f i d u c i a l hyb18t512[40/80/16]0af?[3/3s/3.7/5] 512-mbit ddr2 sdram product namenclature data sheet 116 rev. 1.3, 2005-01 09112003-sdm9-iq3p 10 product namenclature table 62 nomenclature fields and examples example for field number 1 234567891011 ddr2 dram hyb 18 t 512 16 0 a c ?3.7 table 63 ddr2 memory components field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3 dram technology t ddr2 4 component density [mbit] 256 256 m 512 512 m 1g 1 gb 5+6 number of i/os 40 4 80 8 160 16 7 product variations 0 .. 9 look up table 8 die revision a first bsecond 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?3 ddr2?667c 4?4?4 ?3s ddr2?667d 5?5?5 ?3.7 ddr2?533c 4?4?4 ?5 ddr2?400b 3?3?3 11 n/a for components published by infineon technologies ag www.infineon.com |
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