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fibre channel transceiver chip technical data HDMP-1536A transceiver hdmp-1546a transceiver features ? ansi x3.230-1994 fibre channel compatible (fc-0) ? supports full speed (1062.5 mbd) fibre channel ? compatible with fibre channel 10-bit interface specification ? low power consumption, 630 mw ? transmitter and receiver functions incorporated onto a single ic ? auto frequency lock ? small package profile HDMP-1536A, 10x10 mm qfp hdmp-1546a, 14x14 mm qfp ? 10-bit wide parallel ttl compatible i/os ? single +3.3 v power supply ? 5 volt tolerant i/os ? 2 kv esd protection on all pins applications ? 1062.5 mbd fibre channel interface ? fc interface for disk drives and arrays ? mass storage system i/o channel ? work station/server i/o channel ? high speed proprietary interface ? high speed backplane interface description the hdmp-1536/46a transceiver is a single silicon bipolar integrated circuit packaged in a plastic qfp package. it provides a low-cost, low-power physical layer solution for 1062.5 mbd fibre channel or proprietary link interfaces. it provides complete fc-0 functionality for copper transmission, incorporating both the fibre channel fc-0 transmit and receive functions into a single device. this chip is used to build a high- speed interface (as shown in figure 1) while minimizing board space, power, and cost. it is compatible with both the ansi x3.230-1994/am 1 - 1996 document and the fibre channel 10-bit interface specification. the transmitter section accepts 10-bit wide parallel ttl data and multiplexes this data into a high- speed serial data stream. the parallel data is expected to be 8b/10b encoded data, or equivalent. this parallel data is latched into the input register of the transmitter section on the rising edge of the 106.25 mhz reference clock (used as the transmit byte clock). the transmitter sections pll locks to this user supplied 106.25 mhz byte clock. this clock is then multiplied by 10, to generate the 1062.5 mhz serial signal clock used to generate the high- speed output. the high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber-optic module for optical transmission. the receiver section accepts a serial electrical data stream at 1062.5 mbd and recovers the original 10-bit wide parallel data. the receiver pll locks onto the incoming serial signal and
2 figure 1. typical application using the hdmp-15x6a. figure 2. hdmp-15x6a transceiver block diagram. hdmp-15x6a protocol device serial data out receiver section pll transmitter section bytsync enbytsync refclk serial data in pll rbc0 rbc1 ?dout tx pll/clock generator refclk ?din rxcap0 rxcap1 rbc0 rbc1 bytsync enbytsync output driver internal tx clocks input latch data byte rx[0-9] txcap1 txcap0 data byte tx[0-9] internal rx clocks loopen internal loopback output select frame mux rx pll/clock recovery input select frame demux and byte sync input sampler sig_det signal detect
3 output select the output select block provides for an optional internal loopback of the high speed serial signal, for testing purposes. in normal operation, loopen is set low and the serial data stream is placed at dout. when wrap- mode is activated by setting loopen high, the dout pins are held static at logic 1 and the serial output signal is internally wrapped to the input select box of the receiver section. input select the input select block deter- mines whether the signal at din or the internal loop-back serial signal is used. in normal opera- tion, loopen is set low and the serial data is accepted at din. when loopen is set high, the high-speed serial signal is internally looped-back from the transmitter section to the receiver section. this feature allows for loop-back testing exclusive of the transmission medium. rx pll/clock recovery the rx pll/clock recovery block is responsible for frequency and phase locking onto the incom- ing serial data stream and recover- ing the bit and byte clocks. an automatic locking feature allows the rx pll to lock onto the input data stream without external pll training controls. it does this by continually frequency locking onto the 106.25 mhz clock, and then phase locking onto the input data stream. an internal signal detection circuit monitors the presence of the input, and invokes the phase detection as the data stream appears. once bit locked, the receiver generates the high speed recovers the high-speed serial clock and data. the serial data is converted back into 10-bit parallel data, recognizing the 8b/10b comma character to establish byte alignment. the recovered parallel data is presented to the user at ttl compatible outputs. the receiver section also recovers two 53.125 mhz receiver byte clocks that are 180 degrees out of phase with each other. the parallel data is properly aligned with the rising edge of alternating clocks. for test purposes, the transceiver provides for on-chip local loop- back functionality controlled through an external input pin. additionally, the byte synchroniza- tion feature may be disabled. this may be useful in proprietary ap- plications which use alternative methods to align the parallel data. hdmp-1536/46a block diagram the hdmp-1536/46a was designed to transmit and receive 10-bit wide parallel data over a single high-speed line, as specified for the fc-0 layer of the fibre channel standard. the parallel data applied to the transmitter is expected to be encoded per the fibre channel specification, which uses an 8b/10b encoding scheme with special reserve characters for link management purposes. in order to accomplish this task, the hdmp-1536/46a incorporates the following: ? ttl parallel i/os ? high speed phase lock loops ? high speed serial clock and data recovery circuitry ? parallel to serial converter ? comma character recognition circuitry ? byte alignment circuitry ? serial to parallel converter input latch the transmitter accepts 10-bit wide ttl parallel data at inputs tx[0..9]. the user-provided reference clock signal, refclk, is also used as the transmit byte clock. the tx[0..9] and refclk signals must be properly aligned, as shown in figure 3. tx pll/clock generator the transmitter phase lock loop and clock generator (tx pll/ clock generator) block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. these clocks are based on the supplied reference byte clock (refclk). refclk is used as both the frequency reference clock for the pll and the trans- mit byte clock for the incoming data latches. it is expected to be 106.25 mhz and properly aligned to the incoming parallel data (see figure 3). this clock is multiplied by 10 to generate the 1062.5 mhz clock necessary for the high speed serial outputs. frame mux the frame mux accepts the 10- bit wide parallel data from the input latch. using internally generated high speed clocks, this parallel data is multiplexed into the 1062.5 mbd serial data stream. the data bits are trans- mitted sequentially, from the least significant bit (tx[0]) to the most significant bit (tx[9]).
4 sampling clock at 1062.5 mhz for the input sampler, and recovers the two 53.125 mhz receiver byte clocks (rbc1/rbc0). these clocks are 180 degrees out of phase with each other, and are alternately used to clock the 10-bit parallel output data. input sampler the input sampler is responsible for converting the serial input signal into a re-timed serial bit stream. in order to accomplish this, it uses the high speed serial clock recovered from the rx pll/clock recovery block. this serial bit stream is sent to the frame demux and byte sync block. frame demux and byte sync the frame demux and byte sync block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. this block is also responsible for recognizing the comma character (or a k28.5 character) of positive disparity (0011111xxx). when recognized, the frame demux and byte sync block works with the rx pll/clock recovery block to properly align the receive byte clocks to the parallel data. when a comma character is detected and realignment of the receiver byte clocks (rbc1/rbc0) is necessary, these clocks are stretched, not slivered, to the next possible correct alignment position. these clocks will be fully aligned by the start of the second 4-byte ordered set. the second comma character received shall be aligned with the rising edge of rbc1. as per the 8b/10b encoding scheme, comma characters should not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. output drivers the output drivers present the 10-bit parallel recovered data byte properly aligned to the receiver byte clocks (rbc1/rbc0), as shown in figure 5. these output data buffers provide ttl compatible signals. signal detect the signal detect block examines the differential amplitude of the inputs din. when this input signal is too small, it outputs a logic 0 at sig_det (refer to sig_det pin definition for detection thresholds), and at the same time, forces the parallel output rx[0]..rx[9] to all logic one (1111111111). the main purpose of this circuit is to prevent the generation of random data when the serial input lines are disconnected. when the signal at din is of a valid amplitude, sig_det is set to logic 1, and the output of the input select block is passed through.
5 hdmp-1536/46a (transmitter section) timing characteristics t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t setup setup time nsec 2 t hold hold time nsec 1.5 t_txlat [2] transmitter latency nsec 3.5 bits 4.4 notes: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . 2. the transmitter latency, as shown in figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, refclk) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted). figure 3. transmitter section timing. figure 4. transmitter latency. data data tx[0]-tx[9] t setup t hold refclk data data data 1.4 v 2.0 v 0.8 v data byte b data byte c tx[0]-tx[9] data byte a ?dout 1.4 v data byte b t_txlat t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 refclk
6 hdmp-1536/46a (receiver section) timing characteristics t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. b_sync [2,3] bit sync time bits 2500 t valid_before time data valid before rising edge of rbc nsec 3 t valid_after time data valid after rising edge of rbc nsec 1.5 t duty rbc duty cycle % 40 60 t a-b [4] rising edge time difference between nsec 8.9 9.4 9.9 rbc0 and rbc1. t_rxlat [5] receiver latency nsec 24.5 bits 26 notes: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . 2. this is the recovery time for input phase jumps, per the fc-ph specification ref 4.1, sec 5.3. 3. tested using c pll = 0.1 m f. 4. the rbc clock skew is calculated as t a-b(max) - t a-b(min) . 5. the receiver latency, as shown in figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either rbc1 or rbc0). figure 6. receiver latency. figure 5. receiver section timing. data data rx[0]-rx[9] t valid_before t valid_after rbc1 k28.5 data data 1.4 v 2.0 v 0.8 v bytsync rbc0 t a-b 2.0 v 0.8 v 1.4 v data byte a data byte d rx[0]-rx[9] data byte d ?din 1.4 v t_rxlat r5 r6 r7 r8 r9 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r2 r3 r4 r5 rbc1/0 data byte c
7 absolute maximum ratings t a = 25 c, except as specified. operation in excess of any one of these conditions may result in permanent damage to this device. symbol parameter units min. max. v cc supply voltage v -0.5 5.0 v in,ttl ttl input voltage v -0.7 v cc + 2.8 v in,hs_in hs_in input voltage v 2.0 v cc i o,ttl ttl output source current ma 13 t stg storage temperature c -65 +150 t j junction operating temperature c 0 +150 guaranteed operating rates t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v parallel clock rate (mhz) serial baud rate (mbaud) min. max. min. max. 106.20 106.30 1062.0 1063.0 note: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . transceiver reference clock requirements t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter unit min. typ. max. f nominal frequency (for fibre channel compliance) mhz 106.20 106.25 106.30 f tol frequency tolerance ppm -100 +100 symm symmetry (duty cycle) % 40 60 note: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . dc electrical specifications t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter unit min. typ. max. v ih,ttl ttl input high voltage level, guaranteed high signal v 2 v cc for all inputs v il,ttl ttl input low voltage level, guaranteed low signal for v 0 0.8 all inputs v oh,ttl ttl output high voltage level, i oh = -400 m a v 2.2 v cc v ol,ttl ttl output low voltage level, i ol = 1 ma v 0 0.6 i ih,ttl input high current (magnitude), v in = 2.4 v, v cc = max m a40 i il-ttl input low current (magnitude), v in = 0.4 v, v cc = max m a -600 i cc,trx [2,3] transceiver v cc supply current, t a = 25 c ma 205 notes: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . 2. measurement conditions: tested sending 1062.5 mbd prbs 2 7 -1 sequence from a serial bert with dout outputs biased with 150 w resistors. 3. typical specified with v cc = 3.3 volts, maximum specified with v cc = 3.45 volts.
8 ac electrical specifications t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t r,refclk refclk rise time, 0.8 to 2.0 volts nsec 0.7 2.4 t f,refclk refclk fall time, 2.0 to 0.8 volts nsec 0.7 2.4 t r,ttlin input ttl rise time, 0.8 to 2.0 volts nsec 2 t f,ttlin input ttl fall time, 2.0 to 0.8 volts nsec 2 t r,ttlout output ttl rise time, 0.8 to 2.0 volts, 10 pf load nsec 1.5 2.4 t f,ttlout output ttl fall time, 2.0 to 0.8 volts, 10 pf load nsec 1.1 2.4 t rs,hs_out hs_out single-ended (+dout) rise time psec 225 375 t fs,hs_out hs_out single-ended (+dout) fall time psec 200 375 t rd,hs_out hs_out differential rise time psec 225 t fd,hs_out hs_out differential fall time psec 200 v ip,hs_in hs_in input peak-to-peak differential voltage mv 200 1200 2000 v op,hs_out [2] hs_out output peak-to-peak differential voltage mv 1200 1600 2200 notes: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . 2. output peak-to-peak differential voltage specified as dout+ minus dout-. a. differential hs_out output (dout+ minus dout-). figure 7. transmitter dout eye diagrams. b. single-ended hs_out output (dout+). eye diagrams of the high-speed serial outputs from the hdmp-1536/46a as captured on the hp 83480a digital communications analyzer. tested with prbs = 2 7 -1. yaxis = 400 mv/div 22.0680 ns 200.0 ps/div 22.0680 ns 200.0 ps/div yaxis = 200 mv/div
9 output jitter characteristics t a = 0 to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. rj [1] random jitter at dout, the high speed electrical data port, specified as ps 8 1 sigma deviation of the 50% crossing point (rms) dj [1] deterministic jitter at dout, the high speed electrical data port (pk-pk) ps 15 note: 1. defined by fibre channel specification rev 4.1, annex a, section a.4 and tested using measurement method shown in figure 8. thermal and power temperature characteristics, t a [1] = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. max. p d,trx [2,3] transceiver power dissipation, outputs open, parallel data mw 630 850 has 5 ones and 5 zeroes p d,trx [2,3,4] transceiver power dissipation, outputs connected per mw 675 900 recommended bias terminations with idle pattern q jc [5] thermal resistance, junction to case HDMP-1536A c/watt 11 hdmp-1546a 8 notes: 1. device tested and characterized under t a conditions specified, with t c monitored at approximately 20 higher than t a . 2. p d is obtained by multiplying the max v cc by the max i cc and subtracting the power dissipated outside the chip at the high speed bias resistors. 3. typical value specified with v cc = 3.3 volts, maximum value specified with v cc = 3.45 volts. 4. specified with high speed outputs biased with 150 w resistors and receiver ttl outputs driving 10 pf loads. 5. based on independent package testing by agilent technologies. q ja for these devices is 56 c/watt for the HDMP-1536A and 51 c/watt for the hdmp-1546a. q ja is measured on a standard 3x3" fr4 pcb in a still air environment. to determine the actual junction temperature in a given application, use the following: tj = t c + ( q jc x pd), where t c is the case temperature measured on the top center of the package and p d is the power being dissipated. figure 8. transmitter jitter measurement method. a. block diagram of rj measurement method. b. block diagram of dj measurement method. 70841b pattern generator* 83480a oscilloscope HDMP-1536A 70311a clock source + data - data 0000011111 trigger ch1 ch2 +dout -dout refclk loopen tx[0..9] bias tee 1.4 v 0011111000 (static k28.7) 1.0625 ghz 106.25 mhz * pattern generator provides a divide by 10 function. 70841b pattern generator* 83480a oscilloscope HDMP-1536A 70311a clock source + data - data +k28.5, -k28.5 trigger ch1 ch2 +dout -dout refclk loopen tx[0..9] 1.0625 ghz 106.25 mhz enbytsync rx[0..9] -din +din divide by 2 circuit divide by 10 circuit (dual output) variable delay ttl
10 i/o type definitions i/o type definition i-ttl input ttl, floats high when left open o-ttl output ttl hs_out high speed output, ecl compatible hs_in high speed input c external circuit node s power supply or ground pin input capacitance symbol parameter units typ. max. c input input capacitance on ttl input pins pf 1.6 figure 10. hs_out and hs_in simplified circuit schematic. notes: 1. hs_in inputs should never be connected to ground as permanent damage to the device may result. 2. the optional series padding resistors (r pad ) help dampen load reflections. typical r pad values for mismatched loads range between 25-75 w . * enhanced esd protection. figure 9. o-ttl and i-ttl simplified circuit schematic. v cc r v bb 1.4 v r gnd v cc *esd protection gnd_rxttl v cc _rxttl r r r o_ttl i_ttl gnd *esd protection v cc hs_out r 0.01 ? 0.01 ? zo = 75 w zo = 75 w v cc _txhs v cc _txecl gnd *esd protection -dout +dout 150 150 r pad r pad gnd_txhs +din -din *esd protection r + + hs_in 150 v cc gnd gnd v cc
11 *n/c: this pin is connected to an isolated pad and has no functionality. it can be left open, however, ttl levels can also be applied to this pin. *v cc : this pin is bonded to an isolated pad and has no functionality. however, it is recommended that this pin be connected to v cc in order to conform with the x3t11 10-bit specification, and to help dissipate heat. *gnd: this pin is bonded to an isolated pad and has no functionality. however, it is recommended that this pin be connected to gnd in order to conform with the x3t11 10-bit specification, and to help dissipate heat. figure 11. hdmp-1536/46a (trx) package layout and marking, top view. rxcap0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd_txhs hdmp-15x6a xxxx-x rz.zz s yyww 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bytsync gnd_rxttl rx[0] rx[1] rx[2] v cc _rxttl rx[3] rx[4] rx[5] rx[6] v cc _rxttl rx[7] rx[8] rx[9] gnd_rxttl *gnd tx[0] tx[1] tx[2] *v cc tx[3] tx[4] tx[5] tx[6] *v cc tx[7] tx[8] tx[9] *gnd gnd_txa txcap1 v cc _txhs +dout -dout v cc _txecl v cc gnd v cc gnd* v cc * +din v cc * -din gnd_rxa v cc _rxa rxcap1 txcap0 v cc _txa loopen v cc gnd refclk v cc enbytsync gnd sig_det *n/c v cc v cc _rxttl rbc1 rbc0 gnd_rxttl xxxx-x = wafer lot number?uild number rz.zz = die revision s = supplier code yyww = date code (yy = year, ww = work week) country = country of manufacture (marked on back of device)
12 trx i/o definition name pin type signal bytsync 47 o-ttl byte sync output: an active high output. used to indicate detection of a comma character (0011111xxx). it is only active when enbytsync is enabled. -din 52 hs_in serial data inputs: high-speed inputs. serial data is accepted from the +din 54 din inputs when loopen is low. -dout 61 hs_out serial data outputs: high-speed outputs. these lines are active when +dout 62 loopen is set low. when loopen is set high, these outputs are held static at logic level 1. enbytsync 24 i-ttl enable byte sync input: when high, turns on the internal byte sync function to allow clock synchronization to a comma character (0011111xxx). when the line is low, the function is disabled and will not reset registers and clocks, or strobe the bytsync line. gnd 21 s logic ground: normally 0 volts. this ground is used for internal pecl 25 logic. it should be isolated from the noisy ttl ground as well as possible. 58 *gnd 1 this pin is bonded to an isolated pad and has no functionality. however, 14 it is recommended that this pin be connected to gnd in order to conform 56 with the x3t11 10-bit specification, and to help dissipate heat. gnd_rxa 51 s analog ground: normally 0 volts. used to provide a clean ground plane for the receiver pll and high-speed analog cells. gnd_rxttl 32 s ttl receiver ground: normally 0 volts. used for the ttl output cells 33 of the receiver section. 46 gnd_txa 15 s analog ground: normally 0 volts. used to provide a clean ground plane for the pll and high-speed analog cells. gnd_txhs 64 s ground: normally 0 volts. loopen 19 i-ttl loopback enable input: when set high, the high-speed serial signal is internally wrapped from the transmitters serial loopback outputs back to the receivers loopback inputs. also, when in loopback mode, the dout outputs are held static at logic level 1. when set low, dout outputs and din inputs are active. *n/c 27 this pin is connected to an isolated pad and has no functionality. it can be left open, however, ttl levels can also be applied to this pin. rbc1 30 o-ttl receiver byte clocks: the receiver section recovers two 53.125 mhz rbc0 31 receive byte clocks. these two clocks are 180 degrees out of phase. the receiver parallel data outputs are alternatively clocked on the rising edge of these clocks. the rising edge of rbc1 aligns with the output of the comma character (for byte alignment) when detected. refclk 22 i-ttl reference clock and transmit byte clock: a 106.25 mhz clock supplied by the host system. the transmitter section accepts this signal as the frequency reference clock. it is multiplied by 10 to generate the serial bit clock and other internal clocks. the transmit side also uses this clock as the transmit byte clock for the incoming parallel data tx[0]..tx[9]. it also serves as the reference clock for the receive portion of the transceiver.
13 trx i/o definition (contd.) name pin type signal rx[0] 45 o-ttl data outputs: one 10 bit data byte. rx[0] is the first bit received. rx[1] 44 rx[0] is the least significant bit. rx[2] 43 rx[3] 41 rx[4] 40 rx[5] 39 rx[6] 38 rx[7] 36 rx[8] 35 rx[9] 34 rxcap0 48 c loop filter capacitor: a loop filter capacitor for the internal pll must rxcap1 49 be connected across the rxcap0 and rxcap1 pins. (typical value = 0.1 m f). sig_det 26 o-ttl signal detect: indicates a loss of signal on the high-speed differential inputs, din, as in the case where the transmission cable becomes disconnected. if din > = 200 mv peak-to-peak, sig_det = logic 1. if din < = 200 mv and din > 50 mv, sig_det = undefined. if din < = 50 mv, sig_det = logic 0, rx[0:9] = 1111111111. tx[0] 2 i-ttl data inputs: one, 10 bit, pre-encoded data byte. tx[0] is the first bit tx[1] 3 transmitted. tx[0] is the least significant bit. tx[2] 4 tx[3] 6 tx[4] 7 tx[5] 8 tx[6] 9 tx[7] 11 tx[8] 12 tx[9] 13 txcap1 16 c loop filter capacitor: a loop filter capacitor must be connected across txcap0 17 the txcap1 and txcap0 pins (typical value = 0.1 m f). v cc 20,23 s logic power supply: normally 3.3 volts. used for internal receiver 28 pecl logic. it should be isolated from the noisy ttl supply as well as 57,59 possible. v cc _rxa 50 s analog power supply: normally 3.3 volts. used to provide a clean supply line for the pll and high-speed analog cells. *v cc 5 s this pin is bonded to an isolated pad and has no functionality. however, 10 it is recommended that this pin be connected to v cc in order to conform 53,55 with the x3t11 10-bit specification, and to help dissipate heat. v cc _rxttl 29 s ttl power supply: normally 3.3 volts. used for all ttl receiver output 37 buffer cells. 42 v cc _txa 18 s analog power supply: normally 3.3 volts. used to provide a clean supply line for the pll and high-speed analog cells. v cc _txecl 60 s high-speed ecl supply: normally 3.3 volts. used only for the last stage of the high-speed transmitter output cell (hs_out) as shown in figure 10. due to high current transitions, this v cc should be well bypassed to a ground plane. v cc _txhs 63 s high-speed supply: normally 3.3 volts. used by the transmitter side for the high-speed circuitry. noise on this line should be minimized for best operation.
14 figure 12. power supply bypass. start-up procedure: the transceiver start-up procedure(s) use the following conditions: v cc = +3.3 v 5% and refclk = 106.25 mhz 100 ppm. after the above conditions have been met, apply valid data using a balanced code such as 8b/10b. frequency lock occurs within 500 m s. after frequency lock, phase lock occurs within 2500 bit times. rxcap0 v cc _rxttl v cc _rxttl gnd_txhs top view gnd_rxttl gnd* v cc * v cc * gnd* gnd_txa txcap1 v cc _txhs v cc _txecl v cc gnd v cc gnd* v cc * v cc * gnd_rxa v cc _rxa rxcap1 * it is recommended that these pins be connected to the appropriate supply line, either v cc or gnd, even though the pin is bonded to an isolated pad. refer to the i/o definitions section for these pins for more details. ** supply voltage into v cc _rxa and v cc _txa should be from a low noise source. all bypass capacitors and pll filter capacitors are 0.1 ?. v cc gnd v cc v cc ** v cc gnd_rxttl txcap0 v cc _txa gnd v cc gnd_rxttl v cc _rxttl v cc c pllt v cc ** c pllr v cc transceiver power supply bypass and loop filter capacitors bypass capacitors should be used and placed as close as possible to the appropriate power supply pins of the hdmp-1536/46a as shown on the schematic of figure 12. all bypass chip capacitors are 0.1 m f. the v cc _rxa and v cc _txa pins are the analog power supply pins for the pll sections. the voltage into these pins should be clean with minimum noise. the pll loop filter capacitors and their pin locations are also shown on figure 12. notice that only two capacitors are required: c pllt for the transmitter and c pllr for the receiver. nominal capacitance is 0.1 m f. the voltage across the capacitors is on the order of 1 volt maximum, so the capacitor can be a low voltage type and physically small. the pll capacitors are placed physically close to the appropriate pins on the hdmp-1536/46a. keeping the lines short will prevent them from picking up stray noise from surrounding lines or components. caution: as with all semiconductor ics, it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (esd).
15 package information item details package material plastic lead finish material 85% tin, 15% lead lead finish thickness 300-800 m m lead coplanarity HDMP-1536A: 0.08 mm max. hdmp-1546a: 0.10 mm max. mechanical dimensions figure 13. mechanical dimensions of hdmp-1536/46a. part number a1 a2 b1 b2 b3 b4 b5 c1 c2 c3 HDMP-1536A 10.00 13.20 0.22 0.50 0.60 0.17 0.25 2.00 0.25 min. 2.45 hdmp-1546a 14.00 17.20 0.35 0.80 0.88 0.17 0.25 2.00 0.25 max. 2.35 tolerance 0.10 0.25 0.05 basic +0.15/ max. +0.10/-0.05 max. -0.10 a1 a2 pin #1 id a1 a2 b1 b4 b3 c1 c2 b2 b5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 hdmp-15x6a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c3
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. obsoletes 5966-0232e 5966-2717e (11/99)

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