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ds05-10197-1e fujitsu semiconductor data sheet memory cmos 256k 16 bits hyper page mode dynamic ram mb81v4265-60/-70 cmos 262,144 16 bits hyper page mode dynamic ram n description the fujitsu mb81v4265 is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells accessible in 16-bit increments. the mb81v4265 features the ?yper page mode of operation which provides extended valid time for data output and higher speed random access of up to 512 16-bits of data within the same row than the fast page mode. the mb81v4265-60/-70 drams are ideally suited for memory applications such as embedded control, buffer, portable computers, and video imaging equipment where very low power dissipation and high bandwidth are basic requirements of the design. the mb81v4265 is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. n product line & features parameter mb81v4265-60 MB81V4265-70 ras access time 60 ns max. 70 ns max. cas access time 20 ns max. 20 ns max. address access time 30 ns max. 35 ns max. random cycle time 104 ns min. 119 ns min. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current 378 mw max. 335 mw max. standby current 7.2 mw max. (lvttl level)/3.6 mw max. (cmos level) 262,144 words 16 bits organization silicon gate, cmos, advanced stacked capacitor cell all input and output are lvttl compatible 512 refresh cycles every 8.2 ms 9 rows 9 columns, addressing scheme early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb81v4265-60/-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out e0.5 to +4.6 v voltage of v cc supply relative to v ss v cc e0.5 to +4.6 v power dissipation p d 1.0 w short circuit output current i out e50 to +50 ma storage temperature t stg e55 to +125 c temperature under bias t bias 0 to +70 c lcc-40p-m01 package and ordering information e 40-pin plastic (400 mil) soj,order as mb81v4265- pj e 44-pin plastic (400 mil) tsop-ii with normal bend leads,order as mb81v4265- pftn fpt-44p-m07 (normal bend) marking side plastic soj package plastic tsop package
3 mb81v4265-60/-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 to a 8 c in1 ?5pf input capacitance, ras , lcas , ucas , we , oe c in2 ?7pf input/output capacitance, dq 1 to dq 16 c dq ?7pf mode control write clock gen a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 a 0 ras lcas clock gen #2 data in buffer we dq 1 to dq 16 oe v cc v ss data out buffer column decoder clock gen #1 sense ampl & i/o gate address buffer & pre- decoder row decoder substrate bias gen refresh address counter ucas 4,194,304 bit storage cell fig. 1 e mb81v4265s dynamic ram - block diagram
4 mb81v4265-60/-70 n pin assignments and descriptions 1 2 3 4 5 9 10 11 12 13 14 6 7 8 15 16 17 18 19 20 27 28 38 37 36 35 34 30 29 33 32 31 40 39 26 25 24 23 22 21 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 (marking side) 1 pin index dq 1 to dq 16 a 0 to a 8 data input/ output write enable row address strobe address inputs +3.3 volt power supply lower column address strobe circuit ground output enable upper column address strobe : a 0 to a 8 : a 0 to a 8 row column ras lcas ucas we oe n.c. no connection v cc v ss 40-pin soj: (top view) 44-pin tsop: (top view) v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 n.c. n.c. a 0 a 1 a 2 a 3 v cc we ras v ss v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 n.c. a 8 a 7 a 6 a 5 a 4 lcas ucas oe v cc dq 1 dq 2 dq 3 dq 4 v cc v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 n.c. a 0 a 1 a 2 a 3 v cc n.c. v ss n.c. a 8 a 7 a 6 a 5 a 4 we ras lcas ucas oe n.c. n.c. designator function
5 mb81v4265-60/-70 n recommended operating conditions * : undershoots of up to e2.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. since only nine address bits (a0 to a8) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, nine row address bits are input on pins a0-through-a9 and latched with the row address strobe (ras ) then, nine column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?ow-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways : an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas / ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq 1 to dq 8 is strobed by lcas and dq 9 to dq 16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas / ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas / ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are lvttl compatible with a fanout of one ttl load. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satisted. t cac : from the falling edge of lcas (for dq 1 to dq 8 ) ucas (for dq 9 to dq 16 ) when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max), and t rcd (max) is satisted. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and lcas (and/or ucas ) are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 3.0 3.3 3.6 v 0 c to +70 c v ss 0 0 0 input high voltage, all inputs *1 v ih 2.0 ? v cc +0.3 v input low voltage, all inputs* *1 v il e0.3 ? 0.8 v
6 mb81v4265-60/-70 hyper page mode of operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 512 16-bits can be accessed and, when multiple mb81v4265s are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated. n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol condition value unit min. max. output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = 2.0 ma 0.4 input leakage current (any input) i i(l) 0 v ? v in ? 3.6 v; 3.0 v ? v cc ? 3.6 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i dq(l) 0 v ? v out ? 3.6 v; data out disabled ?0 10 operating current (average power supply current) *2 mb81v4265-60 i cc1 ras & lcas , ucas cycling; t rc = min ?a MB81V4265-70 standby current (power supply current) lvttl level i cc2 ras = lcas = ucas = v ih ?a cmos level ras = lcas = ucas ? v cc ?.2 v refresh current #1 (average power supply current) *2 mb81v4265-60 i cc3 lcas = ucas = v ih , ras cycling; t rc = min ?a MB81V4265-70 hyper page mode current *2 mb81v4265-60 i cc4 ras = v il, lcas / ucas cycling; t hpc = min ?a MB81V4265-70 refresh current #2 (average power supply current) *2 mb81v4265-60 i cc5 ras cycling; cas -before-ras ; t rc = min ?a MB81V4265-70 105 93 2.0 1.0 105 93 105 93 105 93
7 mb81v4265-60/-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb81v4265-60 MB81V4265-70 unit min. max. min. max. 1 time between refresh t ref ? 8.2 ? 8.2 ms 2 random read/write cycle time t rc 104 ? 119 ? ns 3 read-modify-write cycle time t rwc 138 ? 158 ? ns 4 access time from ras *6,9 t rac ?60?70ns 5 access time from cas *7,9 t cac ?20?20ns 6 column address access time *8,9 t aa ?30?35ns 7 output hold time t oh 5?5?ns 8 output hold time from cas t ohc 5?5?ns 9 output buffer turn on delay time t on 0?0?ns 10 output buffer turn off delay time *10 t off ?15?15ns 11 output buffer turn off delay time from ras t ofr ?15?15ns 12 output buffer turn off delay time from we t wez ?15?15ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?45?ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 20?20?ns 17 cas to ras precharge time *21 t crp 0?0?ns 18 ras to cas delay time *11,12, 22 t rcd 14 40 14 50 ns 19 cas pulse width t cas 10?10?ns 20 cas hold time t csh 40?50?ns 21 cas precharge time (normal) *19 t cpn 10?10?ns 22 row address set up time t asr 0?0?ns 23 row address hold time t rah 10?10?ns 24 column address set up time t asc 0?0?ns 25 column address hold time t cah 10?10?ns 26 ras to column address delay time *13 t rad 12 30 12 35 ns 27 column address to ras lead time t ral 30?35?ns 28 column address to cas lead time t cal 23?28?ns 29 read command and set up time t rcs 0?0?ns 30 read command hold time referenced to ras *14 t rrh 0?0?ns 31 read command hold time referenced to cas *14 t rch 0?0?ns 32 write command set up time *15 t wcs 0?0?ns 33 write command hold time t wch 10?10?ns 34 we pulse width t wp 10?10?ns 35 write command to ras lead time t rwl 15?20?ns
8 mb81v4265-60/-70 (continued) no. parameter notes symbol mb81v4265-60 MB81V4265-70 unit min. max. min. max. 36 write command to cas lead time t cwl 10?10?ns 37 din set up time t ds 0?0?ns 38 din hold time t dh 10?10?ns 39 ras to we delay time t rwd 77?87?ns 40 cas to we delay time t cwd 37?37?ns 41 column address to we delay time *20 t awd 47?52?ns 42 ras precharge time to cas active time (refresh cycles) t rpc 10?10?ns 43 cas set up time for cas -before-ras refresh t csr 0?0?ns 44 cas hold time for cas -before-ras refresh t chr 10?10?ns 45 access time from oe *9 t oea ?20?20ns 46 output buffer turn off delay from oe *10 t oez ?15?15ns 47 oe to ras lead time for valid data t oel 10?10?ns 48 oe to cas lead time t col 5?5?ns 49 oe hold time referenced to we *16 t oeh 0?0?ns 50 oe to data in delay time t oed 15?15?ns 51 din to cas delay time *17 t dzc 0?0?ns 52 din to oe delay time *17 t dzo 0?0?ns 53 cas to data in delay time t cdd 15?15?ns 54 ras to data in delay time t rdd 15?15?ns 55 column address hold time from ras t ar 26?26?ns 56 write command hold time from ras t wcr 24?24?ns 57 din hold time referenced to ras t dhr 24?24?ns 58 oe precharge time t oep 10?10?ns 59 oe hold time referenced to cas t oech 10?10?ns 60 we precharge time t wpz 10?10?ns 61 we to data in delay time t wed 15?15?ns 62 hyper page mode ras pulse width t rasp 60 200000 70 200000 ns 63 hyper page mode read/write cycle time t hpc 25?30?ns 64 hyper page mode read-modify-write cycle time t hprwc 66?71?ns 65 access time from cas precharge *9,18 t cpa ?35?40ns 66 hyper page mode cas pulse width t cp 10?10?ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?40?ns 68 hyper page mode cas precharge to we delay time t cpwd 52?57?ns
9 mb81v4265-60/-70 notes:*1. referenced to v ss . to all v cc (v ss ) pins, the same supply voltage should be applied. *2. i cc depends on the output load conditions and cycle rates; the specited values are obtained with the output open. i cc depends on the number of address change as ras = v il and ucas = v ih , lcas = v ih , v il > e0.3 v. i cc1 , i cc3 and i cc5 are specited at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc4 is specited at one time of address change during one page cycle. *3. an initial pause (ras =cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 2 ns. *5. input voltage levels are 0 v and 3.0 v, and input reference levels are v ih (min) and v il (max) for measuring timing of input signals. also, the transition time(t t ) is measured between v ih (min) and v il (max). the output reference levels are v oh =2.0 v and v ol =0.8 v. *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to one ttl load and 100 pf. *10. t off and t oez are specited that output buffer change to high impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specited as a reference point only; if t rcd is greater than the specited t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min)+ 2t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is specited as a reference point only; if t rad is greater than the specited t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satisted for a read cycle. *15. t wcs is specited as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satisted. *18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from l to h). therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. the last cas rising edge. *21. the trst cas falling edge.
10 mb81v4265-60/-70 n functional truth table x : h or l * : it is impossible in hyper page mode. operation mode clock input address input input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs ? t rcs (min) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs ? t wcs (min) read-modify- write cycle l l h l h l l h ll h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes cas -before- ras refresh cycle l l l x x high-z high-z yes t csr t csr (min) hidden refresh cycle h l l h l h l l h l valid high-z valid high-z valid valid yes previous data is kept. fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rad (ns) t cp (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad t rac (ns) t cpa (ns) 60 100 80 120 20 060 40 100 80 70ns version 60ns version 70 60 90 80 100 20 040 30 60 50 70ns version 40 60 50 70 10 030 20 50 40 60ns version 10 140 70ns version 60ns version
11 mb81v4265-60/-70 h or l description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. dq 8 to dq 16 pins is valid when ras and cas are high or until oe goes high. the access time is determined by ras (t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea. however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satisfied. fig. 5 e read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol lcas or ucas we dq (output) a 0 to a 8 v ih v il dq (input) v ih v il oe column add row add high-z high-z valid data t rc t ras t ra t crp t csh t rcd t rsh t cas t rp t rad t asr t rah t asc t cah t ral t cal t cdd t rdd t oel t col t rcs t rrh t rch t wpz t aa t cac t rac t dzc t on t oea t oez t dzo t on t oh t oed t wed t wez t oh t off
12 mb81v4265-60/-70 lcas or ucas h or l description a write cycle is similar to a read cycle except we is set to a low state and oe is an h or l signal. a write cycle can be imple- mented in either of three ways e early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satisfied. in the early write cycle shown above t wcs satisfied, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. fig. 6 e early write cycle ras a 0 to a 8 we dq (input) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq (output) column add t rc t ras low add high-z valid data in t csh t rp t rsh t rcd t crp t cas t ar t asr t rah t asc t cah t wcr t wcs t wch t dhr t ds t dh
13 mb81v4265-60/-70 h or l invalid data description in the delayed write cycle, t wcs is not satisfied; thus, the data on the dq pins are latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 e delayed write cycle (oe controlled) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 8 we dq (input) oe v oh v ol dq (output) row lcas or ucas t rc t ras add col add high-z high-z high-z t crp t ar t rp t csh t cas t rsh t rcd t asr t rah t asc t cah t rcs t wch t cwl t rwl t wp t ds t dh t dzc t oed t on t dzo t on t oez t oeh valid data i n
14 mb81v4265-60/-70 lcas or ucas fig. 8 e read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v oh v ol ras we a 0 to a 8 dq (output) h or l description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. v ih v il dq (input) v ih v il oe valid row t rp t rwc t ras t ar t crp t rcd t rad high-z high-z high-z add col add valid data i n t asr t rah t asc t cah t rwd t cwl t rwl t awd t cwd t rcs t dzc t rac t ds t wp t dh t oeh t oed t cac t aa t on t on t oea t dzo t oh t oez data
15 mb81v4265-60/-70 lcas or ucas description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 9 e hyper page mode read cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) v ih v il oe t rasp t crp t asr t asc t rcs t rhcp h or l t rp t rcd row add col add t cas t rsh t hpc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cpa t dzc t dzc t cah t ar t cah t rah t asc t rrh t cah t asc t rch t cdd valid data t on t cac t on t aa t rad col add t csh t ral high-z high-z t dzo t aa high-z t rac t rdd t oh high-z t ofr t off t oh t oez t oed t cpa t oh t on t ohc t cac t ohc t cac during one cycle is achieved, the input/output timing apply the same manner as the former cycle. col add
16 mb81v4265-60/-70 lcas or ucas fig. 10 ? hyper page mode read cycle (oe = ? or ?? v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. v ih v il we t rasp t asc t rcs t rhcp ? or ? t rp t rcd row t cas t rsh t hpc t cas t cas t cp t cah t cah t rah t asc t rrh t cah t asc t rch valid data t rad col add t csh t ral t ofr t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t oh t oh t cpa t cac t on t oep t oh t oech t oez t on t oez t oh t oech t oep t oea t dzo t on t cp t cal t cdd t col high-z t col t col t ar t aa t cac t aa t cpa t aa t rac t cac t oea t oea high-z t crp t asr t dzc high-z t rdd col add col add
17 mb81v4265-60/-70 lcas or ucas fig. 11 ? hyper page mode read cycle (we = ? or ?? v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row ad- dress. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring.. v ih v il oe t rasp t crp t asr t asc t rcs t rhcp ? or ? t rp row col add t cas t rsh t hpc t cas t cas t dzc t csh t cah t rah t csh t asc t rch valid data t cac t aa t csh t ral high-z t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t oh t oh t aa t cac t aa t oea t dzo t on t rac t rcd t ofr t rcs t rch t wpz t rcs t rch t cal t wez t cac t on t wpz t on t wez t wpz t cdd t wed t wez t on t asc t rdd high-z high-z t rad col add t ar col add
18 mb81v4265-60/-70 lcas or ucas fig. 12 e hyper page mode early write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) h or l row add high-z description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq1 to dq8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the hyper page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satisfied. t rasp t rp t rsh during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cas t hpc t csh t crp t rcd t cas t cp t cas t cah t ral t asc t cah t asc t asc t cah t ar t rah t asr t wcr t wcs t cwl t wch t wcs t cwl t wch t wch t wcs t cwl t rwl t dh t ds t dh t ds t ds t dh t dhr col add col add col add valid data valid data valid data t rhcp
19 mb81v4265-60/-70 lcas or ucas description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 13 e hyper page mode delayed write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il we dq (input) v oh v ol dq (output) v ih v il oe h or l high-z t rasp t rp t hpc row add invalid data t rsh t cas t cas t cp t csh t rcd t crp t asr t rah t ar t asc t cah t asc t cah t cwl col add col add valid data i n valid data i n t rwl t wch t wp t cwl t wch t rcs t wp t dzc t ds t dh t dh t ds t oed t on t on t oed t oeh t on t dzo t oez t on t oez t oeh a 0 to a 8
20 mb81v4265-60/-70 t ds lcas or ucas fig. 14 e hyper page mode read/write mixed cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) v ih v il oe description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min) is invalid. h or l valid data valid col add col add high-z row add high-z high-z data i n col add t rasp t csh t cas t rad t crp t cas t cas t rcd t rp t rsh t asr t rah t cah t asc t cah t asc t rhcp t asc t cah t cal t ral t hpc t cp t rac t rch t wed t wch t rcs t wcs t dzc t dh t cac t ohc t aa t cpa t cac t oed t wez t aa t oez t on t oea t on t dzo t cal
21 mb81v4265-60/-70 lcas or ucas fig. 15 e hyper page mode read-modify-write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 8 we dq (input) v oh v ol dq (output) v ih v il oe h or l high-z description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. t rasp t rp t crp col add valid data col add valid valid t rcd t cwd t rwl t hprwc t cwd t cp t asc t cah t asc t cah t rad t rah t asr t rcs t awd t cpwd t cwl t rcs t cwl t wp t wp t ds t dh t dh t ds t rwd t dzc t oed t cac t aa t on t on t aa t cac t oed t on t on t rac t dzo t oea t cpa t oeh t oez t oea t oeh t oez data data row add
22 mb81v4265-60/-70 lcas or ucas lcas or ucas fig. 16 e ras -only refresh (we = oe = h or l) fig. 17 e cas -before-ras refresh (addresses = we = oe = h or l) v ih v il ras v ih v il v ih v il v oh v ol a 0 to a 8 v ih v il v oh v ol v ih v il ras dq (output) row address h or l description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every 8.2-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be re- freshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. h or l description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the specified setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh ad- dress counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incre- mented in preparation for the next cas -before-ras refresh operation. dq (output) high-z t ras t rc t rp t rpc t crp t rah t asr t crp t off t oh high-z t rc t rp t ras t cpn t csr t chr t rpc t csr t cpn t off t oh
23 mb81v4265-60/-70 lcas or ucas fig. 18 e hidden refresh cycle v ih v il ras v ih v il v ih v il v ih v il v oh v ol a 0 to a 8 we v ih v il v ih v il dq (output) oe h or l row address description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. dq (input) high-z t rc t ras column address t ras t rc t rp t oel t rcd t rsh t rad t chr t rp t crp t rah t asr t asc t ral t cah t rcs t rrh t aa t rac t cac t dzc t cdd t off t oh t ofr t oh valid data out high-z t dzo t oea t on t oez t oed t ar
24 mb81v4265-60/-70 lcas or ucas fig. 19 e cas -before-ras refresh counter test cycle parameter unit min. max. m s no. min. max. ? ? 55 55 (at recommended operating conditions unless otherwise noted.) symbol 30 ?? ns 30 92 93 94 80 ?? ns 80 55 ?? m s 55 55 ?? ns 55 mb81v4265-60 MB81V4265-70 access time from cas column address hold time cas to we delay time cas pulse width ras hold time note: assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras a 0 to a 8 v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) oe 91 90 t fcac t fcah t fcwd t fcas t frsh h or l valid data column addresses description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function- ality of cas -before-ras refresh circuitry. after a cas -before-ras refresh cycle, if lcas or ucas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are defined as follows: row address: bits a 0 through a 8 are defined by the on-chip refresh counter. column address: bits a 0 through a 8 are defined by latching levels on a 0 to a 8 at the second falling edge of lcas or ucas the cas -before-ras counter test procedure is as follows; 1) normalize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write 0 to all 512 row addresses at the same column address by using cbr refresh counter test cycles. 4) read 0 written in procedure 3) by using normal read cycle and check; after reading 0 and check are completed (or simultaneously), write 1 to the same addresses by using normal write cycle (or read-modify-write cycle). 5) read and check data 1 written in procedure 4) by using cbr refresh counter test cycle for all 512 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) t frsh t rp high-z high-z high-z t chr t csr t cp t fcas t fcah t asc t rcs t cwl t rwl t wp t ds t dh t dzc t oed t fcac t oeh t oez t oea t on t dzo t fcwd t fcsh 95 cas hold time 85 ?? 85 valid data in ns
25 mb81v4265-60/-70 n package dimensions 26.030.13(1.0250.05) 3.50 +0.25 ?0.20 +.010 ?.008 .138 .008 ?.001 +.002 ?0.02 +0.05 0.20 (.370.020) 9.400.51 r0.89(.035)typ 0.64(.025)min 2.31(.091)nom 0.81(.032)max. 0.430.10(.017.004) details of "a" part 2.60(.102)nom 0.10(.004) index 20 21 40 1 1.270.13 (.050.005) 24.13(.950)ref (.440.005) 11.180.13 nom 10.16(.400) * "a" lead no 1995 fujitsu limited c40051s-3c-1 c dimensions in mm (inches) 40 pin, plastic soj (lcc-40p-m01) (continued)
26 mb81v4265-60/-70 (continued) +0.10 C0.05 +.004 C.002 35 44 32 23 22 13 * 0.25(.010) 0.15(.006) 0.40(.016)max 0.15(.006)max lead no. index "a" 1 10 (.006.002) 0.150.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.463.008) 11.760.20 (.400.004) 10.160.10 1.10 .043 (stand off) 0(0)min 0.10(.004) 16.80(.661)ref 0.80(.0315)typ 0.13(.005) m (.725.004) 18.410.10 (.012.004) 0.300.10 details of "a" part 1994 fujitsu limited f44016s-1c-2 c * resin protrusion. (each side: 0.15(.006)max.) dimensions in mm (inches) 44 pin, plastic tsop(ii) (fpt-44p-m07)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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