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CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 18-mbit ddr ii+ sram two-word burst architecture (2.5 cycle read latency) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53199 rev. *i revised january 31, 2011 18-mbit ddr ii+ sram two-burst architecture (2.5 cycle read latency) features 18-mbit density (2 m 8, 2 m 9, 1 m 18, 512 k 36) 550 mhz clock for high bandwidth 2-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 1100 mhz) at 550 mhz available in 2.5 clock cycle latency two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high-speed systems data valid pin (qvld) to indicate valid data on the output synchronous internally self-timed writes ddr ii+ operates with 2.5 cycle read lat ency when doff is asserted high operates similar to ddr i device with 1 cycle read latency when doff is asserted low core v dd = 1.8 v 0.1 v; i/o v ddq = 1.4 v to v dd [1] ? supports both 1.5 v and 1.8 v i/o supply hstl inputs and variable drive hstl output buffers available in 165-ball fbga package (13 15 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatible test access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: CY7C11661KV18 ? 2 m 8 cy7c11771kv18 ? 2 m 9 cy7c11681kv18 ? 1 m 18 cy7c11701kv18 ? 512 k 36 functional description the CY7C11661KV18, cy7c11771kv18, cy7c11681kv18, and cy7c11701kv18 are 1.8 v synchronous pipelined srams equipped with ddr ii+ architecture. the ddr ii+ consists of an sram core with advanced synchronous peripheral circuitry. addresses for read and write are latched on alternate rising edges of the input (k) clock. writ e data is registered on the rising edges of both k and k . read data is driven on the rising edges of k and k . each address location is associated with two 8-bit words (CY7C11661KV18), 9-bit words (cy7c11771kv18), 18-bit words (cy7c11681kv18), or 36-bit words (cy7c11701kv18) that burst sequentially into or out of the device. asynchronous inputs include an output impedance matching input (zq). synchronous data outputs (q, sharing the same physical pins as the data inputs d) are tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each indivi dual ddr sram in the system design. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchron ous self-timed write circuitry. table 1. selection guide description 550 mhz 500 mhz 450 mhz 400 mhz unit maximum operating frequency 550 500 450 400 mhz maximum operating current x8 740 690 630 580 ma x9 740 690 630 580 x18 760 700 650 590 x36 970 890 820 750 note 1. the cypress qdr ii+ devices surpass the q dr consortium specification and can support v ddq = 1.4 v to v dd . [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 2 of 26 logic block diagram (CY7C11661KV18) logic block diagram (cy7c11771kv18) write reg write reg clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 8 16 8 nws [1:0] v ref write add. decode 8 20 8 ld control r/w doff 1 m 8 array 1 m 8 array 8 dq [7:0] 8 cq cq qvld write reg write reg clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 9 18 9 bws [0] v ref write add. decode 9 20 9 ld control r/w doff 1 m 9 array 1 m 9 array 9 dq [8:0] 9 cq cq qvld [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 3 of 26 logic block diagram (cy7c11681kv18) logic block diagram (cy7c11701kv18) write reg write reg clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 18 36 18 bws [1:0] v ref write add. decode 18 19 18 ld control r/w doff 512 k 18 array 512 k 18 array 18 dq [17:0] 18 cq cq qvld write reg write reg clk a (17:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 36 72 36 bws [3:0] v ref write add. decode 36 18 36 ld control r/w doff 256 k 36 array 256 k 36 array 36 dq [35:0] 36 cq cq qvld [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 4 of 26 contents functional overview ........................................................ 5 read operations ......................................................... 5 write operations ......................................................... 5 byte write operations ................................................. 5 ddr operation ............................................................ 5 depth expansion ......................................................... 5 programmable impedance ........ .............. ........... ......... 5 echo clocks .......... .............. .............. .............. ............ 5 valid data indicator (qvld) ........................................ 6 pll .............................................................................. 6 application example ........................................................ 6 truth table ........................................................................ 7 write cycle description ? CY7C11661KV18 and cy7c11681kv18 ............................................................... 7 write cycle descriptions ? cy7c11771kv18 ................. 8 write cycle descriptions ? cy7c11701kv18 ................. 8 ieee 1149.1 serial boundary sc an (jtag) ... ........... ...... 9 disabling the jtag feature ........................................ 9 test access port?test clock ..................................... 9 test mode select (tms) ............................................. 9 test data-in (tdi) ....................................................... 9 test data-out (tdo) ................................................... 9 performing a tap re set ............................................. 9 tap registers ............................................................. 9 tap instruction set ..................................................... 9 tap electrical characteristics ...................................... 12 tap ac switching characteristics ............................... 13 tap timing and test conditions .................................. 13 power-up sequence in ddr ii+ sram ... .............. ........ 16 power-up sequence .. .............. ............... ........... ........ 16 pll constraints ......................................................... 16 maximum ratings ........................................................... 17 operating range ............................................................. 17 neutron soft error immunity ......................................... 17 electrical characteristics ............................................... 17 dc electrical characteristics ..................................... 17 ac electrical characteristics ........................................ 19 capacitance .................................................................... 19 thermal resistance ........................................................ 19 switching characteristics .............................................. 20 switching waveforms .................................................... 21 read/write/deselect sequence ............. ........... ........ 21 ordering information ...................................................... 22 ordering code definitions ..... .................................... 22 package diagram ............................................................ 23 acronyms ........................................................................ 24 document conventions ................................................. 24 units of measure ....................................................... 24 document history page ................................................. 25 sales, solutions, and legal information ...................... 26 worldwide sales and design s upport ......... .............. 26 products .................................................................... 26 psoc solutions ......................................................... 26 [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 5 of 26 functional overview the CY7C11661KV18, cy7c11771kv18, cy7c11681kv18, and cy7c11701kv18 are synchronous pipelined burst srams equipped with a ddr interface, which operates with a read latency of two and half cycles when doff pin is tied high. when doff pin is set low or connected to v ss , the device behaves in ddr i mode with a read latency of one clock cycle. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input and output timing are referenced from the rising edge of t he input clocks (k and k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the rising edge of the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the input clocks (k and k ). all synchronous control (r/w , ld , nws [x:0] , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clock (k). cy7c11681kv18 is described in the following sections. the same basic descriptions apply to CY7C11661KV18, cy7c11771kv18, and cy7c11701kv18. read operations the cy7c11681kv18 is organized internally as two arrays of 512 k 18. accesses are complete d in a burst of two sequential 18-bit data words. read operat ions are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next two k clock rise, the corresponding 18-bit word of data from this address location is driven onto the q [17:0] using k as the output timing reference. on the subsequent rising edge of k, the next 18-bit data word is driven onto the q [17:0] . the requested data is valid 0.45 ns from the rising edge of the input clock (k and k ). to maintain the internal logic, each read access must be allowed to complete. read accesses can be initiated on every rising edge of the positive input clock (k). when read access is deselected, the cy7c11681kv18 first completes the pending read transactions. synchronous internal circuitry automatically tristates the output following the next rising edge of the negative input clock (k ). this enables a transition between devices without the insert ion of wait states in a depth expanded memory. write operations write operations are init iated by asserting r/w low and ld low at the rising edge of the po sitive input clock (k). the address presented to address inputs is stored in the write address register. on the following k clock rise, the data presented to d [17:0] is latched and stored into the 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. write accesses can be initiated on every rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when the write access is dese lected, the device ignores all inputs after the pending write operations have been completed. byte write operations byte write operations are supp orted by the cy7c11681kv18. a write operation is initiated as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte wr ite select input during the data portion of a write latches the dat a being presented and writes it into the device. deasserting the byte write select input during the data portion of a write enab les the data stored in the device for that byte to remain unalte red. this feature can be used to simplify read, modify, or write operations to a byte write operation. ddr operation the cy7c11681kv18 enables high performance operation through high clock frequencies (achieved through pipelining) and ddr mode of operation. the cy7c11681kv18 requires two no operation (nop) cycle during transition from a read to a write cycle. at higher frequencies, some applications require third nop cycle to avoid contention. if a read occurs after a write cycle, address and data for the write are stored in registers. the writ e information is stored because the sram cannot perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle occurs. on the fi rst write cycle after the read(s), the stored data from the earlier write is written into the sram array. this is called a posted write. if a read is performed on the same address on which a write is performed in the previous cycle , the sram reads out the most current data. the sram does this by bypassing the memory array and reading the data from the registers. depth expansion depth expansion requir es replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedanc e matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5 v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the ddr ii+ to simplify data capture on high speed systems. two echo clocks are generated by the ddr ii+. cq is referenced with respect to k and cq is referenced with respect to k . these are free-running clocks and are synchronized to the input clock of the ddr ii+. the timing for the echo clocks is shown in the switching characteristics on page 20. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 6 of 26 valid data indicator (qvld) qvld is provided on the ddr ii+ to simplify data capture on high speed systems. the qvld is g enerated by the ddr ii+ device along with data output. this signal is also edge aligned with the echo clock and follows the timing of any data pin. this signal is asserted half a cycle befo re valid data arrives. pll these chips use a pll that is designed to function between 120 mhz and the specified maximum clock frequency. during power-up, when the doff is tied high, the pll is locked after 20 ? s of stable clock. the pll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary to reset the pll to lock to the desired frequency. the p ll automatically locks 20 ? s after a stable clock is presented. the pll may be disabled by applying ground to the doff pin. when the pll is turned off, the device behaves in ddr i mode (with one cycle latency and a longer access time). for information, refer to the application note, pll considerations in q drii/ddrii/q drii+/ddrii+ . application example figure 1 shows two ddr ii+ used in an application. figure 1. application example dq a sram#2 ld cq/cq k zq k r/w bws bus master (cpu or asic) dq addresses ld r/w r = 250ohms source clk source clk echo clock1/echo clock1 echo clock2/echo clock2 r = 250ohms bws dq a sram#1 ld k zq cq/cq k r/w bws [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 7 of 26 truth table the truth table for the CY7C11661KV18, cy7c11771 kv18, cy7c11681kv18, and cy7c11701kv18 follows. [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq write cycle: load address; wait one cycle; input write data on consecutive k and k rising edges. l-h l l d(a) at k(t + 1) ? d(a+1) at k (t + 1) ? read cycle: (2.5 cycle latency) load address; wait two and half cycles; read data on consecutive k and k rising edges. l-h l h q(a) at k (t + 2) ? q(a+1) at k(t + 3) ? nop: no operation l-h h x high z high z standby: clock stopped stopped x x previous state previous state write cycle description ? CY7C11661KV18 and cy7c11681kv18 the write cycle description table for CY7C11661KV18 and cy7c11681kv18 follows. [2, 8] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence ? CY7C11661KV18 ?? both nibbles (d [7:0] ) are written into the device. cy7c11681kv18 ?? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence ? CY7C11661KV18 ?? both nibbles (d [7:0] ) are written into the device. cy7c11681kv18 ?? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence ? CY7C11661KV18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c11681kv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence ? CY7C11661KV18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c11681kv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence ? CY7C11661KV18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c11681kv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence ? CY7C11661KV18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c11681kv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 2. x = ?do not care,? h = logic high, l = logic low, ? ? represents rising edge. 3. device powers up deselected with the outputs in a tristate condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 1 represents the address sequence in the burst. 5. ?t? represents the cycle at which a read/w rite operation is started. t + 1 and t + 2 are the first and second clock cycles su cceeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges as well. 7. ensure that when clock is stopped k = k and c = c = high. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. is based on a write cycle that was initiated in accordance with the write cycle description ? CY7C11661KV18 and cy7c11681kv18 table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 8 of 26 write cycle descriptio ns ? cy7c11771kv18 the write cycle description tabl e for cy7c11771kv18 follows. [2, 8] bws 0 k k comments l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device during this portion of a write operation. h ? l?h no data is written into the device during this portion of a write operation. write cycle descriptio ns ? cy7c11701kv18 the write cycle description tabl e for cy7c11701kv18 follows. [2, 8] bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll?l?hduring the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 9 of 26 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. th is part is fully compliant with ieee standard #1149. 1-2001. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull-up resistor. tdo must be left unconnected. upon power-up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram on page 11. tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 14). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram te st circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 12. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 15 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 14. tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 14. three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 10 of 26 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power-up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regi ster cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed, that is, while the data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #108. when this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 11 of 26 the state diagram for the tap controller follows. [9] figure 2. tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 9. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 12 of 26 figure 3. tap controller block diagram tap electrical ch aracteristics over the operating range [10, 11, 12] parameter description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 v v oh2 output high voltage i oh = ?? 100 a 1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltage ?0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd ?5 5 ? a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 10. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the dc electrical characteristics table. 11. overshoot: v ih (ac) < v ddq + 0.3 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 0.3 v (pulse width less than t cyc /2). 12. all voltage referenced to ground. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 13 of 26 tap ac switchi ng characteristics over the operating range [13, 14] parameter description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns tap timing and test conditions figure 4 shows the tap timing and test conditions. [14] figure 4. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9 v 50 ? 1.8 v 0 v all input pulses 0.9 v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 13. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 14. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 14 of 26 table 2. identificati on register definitions instruction field value description CY7C11661KV18 cy7c11771kv18 cy7c11681kv18 cy7c11701kv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010111000000100 11010111000001100 11010111000010100 11010111000100100 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. table 3. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 table 4. instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the bou ndary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 15 of 26 table 5. boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n 329f 605c 882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 16 of 26 power-up sequence in ddr ii+ sram ddr ii+ srams must be powered-up and initialized in a predefined manner to prevent undefined operations. power-up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 20 ? s to lock the pll. pll constraints pll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the pll functions at frequencies down to 120 mhz. if the input clock is unstable and the pll is enabled, then the pll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 20 ? s of stable clock to relock to the desired clock frequency. figure 5. po wer-up waveforms > 20 p s stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tie to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 17 of 26 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied . ?55 c to +125 c supply voltage on v dd relative to gnd ........?0.5 v to +2.9 v supply voltage on v ddq relative to gnd....... ?0.5 v to +v dd dc applied to outputs in high z..........?0.5 v to v ddq + 0.3 v dc input voltage [11] ............................. ?0.5 v to v dd + 0.3 v current into outputs (low) ......................................... 20 ma static discharge voltage (mil-std-883, m 3015)... > 2001 v latch-up current .................................................... > 200 ma electrical characteristics operating range range ambient temperature (t a ) v dd [15] v ddq [15] commercial 0 c to +70 c 1.8 0.1 v 1.4 v to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 197 216 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to appli- cation note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? dc electrical characteristics over the operating range [12] parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 16 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 17 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ? 0.2 v v ih input high voltage v ref + 0.1 ? v ddq + 0.15 v v il input low voltage ?0.15 ? v ref ? 0.1 v i x input leakage current gnd ? v i ? v ddq ? 2 ? 2 a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 2 ? 2 a v ref input reference voltage [18] typical value = 0.75 v 0.68 0.75 0.95 v notes 15. power-up: assumes a linear ramp from 0 v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 16. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 17. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 18. v ref (min) = 0.68 v or 0.46 v ddq , whichever is larger, v ref (max) = 0.95 v or 0.54 v ddq , whichever is smaller. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 18 of 26 i dd [19] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 550 mhz (x8) ? ? 740 ma (x9) ? ? 740 (x18) ? ? 760 (x36) ? ? 970 500 mhz (x8) ? ? 690 ma (x9) ? ? 690 (x18) ? ? 700 (x36) ? ? 890 450 mhz (x8) ? ? 630 ma (x9) ? ? 630 (x18) ? ? 650 (x36) ? ? 820 400 mhz (x8) ? ? 580 ma (x9) ? ? 580 (x18) ? ? 590 (x36) ? ? 750 i sb1 automatic power-down current max v dd , both ports deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc , inputs static 550 mhz (x8) ? ? 380 ma (x9) ? ? 380 (x18) ? ? 380 (x36) ? ? 380 500 mhz (x8) ? ? 360 ma (x9) ? ? 360 (x18) ? ? 360 (x36) ? ? 360 450 mhz (x8) ? ? 340 ma (x9) ? ? 340 (x18) ? ? 340 (x36) ? ? 340 400 mhz (x8) ? ? 320 ma (x9) ? ? 320 (x18) ? ? 320 (x36) ? ? 320 dc electrical characteristics (continued) over the operating range [12] parameter description test conditions min typ max unit note 19. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 19 of 26 ac electrical characteristics over the operating range [11] parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? v ddq + 0.24 v v il input low voltage ?0.24 ? v ref ? 0.2 v capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 4 pf c o output capacitance 4 pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 165-fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 13.7 c/w ? jc thermal resistance (junction to case) 3.73 c/w figure 6. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [20] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 20. unless otherwise noted, test conditions assume signal transit ion time of 2 v/ns, timing reference levels of 0.75 v, v ref = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 20 of 26 switching characteristics over the operating range [20, 21] cypress parameter consortium parameter description 550 mhz 500 mhz 450 mhz 400 mhz unit min max min max min max min max t power v dd (typical) to the first access [22] 1?1?1?1?ms t cyc t khkh k clock cycle time 1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4 ns t kh t khkl input clock (k/k ) high 0.4?0.4?0.4?0.4? ns t kl t klkh input clock (k/k ) low 0.4?0.4?0.4?0.4? ns t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 0.77?0.85?0.94?1.06? ns setup times t sa t avkh address setup to k clock rise 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns t sc t ivkh control setup to k clock rise (ld , r/w ) 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns t scddr t ivkh double data rate control setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.18?0.20?0.22?0.28? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.18?0.20?0.22?0.28? ns hold times t ha t khax address hold after k clock rise 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns t hc t khix control hold after k clock rise (ld , r/w ) 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.18?0.20?0.22?0.28? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.18?0.20?0.22?0.28? ns output times t co t chqv k/k clock rise to data valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns t doh t chqx data output hold after output k/k clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t ccqo t chcqv k/k clock rise to echo clo ck valid ?0.45?0.45?0.45?0.45ns t cqoh t chcqx echo clock hold after k/k clock rise ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid ? 0.15 ? 0.15 ? 0.15 ? 0.20 ns t cqdoh t cqhqx echo clock high to data invalid ?0.15 ? ?0.15 ? ?0.15 ? ?0.20 ? ns t cqh t cqhcql output clock (cq/cq ) high [23] 0.655 ? 0.75 ? 0.85 ? 1.00 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [23] 0.655 ? 0.75 ? 0.85 ? 1.00 ? ns t chz t chqz clock (k/k ) rise to high z (active to high z) [24, 25] ?0.45?0.45?0.45?0.45ns t clz t chqx1 clock (k/k ) rise to low z [24, 25] ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t qvld t cqhqvld echo clock high to qvld valid [26] ?0.15 0.15 ?0.15 0.15 ? 0.15 0.15 ?0.20 0.20 ns pll timing t kc var t kc var clock phase jitter ? 0.15 ? 0.15 ? 0.15 ? 0.20 ns t kc lock t kc lock pll lock time (k) 20?20?20?20? s t kc reset t kc reset k static to pll reset [27] 30?30?30?30? ns notes 21. when a part with a maximum frequency above 400 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 22. this part has an internal voltage regulator; t power is the time that the power is supplied above v dd min initially before a read or write operation can be initiated. 23. these parameters are extrapolated from the input timing parameters (t cyc /2 ? 250 ps, where 250 ps is the internal jitter). these parameters are only guaranteed by design and are not tested in production. 24. t chz , t clz are specified with a load capacitance of 5 pf as in (b) of ac test loads and waveforms . transition is measured ? 100 mv from steady-state voltage. 25. at any voltage and temperature t chz is less than t clz and t chz less than t co . 26. t qvld specification is applicable for both rising and falling edges of qvld signal. 27. hold to >v ih or CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 21 of 26 switching waveforms read/write/deselect sequence [28, 29, 30] figure 7. waveform for 2.5 cycle read latency 12 3 4 5 6 7 89 10 read read nop write write t nop 11 ld r/w a t kh t kl t cyc t hc t sa t ha dont care undefined sc a0 a1 a2 a3 a4 cq cq k qvld t nop nop dq k t ccqo t cqoh t ccqo t cqoh qvld t qvld t qvld t khkh 12 read (read latency = 2.5 cycles) nop nop t clz t chz cqdoh q00 q11 q01 q10 t doh t co q40 t sd hd t sd t hd d20 d21 d30 d31 t t cqd t t cqh t cqhcqh notes 28. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0 + 1. 29. outputs are disabled (high z) one clock cycle after a nop. 30. in this example, if address a4 = a3, then data q40 = d30 and q41 = d31. write data is forwarded immediately as read results. this note applies to the whole diagram. [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 22 of 26 ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distri butors. to find the office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . ordering code definitions table 6. ordering information speed (mhz) ordering code package diagram package type operating range 450 cy7c11681kv18-450bzc 51-85180 165-ball fpbga (13 15 1.4 mm) commercial cy7c11681kv18-450bzxc 165-ball f pbga (13 15 1.4 mm) pb-free 400 cy7c11681kv18-400bzc 51-85180 165-ball fpbga (13 15 1.4 mm) commercial cy7c11701kv18-400bzxc 165-ball f pbga (13 15 1.4 mm) pb-free temperature range: c = commercial package type: xxx = bz or bzx bz = 165-ball fpbga bzx = 165-ball fpbga (pb-free) frequency range: xxx = 450 mhz or 400 mhz voltage: 1.8 v 65 nm die revision part identifier: 11xxx = 11681 or 11701 = 18 -mbit ddr ii+ two-word burst architecture marketing code : 7c = sram company id: cy = cypress 7c cy 11xxx k v18 - xxx c xxx [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 23 of 26 package diagram figure 8. 165-ball fbga (13 15 1.4 mm), 51-85180 a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.08 m c b a 0.15(4x) seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / issue e package code : bb0ac 51-85180 *c [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 24 of 26 acronyms document conventions units of measure acronym description ddr double data rate fbga fine-pitch ball grid array hstl high speed transceiver logic jedec joint electron device engineering council jtag joint test action group lmbu logical multiple-bit upset lsbu logical single-bit upset pll phase-locked loop qdr quad data rate sel single event latch-up tap test access port tck test clock tdi test data in tdo test data out tms test mode select symbol unit of measure c degree celsius mhz megahertz a micro amperes ma milliamperes ns nano seconds ? ohms pf pico farad vvolts wwatts [+] feedback
CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 document number: 001-53199 rev. *i page 25 of 26 document history page document title: CY7C11661KV18/cy 7c11771kv18/cy7c11681kv18/cy7c11701kv 18, 18-mbit ddr ii+ sram two-word burst architecture (2.5 cycle read latency) document number: 001-53199 revision ecn orig of change submission date description of change ** 2702744 vkn/pyrs 05/06/09 new datasheet *a 2747707 vkn/aesa 08/03/2009 converted from preliminary to final for 550 mhz, 500 mhz, and 450 mhz bins, changed t co , t ccqo , t chz to 450 ps and t doh , t cqoh , t clz to ?450 ps included soft error immunity data modified ordering information table by including parts that are available and modified the disclaimer for the ordering information *b 2761928 aju 09/10/2009 post to external web *c 2767155 vkn 09/23/2009 changed input capacitance (c in ) from 2 pf to 4 pf changed output capacitance (c o ) from 3 pf to 4 pf modified ordering code disclaimer *d 2785104 vkn 10/16/2009 updated ordering information table *e 2855911 vkn 01/18/2010 included ?cy7c11701kv18-400bzxc? part in the ordering information table updated package outline diagram added contents. *f 2896003 njy 03/19/2010 removed inactive parts from ordering information . updated package diagram. updated links in sales, solutions, and legal information . *g 2950522 cs/njy 08/16/10 added partnumber cy7c11701kv18-450bzxc and cy7c11701kv18-400bzxc to the ordering information table. template update. added ordering code definitions, acronyms, and units of measure. *h 3056557 njy 10/12/2010 added new cy7c11681kv18-400bzxc part number to the ordering information table. *i 3158084 aju 01/31/2011 updated ordering information . [+] feedback
document number: 001-53199 rev. *i revised january 31, 2011 page 26 of 26 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. CY7C11661KV18, cy7c11771kv18 cy7c11681kv18, cy7c11701kv18 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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