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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. AD9875 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 a broadband modem mixed-signal front end functional block diagram register control rx mux adc pga lpf pga txdac+ kx interpolation lpf/bpf tx mux pll-a l pll-b m/n vrc 3 10 10 10 AD9875 tx+ tx gate fb oscin xtal rx+ rx pwr dn tx quiet gain tx [5:0] tx sync clk-a clk-b rx sync rx [5:0] sport v ref clock gen product description the AD9875 is a single supply broadband modem mixed- signal front end (mxfe) ic. the devices contain a transmit path interpolation filter and dac, and a receive path pga, lpf and adc supporting a variety of broadband modem appli cations. also on-chip is a pll clock multiplier that pro- vides all required clocks from a single crystal or clock input. the AD9875 provides 10-bit converter performance on both the tx and rx paths. the txdac+ uses a selectable digital 2 or 4 interpolation low-pass or band-pass filter to further oversample transmit data and reduce the complexity of analog reconstruction filtering. the transmit path signal bandwidth can be as high as 26 mhz at an input data rate of 64 msps. the 10-bit dac provides differential current outputs for optimum noise and distortion performance. the dac full-scale current can be adjusted from 2 ma to 20 ma by a single resistor, providing 20 db of additional gain range. the receive path consists of a pga, lpf, and adc. the two-stage pga has a gain range of ? db to +36 db, and is programmable in 2 db steps, adding 42 db of dynamic range to the receive path. mxfe is a trademark of analog devices, inc. txdac+ is a registered trademark of analog devices, inc. the receive path lpf cutoff frequency can be programmed to either 12 mhz or 26 mhz. the filter cutoff frequency can also be tuned or bypassed where filter requirements differ. the 10-bit adc uses a multistage differential pipeline architecture to achieve excellent dynamic performance with low power consumption. the AD9875 provides a voltage regulator controller (vrc) that can be used with an external power mosfet transistor to form a cost-effective 1.3 v linear regulator. the digital transmit and receive ports are each multiplexed to a bus width of 5/6 bits and are clocked at a frequency of twice the 10-bit word rate. the AD9875 adc and/or dac can also be used at higher sampling rates as high as 64 msps in a 5-bit resolution non- multiplexed mode. the AD9875 is pin-c ompatible with the 12-bit ad9876. both are available in a space-saving 48-lead lqfp package. they are speci- fied over the industrial (?0 c to +85 c) temperature range. features low cost 3.3 v-cmos mixed-signal front end ( mxfe? ) converter for broadband modems 10-/12-bit d/a converter (txdac+ ? ) 64/32 msps input word rate 2 /4 interpolating lpf or bpf transmit filter 128 msps dac output update rate wide (26 mhz) transmit bandwidth power-down mode 10-/12-bit, 50 msps a/d converter fourth order low-pass filter 12 mhz or 26 mhz with bypass C6 db to +36 db programmable gain amplifier internal clock multiplier (pll) clock outputs voltage regulator controller 48-lead lqfp package applications powerline networking home phone networking xdsl broadband wireless home rf
rev. 0 C2C AD9875?pecifications test parameter temp level min typ max unit osc in characteristics frequency range full ii 10 64 mhz duty cycle 25 cii 405060 % input capacitance 25 c iii 3 pf input impedance 25 c iii 100 m ? clock output characteristics clka jitter (f clka derived from pll) 25 c iii 14 ps rms clka duty cycle 25 c iii 50 5% clkb jitter (f clkb derived from pll) 25 c iii 33 ps rms clkb duty cycle 25 c iii 50 5% tx characteristics tx path latency, 4 interpolation full ii 82 f dac cycles interpolation filter bandwidth (?.1 db) 4 interpolation, lpf full ii 13 mhz 2 interpolation, lpf full ii 26 mhz txdac resolution full ii 10 bits conversion rate full ii 10 128 mhz full-scale output current full ii 2 10 20 ma voltage compliance range full ii ?.5 +1.5 v gain error full ii ? 2+5 % fs output offset full ii 0 7 19 a differential nonlinearity 25 c iii 0.5 lsb integral nonlinearity 25 c iii 1 lsb output capacitance 25 c iii 5 pf phase noise @ 1 khz offset, 10 mhz signal 25 c iii ?0 dbc/hz signal-to-noise and distortion (sinad) 10 mhz analog out AD9875 (20 mhz bw) full i 59 61 db wideband sfdr (to nyquist, 64 mhz max) 25 c iii 5 mhz analog out 25 c iii 78 dbc 10 mhz analog out 25 c iii 72 dbc narrowband sfdr (3 mhz window): 10 mhz analog out 25 c iii 80 dbc imd (f1 = 6.9 mhz, f2 = 7.1 mhz) 25 c iii ?6 dbfs rx path characteristics resolution full ii 10 bits conversion rate full ii 7.5 55 mhz pipeline delay, adc clock cycles full ii 5.5 cycles dc accuracy differential nonlinearity 25 c ii ?.0 0.25 +1.0 lsb integral nonlinearity 25 c ii ?.0 0.5 +2.0 lsb dynamic performance (a in = ?.5 dbfs, f = 5 mhz) @ f oscin = 32 mhz signal-to-noise and distortion ratio (sinad) 25 c iii 59.6 db effective number of bits (enob) 25 c iii 9.5 bits signal-to-noise ratio (snr) 25 c iii 60 db total harmonic distortion (thd) 25 c iii ?5 db spurious free dynamic range (sfdr) 25 c iii 68 db dynamic performance ( a in = ?.5 dbfs, f = 10 mhz ) @ f pllb/2 = 50 mhz signal-to-noise and distortion ratio (sinad) 25 c iii 54 db effective number of bits (enob) 25 c iii 8.6 bits signal-to-noise ratio (snr) 25 c iii 55 db total harmonic distortion (thd) 25 c iii ?1 db spurious free dynamic range (sfdr) 25 c iii 68 db (v s = 3.3 v 10%, f oscin = 32 mhz, f dac = 128 mhz, gain = ? db, r set = 4.02 k , 100 dac single-ended load, unless otherwise noted. )
rev. 0 C3C AD9875 test parameter temp level min typ max unit rx path gain/offset minimum programmable gain 25 c iii ? db maximum programmable gain (12 mhz filter) 25 c iii 36 db (26 mhz filter) 25 c iii 30 db gain step size 25 c iii 2 db gain step accuracy 25 c iii 0.4 db gain range error 25 c iii 1.0 db offset error, pga gain = 0 db (AD9875) 25 c iii 4.0 lsb absolute gain error, pga gain = 0 db 25 c iii 0.8 db rx path input characteristics input voltage range 25 c iii 4 vppd input capacitance 25 c iii 4 pf differential input resistance 25 c iii 270 ? input bandwidth (? db) 25 c iii 50 mhz input referred noise (at +36 db gain with filter) 25 c iii 16 v rms input referred noise (at ? db gain with filter) 25 c iii 684 v rms common-mode rejection 25 c iii 40 db rx path lpf (low cutoff frequency) cutoff frequency 25 c iii 12 mhz cutoff frequency variation 25 c iii 7% attenuation @ 22 mhz 25 c iii 20 db passband ripple 25 c iii 1.0 db group delay variation 25 c iii 30 ns settling time (to 1% fs, min to max gain change) 25 c iii 150 ns total harmonic distortion at max gain (thd) 25 c iii ?8 dbc rx path lpf (high cutoff frequency) cutoff frequency 25 c iii 26 mhz cutoff frequency variation 25 c iii 7% attenuation @ 44 mhz 25 c iii 20 db passband ripple 25 c iii 1.2 db group delay variation 25 c iii 15 ns settling time (to 1% fs, min to max gain change) 25 c iii 80 ns total harmonic distortion at max gain (thd) 25 c iii ?5 dbc rx path digital hpf latency (adc clock source cycles) full ii 1 cycle roll-off in stopband full ii 6 db/octave ? db frequency full ii f adc /400 hz rx path distortion performance imd: f1 = 6.9 mhz, f2 = 7.1 mhz 12 mhz filter: 0 db 25 c iii ?5 dbc : 30 db 25 c iii ?7 dbc 28 mhz filter: 0 db 25 c iii ?5 dbc : 30 db 25 c iii ?6 dbc power-down/disable timing power-up delay (power-down-to-active) dac 25 cii 40 s pll 25 cii 10 s adc 25 c ii 1000 s pga 25 cii 1 s lpf 25 cii 1 s interpolator 25 c ii 200 ns vrc 25 cii 2 s minimum reset pulsewidth low (t rl ) full iii 5 f oscin cycle dac i out off after tx quiet asserted 25 c ii 200 ns dac i out on after tx quiet deasserted 25 cii 1 s power-down delay (active-to-power-down) dac 25 c ii 400 ns interpolator 25 c ii 200 ns
rev. 0 C4C AD9875?pecifications test parameter temp level min typ max unit tx path interface maximum input nibble rate, 2 interp. full ii 128 mhz tx-set up time (t su ) full ii 3.0 ns tx-hold time (t hd ) full ii 0 ns rx path interface maximum output nibble rate full i 110 mhz rx-datavalid time (t vt ) full ii 3.0 ns rx-data hold time (t ht ) full ii 1.5 ns cmos logic inputs logic ??voltage full ii v drvdd ?0.7 v logic ??voltage full ii 0.4 v logic ??current full ii 12 a logic ??current full ii 12 a input capacitance 25 c iii 3 f cmos logic outputs (1 ma load) logic ??voltage full ii v drvdd ?0.6 v logic ??voltage full ii 0.4 v digital output rise/fall time full ii 1.5 2.5 ns power supply all blocks powered up i s_total (total supply current) full i 262 288 ma i s_total (tx_quiet pin asserted) 25 c iii 172 ma digital supply current (i drvdd + i dvdd )25 c iii 77 ma analog supply current (i avdd )25 c iii 185 ma power consumption of functional blocks: rx lpf 25 c iii 110 ma adc and fpga 25 c iii 55 ma rx reference 25 c iii 2 ma interpolator 25 c iii 33 ma dac 25 c iii 18 ma pll-b 25 c iii 8 ma pll-a 25 c iii 24 ma voltage regulator controller 25 c iii 1 ma all blocks powered down supply current i s , f oscin = 32 mhz full ii 19 22 ma supply current i s , f oscin idle full ii 10 12 ma power supply rejection tx path ( ? v s = 10%) 25 c iii 62 db rx path ( ? v s = 10%) 25 c iii 54 db serial control bus maximum sclk frequency (f sclk ) full ii 25 mhz clock pulsewidth high (t pwh ) full ii 18 ns clock pulsewidth low (t pwl ) full ii 18 ns clock rise/fall time full ii 1 ms data/chip-select setup time (t ds ) full ii 25 ns data hold time (t dh ) full ii 0 ns data valid time (t dv ) full ii 20 ns receive-to-transmit isolation (10 mhz, full-scale sinewave output/output) isolation: tx path to rx path, gain = +36 db 25 c iii ?5 db isolation: rx path to tx path, gain = ? db 25 c iii ?0 db voltage regulator controller output voltage (v fb with si2301 connected) full i 1.25 1.30 1.35 v line regulation ( ? v fb% / ? v dvdd% 100%) 25 c iii 100 % load regulation ( ? v fb / ? i load )25 c iii 60 m ? maximum load current (i load ) full ii 250 ma specifications subject to change without notice. (continued)
rev. 0 AD9875 C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9875 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. model temperature range package description package option AD9875bst ?0 c to +85 c 48-lead lqfp st-48 AD9875-eb ?0 c to +85 c evaluation board AD9875bstrl ?0 c to +85 c bst reel absolute maximum ratings * power supply (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs . . . . . . . . . . . . . . . . . ?.3 v to drvdd 0.3 v analog inputs . . . . . . . . . . . . . . . . . . ?.3 v to avdd 0.3 v operating temperature . . . . . . . . . . . . . . . . . ?0 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i devices are 100% production tested at 25 c and guaran- teed by design and characterization testing for industrial operating temperature range (?0 c to +85 c). ii parameter is guaranteed by design and/or characterization testing. iii parameter is a typical value only. thermal characteristics thermal resistance 48-lead lqfp ja = 57 c/w jc = 28 c/w warning! esd sensitive device ordering guide
rev. 0 AD9875 C6C pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 drvss drvdd rx [0] rx [1] rx [2] rx [3] rx [4] rx [5] rx sync clk-b clk-a tx sync 13 14 15 16 17 18 19 20 21 22 23 24 dvss dvdd fb gate gain tx quiet tx [5] tx [4] tx [3] tx [2] tx [1] tx [0] 1 2 3 4 5 6 7 8 9 10 11 12 oscin senable sclk sdata avdd avss tx+ tx avss fsadj refio pwr dn 48 47 46 45 44 39 38 37 43 42 41 40 xtal avdd avss rx rx+ avss avss reft refb avss avdd reset pin 1 identifier top view (not to scale) AD9875 pin name function 1 oscin crystal oscillator inverter input 2 senable serial bus enable input 3 sclk serial bus clock input 4 sdata serial bus data i/o 5, 38, 47 avdd analog 3.3 v power supply 6, 9, 39, 42, 43, 46 avss analog ground 7 tx+ transmit dac+ output 8 tx transmit dac?output 10 fsadj dac full-scale output current adjust with external resistor 11 refio dac bandgap decoupling node 12 pwr dn power-down input 13 dvss digital ground 14 dvdd digital 3.3 v power supply 15 fb regulator feedback input 16 gate regulator output to fet gate 17 gain transmit data port (tx[5:0]) mode select input 18 tx quiet transmit quiet input 19?4 tx[5:0] transmit data input 25 tx sync transmit synchronization strobe input 26 clk-a l f oscin clock output 27 clk-b m/n f oscin clock output 28 rx sync receive data synchronization strobe output 29?4 rx[5:0] receive data output 35 drvdd digital i/o 3.3 v power supply 36 drvss digital i/o ground 37 reset reset input 40 refb adc reference decoupling node 41 reft adc reference decoupling node 44 rx+ receive path + input 45 rx receive path ?input 48 xtal crystal oscillator inverter output pin function descriptions
rev. 0 AD9875 C7C definitions of specifications clock jitter the clock jitter is a measure of the intrinsic jitter of the pll generated clocks. it is a measure of the jitter from one rising and of the clock with respect to another edge of the clock nine cycles later. differential nonlinearity error (dnl, no missing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?egative full scale?through ?ositive full scale.?the point used as ?egative full scale?occurs 1/2 lsb before the first code transition. ?ositive full scale?is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. phase noise single-sideband phase noise power density is specified relative to the carrier (dbc/hz) at a given frequency offset (1 khz) from the carrier. phase noise can be measured directly on a generated single tone with a spectrum analyzer that supports noise marker measurements. it detects the relative power between the carrier and the offset (1 khz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). it also adds a correction factor that compensates for the imple- mentation of the resolution bandwidth, log display and detector characteristic. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation, resulting in nonlinear per- formance or breakdown. spurious?ree dynamic range (sfdr) the difference, in db, between the rms amplitude of the dacs output signal (or adc? input signal) and the peak spurious signal over the specified bandwidth (nyquist bandwidth unless otherwise noted). pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. offset error first transition should occur for an analog value 1/2 lsb above negative full scale. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. input referred noise the rms output noise is measured using histogram techniques. the adc output codes?standard deviation is calculated in lsb, and converted to an equivalent voltage. this results in a noise figure that can be directly referred to the rx input of the AD9875. signal-to-noise and distortion ratio (sinad) sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula, n = ( sinad ?1.76) db/6.02 it is possible to get a measure of performance expressed as n , the effective number of bits. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. power supply rejection power supply rejection specifies the converters maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.
rev. 0 typical tx digital filter performance characteristics C8C normalized f s 10 60 100 0 50 70 80 10 30 20 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db interpolation filter including sin(x)/x tpc 1. 4 low-pass interpolation filter normalized f s 10 60 100 0 50 70 80 10 30 20 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db interpolation filter including sin(x)/x tpc 2. 2 low-pass interpolation filter normalized f s 10 60 100 0 50 70 80 10 30 20 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db interpolation filter including sin(x)/x tpc 3. 4 bandpass interpolation filter, f s /2 modulation, adjacent image preserved normalized f s 60 100 50 70 80 30 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db 10 0 10 20 interpolation filter including sin(x)/x tpc 4. 2 bandpass interpolation filter, f s /2 modulation, adjacent image preserved normalized f s 10 60 100 0 50 70 80 10 30 20 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db interpolation filter including sin(x)/x tpc 5. 4 bandpass interpolation filter, f s /4 modulation, lower image preserved normalized f s 10 60 100 0 50 70 80 10 30 20 40 90 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db including sin(x)/x interpolation filter tpc 6. 4 bandpass interpolation filter, f s /4 modulation, upper image preserved AD9875
rev. 0 AD9875 C9C frequency mhz 0 13263851647790102115128 0 10 10 20 30 40 50 60 70 80 90 magnitude dbc tpc 7. single tone spectral plot @ f data = 32 msps, f out = 5 mhz, 4 lpf frequency mhz 0 10 10 20 30 40 50 60 70 80 90 magnitude dbc 0 10203040506070 8090100 tpc 8. single tone spectral plot @ f data = 50 msps, f out = 11 mhz, 2 lpf f out mhz 90 85 60 80 75 70 65 13 246 579 81012 11 13 15 14 16 18 17 magnitude dbc f data = 32msps f data = 50msps tpc 9. in band sfdr vs. f out @ f data = 32 msps and 50 msps f out mhz 90 85 60 80 75 70 65 13 246 579 81012 11 13 15 14 16 18 17 magnitude dbc f data = 50msps f data = 50msps +,-. =; 2>31 ;7+ 9 + :$#53,3 &53,3 frequency mhz 0 10 10 20 30 40 50 60 70 80 90 100 7.5 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 magnitude dbc tpc 11. dual tone spectral plot @ f data = 32 msps, f out = 6.9 mhz and 7.1 mhz, 4 lpf frequency mhz 0 10 10 20 30 40 50 60 70 80 90 100 7.5 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 magnitude dbc tpc 12. dual tone spectral plot @ f data = 50 msps, f out = 6.9 mhz and 7.1 mhz, 2 lpf typical ac characteristics curves for txdac (r set = 4.02 k , r dac = 100 )
rev. 0 AD9875 C10C frequency offset khz 0 10 10 20 30 40 50 60 70 80 90 100 magnitude dbc 101 23456789 tpc 13. phase noise plot @ f data = 32 msps, f out = 10 mhz, 4 lpf frequency offset khz 0 10 10 20 30 40 50 60 70 80 90 100 magnitude dbc 101 23456789 tpc 14. phase noise plot @ f data = 50 msps, f out = 10 mhz, 2 lpf frequency mhz 0 10 10 20 30 40 50 60 70 magnitude dbc 3 5 7 9 11 13 15 17 19 21 23 tpc 15. in band multitone spectral plot @ f data = 50 msps, f out = k 195 khz, 2 lpf 311 31 21 41 51 61 71 81 91 101 frequency mhz 0 10 10 20 30 40 50 60 70 magnitude dbc tpc 16. wide-band multitone spectral plot @ f data = 50 msps, f out = k 195 khz, 2 lpf typical ac characteristics curves for txdac (r set = 4.02 k , r dac = 10.0 )
rev. 0 AD9875 C11C 20 22 24 26 28 30 34 32 36 38 40 64 80 96 112 128 144 160 176 192 frequency mhz tpc 17. rx vs. tuning target, f adc = 32 mhz, lpf with wideband rx lpf = 1 vga gain db magnitude db 0.80 0.60 0.40 0.20 0.00 0.20 0.60 0.40 6 4 2024681012141618202224262830323436 tpc 18. pga gain error vs. gain 8 9 10 11 12 13 15 14 16 17 18 48 64 80 96 112 128 144 160 176 192 frequency mhz +,-.8 - ++
- :$#5</,1 @a/,1: vga gain db magnitude db 1.5 1.6 1.7 1.8 1.9 2.0 2.2 2.1 2.3 2.4 2.5 6 4 2024681012141618202224262830323436 tpc 20. pga gain step size vs. gain typical ac characterization curves for rx path
rev. 0 AD9875 C12C 1mhz 10mhz 100mhz 10.8mhz 0 log mag 5db/ref 0db 3.0db tpc 21. rx lpf frequency response, low f c nominal tuning targets 26.5mhz 1mhz 10mhz 100mhz 0 log mag 5db/ref 0db 3.0db tpc 22. rx lpf frequency response, high f c nominal tuning targets 14.5mhz 1mhz 10mhz 100mhz 0 log mag 5db/ref 0db 3.0db tpc 23. rx lpf frequency response, low f c , 0 60 and 0 96 tuning targets 9.0mhz 1mhz 10mhz 100mhz 0 delay 10ns/ref 0s 72.188ns tpc 24. rx lpf group delay, low f c nominal tuning targets 22.5mhz 1mhz 10mhz 100mhz 0 delay 5ns/ref 0s 34.431ns tpc 25. rx lpf group delay, high f c , nominal tuning targets 1mhz 10mhz 100mhz 0 14.5mhz delay 10ns/ref 0s 51.244ns tpc 26. rx lpf group delay, low f c , 0 60 and 0 96 tuning targets typical ac characterization curves for rx path (f adc = 32 mhz)
rev. 0 AD9875 C13C 33.5mhz 1mhz 10mhz 100mhz 0 log delay 5db/ref 2db 5.1933db tpc 27. rx lpf frequency response, high f c , 0 60 and 0 96 tuning targets 78.8mhz 0 log mag 5db/ref 0db 3.01db 10khz 100khz 1mhz tpc 28. rx hpf frequency response, f adc = 32 mhz adc clock cycles adc output code 600 650 700 750 800 850 900 950 1000 0 5 10 15 20 25 30 35 40 f adc = 50mhz f adc = 32mhz tpc 29. rx path setting, 1/2 scale rising step with gain change 29.5mhz 0 1mhz 10mhz 100mhz log delay 5ns/ref 0s 29.97ns +,-$ a/,1b
- 60 and 0 96 tuning targets gain setting db 700 600 100 500 400 300 200 0 614 42434 adc input rms noise v filter enabled filter bypassed tpc 31. rx input referred noise vs. gain @ f adc = 32 msps, f in = 1 mhz 600 650 700 750 800 850 900 950 1000 adc clock cycles adc output code 0 5 10 15 20 25 30 35 40 f adc = 50mhz f adc = 32mhz tpc 32. rx path setting, 1/2 scale falling step with gain change typical ac characterization curves for rx path (f adc = 32 mhz)
rev. 0 AD9875 C14C f s mhz enob 10.0 9.0 7.0 10 20 30 40 50 8.0 8.5 9.5 7.5 f oscin f pllb/2 15 25 35 45 tpc 33. rx path enob vs. f adc f in mhz enob 10.0 9.0 7.0 0 8.0 8.5 9.5 7.5 f oscin f pllb/2 2468101214161820 tpc 36. rx path enob vs. f in gain db enob 10.0 60 612 f poscin f pllb/2 18 24 30 36 9.5 9.0 8.5 8.0 tpc 39. rx path enob vs. gain f s mhz magnitude db 60 56 48 52 54 58 50 10 20 25 30 15 35 40 45 50 f oscin f pllb/2 tpc 34. rx path snr vs. f adc f in mhz magnitude db 0 46810 2 1214161820 70 60 40 50 55 65 45 f oscin f pllb/2 tpx 37. rx path snr vs. f in gain db magnitude db 65 60 45 66 12 18 50 55 0 243036 f oscin f pllb/2 tpc 40. rx path snr vs. gain f s mhz magnitude db 50 10 f oscin f pllb/2 15 20 25 30 35 40 45 50 55 60 65 70 75 80 tpc 35. rx path thd vs. f adc f in mhz magnitude db 50 55 70 0 65 60 f oscin f pllb/2 2468101214161820 75 80 tpc 38. rx path thd vs. f in gain db magnitude - db 50 70 66 24 36 65 60 55 f oscin f pllb/2 0121830 tpc 41. rx path thd vs. gain typical ac characterization curves for rx path (gain = 6 db, f in = 5 mhz)
rev. 0 AD9875 C15C transmit path the AD9875 transmit path consists of a digital interface port, a programmable interpolation filter, and a transmit dac. all clock signals required by these blocks are generated from the f oscin signal by the pll-a clock generator. the block diagram below shows the interconnection between the major functional components of the transmit path. tx+ tx oscin xtal kx interpolation lpf/bpf clock gen pll-a l tx quiet gain tx [5:0] tx sync clk-a f clk-a f dac = l f oscin f oscin 10 10 tx demux txdac+ AD9875 figure 1 . transmit path block diagram digital interface port the transmit digital interface port has several modes of operation. in its default configuration, the tx port accepts six bit nibbles through the tx[5:0] and txsync pins and demul- tiplexes the data into 12-bit words before passing it to the interpolation filter. the input data is sampled on the rising edge of f clk-a . additional programming options for the tx port allow; sampling the input data on the falling edge of f clk? , inversion or dis- abling of f clk-a , reversing the order of the nibbles, and inputting nibble widths of 5 bits/5 bits. also, the tx port interface can be controlled by the gain pin to provide direct access to the rx path gain adjust register. all of these modes are fully described in the register programming definitions section of this data sheet. the data format is two? complement, as shown below: 011 . . 11: maximum 000 . . 01: midscale + 1 lsb 000 . . 00: midscale 111 . . 11: midscale ?1 lsb 111 . . 10: midscale ?2 lsb 100 . . 00: minimum the data can be translated to straight binary data format by simply inverting the most significant bit. the timing of the interface is fully described in the transmit timing section of this data sheet. pll-a clock distribution figure 1 shows the clock signals used in the transmit path. the dac sampling clock, f dac , is generated by dpll-a. f dac has a frequency equal to l f oscin , where f oscin is the internal signal generated either by the crystal oscillator when a crystal is con- nected between the oscin and xtal pins, or by the clock that is fed into the oscin pin, and l is the multiplier programmed through the serial port. l can have the values of 1, 2, 4, or 8. the transmit path expects a new half-word of data at the rate of f clk-a . when the tx multiplexer is enabled, the frequency of the tx port is: f clk-a = 2 f dac /k = 2 l f oscin /k where k is the interpolation factor that can be programmed to be 1, 2, or 4. when the tx multiplexer is disabled, the frequency of the tx port is: f clk-a = f dac /k = l f oscin /k . interpolation filter the interpolation filter can be programmed to run at 2 and 4 upsampling ratios in each of three different modes. the transfer functions of these six configurations are shown in tpcs 1?. the x-axis of each of these figures corresponds to the frequency normalized to f dac . these transfer functions show both the discrete time transfer function of the interpolation filters alone and with the sin(x)/x transfer function of the dac. the inter- polation filter can also be programmed into a pass-through mode if no interpolation filtering is desired. the contents of the interpolation filters are not cleared by hardware or software resets. it is recommended to ?lush?the transmit data path with zeros before transmitting data. table i contains the following parameters as a function of the mode that it is programmed: latency ?the number of clock cycles from the time a digital impulse is written to the dac until the peak value is output at the tx pins. flush ?the number of clock cycles from the time a digital impulse is w ritten to the dac until the output at the tx pins settles to zero. f lower (0.1 db, 3 db) ?this indicates the lower 0.1 db or 3 db cutoff frequency of the interpolation filter as a fraction of f dac , the dac sampling frequency. f upper (0.1 db, 3 db) ?this indicates the upper 0.1 db or 3 db cutoff frequency of the interpolation filter as a fraction of f dac , the dac sampling frequency. table i. interpolation filter parameters vs. mode register 7[7:4] 0 00 10 40 50 80 c mode 4 lpf 2 lpf 4 bpf 2 bpf 4 bpf 4 bpf adj. adj. lower upper latency, f dac 86 30 86 30 86 86 clock cycles flush, f dac 128 48 128 48 142 142 clock cycles f lower, 0.1 db 0 0 0.398 0.276 0.148/ 0.274/ 0.774 0.648 f upper, 0.1 db 0.102 0.204 0.602 0.724 0.226/ 0.352/ 0.852 0.762 f lower, 3 db 0 0 0.381 0.262 0.131/ 0.257/ 0.757 0.631 f upper, 3 db 0.119 0.238 0.619 0.738 0.243/ 0.369/ 0.869 0.743
rev. 0 AD9875 C16C d/a converter the AD9875 dac provides differential output current on the tx+ and tx?pins. the value of the output currents are compli- mentary, meaning that they will always sum to i fs , the full-scale current of the dac. for example, when the current from tx+ is at full-scale, the current from tx?is zero. the two currents will typically drive a resistive load which will convert the output currents to a voltage. the tx+ and tx?output currents are inherently ground seeking and should each be connected to matching resistors, r l , that are tied directly to agnd. the full-scale output current of the dac is set by the value of the resistor placed from the fsadj pin to agnd. the relation- ship between the resistor, r set , and the full-scale output current is governed by the following equation: i fs = 39.4/ r set the full-scale current can be set from 2 ma to 20 ma. gener- ally, there is a trade-off between dac performance and power consumption. the best dac performance will be realized at an i fs of 20 ma. however, the value of i fs adds directly to the overall current consumption of the device. the single-ended voltage output appearing at the tx+ and tx nodes are: v tx+ = i tx+ r l v tx = i tx r l note that the full-scale voltage of v tx+ and v tx should not exceed the maximum output compliance range of 1.5 v to pre- vent signal compression. to maintain optimum distortion and linearity performance, the maximum voltages at v tx+ and v tx should not exceed 0.5 v. the single ended full-scale voltage at either output node will be: v fs = i fs r l the differential voltage, v diff , appearing across v tx+ and v tx is: v diff = (i tx+ ?i tx ) r l and v diff_fs = i fs r l for optimum performance, a differential output interface is recommended since any common-mode noise or distortion can be supressed. it should be noted that the differential output impedance of the dac is 2 r l and any load connected across the two output resistors will load down the output voltage accordingly. receive path description the receive path consists of a two-stage pga, a continuous time, 4-pole lpf, an adc, a digital hpf and a digital data multiplexer. also working in conjunction with the receive path is an offset correction circuit and a digital phase lock loop. each of these blocks will be discussed in detail in the following sections. programmable gain amplifier the pga has a programmable gain range from ? db to +36 db if the narrower (approximately 12 mhz) lpf bandwidth is selected, or if the lpf is bypassed. if the wider (approximately 26 mhz) lpf bandwidth is selected, the gain range is ? db to +30 db. the pga is comprised of two sections, a continuous time pga (cpga) and a sw itched capacitor pga (spga). the cpga has possible gain settings of ?, 0, 6, 12, 18, and 24. the spga has possible gain settings of 0, 2, 4, 6, 8, 10, and 12 db. table i shows how the gain is distributed for each programmed gain setting. the cpga input appears at the device rx+ and rx?input pins. the input impedance of this stage is nominally 270 ? differen- tial and is not gain dependent. it is best to ac-couple the input signal to this stage and let the inputs self bias. this will lower the offset voltage of the input signal, which is important at higher gains, as any offset will lower the output compliance range of the cpga output. when the inputs are driven by direct coupling, the dc level should be avdd/2. however, this could lead to larger dc offsets and consequently reduce the dynamic range of the rx path. low-pass filter the low-pass filter (lpf) is a programmable, multistage, fourth order low-pass filter comprised of two real poles and a complex pole pair. the first real pole is implemented within the cpga. the second filter stage implements a complex pair of poles. the last real pole is implemented in a buffer stage that drives the spga. there are two passband settings for the lpf. within each pass- band the filters are tunable over about a 30% frequency range. the formula for the cutoff frequency is: f cutoff low = f adc 64 /( 64 + target) f cutoff high = f adc 158 /( 64 + target) where target is the decimal value programmed as the tuning target in register 5. this filter may also be bypassed by setting bit 0 of register 4. in this case, the bandwidth of the rx path will decrease with increasing gain and be approximately 50 mhz at the highest gain settings. adc the AD9875? analog-to-digital converter implements a pipelined multistage architecture to achieve high sample rates while con- suming low power. the adc distributes the conversion over several smaller a/d subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. as a consequence of the distributed conversion, adcs require a small fraction of the 2 n comparators used in a tradi- tional n-bit flash-type a/d. a sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. each stage of the pipeline, excluding the last, consists of a low resolution flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipe- line. one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash a/d.
rev. 0 AD9875 C17C ainp ainn gain sha gain correction logic a/d d/a sha a/d d/a a/d AD9875 figure 2. adc theory of operation the digital data outputs of the adc are represented in two? complement format. they saturate to full-scale or zero when the input signal exceeds the input voltage range. the two? complement data format is shown below: 011 . . 11: maximum 000 . . 01: midscale + 1 lsb 000 . . 00: midscale 111 . . 11: midscale ?1 lsb 111 . . 10: midscale ?2 lsb 100 . . 00: minimum the maximum value will be output from the adc when the rx+ input is 1v or more greater than the rx?input. the mini- mum value will be output from the adc when the rx?input is 1 v or more greater than the rx+ input. this results in a full- scale adc voltage of 2 vppd. the data can be translated to straight binary data format by simply inverting the most significant bit. the best adc performance will be achieved when the adc clock source is selected from f oscin and f oscin is provided from a low jitter clock source. the amount of degradation from jitter on the adc clock will depend on how quickly the input is varying at the sampling instance. tpc 36 charts this effect in the form of enob vs. input fre quency for the two clocking scenarios. the maximum sample rate of the adc in full-precision mode, that is outputting 10 bits, is 55 msps. tpc 33 shows the adc performance in enob vs. f adcclk . the maximum sample rate of the adc in half-precision mode, that is outputting five bits, is 64 msps. the timing of the interface is fully described in the receive timing section of this data sheet. digital hpf following the adc there is a bypassable digital hpf. the response is a single pole iir hpf. the transfer function is approximately: h(z) = (z ? 0.99994 )/(z ? 0.98466 ) where the sampling period is equal to the adc clock period. this results in a 3 db frequency approximately 1/400th of the adc sampling rate. the transfer functions are plotted for 32 msps and 50 msps in tpc 31 and tpc 32. the digital hpf introduces a 1 adc clock cycle latency. if the hpf function is not desired, the hpf can be bypassed and the latency will not be incurred. clock and oscillator circuitry the AD9875? internal oscillator generates all sampling clocks from a fundamental frequency quartz crystal. figure 3a shows how the quartz crystal is connected between oscin (pin 1) and xtal (pin 48) with parallel resonant load capacitors as speci fied by the crystal manufacturer. the internal oscillator circuitry can also be overdriven by a ttl level clock applied to oscin with xtal left unconnected. the pll has a frequency capture range between 10 mhz and 64 mhz. voltage regulator controller the AD9875 contains an on-chip voltage regulator controller (vrc) for providing a linear 1.3 v supply for low voltage digital circuitry or other external use. the vrc consists of an op amp and a resistive voltage divider. as shown in figure 3b, the resis- tive divider establishes a voltage of 1.3 v at the inverting input of the amplifier when dvdd is equal to its nominal voltage of 3.3 v. the feedback loop around the op amp will adjust the gate voltage such that the voltage at the fb pin, v fb , will be equal to the voltage at the inverting input of the op amp. xtal c2 AD9875 oscin c1 xtal y1 figure 3a. connections for fundamental mode crystal dvdd gate fb v fb = 1.3v v out si2301 1.3r 2r 3.3v s g d c AD9875 figure 3b. connections for a 1.3 v linear regulator the maximum current output from the circuit is largely depen- dent on the mosfet device. for the si2301 shown, 250 ma can be delivered. the regulated output voltage should have bulk decoupling and high frequency decoupling capacitors to ground as required by the load. the regulator circuit will be stable for capacitive loads between 0.1 f and 47 f. it should be noted that the regulated output voltage, v fb , is proportional to dvdd. therefore, the percentage variation in dvdd will also be seen at the regulated output voltage. the load regulation is roughly equal to the on resistance of the mosfet device chosen. for the si2301, this is about 60 m ? .
rev. 0 AD9875 C18C agc timing considerations when implementing the agc timing loop it is important to consider the delay and settling time of the rx path in response to a change in gain. figure 4 shows the delay the receive signal experiences through the blocks of the rx path. whether the gain is programmed through the serial port or over the tx[5:0] pins, the gain takes effect immediately with the delays shown below. when gain changes do not involve the cpga, the new gain will be evident in samples after seven adc clock cycles. when the gain change does involve the cpga, it takes an additional 45 ns to 70 ns due to the propagation delays of the buffer, lpf and pga. table iii, in the register programming section, details the pga programming map. gain register 5ns decode logic digital hpf adc sha lpf 1 clk cycle 5 clk cycle 1/2 clk cycle 10ns 25ns or 50ns 10ns buffer pga figure 4. agc timing transmit port timing the AD9875 transmit port consists of a 6-bit data bus tx[5:0], a clock and a tx sync signal. two consecutive nibbles of the tx data are multiplexed together to form a 10-bit data word. the clock appearing on the clk-a pin is a buffered version of the internal tx data sampling clock. data from the tx port is read on the rising edge of this sampling clock. the tx sync signal is used to indicate to which word a nibble belongs. the first nibble of every word is read while tx sync is low, the second nibble of that same word is read on the following tx sync high level. the timing is illustrated in the figure 5. tx2 lsb tx3 msb tx1 lsb tx2 msb tx0 lsb tx1 msb t su t hd clk-a tx sync tx [5:0] figure 5. transmit timing diagram AD9875 the tx port is highly configurable and offers the following options: negative edge sampling can be chosen by two different methods; either by setting the tx port negative edge sampling bit (register 3, bit 7) or the invert clk-a bit (register 8, bit 6). the main differ- ence between the two methods is that setting register 3, bit 7 inverts the internal sampling clock and will affect only the transmit path, even if clk? is used to clock the rx data. inverting clk-a would affect both the rx and tx paths if they both use clk-a. the first nibble of each word can be read in as the least signifi cant nibble by setting the tx ls nibble first bit (register 7, bit 2). for the AD9875, the most significant nibble defaults to six bits and the least significant nibble defaults to form four bits. this can be changed so that the least significant nibble and most significant nibble have five bits each. this is done by setting the tx port width five bits bit (register 7, bit 1). in all cases, the nibbles are justified toward bit 5. also, the tx path can be used in a reduced resolution mode by setting the tx port multiplexer bypass bit (register 7, bit 0). in this mode the tx data word becomes six bits and is read in a single cycle. the clocking modes are the same as described above, but the level of tx sync is irrelevant. if tx sync is low for more than one clock cycle, the last trans- mit data will read continuously until tx sync is brought high for the second nibble of a new transmit word. this feature can be used to ?lush?the interpolator filters with zeros. pga gain adjust timing in addition to the serial port, the tx[5:1] pins can be used to write to the rx path gain adjust bits (register 6, bits 4:0). this provides a faster way to update the pga gain. a high level on the gain pin with tx sync low programs the pga setting on the rising edge of clk-a. a low level on the gain pin enables data to be fed to the interpolator and dac. the gain pin must be held high, the tx sync must be held low, and the gain data must be stable for three clock cycles to successfully update the pga gain value. it should be noted that tx sync must be held low and tx gain must be held high to update the gain register. if tx gain and tx sync are both high, no data is written to the gain register of the tx data path. tx [5:0] gain gain t su clk-a tx sync t hd figure 6. gain programming receive port timing the AD9875 receives port consists of a six bit data bus rx[5:0], a clock and an rx sync signal. two consecutive nibbles of the rx data are multiplexed together to form a 10-bit data word. the rx data is valid on the rising edge of clk-a when the adc clock source pll-b/2 bit (register 3, bit 6) is set to 0. the rx sync signal is used to indicate to which word a nibble belongs. the first nibble of every word is transmitted while rx sync is low, the second nibble of that same word is transmit- ted on the following rx sync high level. when rx sync is low, the sampled nibble is read as the most significant nibble. when the rx sync is high, the sampled nibble is read as the least significant nibble. the timing is illustrated in figure 7. t vt rx2 lsb rx3 msb rx1 lsb rx2 msb rx0 lsb rx1 msb rx [5:0] t ht clk-a (-b) rx sync figure 7. receive timing diagram the rx port is highly configurable and offers the following options: negative edge sampling can be chosen by setting the invert clk-a bit (register 8, bit 6) or the invert clk-b bit (register 8, bit 7), depending on the clock selected as the adc sampling source. inverting clk-a would affect the tx sampling edge as well as the rx sampling edge. the first nibble of each word can be read in as the least signifi- cant nibble by setting the rx ls nibble first bit (register 8, bit 2).
rev. 0 AD9875 C19C bits i4:i0 ?a4:a0 these bits determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remain- ing register addresses are generated by the AD9875. serial interface port pin description sclk?erial clock the serial clock pin is used to synchronize data transfers to and from the AD9875 and to run the internal state machines. sclk maximum frequency is 25 mhz. all data transmitted to the AD9875 is sampled on the rising edge of sclk. all data read from the AD9875 is validated on the rising edge of sclk and is updated on the falling edge. senable ?erial interface enable the senable pin is active low. it enables the serial communi- cation to the device. senable select should stay low during the entire communication cycle. all input on the serial port is ignored when senable is inactive. sdata?erial data i/o the signal on this line is sampled on the first eight rising edges of sclk after senable goes active. data is then read from or written to the AD9875 depending on what was read. figures 8 and 9 show the timing relationships between the three spi signals. senable sclk sdata t dh t ds t ds t pwh t sclk t pwl instruction bit 7 instruction bit 6 figure 8. timing diagram register write to AD9875/ad9876 senable sclk sdata data bit n data bit n 1 t dv 1
8 +

8*)&48*)( msb/lsb transfers the AD9875 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. the bit order is controlled by the spi lsb first bit (register 0, bit 6). the default is value is 0, msb first. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. the AD9875 will automatically decrement the address for each successive byte required for the multibyte communication cycle. when the spi lsb first bit (register 0, bit 6) is set high, the serial port interprets both instruction and data bytes lsb first. multibyte data transfers in lsb format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. the AD9875 will automatically increment the address for each successive byte required for the multibyte communication cycle. for the AD9875, the most significant nibble defaults to six bits and the least significant nibble defaults to four bits. this can be changed so that the least significant nibble and most significant nibble have five bits each. this is done by setting the rx port width five bits bit (register 8, bit 1). in all cases, the nibbles are justified toward bit 5. also, the rx path can be used in a reduced resolution mode by setting the rx port multiplexer bypass bit (register 8, bit 0). in this mode the rx data word becomes six bits and is read in a single cycle. the clocking modes are the same as described above, but the level of rx sync will stay low. the rx[5:0] pins can be put into a high impedance state by setting the three-state rx port bit (register 8, bit 3). serial interface for register control the serial port is a three wire serial communications port c onsisting of a clock (sclk), chip select ( senable ), and a bidirectional data (sdata) signal. the interface allows read/write access to all registers that configure the AD9875 internal parameters. single or multiple byte transfers are supported as well as msb first or lsb first transfer formats. general operation of the serial interface serial communication over the serial interface can be from 1 to 5 bytes in length. the first byte is always the instruction byte. the instruction byte establishes whether the communication is going to be a read or write access, the number of data bytes to be transferred and the address of the first register to be accessed. the instruction byte transfer is complete immediately upon the eighth rising edge of sclk after senable is asserted. like- wise, the data registers change immediately upon writing to the eighth bit of each data byte. instruction byte the instruction byte contains the following information as shown below: table ii. instruction byte information b s mb s l 7 i6 i5 i4 i3 i2 i1 i0 i w / r1 n0 n4 a3 a2 a1 a0 a bit i7 ?r/w this bit determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation; logic zero indicates a write operation. bits i6:i5 ?n1:n0 these two bits determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the table below: table iii. decode bits n1:n0 description 0:0 transfer 1 byte 0:1 transfer 2 bytes 1:0 transfer 3 bytes 1:1 transfer 4 bytes
rev. 0 AD9875 C20C figures 10a and 10b show how the serial port words are built for each of these modes. senable sclk sdata r/w i6 (n) i5 (n) i3 i4 i2 i1 i0 d7 n d6 n d2 0 d1 0 d0 0 instruction cycle data transfer cycle figure 10a. serial register interface timing msb-first senable sclk sdata i0 i6 (n) i5 (n) i3 i4 i2 i1 r/w d7 n d6 n d2 0 d1 0 d0 0 instruction cycle data transfer cycle figure 10b. serial register interface timing lsb-first notes on serial port operation the serial port is disabled and all registers are set to their default values during a hardware reset. during a software reset, all registers except register 0 are set to their default values. register 0 will remain at the last value sent, with the exception that the software reset bit will be set to 0. the serial port is operated by an internal state machine and is dependent on the number of sclk cycles since the last time senable went active. on every eighth rising edge of sclk, a byte is transferred over the spi. during a multibyte write cycle, this means the registers of the AD9875 are not simultaneously updated, but occur sequentially. for this reason, it is recom- mended that single byte transfers be used when changing the spi configuration or performing a software reset. table iv. register layout address default (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) comments 0 spi software 0 00 read/write lsb first reset 1 power- power- power- power- power- power- power- power- 0 00 read/write down down down down down down down down pwr dn regulator pll-b pll-a dac interpolator rx adc and rx lpf and pin low reference fpga cpga 2 power- power- power- power- power- power- power- power- 0 9f read/write down down down down down down down down pwr dn regulator pll-b pll-a dac interpolator rx adc and rx lpf and pin high reference fpga cpga 3 tx port adc clock pll-b pll-b pll-a 0 02 read/write negative source ( m) multiplier ( ) divider ( m) multiplier edge pll-b/2 < 5:4> < 3:3> < 1:0> sampling 4 tx port rx lpf rx path rx digital fast adc wi deband e nable rx lpf 0 01 read/write tuning tuning dc offset hpf sampling rx lpf 1-pole bypass update in progress correction bypass rx lpf disable (read only) 5 rx lpf fc adjust <4:0> 0 80 read/write 6 pga rx path gain adjust <4:0> 0 00 read/write gain set by register 7 interpolation filter select power-down tx port tx port tx port 0 00 read/write <3:0> interpolator ls nibble width multiplexer at first 5-bits bypass tx quiet pin low 8 invert invert invert invert three-state rx port rx port rx port 0 00 read/ write clk b clk b clk b clk b rx port ls nibble width multiplexer first 5-bits bypass f die revision number <3:0> read only
rev. 0 AD9875 C21C register programming definitions register 0?eset/spi configuration bit 5: software reset setting this bit high resets the chip. the plls will relock to the input clock and all registers (except register 0 0, bit 6) revert to their default values. upon completion of the reset, bit 5 is reset to 0. the content of the interpolator stages are not cleared by software or hardware resets. it is recommended to ?lush?the transmit path with zeros before transmitting data. bit 6: lsb/msb first setting this bit high causes the serial port to send and receive data least significant bit (lsb) first. the default low state con- figures the serial port to send and receive data most significant bit (msb) first. registers 1 and 2?ower-down the combination of the pwr dn pin and registers 1 and 2 allow for the configuration of two separate pin selectable power settings. the pwr dn pin selects between two sets of individu- ally programmed operation modes. when the pwr dn pin is low, the functional blocks corre- sponding to the bits set in register 1 will be powered down. when the pwr dn pin is high, the functional blocks corre- sponding to the bits set in register 2 will be powered down bit 0: power-down receive filter and cpga setting this bit high powers down and bypasses the rx lpf and coarse programmable gain amplifier. bit 1: power-down adc and fpga setting this bit high powers down the adc and fine program- mable gain amplifier (fpga). bit 2: power-down rx reference setting this bit high powers down the adc reference. this bit should be set if an external reference is applied. bit 3: power-down interpolators setting this bit high powers down the transmit digital interpola- tors. it does not clear the content of the data path. bit 4: power-down dac setting this bit high powers down the transmit dac. bit 5, bit 6: power-down pll-a, pll-b setting these bits high powers down the on-chip phase lock loops which generated clk-a and clk-b respectively. when powered down these clocks are high impedance. bit 7: power-down regulator setting this bit high powers down the on-chip voltage control regulator. register 3?lock source configuration the AD9875 integrates two independently programmable plls referred to as pll-a and pll-b. the output of the plls are used to generate all the chips internal and external clock signals from the f clkin signal. all tx path clock signals are derived from pll-a. if f clkin is programmed as the adc sampling clock source, the rx port clocks are also derived from pll-a. otherwise, the adc sampling clock is pll-b/2 and the rx path clocks are derived from pll-b. bit 1,0: pll-a multiplier bits 1 and 0 determine the multiplication factor (l) for pll-a and the dac sampling clock frequency, f dac . f dac = l f clkin bit 1,0 0,0: l = 1 0,1: l = 2 1,0: l = 4 1,1: l = 8 bit 5 to 2: pll-b multiplier/divider bits 5 to 2 determine the multiplication factor (m) and division factor (n) for pll-b and the clk-b frequency. for multiplexed 10-/12-bit data, f clk-b = f clkin m/n. for nonmultiplexed 6-bit data, f clk-b = (f clkin /2) m/n. all nine combinations of m and n values are valid, yielding seven unique m/n ratios. bit 5,4 bit 3,2 0,0: m = 3 0,0: n = 2 0,1: m = 4 0,1: n = 4 1,0: m = 6 1,0: n = 1 bit 6: adc clock source pll-b/2 setting bit 6 high selects pll-b/2 as the adc sampling clock source. in this mode, the rx data and clk-b will run at a rate of f clk-b . rxsync will run at f clk-b /2. setting bit 6 low selects the f clkin signal as the adc sampling clock source. this mode of operation yields the best adc performance if an external crystal is used or a low jitter clock source drives the oscin pin. bit 7: tx port negative edge sampling setting bit 7 high will cause the tx port to sample the txdata and txsync on the falling edge of clk-a. by default, the tx port sampling occurs on the rising edge of clk-a. the timing is shown in figure 5. register 4?eceive filter selection the AD9875 receive path has a continuous time 4-pole lpf and a 1-pole digital hpf. the 4-pole lpf has two selectable cutoff frequencies. additionally, the filter can be tuned around those two cutoff frequencies. these filters can also be bypassed to different degrees as described below. the continuous time 4-pole low-pass filter is automatically calibrated to one of two selectable cutoff frequencies. the cutoff frequency f cutoff is described as a function of the adc sampling frequency f adc and can be influenced ( 30%) by the rx-filter tuning target word in register 5. f cutoff low = f adc 64/( target + 64) f cutoff high = f adc 158/( target + 64) bit 0: rx lpf bypass setting this bit high bypasses the 4-pole lpf. the filter is automatically pow ered down when this bit is set. bit 1: enable 1-pole rx lpf the AD9875 can be configured with an additional 1-pole ~16 mhz input filter for applications that require steeper filter roll-off or want to use the 1-pole filter instead of the 4-pole receive low-pass filter. the 1-pole filter is untrimmed and subject to cutoff frequency variations of 20%.
rev. 0 AD9875 C22C table v. pga programming map rx path rx path cpga spga gain [4:0] gain gain gain 0 00 ? ? 0 0 01 ? ? 2 0 02 ? ? 4 0 03 0 6 6 0 04 2 6 8 0 05 4 6 10 0 06606 0 07808 0 08 10 0 10 0 09 12 6 6 0 0a 14 6 8 0 0b 16 6 10 0 0c 18 12 6 0 0d 20 12 8 0 0e 22 12 10 0 0f 24 18 6 0 10 26 18 8 0 11 28 18 10 0 12 * 30/30 18/24 12/6 0 13 * 30/32 18/24 12/8 0 14 * 30/34 18/24 12/10 0 15 * 30/36 18/24 12/12 * when the wideband rx filter bit is set high, the rx path gain is limited to 30 db. the first of the two values in the chart refers to this mode. the second number refers to the mode when the lower rx lpf cutoff frequency is chosen, or the rx lpf filter is bypassed. register 7?ransmit path settings the AD9875 transmit path has a programmable interpolation filter that precedes the transmit dac. the interpolation filter can be programmed to operate in seven different modes. also, the digital interface can be programmed to operate in several different modes. these modes are described below. bit 0: transmit port demultiplexer bypass setting bit 0 high bypasses the input data demultiplexer. in this mode, consecutive nibbles on the txdata(5:0) pins are treated as individual words to be sent through the tx path. this creates a six bit data path. the state of txsync is ignored in this mode. bit 1: transmit port width if bit 1 is set high, the tx port will operate such that the most significant nibble and the least significant nibble are each five bits wide. the default mode is six bits for the most significant nibble and four bit for the least significant nibble. the data is always aligned to the msb pin tx[5]. enabling this pin on the AD9875 allows for a five pin versus the default six pin interface. bit 2: transmit port least significant nibble first setting bit 2 high reconfigures the AD9875 for a transmit mode that expects least significant nibble before the most significant nibble. bit 2: wideband rx lpf this bit selects the nominal cutoff frequency of the 4-pole lpf. setting this bit high selects a nominal cutoff frequency of 28.8 mhz. when the wideband filter is selected, the rx path gain is limited to 30 db. bit 3: fast adc sampling setting this bit increases the quiescent current in the svga block. this may provide some performance improvement when the adc sampling frequency is greater than 50 msps (in 6-bit mode). bit 4: rx digital hpf bypass setting this bit high bypasses the 1-pole digital hpf that follows the adc. the digital filter must be bypassed for adc sampling above 50 msps. bit 5: rx path dc offset correction writing a one to this bit triggers an immediate receive path offset correction and reads back zero after the completion of the offset correction. bit 6: rx lpf tuning update in progress this bit indicates when receive filter calibration is in progress. the duration of a receive filter calibration is about 500 ms. writing to this bit has no effect. bit 7: rx lpf tuning update disable setting this bit high disables the automatic background receive filter calibration. the AD9875 automatically calibrates the receive filter on reset and every few (~2) seconds thereafter to compensate for process and temperature variation, power supply and long term drift. programming a one to this bit disables this function. programming a zero triggers an immediate first cali- bration and enables the periodic update. register 5?eceive filter tuning target this register sets the filter tuning target as a function of f oscin . see register 4 description. register 6?x path gain adjust the AD9875 uses a combination of a continuous time pga (cpga) and a switched capacitor pga (spga) for a gain range of ? to 36 db with a resolution of 2 db. the rx path gain can be programmed over the serial interface by writing to the rx path gain adjust register or directly using the gain and msb aligned tx[5:1] bits. the register default value is 0 00 for lowest gain setting (? db). the register always reads back the actual gain setting irrespective of which of the two programming modes were used. table v describes the gains and how they are achieved as a function of the rx path adjust bits. bit 5: pga gain set through register setting this bit high will result in the rx path gain being set by writing to the pga gain control register. default is zero which selects writing the gain through the tx[5:1] pins in conjunction with the gain pin.
rev. 0 AD9875 C23C bit 3: power-down interpolator at txquiet pin low setting bit 3 high enables the txquiet pin to shut off the dac output. if the bit is set to one, then pulling the txquiet pin low will power down the interpolator filters. in most appli- cations the interpolator filter will need to be flushed with zeros before or after being powered down. bit 4 to bit 7: interpolation filter select bits 4 to 7 define the interpolation filter characteristic and inter- polation rate. bits 7:4; 0 2; interpolation bypass. 0 0; see tpc 1. 4 interp, lpf. 0 1; see tpc 2. 2 interp, lpf. 0 4; see tpc 3. 4 interp, bpf, adj image. 0 5; see tpc 4. 2 interp, bpf, adj image. 0 8; see tpc 5. 4 interp, bpf, lower image. 0 c; see tpc 6. 4 interp, bpf, upper image. the interpolation factor has a direct influence on the clk-a output frequency. when the transmit input data multiplexer is enabled (10-bit mode): f clk-a = 2 f dac /k where k is the interpolation factor. when the transmit input data multiplexer is disabled (5-/6-bit mode): f clk-a = f dac /k where k is the interpolation factor. register 8?eceiver and clock output settings bit 0: rx port multiplexer bypass setting this bit high bypasses the rx port output multiplexer. this will output only the 6 msbs of the adc word. this mode enables adc sampling rates above 55 msps. bit 1: rx port width five bits if the bit is set high, the rx port data will be output in two nibbles of five bits each (on pins rx[5:1]). when this bit is low (default), the most significant nibble will contain six bits and the least significant nibble will have four bits. the default mode makes the AD9875 pin compatible with the ad9876. bit 2: rx port ls nibble first reconfigures the AD9875 for a receive mode that expects less significant bits before the most significant bits. bit 3: three-state rx port this bit sets the receive output rx[5:0] into a high impedance three-state mode. it allows for sharing the bus with other devices. bit 4, bit 5: disable clk-a, disable clk-b setting bit 4 or bit 5 stops clk-a or clk-b respectively, from toggling. the output is held to a logic 0 level. bit 4, bit 5: disable clk-a, disable clk-b setting bit 4 or bit 5 fixes clk-a or clk-b to a low output level, respectively. bit 6: clk-a output invert setting bit 6 high inverts the clk-a output signal. bit 7: clk-b output invert setting this bit high inverts the clk-b output signal. this effec- tively changes the timing of the rx[5:0] and rxsync signals from rising edge triggered to falling edge triggered with respect to the clk-b signal. register f, die revision this register stores the die revision of the chip. it is a read- only register. pcb design considerations although the AD9875 is a mixed-signal device, the part should be treated as an analog component. the digital circuitry on-chip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. following the power, grounding and layout recommen- dations in this section will help you get the best performance from the mxfe. component placement if the three following guidelines of component placement are followed, chances for getting the best performance from the mxfe are greatly increased. first, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. in order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this will keep the highest frequency return current paths short, and prevent them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device which will further reduce the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the mxfe. the analog circuits should be placed furthest from the power supply. the AD9875 has several pins which are used to decouple sensi- tive internal nodes. these pins are refio, refb, and reft. the decoupling capacitors connected to these points should have low esr and esl. these capacitors should be placed as close to the mxfe as possible and be connected directly to the analog ground plane. the resistor connected to the fsadj pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling the AD9875 evaluation board demonstrates a good power supply distribution and decoupling strategy. the board has four layers; two signal layers, one ground plane and one power plane. the power plane is split into a 3vdd section used for the 3 v digital logic circuits, a dvdd section used to supply the digital supply pins of the AD9875, an avdd section used to supply the analog supply pins of the AD9875, and a vanlg section that supplies the higher voltage analog components on the board. the 3vdd section will typically have the highest frequency currents on the power plane and should be kept the furthest from the mxfe and analog sections of the board. the dvdd portion of the plane brings the current used to power the digital portion of the mxfe to the device. this should be treated simi larly to the 3vdd power plane and be kept from going underneath the mxfe or analog components. the mxfe should largely sit on the avdd portion of the power plane.
C24C c02488C1C7/01(0) printed in u.s.a. rev. 0 the avdd and dvdd power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the dvdd portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source and dvdd, and between the source and avdd. both dvdd and avdd should have a low esr, bulk decoupling capacitor on the mxfe side of the ferrite as well as a low esr, esl decoupling capacitors on each supply pin (i.e., the AD9875 requires five power supply decoupling caps, one each on pins 5, 38, 47, 14, and 35). the decoupling caps should be placed as close to the mxfe supply pins as possible. an example of the proper decoupling is shown in the AD9875 evaluation board schematic. ground planes in general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. all ground connections should be made as short as possible. this will result in the lowest impedance return paths, and the quietest ground connections. if the components cannot be placed in a manner that will keep the high-frequency ground currents from traversing under the mxfe and analog components, it may be necessary to put current steering channels into the ground plane to route the high-frequency currents around these sensitive areas. these current steering channels should be made only when and where necessary. signal routing the digital rx and tx signal paths should be kept as short as possible. also, the impedance of these traces should have a controlled characteristic impedance of about 50 ? . this will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, then series-termination resistors (33 ? to 47 ? ) should be placed close to all signal sources. it is a good idea to series-terminate all clock signals at their source, regardless of trace length. the receive rx signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the rx signals form a differ ential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals will appear as common-mode and will be largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe will further reduce the possibility of noise corrupting these signals. outline dimensions AD9875 dimensions shown in inches and (mm). 48-lead lqfp (st-48) 0.039 (1.00) ref top view (pins down) 1 12 13 25 24 36 37 48 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) 0.019 (0.50) bsc 0.276 (7.00) bsc sq 0.354 (9.00) bsc sq seating plane 0.063 (1.60) max 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) view a 7 3.5 0 0.008 (0.20) 0.004 (0.09) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) 0.003 (0.08) max view a rotated 90 ccw controlling dimensions are in millimeters.

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