preliminary HY5V52CF 4 banks x 2m x 32bit synchronous dram this document is a general product descrip tion and is subject to change without notice. hynix semiconductor inc. does not assum e any responsibility for use of circuits des cribed. no patent licenses are implied. rev. 0.2/jun 02 description the hynix HY5V52CF is a 268,435,456bit cmos synchronous dram, ideally suited for the memory applications which require wide data i/o and high bandwidth. hy 5v52cf is organized as 4banks of 2,097,152x32. HY5V52CF is offering fully synchronous o peration referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high band- width. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read lat ency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a bu rst of read or write cycles in progre ss can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? jedec standard 3.3v power supply ? all device pins are compatible with lvttl interface ? 90ball fbga with 0.8mm of pin pitch ? all inputs and outputs refer enced to positive edge of system clock ? data mask function by dqm0,1,2 and 3 ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ? burst read single write operation ordering information part no. clock frequency organization interface package hy5v52(l)f-8 125mhz 4banks x 2mbits x32 lvttl 90ball fbga hy5v52(l)f-p 100mhz 4banks x 2mbits x32 lvttl 90ball fbga hy5v52(l)f-s 100mhz 4banks x 2mbits x32 lvttl 90ball fbga
rev. 0.2/jun 02 3 HY5V52CF ball configuration ball description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and wh en deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for in ternal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection top view a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /cas /w e dq m0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456 top view a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /cas /w e dq m0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456 a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /cas /w e dq m0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /cas /w e dq m0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /cas /w e dq m0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456
rev. 0.2/jun 02 4 HY5V52CF absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta=0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration with no input clamp diodes 3.v il (min) is acceptable -2.0v ac pulse width with 3 ns of duration with no input clamp diodes ac operating condition (ta=0 to 70 c , 3.0v v dd 3.6v, v ss =0v - note1) note : 1.output load to measure access times is equiva lent to two ttl gates and one capacitor (30pf) for details, refer to ac/dc output load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.135 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il v ssq - 0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for acce ss time measurement cl 30 pf 1
rev. 0.2/jun 02 5 HY5V52CF capacitance (ta=25 c , f=1mhz, vdd=3.3v) output load circuit dc characteristics i (dc operating conditions unless otherwise noted) note : 1.v in = 0 to 3.6v, all other pins are not under test = 0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 tbd tbd pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , dqm0~3 ci 2 tbd tbd pf data input / output capacitance dq0 ~ dq31 c i/o tbd tbd pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma vtt=1.4v rt=500 ? 30pf output dc output load circuit ac output load circuit vtt=1.4v rt=50 ? 30pf output z0 = 50 ?
rev. 0.2/jun 02 6 HY5V52CF dc characteristics ii (dc operating conditions unless otherwise noted) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specifie d values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.HY5V52CF-8/p/s 4.hy5v52cl:f-8/p/s parameter symbol test condition speed unit note -8 -p s operating current idd1 burst length=1, one bank active t rc t rc (min), i ol =0ma tbd tbd tbd ma 1 precharge standby current in power down mode idd2p cke v il (max), t ck = 10ns tbd ma idd2ps cke v il (max), t ck = tbd precharge standby current in non power down mode idd2n cke v ih (min), cs v ih (min), t ck = 10ns input signals are changed one time during 2clks. all other pins vdd-0.2v or 0.2v tbd ma idd2ns cke v ih (min), t ck = input signals are stable. tbd active standby current in power down mode idd3p cke v il (max), t ck = 10ns tbd ma idd3ps cke v il (max), t ck = tbd active standby current in non power down mode idd3n cke v ih (min), cs v ih (min), t ck = 10ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v tbd ma idd3ns cke v ih (min), t ck = input signals are stable. tbd burst mode operating current idd4 t t ck t ck (min), i ol =0ma all banks active cl=3 tbd tbd tbd ma 1 cl=2 - tbd tbd auto refresh current idd5 t rc t rc (min), all banks active tbd tbd tbd ma 2 self refresh current idd6 cke 0.2v tbd ma 3 tbd 4
rev. 0.2/jun 02 7 HY5V52CF ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be me asured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3. data-out hold time to be measure d under 30pf load condition, wi thout vt termination parameter symbol -8 -p -s unit note min max min max min max system clock cycle time cas latency = 3 tck3 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 -10 10 12 ns clock high pulse width tchw 3 - 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 6 - 6 - 6 ns 2 cas latency = 2 tac2 - 6 - 6 - 6 ns data-out hold time toh 2 - 2 - 2 - ns 3 data-input setup time tds 2 - 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - 1 - ns 1 address setup time tas 2 - 2 - 2 - ns 1 address hold time tah 1 - 1 - 1 - ns 1 cke setup time tcks 2 - 2 - 2 - ns 1 cke hold time tckh 1 - 1 - 1 - ns 1 command setup time tcs 2 - 2 - 2 - ns 1 command hold time tch 1 - 1 - 1 - ns 1 clk to data output in low z-time tolz 1 - 1 - 1 - ns clk to data output in high z-time cas latency = 3 tohz3 - 6 - 6 - 6 ns cas latency = 2 tohz2 - 6 - 6 - 6 ns
rev. 0.2/jun 02 8 HY5V52CF ac characteristics ii (ac operating conditions unless otherwise noted) parameter symbol -8 -p -s unit not e min max min max min max ras cycle time operation trc 64 - 70 - 70 - ns auto refresh trrc 64 - 70 - 70 - ns ras to cas delay trcd 20 - 20 - 20 - ns ras active time tras 48 100 k 50 100 k 50 100 k ns ras precharge time trp 20 - 20 - 20 - ns ras to ras bank active delay trrd 2 - 20 - 20 - clk cas to cas delay tccd 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - clk data-in to precharge command tdpl 1 - 1 - 1 - clk data-in to active command tdal 4 - 4 - 4 - clk dqm to data-out hi-z tdqz 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - 2 - clk power down exit time tpde 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 ms note : 1. a new command can be given trrc after self refresh exit
rev. 0.2/jun 02 9 HY5V52CF command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation 3. the burst read sigle write mode is entered by programming the write burst mode bit (a9) in the mode register to a logic 1. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read h x lhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x llllx a9 pin high (other pins op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
rev. 0.2/jun 02 10 HY5V52CF package information 90ball fbga with 0.8mm of pin pitch ( using ?multi chip package? technology) 1.30 1.30
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