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vitesse semiconductor corporation page 1 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 features general description the vsc7133 is a full-speed fibre channel and gigabit ethernet transceiver with industry-standard pinouts. it accepts 10-bit 8b/10b encoded transmit data, latches it on the rising edge of the ttl/pecl ref- clk and serializes it onto the tx pecl differential outputs at a baud rate which is ten times the refclk fre- quency. serial data input on the rx pecl differential inputs is resampled by the clock recovery unit, deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty clocks. the vsc7133 r eceiver detects comma characters for frame alignment. an analog/digital signal detection circuit indicates that a valid signal is present on the rx input. a cable equalizer compensates for inter symbol interfer- ence in order to increase maximum cable distances. the vsc7133 contains pll circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. the vsc7133 is similar to the vsc7123 but has either a ttl or a pecl reference clock. vsc7133 block diagram ? 802.3z gigabit ethernet compliant 1.25 gb/s transceiver ? ansi x3t11 fibre channel compliant 1.0625 gb/s transceiver ? 0.98 to 1.36 gb/s full duplex operation ? 10 bit ttl interface for transmit and receive data ? ttl or pecl reference clock ? automatic lock-to-reference ? rx cable equalization and signal detect ? jtag access port for testability ? 64-pin, 10mm pqfp packaging ? single +3.3v supply, 650 mw rx+ rx- q d serial to parallel clock recovery ? 10 comma r(0:9) comdet encdet t(0:9) x10 clock multiply parallel to serial tx+ tx- ewrap ? 20 rclk 10 10 2:1 rclkn signal detect q d qd detect sigdet d q d q not shown: jtag boundary scan refclkp refclkn
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 2 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 functional description clock synthesizer the vsc7133 clock synthesizer multiplies the reference frequency provided on the refclk pin by 10 to achieve a baud rate clock between 0.98 and 1.36 ghz. the on-chip pll uses a single external 0.1uf capacitor to control the loop filter. the refclk is either ttl or lv pecl. if ttl, connect the ttl input to reflkp and leave refclkn open, it is biased for a ttl switch level. if pecl, connect both refclkp and refclkn. serializer the vsc7133 accepts ttl input data as a parallel 10 bit character on the t(0:9) bus, which is latched into the input register on the rising edge of refclk. this data is serialized and transmitted on the tx pecl differ- ential outputs at a baud rate that is ten times the frequency of the refclk, with bit t0 transmitted first. user data should be encoded using 8b/10b block code or equivalent. transmission character interface an encoded byte is 10 bits and is referred to as a transmission character. the 10 bit interface on the vsc7133 corresponds to a transmission character. this mapping is illustrated in figure 1. figure 1: transmission order and mapping of an 8b/10b character clock recovery the vsc7133 accepts differential high speed serial inputs on the rx+/rx- pins, extracts the clock and retimes the data. equalizers are included in the receiver to open the data eye and compensate for intersymbol interference (isi) which may be present in the incoming data. the serial bit stream should be encoded so as to provide dc balance and limited run length by an 8b/10b encoding scheme. the clock recovery unit (cru) is completely monolithic and requires no external components. for proper operation, the baud rate of the data stream to be recovered should be within +200 ppm of ten times the refclk frequency. for example, gigabit ethernet systems would use 125 mhz oscillators with a +/-100ppm accuracy resulting in +/-200 ppm between vsc7133 pairs. first data bit transmitted last data bit transmitted parallel data bits 8b/10b bit position t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 j hgf i edcba comma character xxx1111100
vitesse semiconductor corporation page 3 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 deserializer the recovered serial bit stream is converted into a 10-bit parallel output character. the vsc7133 provides complementary ttl recovered clocks, rclk and rclkn, which are one twentieth of the serial baud rate. the clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data. the serial data is retimed, deserialized and output on r(0:9). the parallel data will be captured by the adjoin- ing protocol logic on the rising edges of rclk and rclkn. if serial input data is not present, or does not meet the required baud rate, the vsc7133 will continue to produce a recovered clock so that downstream logic may continue to function. the rclk/rclkn output fre- quency under these circumstances will differ from its expected frequency by no more than +1%. word alignment the vsc7133 provides 7-bit comma character recognition and data word alignment. word synchronization is enabled by asserting encdet high. when synchronization is enabled, the receiver examines the recovered serial data for the presence of the comma character. this pattern is 0011111xxx, where the leading zero corresponds to the first bit received. the comma sequence is not contained in any normal 8b/10b coded data character or pair of adjacent characters. it occurs only within special characters, known as k28.1, k28.5 and k28.7, which are defined for synchronization purposes. improper alignment of the comma character is defined as any of the following conditions: 1) the comma is not aligned within the 10-bit transmission character such that r(0..6) = 0011111. 2) the comma straddles the boundary between two 10-bit transmission characters. 3) the comma is properly aligned but occurs in the received character presented during the rising edge of rclk rather than rclkn. when encdet is high and an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to r(0:9). this results in proper character and word alignment. when the parallel data alignment changes in response to a improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. also, the first comma pattern may be lost or corrupted. subsequent data will be output correctly and properly aligned. when encdet is low, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. on encountering a comma character, comdet is driven high. the comdet pulse is presented simul- taneously with the comma character and has a duration equal to the data, or half of an rclk period. the com- det signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of rclkn. functional waveforms for synchronization are given in figure 2 and figure 3. figure 2 shows the case when a comma character is detected and no phase adjustment is necessary. it illustrates the position of the comdet pulse in relation to the comma character on r(0:9). figure 3 shows the case where the k28.5 is detected, but it is misaligned so a change in the output data alignment is required. note that up to three characters prior to the comma character may be corrupted by the realignment process.
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 4 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 signal detection: the receiver has an output, sigdet, indicating, when high, that the rx input contains a valid fibre channel or gigabit ethernet signal. a combination of one analog and three digital checks are used to determine if the incoming signal contains valid data. sigdet is updated every four rclks. if during the current period, all the four criteria are met, sigdet will be high during the next 4 rclk period. if during the current period, any of the four criteria is not met, sigdet will be low during the next 4 rclk period. 1.) analog transition detection is performed on the input to verify that the signal swings are of adequate amplitude. the rx+/- input buffer contains a differential voltage comparator which will go high if the differen- tial peak-to-peak amplitude is greater than 400mv or low if under 200mv. if the amplitude is between 200 and 400mv, the output is indeterminate. 2.) data on r(0:9) is monitored for all zeros (0000000000). if this pattern is encountered during the current rclk interval, the sigdet output will go low during the next four rclk interval. 3.) data on r(0:9) is monitored for all ones (1111111111). if this pattern is encountered during the current rclk interval, the sigdet output will go low during the next four rclk interval. 4.) data on r(0:9) is monitored for k28.5- (0011111010). unlike previous patterns, the interval during which a k28.5- must occur is 64k+24 10-bit characters in length. valid fibre channel or gigabit ethernet data will contain a k28.5- character during any period of this length. if a k28.5- is not detected during the monitor- ing period , sigdet will go low during the next period. the behavior of sigdet is affected by ewrap and encdet as shown below. table 1: signal detect behaviour comdet, rclk, rclkn and r(0:9) are unaltered by sigdet. jtag access port a jtag access port is provided to assist in board-level testing. through this port most pins can be accessed or controlled and all ttl outputs can be tri-stated. a full description of the jtag functions on this device is available in vsc7123/vsc7133 jtag access port functionality. ewrap encdet transition detect all zeros/ all ones k28.5 presence mode 0 0 enabled enabled enabled normal 0 1 enabled enabled disabled comdet disable 1 0 enabled disabled disabled loopback 1 1 enabled disabled disabled loopback
vitesse semiconductor corporation page 5 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 figure 2: detection of a properly aligned comma character figure 3: detection and resynchronization of an improperly aligned comma tchar: 10 bit transmission character comdet r(0:9) rclk rclkn k28.5 tchar tchar tchar comdet receiving two consecutive k28.5+tchar transmission words k28.5 tchar tchar tchar k28.5 tchar potentially corrupted r(0:9) rclk rclkn clock stretching
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 6 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 ac characteristics figure 4: transmit timing waveforms table 2: transmit ac characteristics parameters description min max units conditions t 1 t(0:9) setup time to the rising edge of refclk 1.5 ns. measured between the valid data level of t(0:9) to the 1.4v point of refclk t 2 t(0:9) hold time after the rising edge of refclk 1.0 ns. t sdr ,t sdf tx+/tx- rise and fall time 300ps. 20% to 80%, 50 ohm load to v dd -2.0 t lat latency from rising edge of refclk to t0 appearing on tx+/tx- 8bc 8bc+ 4ns ns bc = bit clocks ns = nano second transmitter output jitter allocation t j total data output jitter 192ps. ieee 802.3z clause 38.68, t dj serial data output deterministic jitter (p-p) 80ps. ieee 802.3z clause 38.68, data valid t(0:9) t 1 t 2 refclk data valid data valid
vitesse semiconductor corporation page 7 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 figure 5: receive timing waveforms table 3: receive ac characteristics parameters description min. max. units conditions t 1 ttl outputs valid prior to rclk/rclkn rise 4.0 3.0 ns @ 1.0625gb/s @ 1.25gb/s t 2 ttl outputs valid after rclk or rclkn rise 3.0 2.0 ns @ 1.0625gb/s @ 1.25gb/s t 3 delay between rising edge of rclk to rising edge of rclkn 10 x t rx -500 10 x t rx +500 ps t rx is the bit period of the incoming data on rx. t 4 period of rclk and rclkn 1.98 x t refclk 2.02 x t refclk ps whether or not locked to serial data. t r , t f r(0:9), comdet, sigdet, rclk and rclkn rise and fall time 2.4ns between v il(max) and v ih(min) , into 10 pf. load. r lat latency from rx to r(0:9) 12 bc + 1 ns 13 bc + 9 ns bc ns bc = bit clock ns = nano second t lock * data acquisition lock time 1400bc 8b/10b idle pattern. bc= bit clocks * note: probability of recovery for data acquisition is 95% per section 5.3 of fc-ph rev. 4.3 rclk r(0:9) rclkn t 2 t 3 data valid data valid t 1 t 4 data valid
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 8 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 figure 6: refclk timing waveforms table 4: reference clock requirements parameter description min max units conditions fr frequency range 98 136 mhz range over which both transmit and receive reference clocks on any link may be centered fo frequency offset -200 200 ppm. maximum frequency offset between transmit and receive reference clocks on one link dc refclk duty cycle 35 65 % measured at 1.5v t r ,t f refclk rise and fall time 1.5ns. between v il(max) and v ih(min) refclkp v il(max) v ih(min) t l t h t r t f reflkn
vitesse semiconductor corporation page 9 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 figure 7: parametric measurement information serial input rise and fall time ttl input and output rise and fall time ttl a.c. output load receiver input eye diagram jitter tolerance mask serial output load tr tf 80% 20% tr tf vih(min) vil(min) 10 pf z0 = 50 or 75w 50 or 75w v dd C 2.0v bit time 24% minimum eye width% amplitude parametric test load circuit
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 10 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 absolute maximum ratings (1) power supply voltage, (v dd ) ............................................................................................................-0.5v to +4v dc input voltage (pecl inputs)............................................................................................ -0.5v to v dd +0.5v dc input voltage (ttl inputs) .................................................................................................. ....-0.5v to +5.5v dc output voltage (ttl outputs)........................................................................................ -0.5v to v dd + 0.5v output current (ttl outputs) ................................................................................................... .............. +/-50ma output current (pecl outputs).................................................................................................. ..............+/-50ma case temperature under bias .................................................................................................... .....-55 o to +125 o c storage temperature............................................................................................................ ......... -65 o c to +150 o c maximum input esd (human body model)........................................................................................... ... 2000 v maximum input esd (charge device model) ........................................................................................ ... 1000 v recommended operating conditions power supply voltage, (v dd ) ................................................................................................................+3.3v+ 5% operating temperature range ............................................................ 0 o c ambient to +95 o c case temperature notes: (1) caution: stresses listed under absolute maximum ratings may be applied to devices one at a time without causing per- manent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability.
vitesse semiconductor corporation page 11 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 dc characteristics (over recommended operating conditions). parameters description min typ max units conditions v oh output high voltage (ttl) 2.4 v i oh = -1.0 ma v ol output low voltage (ttl) 0.5 v i ol = +1.0 ma v ih input high voltage (ttl) 2.0 5.5 v 5v tolerant inputs v il input low voltage (ttl) 00.8 v i ih input high current (ttl) 50500 m a v in = 2.4v i il input low current (ttl) -500 m a v in =0.5v d v out75 1 tx output differential peak- to-peak voltage swing 1200 2200 mvp-p 75 w to v dd C 2.0 v (tx+) - (tx-) d v out50 1 tx output differential peak- to-peak voltage swing 1000 2200 mvp-p 50 w to v dd C 2.0 v (tx+) - (tx-) d v in 1 rx input differential peak- to-peak input sensitivity 300 2600 mvp-p internally biased to vdd/2 (rx+) - (rx-) v dd supply voltage 3.14 3.47 v 3.3v5% p d power dissipation 650 900 mw outputs open, v dd = v dd max i dd supply current (all supplies) 190 260 ma outputs open, v dd = v dd max i dda analog supply current 100ma v dda = v dda max 1 note: refer to application note, an-37, for differential measurement techniques.
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 12 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 figure 8: input structures input input high speed input (rx+/rx-) v ddd gnd ttl inputs (not refclk) input gnd v ddd 3k vddp gnd vddd tx+ tx- hi speed outputs (tx+/-) 3k 4k 4k vddt vsst output ttl outputs refclk refclk ttl input v dd gnd +3.3 v 12.6k 12.6k 9.3k 9.3k vssd
vitesse semiconductor corporation page 13 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 package pin descriptions figure 9: pin diagram table 5: pin identification pin # name description 2,3,4,6 7,8,9,11 12,13 t0,t1,t2,t3 t4,t5,t6,t7 t8,t9 inputs - ttl 10-bit transmit character. parallel data on this bus is clocked in on the rising edge of refclk. the data bit corresponding to t0 is transmitted first. t5 tdo v ddd v ddt rclkn rclk v sst t4 v ddd t7 t8 t9 v ssd rx- v ssd v ddd v ddd v ddp tx+ tck trstn r6 r5 comdet r4 v ddt r7 r8 t2 v ddd t3 v ssd r2 v ssd tdi v sst cap1 encdet v dda t6 cap0 v ssd v ssa ewrap refclkp refclkn v ddd v ssd sigdet r9 r3 r1 r0 v sst n/c v ddt v ddp tx- t1 t0 v ddd v ssd tms rx+ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 33 35 37 39 41 43 45 47 (top view)
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 14 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 22 23 refclkp refclkn input - differential pecl or single-ended ttl this rising edge of this clock latches t(0:9) into the input register. it also provides the reference clock, at one tenth the baud rate to the pll. if ttl, connect to refclkp but leave refclkn open. if pecl, connect both refclkp and refclkn. 62, 61 tx+, tx- outputs - differential pecl (ac coupling recommended) these pins output the serialized transmit data when ewrap is low. when ewrap is high, tx+ is high and tx- is low. 45,44,43,41 40,39,38,36 35,34 r0,r1,r2,r3 r4,r5,r6,r7 r8,r9 outputs - ttl 10-bit received character. parallel data on this bus is clocked out on the rising edges of rclk and rclkn. r0 is the first bit received on rx+/rx-. 19 ewrap input - ttl low for normal operation. when high, an internal loopback path from the transmitter to the receiver is enabled and the tx outputs are held high. 54, 52 rx+, rx- inputs - differential pecl (ac coupling recommended) the serial receive data inputs selected when ewrap is low. internally biased to vdd/2, with 3.3k w resistors from each input pin to vdd and gnd. 31, 30 rclk, rclkn output - complementary ttl recovered clocks derived from one twentieth of the rx+/- data stream. each rising transition of rclk or rclkn corresponds to a new word on r(0:9). 24 encdet input - ttl enables comdet and word resynchronization when high. when low, keeps current word alignment and disables comdet. 47 comdet output - ttl this output goes high for half of an rclk period to indicate that r(0:9) contains a comma character (0011111xxx). comdet will go high only during a cycle when rclkn is rising. comdet is enabled by encdet being high. 26 sigdet output - ttl signal detect. this output goes high when the rx input contains a valid fibre channel or gigabit ethernet signal. a low indicates an invalid signal. 16, 17 cap0, cap1 analog: differential capacitor for the cmus vco. 0.1 uf nominal. 49 tck input - ttl: jtag clock input. not normally connected. 48 tdi input - ttl: jtag data input. not normally connected. 55 tms input - ttl: jtag mode select input. normally tied to v ddd 56 trstn input - tll: jtag reset input. tie to v ssd for normal operation. 27 tdo outpu - ttl: jtag data output. normally tri-stated. 18 vdda analog power supply. table 5: pin identification pin # name description
vitesse semiconductor corporation page 15 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 15 vssa analog ground 5,10,20,28 50,57,59 vddd digital logic power supply 1,14,21,25 51,58,64 vssd digital logic ground 29, 37, 42 vddt ttl output power supply 32, 33, 46 vsst ttl output ground 60,63 vddp pecl i/o power supply 53 n/c no connection. table 5: pin identification pin # name description
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 16 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 package information: 64-pin pqfp 64 49 1 48 33 32 17 g f ih 16 10 o typ 10 0 typ a k a2 0.102 max. lead coplanarity 0.17 max. a 0.25 j 0 o - 8 o 0.25 max. e 0.30 rad. typ. 0.20 rad. typ. standoff item 10 mm tol erance a2.45 max a2 2.00 +0.10/-0.05 e0.22 0.05 f 13.20 0.25 g 10.00 0.10 h 13.20 0.25 i 10.00 0.10 j 0.88 +0.15/-0.10 k0.50 basic notes: drawing not to scale. all units in mm unless otherwise noted.
vitesse semiconductor corporation page 17 1/17/00 7 41 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation 10-bit transceiver for fibre channel and gigabit ethernet advance product information vsc7133 g52187-0 rev. 2.4 thermal considerations the vsc7133 is packaged in a 10mm, thermally enhanced pqfp with an internal heat spreader. these packages use industry-standard eiaj footprints, but have been enhanced to improve thermal dissipation. the construction of the packages are shown below. figure 10: package cross section table 6: thermal resistance the vsc7133 is designed to operate with a case temperature up to 95 o c. the user must guarantee that the case temperature specification is not violated. with the thermal resistances shown above, the 10mm thermally enhanced pqfp can operate in still air ambient temperatures of 50 o c [50 o c = 95 o c - 0.9w * 50]. if the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. moisture sensitivity level this device is rated at with a moisture sensitivity level 3 rating. refer to application note an-20 for appropriate handling procedures. symbol description 10mm units q jc thermal resistance from junction to case 10 o c/w q ca thermal resistance from case to ambient in still air including conduction through the leads. 50 o c/w q ca-100 thermal resistance from case to ambient with 100 lfm airflow 41 o c/w q ca-200 thermal resistance from case to ambient with 200 lfm airflow 37 o c/w q ca-400 thermal resistance from case to ambient with 400 lfm airflow 32 o c/w q ca-600 thermal resistance from case to ambient with 600 lfm airflow 28 o c/w internal heat spreader die plastic molding compound lead bond wire insulator
vitesse semiconductor corporation advance product information vsc7133 10-bit transceiver for fibre channel and gigabit ethernet page 18 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 1/17/00 g52187-0 rev. 2.4 ordering information the part number for this product is formed by a combination of the device number and the package style: VSC7133QU device type: vsc7133: 10-bit transceiver package style (64-pin) qu: 10mm pqfp marking information the package is marked with three lines of text as shown below. figure 11: package marking information notice this document contains information about a product during its fabrication or early sampling phase of devel- opment. the information contained in the document is based on design targets, simulation results or early proto- type test results. characteristic data and other specifications are subject to change without notice. therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement. warning vitesse semiconductor corporations product are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without written consent is prohibited. vitesse VSC7133QU ####aaaa part number date code package suffix lot tracking code pin 1 identifier

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