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te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 1 publication date: aug. 2002 to change products or specifications without notice. revision:0.a sram 128k x 16 high speed cmos static ram features ? fast access time : 8/10/12/15 ns ? low-power consumption : stand-by current (cmos input/output) max. 300 ua ? single +3.0v to 3.6v power supply ? ttl compatible , tri-state output ? common i/o capability ? automatic power-down when deselected ? available in 44-pin tsop-ii and 48-pin csp packages part number examples part number access time package T14L2M16A-10s 10ns tsop -ii T14L2M16A-12c 12ns csp T14L2M16A-10s 10ns tsop -ii T14L2M16A-12c 12ns csp general description the T14L2M16A is a very fast access time cmos static ram, organized as 131,072 words by 16 bits . this device is fabricated by high performance cmos technology. it can be operated under wide power supply voltage range from +3.0v to +3.6v. the T14L2M16A inputs and three-state outputs are ttl compatible and allow for direct interfacing with common system bus structures. data retention is guaranteed at a power supply voltage as low as 2v. block diagram decoder a0 a16 i/o1 6 vcc data i/o core array vss i/o1 we oe ce control circuit ub lb . . . . . . 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 2 publication date: aug. 2002 to change products or specifications without notice. revision:0.a pin configurations tsop-ii 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 ce i/o1 i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 nc lb oe i/o9 vcc vss i/o10 i/o15 i/o16 nc a8 a14 nc a15 a12 a13 a9 a10 we a11 nc i/o8 i/o7 a6 nc vcc vss ub i/o3 i/o1 a0 a1 a2 ce a4 a3 a5 a 6 5 4 3 2 1 h g f e d c b i/o11 i/o12 i/o13 i/o14 nc nc a7 a16 i/o2 i/o4 i/o5 i/o6 48-ball csp top view (ball down) pin descriptions symbol descriptions symbol descriptions a0 ~ a16 address inputs lb lower byte (i/o 1~8) i/o1~i/o16 data inputs/outputs ub upper byte (i/o 9~16) ce chip enable vcc power supply we write enable input v ss ground oe output enable input nc no connection 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 3 publication date: aug. 2002 to change products or specifications without notice. revision:0.a absolute maximum ratings* parameter sym min. max. unit voltage on any pin relative to vss v r -0.5 +4.6 v v power dissipation p d - 1.0 w storage temperature t stg -55 +150 c temperature under bias i bias 0 +70 c *note: stresses greater than those listed above absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table ce oe we lb ub i/o 1~8 i/o 9~16 mode power h x* x* x* x* high-z high-z deselected standby l x* x* h h high-z high-z output disabled active l h h l x* high-z high-z output disabled active l h h x* l high-z high-z output disabled active l l h l h data out high-z lower byte read active l l h h l high-z data out upper byte read active l l h l l data out data out word read active l x* l l h data in high-z lower byte write active l x* l h l high-z data in upper byte write active l x* l l l data in data in word write active *note: x = don?t care (must be low or high state), l = low, h = high 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 4 publication date: aug. 2002 to change products or specifications without notice. revision:0.a recommended operating conditions - (ta = 0 ~ +70 c ) parameter sym min typ max unit vcc 3.0 3.3 3.6 v supply voltage v ss 0.0 0.0 0.0 v v ih 2.0 - vcc+0.3 v input voltage v il -0.2 - 0.8 v operating characteristics - (vcc = 3.0 to 3.6v, v ss = 0v, ta = 0 ~ +70 c ) -8 -10 -12 -15 unit parameter sym. test conditions min max min max min max min max input leakage current i li vcc = max, v in = v ss to vcc - 1 - 1 - 1 - 1 ua output leakage current i lo ce = v ih or oe = v ih or we = v il v io = v ss to vcc - 1 - 1 - 1 - 1 ua operating power supply current i cc vcc = max, ce = v il , v in = v ih or v il, i out =0ma, f=max - 60 - 55 - 50 - 45 ma standby power supply current (ttl level) i sb ce = v ih , other input= v il or v ih - 15 - 15 - 15 - 15 ma standby power supply current (cmos level) i sb1 ce vcc-0.2v or v in 0.2v or v in vcc-0.2v - 300 - 300 - 300 - 300 ua output low voltage v ol i ol = 8.0ma - 0.4 - 0.4 - 0.4 - 0.4 v output high voltage v oh i oh = -4.0 ma 2.4 - 2.4 - 2.4 - 2.4 - v 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 5 publication date: aug. 2002 to change products or specifications without notice. revision:0.a capacitance (f = 1 mhz, ta = 25 c,) parameter symbol condition max. unit input capacitance c in v in = 0v 6 pf input/ output capacitance c i/o v in = v out = 0v 8 pf note: this parameter is guaranteed by device characterization and is not production tested. ac test conditions parameter conditions input pulse levels 0.8v to 2.0v input rise and fall times 3.0 ns input and output timing reference level 1.4v output load c l =30pf+1ttl load ac test loads and waveform dq z 0 = 50 ohm 50 ohm 30 pf vt =1.4v fig.a * including scope and jig capacitance ttl c l * fig.b output load equivalent r l c l 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 6 publication date: aug. 2002 to change products or specifications without notice. revision:0.a ac characteristics ( v cc =3.0 to 3.6v, ss v = 0v, ta = 0 ~ +70 c ) (1) read cycle -8 -10 -12 -15 parameter sym. min max min max min max min max unit read cycle time t rc 8 - 10 - 12 - 15 - ns address access time t aa - 8 - 10 - 12 - 15 ns chip enable access time t ace - 8 - 10 - 12 - 15 ns output enable access time t oe - 3 - 4 - 5 - 6 ns output hold from address change t oh 3 - 3 - 3 - 3 - ns chip enable to output in low-z t lz 3 - 3 - 3 - 3 - ns chip disable to output in high-z t hz - 3 - 4 - 5 - 6 ns output enable to output in low-z t olz 0 - 0 - 0 - 0 - ns output disable to output in high-z t ohz - 3 - 4 - 5 - 6 ns lb , ub access time t ba - 3 - 4 - 5 - 6 ns lb , ub enable to output in low-z t blz 0 - 0 - 0 - 0 - ns lb , ub disable to output in high-z t bhz - 3 - 4 - 5 - 6 ns (2)write cycle -8 -10 -12 -15 parameter sym. min max min max min max min max unit write cycle time t wc 8 - 10 - 12 - 15 - ns chip enable to write end t cw 7 - 8 - 8 - 10 - ns address valid to write end t aw 7 - 8 - 8 - 10 - ns address setup time t as 0 - 0 - 0 - 0 - ns write pulse width t wp 6 - 7 - 8 - 10 - ns write recovery time t wr 0 - 0 - 0 - 0 - ns data valid to write end t dw 4 - 5 - 6 - 7 - ns data hold time t dh 0 - 0 - 0 - 0 - ns write enable to output in high-z t whz - 3 - 4 - 5 - 6 ns output active from write end t ow 0 - 0 - 0 - 0 - ns 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 7 publication date: aug. 2002 to change products or specifications without notice. revision:0.a timing waveforms read cycle 1 (address controlled, ce = oe = il v , we = v ih , lb or/and ub = il v ) read cycle 2 ( we = v ih ) don't care undefined ce t oe ub / lb t ba t ohz d out oe t rc t ace t aa t olz t blz t lz high-z t bhz t hz t oh address notes (read cycle) : 1. we are high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition referenced to v oh or v ol levels. 4. at any given temperature and voltage condition. t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 5. transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 6. device is continuously selected with ce =v il . t rc address t oh t aa d out previous data valid data valid 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 8 publication date: aug. 2002 to change products or specifications without notice. revision:0.a write cycle 1 ( we controlled) write cycle 2 ( ce controlled) t wc t whz t dw d in t dh t wr t as t wp add ress ub / lb ce we d out t aw t cw t ow high-z high-z don't care undefined t wc t dw d in t dh t wr t as t wp t cw add ress ce we d out ub / lb t aw high-z high-z high-z 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 9 publication date: aug. 2002 to change products or specifications without notice. revision:0.a write cycle 3 ( ub , lb controlled) notes ( write cycle ) : 1. a write occurs during the overlap of a low ce , a low we . a write begins at the lateat transition among ce goes low, we going low. a write end at the earliest transition among ce going high, we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of ce going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. don't care undefined t wc t dw d in t dh t wr t as t wp t cw address ce we d out ub / lb t aw high-z high-z high-z 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 10 publication date: aug. 2002 to change products or specifications without notice. revision:0.a data retention characteristics parameter sym. test condition min. max. unit v cc for data retention v dr 2.0 - v data retention current i ccdr - 300 ua chip deselect to data retention time t cdr 0 - ns operation recovery time t r ce v cc -0.2v v in vcc -0.2v or v in 0.2v t rc - ns data retention waveform ( ta = 0 ~ +70 c ) t cdr ce t r vcc ce >vcc- 0.2v v dr > 2.0v v ih v ih vcc_typ vcc_typ data retention mode 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 11 publication date: aug. 2002 to change products or specifications without notice. revision:0.a package dimensions 44-lead tsop-ii seating plane index mark mirror finish 22 23 44 ee1 d b1 b e c e2 a a2 a1 l1 l a3 c c1 dimension in mm dimension in inch symbol min nom max min nom max a - - 1.20 - - 0.047 a1 0.05 - 0.1 0.002 - 0.004 a2 0.95 1.00 1.05 0.037 0.039 0.041 a3 - 0.25 - - 0.010 - b - 0.35(typ) - - 0.014(typ) - b1 0.10 0. 15 0.25 0.004 0.006 0.010 c - 0.805 - - 0.032 - c1 - 0.10 - - 0.004 - d 18.31 18.41 18.51 0.721 0.725 0.729 e - 0.80(typ) - - 0.031(typ) - e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.394 0.400 0.405 e2 - 10.76 - - 0.458 - l 0.4 0.5 0.6 0.016 0.020 0.024 l1 - 0.8(typ) - - 0.032(typ) - 0 - 8 0 - 8 4 .com u datasheet
te ch tm preliminary T14L2M16A tm technology inc. reserves the right p. 12 publication date: aug. 2002 to change products or specifications without notice. revision:0.a package dimensions units : millimeters 48-pin csp (8 row x 6 column) 48 ball fine pitch bga (0.75mm ball pitch) bottom view top view b b1 0.50 0.50 c c1 b/2 c1/2 #a1 a1 index mark d 0.36 e2 e1 e a y symbol min typ max a - 0.75 - b 5.95 6.00 6.05 b1 - 3.75 - c 7.95 8.00 8.05 c1 - 5.25 - d 0.25 0.30 0.35 e - 1.10 1.20 e1 - 0.95 - e2 0.20 0.25 0.30 y - - 0.08 notes : 1. bump counts : 48 (8 row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75) typ. 3. all tolerance are 0.050 unless otherwise specified. 4. ?y? is coplanarity : 0.08(max) 5. units : mm 4 .com u datasheet

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