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AS8220A flexray tm basis transceiver objective data sheet www.austriamicrosystems.com rev ision 17920-001-10a 1 - 33 1 general description this objective data sheet describes the intended functionality of the AS8220A bus transceiver. as long the device is not fully qualified, the parameters are not characterized in the means that parameters may change or can be updated during final product qualification and characterization. this docume nt shows the objective of the AS8220A and this document is subjected to change without notice. the AS8220A is a high-speed automotive transceiver for fault tolerant and high speed applications, operating as the bi-directional interface between a generic communication controller and the twisted pair copper wires. the device enables two-way communication with the microcontroller with full mode handling, including the low-power modes. the transmission rates up to 10mbps as well as the implemented bus guardian interface enables this transceiver the usage in fault tolerant and hard real-time applications in the stringent automotive envi ronment. an extended diagnostic interfac e, offers advanced bus- failure detection capabilities with the intelligent combination of bus-current measurement and logical comparators. a thermal sensor circuit with an integral shutdown mechanism prevents damage to the device in extreme temperature conditions. th e symmetrical transient control for the high- and low- side driver for both the bus- minus and bus-plus line allows an ideal balance of communications over differ ent network topologies, with excellent emc performance. the product is available in ssop14 package. 2 key features data transfer up to 10 mbps compliant with flexray electrical physical layer specification v2.1 rev. b excellent emc performances. high common mode range insure excellent emi enable pin for an optional bus guardian automatic thermal shutdown protection low standby current supports 2.5, 3, 3.3, 5 v micro controllers and automatically adapts to interface levels protection against damage due to short circuit conditions on the bus (positive and negative battery voltage) operating temperature range -40oc to +125oc 3 applications the device is ideal for figure 1. block diagram host controller interface bus failure detector communi- cation controller interface bus guardian interface power supply interface receiver transmitter digital logic AS8220A stbn errn rxd txd txen bge v io v cc gnd bm bp v io v io high speed automotive bus systems, backbone bus and gateways, x-by-wire systems, redundant bus systems, bus topologies with active stars, and safety critical applications. designed for flexray, where the basic features are demanded.
www.austriamicrosystems.com rev ision 17920-001-10a 2 - 33 AS8220A objective data sheet - applications contents 1 general description ......................................................................................................... ...................... 1 2 key features ................................................................................................................ ........................... 1 3 applications ................................................................................................................ ............................ 1 4 pin assignments ............................................................................................................. ....................... 4 4.1 pin descriptions ......................................... ................................................................. ......................................4 5 absolute maximum ratings .. .................................................................................................. .............. 5 6 electrical characteristics.................................................................................................. ..................... 6 7 typical operating characteristics ........................................................................................... ........... 11 8 detailed description ........................................................................................................ ..................... 12 8.1 block description........................................ ................................................................. ....................................12 8.2 events.................................................................................................................... .......................................... 12 8.3 operating modes........................................................................................................... .................................. 12 8.3.1 normal mode ............................................................................................................. ........................13 8.3.2 standby mode ............................................................................................................ .......................13 8.4 non operating mode ........................................................................................................ ............................... 13 8.4.1 power off .............................................................................................................. ...............................13 8.5 undervoltage events ....................................................................................................... ................................ 13 8.5.1 undervoltage v io ............................................................................................................................... ....13 8.5.2 undervoltage v cc ............................................................................................................................... ..13 8.6 power on/off events....................................................................................................... ................................ 14 8.7 system description ........................................................................................................ ................................. 14 8.8 fail silent behavior ...................................................................................................... ................................... 15 8.8.1 state transitions due to under voltage detection ....... .............. .............. .............. .............. ......... ...........15 8.8.2 state transitions due to volt age recovery detection ..................................................................... .........15 8.9 mode transitions .......................................................................................................... ................................... 15 8.9.1 errn signalling ................ .............. .............. .............. .............. ........... ........... ........... ..........................16 8.10 loss of ground........................................................................................................... .................................... 16 8.11 error flags description .................................................................................................. ................................ 16 8.11.1 bus error .............................................................................................................. ...............................16 8.11.2 low current on bp high side driver ..................................................................................... ................16 8.11.3 low current on bp low side driver...................................................................................... .................16 8.11.4 low current on bm high side driver........... .......................................................................... ................16 8.11.5 low current on bm low side driver ...................................................................................... ................16 8.11.6 high current on bp high side driver .................................................................................... ................16 8.11.7 high current on bp low side driver ..................................................................................... .................16 8.11.8 high current on bm high side driver .......... .......................................................................... ................17 8.11.9 high current on bm low side driver ........... .......................................................................... ................17 8.11.10 bp open line ....... .............. .............. .............. .............. ............ ........... ........... ......... ............................17 8.11.11 bm open line .......................................................................................................... ...........................17 8.11.12 bp short circuit to v cc .......................................................................................................................17 8.11.13 bp short circuit to gnd ............................................................................................... ......................17 8.11.14 bm short circuit tov cc .......................................................................................................................17 8.11.15 bm short circuit to gnd ............................................................................................... .....................17 8.11.16 short circuit between bp and bm ....................................................................................... ..............17 8.11.17 over temperature ...................................................................................................... ........................17
www.austriamicrosystems.com rev ision 17920-001-10a 3 - 33 AS8220A objective data sheet - applications 8.11.18 txen_bge timeout .......... .............. .............. .............. .............. .............. ............ .......... .....................17 8.11.19 error flag ............................................................................................................ ...............................17 8.12 status flags description................................................................................................. ............................... 17 8.12.1 power on flag .......................................................................................................... ............................17 8.13 transmitter .............................................................................................................. ...................................... 18 8.14 receiver ................................................................................................................. ....................................... 20 8.14.1 bus activity and idle detection (only in norm al mode).................................................................. ...20 8.14.2 bus data detection (normal mode)....................................................................................... ...........20 8.14.3 receiver test signal ................................................................................................... ..........................22 8.14.4 transceiver timing..................................................................................................... .........................23 8.15 test circuits ............................................................................................................ ....................................... 24 9 appendix .................................................................................................................... ........................... 25 10 package drawings and markings.............................................................................................. ........ 31 11 ordering information....................................................................................................... ................... 32
www.austriamicrosystems.com rev ision 17920-001-10a 4 - 33 AS8220A objective data sheet - pin assignments 4 pin assignments table 1. pin descriptions pin name pin number description figure 2. pin assignments ssop14 package pin descriptions v io 1 i/o supply voltage txd 2 transmit data input txen 3 transmitter enable input rxd 4 receive data output bge 5 bus guardian enable input stbn 6 standby input errn 10 error diagnosis output gnd 11 ground bm 12 bus line minus bp 13 bus line plus v cc 14 supply voltage AS8220A 1 2 3 4 5 6 7 10 14 13 12 11 txd txen rxd bge stbn bp bm gnd errn 9 8 v io v cc
www.austriamicrosystems.com rev ision 17920-001-10a 5 - 33 AS8220A objective data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 6 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes supply voltage (v cc )-0.3+7.0v supply voltage (v io )-0.3+7.0v dc voltage at en, stbn, errn, txd, rxd, txen, bge, rxen -0.3 v io + 0.3 vv io < v cc dc voltage at bp and bm -40 +50 v input current (latchup immunity) -100 100 ma according to jedec 78 electrostatic discharge at bus lines bp and bm -4 +4 kv according to aec-q100-002 electrostatic discharge -2 +2 kv according to aec-q100-002 transient voltage on bp, bm -200 +200 v according to iso7637 part3 test pulses a and b; class c; rl=45 w, cl= 100 pf; (see figure 17 on page 24) . total power dissipation (all supplies and outputs) 150 mw storage temperature -55 +150 oc junction temperature -40 +150 oc package body temperature 1 1. the reflow peak soldering temperature (body te mperature) specified is in accordance with ipc/jedec j-std- 020c ?moisture/reflow sensitivity classification fo r non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). 250 oc humidity non-condensing 5 85 %
www.austriamicrosystems.com rev ision 17920-001-10a 6 - 33 AS8220A objective data sheet - electrical characteristics 6 electrical characteristics t vj = -40 to +150 oc, v cc = +4.75v to +5.25v, v io = +2.2 to v cc , r l = 45 symbol parameter conditions min typ max units supply voltage t amb ambient temperature -40 +125 oc v cc -v io difference of supplies -0.1 3.05 v i cc v cc current consumption standby mode 1 v cc = 0v to +5.25v -5 30 a normal mode, driver enabled 045ma normal mode, driver enabled, r bus = ? state transitions t stbn_rxd delay stbn high to rxd high with wake flag set 150s t standby go-to standby hold time inh1 low = 20% v bat 10 70 s transmitter v bus_diff_d0 differential bus voltage low in normal mode (data0) v bpdata0 - v bmdata0 ; 40
www.austriamicrosystems.com rev ision 17920-001-10a 7 - 33 AS8220A objective data sheet - electrical characteristics ibp -5vshortmax absolute max current when bp is shorted to -5 v v bp = -5v +100 ma ibm -5vshortmax absolute max current when bm is shorted to -5 v v bm = -5v +100 ma ibp 27vshortmax absolute max current when bp is shorted to 27 v v bp = 27v +100 ma ibm 27vshortmax absolute max current when bm is shorted to 27 v v bm = 27v +100 ma ibp 48vshortmax absolute max current when bp is shorted to 48 v v bp = 48v +100 ma ibm 48vshortmax absolute max current when bm is shorted to 48 v v bm = 48v +100 ma t txd_bus01 delay time from txd to bus positive edge t txd_rise = 5ns 50 ns t txd_bus10 delay time from txd to bus negative edge t txd_fall = 5ns 50 ns t txd_mismatch delay time from txd to bus mismatch t txd_bus10 - t txd_bus01 -4 4 ns t bus10 fall time differential bus voltage 80% - 20% of v bus 3.75 18.75 ns t bus01 rise time differential bus voltage 20% - 80% of v bus 3.75 18.75 ns t txen_bus_idle_active delay time from txen to bus active 50 ns t txen_bus_active_idle delay time from txen to bus idle 50 ns t txen_mismatch delay time from txen to bus mismatch |t txen_bus_idle_active - t txen_bus_active_idle | 50 ns t bge_bus_idle_active delay time from bge to bus active 50 ns t bge_bus_active_idle delay time from bge to bus idle 50 ns t bus_idle_active differential bus voltage transition time: idle to active 30 ns t bus_active_idle differential bus voltage transition time: active to idle 30 ns t txen_timeout txen timeout 0.64 3.07 ms receiver r bp , r bm bp, bm input resistance idle mode; r bus = symbol parameter conditions min typ max units
www.austriamicrosystems.com rev ision 17920-001-10a 8 - 33 AS8220A objective data sheet - electrical characteristics i bpidle absolute idle output current on pin bp -40v < v bp < 50v 07.5ma i bmidle absolute idle output current on pin bm -40v < v bm < 50v 07.5ma i bpleak , i bmleak absolute leakage current, when not powered v bp = v bm = 5v, v cc = 0v, v bat = 0v; v io = 0v 0 +10 ua v busactivehigh activity detection differential input voltage high normal mode -10v < (v bp , v bm ) < 15v 150 225 400 mv v busactivelow activity detection differential input voltage low normal mode -10v < (v bp , v bm )< 15v -400 -225 -150 mv v data1 data1 detection differential input voltage pre-condition: activity already detected. normal mode. -10v < (v bp , v bm )< 15v 150 225 300 mv v data0 data0 detection differential input voltage pre-condition: activity already detected. normal mode. -10v < (v bp , v bm )< 15v -300 -225 -150 mv v dataerr mismatch between data0 and data1 differential input voltage 2 x ( ?? ? ? ?? ? ? ? ? supply voltage monitor v ccthh v cc under-voltage recovery threshold 3.5 4.5 v v ccthl v cc undervoltage detection threshold 2.5 3.5 v v iothh v io undervoltage recovery threshold 1.25 2.0 v v iothl v io undervoltage detection threshold 0.75 1.5 v table 3. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com rev ision 17920-001-10a 9 - 33 AS8220A objective data sheet - electrical characteristics t uv_detect detection time for undervoltage at v bat , v cc , v io 100 700 ms t uv_rec detection time for undervoltage recovery at v cc , v io 0.7 5 ms bus error detection i thl absolute bus current for low current detection normal mode, transmitter enabled 5ma i thh absolute bus current for high current detection normal mode, transmitter enabled 40 ma v short differential voltage on bp and bm for detecting short circuit between bus lines normal mode, transmitter enabled 225 mv t bus_error bus error detection time normal mode, transmitter enabled 20 s over temperature ot th over temperature threshold 150 180 oc ot tl over temperature hysteresis 10 20 oc communication controller interface v txdih threshold for detecting txd as on logical high 0.7* v io v v txdil threshold for detecting txd as on logical low 0.3* v io v i txdih txd high level input current 30 100 a i txdil txd low level input current -5 5 a v txenih threshold for detecting txen as on logical high 0.7* v io v v txenil threshold for detecting txen as on logical low 0.3* v io v i txenih txen high level input current -5 5 a i txenil txen low level input current -100 -30 a v rxdoh rxd high level output voltage i rxd = -4ma, v io = 5v 0.8* v io 1.0* v io v v rxdol rxd low level output voltage i rxd = 4ma, v io = 5v 0 0.2* v io v host interface v stbnih threshold for detecting stbn as on logical high 0.7* v io v v stbnil threshold for detecting stbn as on logical low 0.3* v io v i stbnih stbn high level input current 30 100 a table 3. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com rev ision 17920-001 -10a 10 - 33 AS8220A objective data sheet - electrical characteristics i stbnil stbn low level input current -5 5 a t stbn_deb_stby stbn de-bouncing time standby mode 0.1 40 s t stbn_deb_norm stbn de-bouncing time normal mode 0.1 2 s v errnoh errn high level output voltage i errn = -4ma, v io = 5v 0.8* v io 1.0* v io v v errnol errn low level output voltage i errn = 4ma, v io = 5v 0 0.2* v io v bus guardian interface v bgeih threshold for detecting bge as on logical high 0.7* v io v v bgeil threshold for detecting bge as on logical low 0.3* v io v i bgeih bge high level input current 30 100 a i bgeil bge low level input current -5 5 a 1. stbn, errn, txd, rxd, txen, and bge open 2. test condition: (v bp + v bm ) / 2 = 2,5v 5% 3. for test signal (see figure 15) table 3. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com rev ision 17920-001 -10a 11 - 33 AS8220A objective data sheet - typical operating characteristics 7 typical operating characteristics figure 3. figure 4. figure 5. figure 6.
www.austriamicrosystems.com rev ision 17920-001 -10a 12 - 33 AS8220A objective data sheet - detailed description 8 detailed description the AS8220A is a high-speed fault tole rant device operating as an interfac e between a generic controller and the copper wire physical bus. the AS8220A is designed to extend the application range for high speed and safety critical time triggered bus systems in an automot ive environment. the drivers are short circuit protected ag ainst the positive and negative supply voltage to increase the robustness and reliability of automotive syst ems. the AS8220A operates at baudrates up to 10 mbps to increase the bandwidth for automotive applications. block description the electrical AS8220A high-speed bus-system transceiver is the interface between a flexray? network node module and the channel. the transceiver provides differential transmit and receive capability to the bus, allowing the node module bidirectional time multiplexed binary data stream transfer. besides the transm it and receive function, the transceiver provides low power management, supply voltage monitoring (under voltage detection) as well as bus failure detection and represents a esd-prote ction barrier between the bus and the ecu. the AS8220A consists of 8 different functional blocks (see figure 1) : table 4. functional blocks functional block short description events transitions in order to change between the operation modes are possible only when events are detected. the device supports two type of events, events on the host controller interface (stbn) and detecti on of undervoltage or supply voltage recovery. whenever an event is recognized, a transition can be performed. operating modes the AS8220A provides the following operating modes: normal: non low power mode standby: low power mode host controller interface (hci) digital interface between the tran sceiver and the host controller (hc) the host interface comprises the read out handler, which delivers failure and status information via the errn pin to the host controller. communication controller interface (cci) digital interface between the transceiver and the flexray communication controller (cc) bus guarding interface (bgi) digital interface between the transceiver and the flexray bus guardian (bg) power supply interface (psi) the power supply interface consists of an sub functional block, the voltage monitor (vm) and includes two analogue inhibit outputs for signalling the internal state of the transceiver internal logic (il) the digital signals from the functional blocks of the device are fed into the internal logic where the forwarding of flexray messages from analogue side to digital interfaces and vice versa is done. the state machine is performed in this block and is dealing the error, wake and power-on flags. bus failure detector (bfd) temperature protection (tp) the bus failure detector is directly connec ted to the bus pins, in order to detect several external failure conditions which may occur on the bus. the temperature protection turns off the output driver when reaching the specified internal temperature in order to protect the device. transmitter the transmitter provides the bus signals as specified on the bus lines. receiver the receiver captures flexray valid si gnals on the bus lines and provides received data streams to the internal logic
www.austriamicrosystems.com rev ision 17920-001 -10a 13 - 33 AS8220A objective data sheet - detailed description normal mode in this mode the transceiver is able to send and receive data signals on the bus. txen and bge control the state of the transmitter. rxd reflects the bus data and reflect the bus state. in this mode, the transmitter state can be selected as shown in the ta b l e 5 . in case the over-temperature flag is set the tr ansmitter is disabled. the bus wires are terminated to v cc /2 via receiver input resistances. table 5. transmitter state bge txen txd transmitter state bus state if the differential bus voltage is higher than v busactivehigh or lower than v busactivelow for a time longer than t busac- tivitydetection , then activity is detected on the bus (bus = active), rxd is released. if, after the activity detection, the differential bus voltage is higher than v data1 , rxd is high. if, after the activity detection, the differential bus voltage is lover than v data0 , rxd is low. if the absolute differential bus voltage is lower than v busactivehigh and higher than v busactivelow for a time longer than t busidledetection , then idle is detected on t he bus (bus=idle), rxd is switched to logical ?high? standby mode in this mode the transceiver is not able to send and rece ive data signals from the bus. the power consumption is significantly reduced respect the norm al mode. the bus wires are terminated to gnd (bus state: idle_lp). non operating mode the AS8220A provides the following non operating mode: power off in this mode the transceiver is not able to operate. rxd is set to high and errn is set to low. the bus wires are not connected to gnd (bus state: idle_hz). undervoltage events undervoltage v io when v io voltage falls below v iothl for a time longer than t uv_detect then the undervoltage v io flag is set and it is reset when v io exceeds the voltage threshold v iothh for a time longer than t uv_rec . the flag can be set or reset in all the operation modes. the flag is reset at power off. undervoltage v cc when v cc voltage falls below v ccthl for a time longer than t uv_detect then the undervoltage v cc flag is set and it is reset when v cc exceeds the voltage threshold v ccthh for a time longer than t uv_rec . the flag can be set or reset in all the operation modes. the flag is reset at power off. h l h enabled data1 (bp is driven high, bm is driven low) h l l enabled data0 (bp is driven low, bm is driven high) x h x disabled idle (bp and bm are not driven) l x x disabled idle (bp and bm are not driven)
www.austriamicrosystems.com rev ision 17920-001 -10a 14 - 33 AS8220A objective data sheet - detailed description power on/off events ? starting from power off mode a power on event occurs in case undervoltage flag is reset. ? starting from every operation mode a power off event occurs in case v cc undervoltage flag is set. system description figure 9. state diagram note: in table 7 the corresponding transition table is shown prefix of ? while ? is always the event and suffix in brackets checks the flags or in case of stbn the input condition. for example: v rec _v bat while (stbn=1) after the event v io supply voltage recovery is detected, the transition is performed if stbn is ?high?. legend: uv_v io : undervoltage event and/or flag for v io supply voltage uv_v cc : undervoltage event and/or flag for v cc supply voltage v rec _v io : voltage recovery event and/or flag for v io supply voltage v rec _v cc : voltage recovery event and/or flag for v cc supply voltage v rec _v io while (stbn=1) or stbn=1 normal standby input: stbn = 1 input: stbn = 0 uv_v io or stbn=0 power off u v _ v c c u v _ v c c v r e c _ v c c v rec _v io while (stbn=0) uv_v cc
www.austriamicrosystems.com rev ision 17920-001 -10a 15 - 33 AS8220A objective data sheet - detailed description fail silent behavior in order to be fail silent, undervoltage detection on the two power supplies v io and v cc is implemented v io : supply voltage for i/o digital level adaptation v cc : supply voltage (+5v) state transitions due to under voltage detection in case of v io undervoltage is detected, standby mode will be ent ered regardless of the voltage present on pin stbn. in case v cc undervoltage is present, the device will enter powe r off mode (bus state: idle_hz), regardless on supply voltage at v io and the voltage present on stbn. state transitions due to voltage recovery detection starting from the power off, the device enters stand by mode only in case vcc undervoltage flag is reset.. when v cc d v ccthl the device is in power off state and the bus wires are not terminated (bus state: idle_hz). mode transitions in case all the undervoltage flags are reset the op eration mode is selected by stbn according to table 6 . table 6. pin signalling and operating modes inputs operation mode output stbn rxd rxen where: h = digital level high l = digital level low x = do not care float = the analog output is not driven hnormal l bus = data_0 l bus = active h bus = idle or data_1 h bus = idle l standby h h table 7. transition table supply voltage flag event host event intial mode v io v cc stbn next mode normal llh o l standby l o hl x standby h o ll h normal lll o h power off x h o l x standby any x l o hxpower off
www.austriamicrosystems.com rev ision 17920-001 -10a 16 - 33 AS8220A objective data sheet - detailed description errn signalling the errn signalling is shown in table 8 . table 8. errn signalling supply voltage flag event v io host command stbn errn note: error means the logic or of the error flags loss of ground in case the ground of the device is disconnected and the hos t pins are open, the bus lines are switched to idle_hz. error flags description bus error the bus error flag is set when 2 consecutive rising edges on the txd pin without any rising edge on the rxd pin are detected or when 2 consecutive falling edges on the txd pin without any falling edge on the rxd pin are detected. this flag is reset when a rising edge on the txd pin is followed by a rising edge on rxd pin before of the next txd rising edge or when a falling edge on the txd pin is followed by a fa lling edge on rxd pin before of the next txd falling edge. this flag can be set or reset only in normal mode when the transmitter is enabled. the flag is reset at power off. low current on bp high side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data1 longer than t bus_error . if the absolute value of the bp pin current is lower than i thl after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. low current on bp low side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data0 longer than t bus_error . if the absolute value of the bp pin current is lower than i thl after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. low current on bm high side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data0 longer than t bus_error . if the absolute value of the bm pin current is lower than i thl after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. low current on bm low side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data1 longer than t bus_error . if the absolute value of the bm pin current is lower than i thl after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. high current on bp high side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data1 longer than t bus_error . if the absolute value of the bp pin current is higher than i thh after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. high current on bp low side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data0 longer than t bus_error . if the absolute value of the bp pin current is higher than i thh after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. l h not failure llh lxl
www.austriamicrosystems.com rev ision 17920-001 -10a 17 - 33 AS8220A objective data sheet - detailed description high current on bm high side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data0 longer than t bus_error . if the absolute value of the bm pin current is higher than i thh after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. high current on bm low side driver this flag can only be set/reset in normal mode when the driver is enabled and during the transmission of a stable data1 longer than t bus_error . if the absolute value of the bm pin current is higher than i thh after t bus_error since the driver enable signal then the flag is set otherwise it is reset. the flag is reset at power off. bp open line this flag is the logical ?and? between: low current on bp high side and low current on bp low side. bm open line this flag is the logical ?and? between: low current on bm high side and low current on bm low side. bp short circuit to v cc this flag is the logical ?and? between: low current on bp high side and high current on bp low side. bp short circuit to gnd this flag is the logical ?and? between: high current on bp high side and low current on bp low side. bm short circuit tov cc this flag is the logical ?and? between: low current on bm high side and high current on bm low side. bm short circuit to gnd this flag is the logical ?and? between: high current on bm high side and low current on bm low side. short circuit between bp and bm this flag can only be set or reset in normal mode when the driver is enabled. after a time t bus_error since txd edge if the absolute value of the differential bus voltage is lower than v short then the flag is set otherwise it is reset. he flag is reset at power off. over temperature this flag can only be set or reset in the non low power mode s. the flag is set when the junction temperature exceeds ot th and it is reset when the junction temperature falls below ot tl . txen_bge timeout this flag can only be set in normal mode when the driver is enabled (txen is low and bge is high) for a time longer than t txen_max . it is reset every transition on txen or bge or if the device exits normal mode. if the flag is set the driver is disabled. error flag this flag is set if at least one error flag or if v io flag is set and it is reset if none of the previous flag is set. status flags description power on flag the power on flag is set leaving the power off state and it is reset entering a low power mode after a non low power mode.
www.austriamicrosystems.com rev ision 17920-001 -10a 18 - 33 AS8220A objective data sheet - detailed description transmitter the transmitter generates out of a digital input signal on txd the flexray differential bus voltage. the transmitter is only active in normal mode when bge is on logical high and txen is on logical low. figure 10. transmitter characteristics (txd
www.austriamicrosystems.com rev ision 17920-001 -10a 19 - 33 AS8220A objective data sheet - detailed description figure 12. timing characteristics (bge
www.austriamicrosystems.com rev ision 17920-001 -10a 20 - 33 AS8220A objective data sheet - detailed description receiver the receiver generates from the flexray differential bus vo ltage a digital signal on the rxd pin. rxd shows the data (data0 and data1). the receiver is only active in normal mode. figure 13. timing characteristics of the bus signals to rxd bus activity and idle detection (only in normal mode) if the absolute differential bus voltage is higher than v busactivelow and less than v busactivehigh for a time longer than t busidledetection , bus idle is dete cted, rxd is switched to logical high after a time t busidlereaction . if the absolute differential bus voltage is hi gher than vbusactivehigh or lower than v busactivelow for a time loner than t busactivitiydetection , bus activity is detected, rxd is following the dete cted bus data states as indicated below with a time t busactivityreaction . table 9. logic table for receiver bus signal detection receiver operation mode bus signals rxd bus data detection (normal mode) if, after the activity detection the di fferential bus voltage is higher than v data1 , rxd will be high after a time t bus_rxd01 . if, after the activity detection the differential bus voltage is lower than v data0 , rxd will be low after a time t bus_rxd10 . normal mode idle h data0 l data1 h v bus -v bus_diff_idle + v bus_diff_idle t rxd_ fall v bus_ activehigh v data1 v bus_ activelow v data0 v rxd 30 % * v io 70 % * v io t bus_rxd10 t bus_ rxd01 t rxd_ rise data0: x * t bit data1 : x * t bit
www.austriamicrosystems.com rev ision 17920-001 -10a 21 - 33 AS8220A objective data sheet - detailed description figure 14. receiver characteristics (bus
www.austriamicrosystems.com rev ision 17920-001 -10a 22 - 33 AS8220A objective data sheet - detailed description receiver test signal figure 15. receiver test signal 22 ns 22 ns t bit t bus_rxd01 t bus_rxd10 v bus rxd t bus_rxd10 v bus rxd 22 ns 22 ns 400 mv 300 mv -300 mv -400 mv 400 mv 300 mv -300 mv -400 mv t bit t bus_rxd01
www.austriamicrosystems.com rev ision 17920-001 -10a 23 - 33 AS8220A objective data sheet - detailed description transceiver timing figure 16. timing diagram txd bge txen v bus rxd 0.7 * vcc 0.3 * vcc 300 mv 30 mv 80 % 20 % 0.7 * v io 0.3 * v io 0.7 * vcc 0.3 * vcc t txen_bus_active_idle t txen_bus_idle_active t bge_bus_active_idle t bge_bus_idle_active t txd_bus01 t txd_bus10 t bus_rxd01 t bus_rxd10 t busidlereaction t busactivityreaction t bus01 t bus10 30 mv -300 mv -300 mv -300 mv t bus_idle_active t bus_active_idle
www.austriamicrosystems.com rev ision 17920-001 -10a 24 - 33 AS8220A objective data sheet - detailed description test circuits figure 17. test circuit for automotive transients figure 18. test circuit for dynamic characteristics as8220 rxd bp bm rl cl 15pf vcc vio 100nf +5v 14 1 4 13 12 1nf 1nf iso 7637 pulse generator transients in accordance with iso 7637 : test pulses 1, 2, 3a, 3b, 4, 5 test conditions : normal mode bus idle normal mode bus active (txd=5 mhz, txen=1 khz) as8220 rxd bp bm rl cl 15pf vcc vio 100nf +5v 14 1 4 13 12
www.austriamicrosystems.com rev ision 17920-001 -10a 25 - 33 AS8220A objective data sheet - appendix 9 appendix the following table shows the comparison of conventions used in AS8220A datasheet and flexray electrical physical layer specification v2.1 rev. b. table 10. comparison table AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description general parameters - battery supply voltage (v bat )- - - supply voltage (v cc )- - - supply voltage (v io )- - - dc voltage at en, stbn, errn, txd, rxd, txen, bge, rxen -- - dc voltage on pin wake, inh1, inh2 - - - dc voltage at bp and bm - - - input current (latchup immunity) - - - electrostatic discharge at bus lines bp, bm, v bat , wake uesdext esd protection on pins that lead to ecu external terminals - electrostatic discharge uesdint esd on all other pins - transient voltage on bp, bm - - - transient voltage on v bat -- - total power dissipation (all supplies and outputs) -- - storage temperature - - - junction temperature - - - package body temperature - - - humidity non-condensing - - supply voltage tamb ambient temperature t ambient temperature v cc - v io difference of supplies - - i cc v cc current consumption -- i io v io current consumption -- state transitions t stbn_rxd delay stbn high to rxd high with wake flag set -- t standby go-to standby hold time - - transmitter v bus_diff_d0 differential bus voltage low in normal mode (data0) -- v bus_diff_d1 differential bus voltage high in normal mode (data1) --
www.austriamicrosystems.com rev ision 17920-001 -10a 26 - 33 AS8220A objective data sheet - appendix v bus_diff matching between data0 and data1 differential bus voltage in normal mode -- v bus_com_d0 common mode bus voltage in case of data0 in normal mode -- v bus_com_d1 common mode bus voltage in case of data1 in normal mode -- v bus_com matching between data0 and data1 common mode voltage -- v bus_diff_idle absolute differential bus voltage in idle mode ubdtxidle absolute value of ubus, while idle ibp bmshortmax ibm bpshortmax absolute max current when bp is shorted to bm ibp bmshortmax ibm bpshortmax absolute maximum output current when bp shorted to bm ibp gndshortmax absolute max current when bp is shorted to gnd ibp gndshortmax absolute maximum output current when shorted to gnd ibm gndshortmax absolute max curre nt when bm is shorted to gnd ibm gndshortmax absolute maximum output current when shorted to gnd ibp -5vshortmax absolute max current when bp is shorted to -5 v ibp -5vshortmax absolute maximum output current when shorted to -5v ibm -5vshortmax absolute max curre nt when bm is shorted to -5 v ibm -5vshortmax a absolute maximu m output current when shorted to -5v ibp 27vshortmax absolute max current when bp is shorted to 27 v ibp bat27vshortmax absolute maximum output current when shorted to 27v ibm 27vshortmax absolute max curre nt when bm is shorted to 27 v ibm bat27vshortmax absolute maximum output current when shorted to 27v ibp 48vshortmax absolute max current when bp is shorted to 48 v ibp bat48vshortmax absolute maximum output current when shorted to 48v ibm 48vshortmax absolute max curre nt when bm is shorted to 48 v ibm bat48vshortmax absolute maximum output current when shorted to 48v t txd_bus01 delay time from txd to bus positive edge dbdtx10 transmitter delay, negative edge t txd_bus10 delay time from txd to bus negative edge dbdtx01 transmitter delay, positive edge t txd_mismatch delay time from txd to bus mismatch dtxasym transmitter delay mismatch | dbdtx10 - dbdtx01 | t bus_10 fall time differential bus voltage dbustx10 fall time differential bus voltage (80% AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description
www.austriamicrosystems.com rev ision 17920-001 -10a 27 - 33 AS8220A objective data sheet - appendix t txen_bus_idle_acti ve delay time from txen to bus ac tive dbdtxia propagation delay idle receiver r bp , r bm bp, bm input resistance rcm1, rcm2 receiver common mode input resistance r diff bp, bm differential input resistance - - v bpidle , v bmidle idle voltage in normal mode on pin bp,bm ubias bus bias voltage during bd_normal mode v bpidle_low , v bmidle_low idle voltage in normal mode on pin bp, bm ubias bus bias voltage during low power modes i bpidle absolute idle output current on pin bp - - i bmidle absolute idle output current on pin bm -- i bpleak , i bmleak absolute leakage current, when not powered ibpleak, ibmleak absolute leakage current, when not powered v busactivehigh activity detection differential input voltage high ubusactivehigh upper receiver threshold for detecting activity v busactivelow activity detection differential input voltage low ubusactivelow lower receiver threshold for detecting activity v data1 data1 detection differential input voltage udata1 receiver threshold for detecting data_1 v data0 data0 detection differential input voltage udata0 receiver threshold for detecting data_0 v dataerr mismatch between data0 and data1 differential input voltage udata mismatch of receiver thresholds t bus_rxd10 delay from bus to rxd negative edge dbdrx10 receiver delay, negative edge t bus_rxd01 delay from bus to rxd positive edge dbdrx01 receiver delay, positive edge table 10. comparison table AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description
www.austriamicrosystems.com rev ision 17920-001 -10a 28 - 33 AS8220A objective data sheet - appendix t bit bit time - - t rxd_asym delay time from bus to rxd mismatch drxasym receiver delay mismatch | dbdrx10 ? dbdrx01 | t busidledetection idle detection time didledetecti on filter-time for idle detection t busactivitydetection activity detection time dactivitydetec tion filter-time for activity detection t busidlereaction idle reaction time dbdrxai idle reaction time t busactivityreaction activity reaction time dbdrxia activity reaction time supply voltage monitor v ccthh v cc undervoltage recovery threshold -- v ccthl v cc undervoltage detection threshold uuvcc undervoltage detection threshold v iothh v io undervoltage recovery threshold -- v iothl v io undervoltage detection threshold uuvio undervoltage detection threshold t uv_detect detection time for undervoltage at v cc , v io duvcc, duvio undervoltage reaction time t uv_rec detection time for undervoltage recovery at v cc , v io -- bus error detection i thl absolute bus current for low current detection -- i thh absolute bus current for high current detection -- v short differential voltage on bp and bm for detecting short circuit between bus lines -- t bus_error bus error dete ction time - detection only required while actively transmitting a data frame, error indication to host latest when transmission stops. over temperature ot th over temperature threshold - - ot tl over temperature hysteresis - - communication controller interface v txdih threshold for detecting txd as on logical high uvio-in-high threshold for detecting a digital input as on logical high table 10. comparison table AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description
www.austriamicrosystems.com rev ision 17920-001 -10a 29 - 33 AS8220A objective data sheet - appendix v txdil threshold for detecting txd as on logical low uvio-in-low threshold for detecting a digital input as on logical low i txdih txd high level input current - - i txdil txd low level input current - - v txenih threshold for detecting txen as on logical high uvio-in-high threshold for detecting a digital input as on logical high v txenil threshold for detecting txen as on logical low uvio-in-low threshold for detecting a digital input as on logical low i txenih txen high level input current - - i txenil txen low level input current - - v rxdoh rxd high level output voltage uvio-out-high output voltage on a digital output, when in logical high state v rxdol rxd low level output voltage uvio-out-low output voltage on a digital output, when in logical low state host interface v stbnih threshold for detecting stbn as on logical high uvio-in-high threshold for detecting a digital input as on logical high v stbnil threshold for detecting stbn as on logical low uvio-in-low threshold for detecting a digital input as on logical low i stbnih stbn high level input current - - i stbnil stbn low level input current - - t stbn_deb_lp stbn de-bouncing time low power modes -- t stbn_deb_nlp stbn de-bouncing time non low power modes -- v errnoh errn high level output voltage uvio-out-high output voltage on a digital output, when in logical high state v errnol errn low level output voltage uvio-out-low output voltage on a digital output, when in logical low state bus guardian interface v bgeih threshold for detecting bge as on logical high uvio-in-high threshold for detecting a digital input as on logical high table 10. comparison table AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description
www.austriamicrosystems.com rev ision 17920-001 -10a 30 - 33 AS8220A objective data sheet - appendix v bgeil threshold for detecting bge as on logical low uvio-in-low threshold for detecting a digital input as on logical low i bgeih bge high level input current - - i bgeil bge low level input current - - table 10. comparison table AS8220A datasheet flexray electrical physical layer specification v2.1 revb symbol parameter name description
www.austriamicrosystems.com rev ision 17920-001 -10a 31 - 33 AS8220A objective data sheet - package drawings and markings 10 package drawings and markings figure 19. package diagram note: 1. dimensioning and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. n is the total number of terminals. table 11. package dimensions symbol min typ max symbol min typ max a 1.73 1.86 1.99 l 0.63 0.75 0.95 a1 0.05 0.13 0.21 l1 1.25 ref a2 1.68 1.73 1.78 n see variations b 0.25 - 0.38 0o 4o 8o b1 0.25 0.30 0.33 r 0.09 0.15 c 0.09 - 0.20 aa 6.07 6.20 6.33 c1 0.09 0.15 0.16 ab 6.07 6.20 6.33 d see variations ac 7.07 7.20 7.33 e 5.20 5.30 5.38 ad 8.07 8.20 8.33 e 0.65 bsc ae 10.07 10.20 10.33 h 7.65 7.80 7.90 af 10.07 10.20 10.33
www.austriamicrosystems.com rev ision 17920-001 -10a 32 - 33 AS8220A objective data sheet - ordering information 11 ordering information table 12. ordering information type marking description delivery form package
www.austriamicrosystems.com rev ision 17920-001 -10a 33 - 33 AS8220A objective data sheet - ordering information copyrights copyright ? 1997-200 8, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unus ual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag b

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