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adv ance informa tion february 1997 d.s. 3920 3.3 sp5610 1.3ghz bidirectional i 2 c bus controlled synthesiser (supersedes edition in 1996 media ic handbook, hb45991.0) the sp5610 is a single chip frequency synthesiser designed for tv tuning systems. control data is entered in the standard i 2 c bus format. the device contains 1 addressable current limited output and 4 addressable bidirectional open collector ports one of which is a 3 bit adc. the information on these ports can be read via the i 2 c bus. the device has one fixed i 2 c bus address and 3 programmable addresses, programmed by applying a specific input voltage to the p3 current limited output. this enables 2 or more synthesisers to be used in a system. features complete 1.3ghz single chip system high sensitivity rf inputs programmable via i 2 c bus on chip oscillator with 1k negative resistance low power consumption (5v , 20ma) low radiation phase lock detector v aractor drive amp disable 5 controllable outputs 5 level adc v ariable i 2 c bus address for multi t uner applications esd protection * switchable 512/1024 reference divider pin and function compatible with sp5510s * normal esd handling procedures should be observed. the sp5510s does not have a switchable reference division ratio. applications satellite tv when combined with sp4902 2.5ghz prescaler cable t uning systems vcr's 116 * = 3bit adc input charge pump crystal q1 crystal q2 sda scl i/o port p7 * i/o port p6 i/o port p5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 = logic level i/o mp16 sp5610s fig. 1 pin connections top view drive output v ee rf input rf input v cc nc p3 output port/ add select i/o port p4 ordering informa tion sp5610s/kg/mpas (tubes) sp5610s/kg/mpad (t ape and reel)
sp5610 2 electrical characteristics t amb = 40 c to 85 c, v cc = 4.5v to 5.5v . reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristic pin value units conditions characteristic pin min typ max units conditions supply current 12 20 27 ma v cc = 4.5v to 5.5v prescaler input v oltage 13, 14 12.5 300 mvrms 50mhz to 1.3ghz sinewave see fig. 5. prescaler input impedance input capacitance 13, 14 50 2 pf sda, scl input high v oltage input low v oltage input high current input low current leakage current 4, 5 4, 5 4, 5 4, 5 4, 5 3 0 5.5 1.5 10 10 10 v v a a a input v oltage = v cc input v oltage = 0v when v cc = 0v sda output v oltage 4 0.4 v i sink = 3ma charge pump current low 1 50 a byte 4 bit 2 = 0, pin 1 = 2v charge pump current high 1 170 a byte 4 bit 2 = 1, pin 1 = 2v charge pump output leakage current 1 5 na byte 4 bit 4 = 1, pin 1 = 2v charge pump drive output current 16 500 a v pin 16 = 0.7v charge pump amplifier gain 6400 recommended crystal series resistance 10 200 ` `parallel resonanto crystal. resistance specified is max under all conditions crystal oscillator drive level 2 80 mvpp crystal oscillator negative resistance 2 750 1000 external reference input frequency 2 2 8 mhz ac coupled sinewave external reference input amplitude 2 70 200 mvrms ac coupled sinewave output ports p3 sink current 10 0.7 1 1.5 ma v out = 12v p3 leakage current 10 10 a v out = 13.2v p4p7 sink current 96 10 ma v out = 0.7v p4p7 leakage current 96 10 a v out = 13.2v input ports p3 input current high 10 +10 a v pin 10 = 13.2v p3 input current low 10 10 a v pin 10 = 0v p4,p5,p7 input v oltage low 9,8,6 0.8 v p4,p5,p7 input v oltage high 9,8,6 2.7 v p6 input current high 7 +10 a see t able 3 for adc levels p6 input current low 7 10 a
sp5610 3 rf in pre amp prescaler programmable 15 bit divider f pd phase comp power on det transceiver i 2 c bus select address adc 3 bit level comp 3 ttl 15 bit la tch divide ratio 5 bit la tch port information det lock control data latches and control logic port output drivers f comp divider osc q 1 crystal pump charge pump charge f l down up cp to os q 2 varicap drive/ out v cc p3 p4 p5 p6 p7 scl sda fig 2. block diagram por 4 1 4 512/1024 v ee 13 14 5 4 2 3 1 16 12 15 109876 8
sp5610 4 functional description the sp5610 is programmed from an i 2 c bus. data and clock are fed in on the sda and scl lines respectively as defined by the i 2 c bus format. the synthesiser can either accept new data (write mode) or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low and read mode if it is high. the tables in fig. 3 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 4 shows how the address is selected by applying a voltage to p3. when the device receives a correct address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. when the device is programmed into the read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode (frequency synthesis) when the device is in write mode bytes 2+3 select the synthesised frequency , while bytes 4+5 control the output port states, charge pump, reference divider ratio and various test modes. once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for frequency information and a logic 1 for control and output port information. when byte 2 is received the device always expects byte 3 next. similarly , when byte 4 is received the device expects byte 5 next. additional data bytes can be entered without the need to readdress the device until an i 2 c stop condition is recognised. this allows a smooth frequency sweep for fine tuning or afc purposes. if the transmission of data is stopped midbyte (e.g. by another device on the bus) then the previously programmed byte is maintained. frequency data from bytes 2 and 3 is stored in a 15bit register and is used to control the division ratio of the 15bit programmable divider. this is preceded by a divideby8 prescaler and amplifier to give excellent sensitivity at the local oscillator input, see fig. 5. the input impedance is shown in fig. 7. the programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency f comp . when frequency data is entered, the phase comparator , via a charge pump and varicap drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phased locked to the comparison frequency. the reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an onboard crystal controlled oscillator. the comparison frequency f comp is derived from the reference frequency via the reference divider. the reference divider division ratio is switchable from 512 to 1024, and is controlled by bit 7 of byte 4 (ts0); a logic 1 for 512; a logic 0 for 1024. the sp5610 dif fers from the sp5510 in this respect, only 512 being available on the sp5510. note, the comparison frequency is 7.8125khz when a 4mhz reference is used, and divide by 512 is selected. bit 2 of byte 4 of the programming data (cp) controls the current in the charge pump circuit, a logic 1 for 170 a and a logic 0 for 50 a allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. when the device is `frequency locked' the charge pump current is internally set to 50 a regardless of cp . bit 4 of byte 4 (t0) disables the charge pump when it is set to a logic 1. bit 8 of byte 4 (os) switches the charge pump drive amplifier's output of f when it is set to a logic 1. bit 3 of byte 4 (t1) enables various test modes when set high. these modes are selected by bits 5, 6, 7 of byte 4 (ts2, ts1, ts0) as detailed in t able 5. when t1 is set low , ts2 and ts1 are assigned a `don't care' condition, and ts0 selects the reference divider ratio as previously described. byte 5 programs the output ports p3 to p7; a logic 0 for a high impedance output and a logic 1 for low impedance (on). read mode when the device is in read mode the status byte read from the device on the sda line takes the form shown in t able 2. bit 1 (por) is the poweron reset indicator and is set to a logic 1 if the v cc supply to the device has dropped below 3v (at 25 c), e.g. when the device is initially turned on. the por is reset to 0 when the read sequence is terminated by a stop command. when por is set high (at low v cc ), the programmed information is lost and the output ports are all set to high impedance. bit 2 (fl) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. bits 3, 4 and 5 (i2, i1, i0) show the status of the i/o ports p7, p5 and p4 respectively. a logic 0 indicates a low level and a logic 1 a high level. if the ports are to be used as inputs they should be programmed to a high impedance state (logic 1). these inputs will then respond to data complying with ttl type voltage levels. bits 6, 7 and 8 (a2, a1, a0) combine to give the output of the 5 level adc. the adc can be used to feed afc information to the microprocessor from the if section of the receiver, as illustrated in the typical application circuit. application a typical application is shown in fig. 4. all input/output interface circuits are shown in fig. 6. the sp5610 is function and pin equivalent to the sp5510 device apart from the switchable reference divider, and has much lower power dissipation, improved rf sensitivity and better esd performance.
fig. 3 data formats sp5610 5 msb lsb address 1 1 0 0 0 ma1 ma0 0 a byte 1 programmable divider 0 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 cp t1 t0 ts2 ts1 ts0 os a byte 4 io por t control data p7 p6 p5 p4 p3 x x x a byte 5 table 1 write data format (msb is transmitted first) address 1 1 0 0 0 ma1 ma0 1 a byte 1 sta tus byte por fl i2 i1 i0 a2 a1 a0 a byte 2 table 2 read data format (msb is transmitted first) a: acknowledge bit ma1, ma0: v ariable address bits (see t able 4) cp: charge pump current select t1: t est mode enable t0: charge pump disable ts2, ts1, ts0: operation mode control bits (see t able 5) os: v aractor drive output disable switch p7,p6,p5,p4,p3: control output states por: power on reset indicator fl: phase lock detect flag i2, i1, i0: digital information from ports p7, p5 and p4, respectively a2, a1, a0: 5 level adc data from p6 (see t able 3) x : don't care a2 a1 a0 v oltage input to p6 1 0 0 0.6v cc to 13.2v 0 1 1 0.45v cc to 0.6v cc 0 1 0 0.3v cc to 0.45v cc 0 0 1 0.15v cc to 0.3v cc 0 0 0 0 to 0.15v cc table 3 adc levels ma1 ma0 voltage input to p3 0 0 0 0.2v cc 0 1 alwa ys v alid 1 0 0.3v cc 0.7v cc 1 1 0.8v cc 13.2v table 4 address selection t1 ts2 ts1 ts0 operation mode description 0 x x 0 normal operation, test modes disabled, reference divider ratio=1024 0 x x 1 normal operation, test modes disabled, reference divider ratio=512 1 0 0 x charge pump source (down). status byte bit fl set to 0 1 0 1 x charge pump sink (up). status byte bit fl set to 1 1 1 0 0 ports p4,p5,p6,p7 set to state x 1 1 0 1 port p7=f pd /2; p4,p5,p6 set to state x 1 1 1 x port p7=f pd ; p6=f comp ; p4, p5 set to state x x=don't care for further details of test modes see t able 6. table 5 operation modes
sp5610 6 +12v +5v if section afc output if signal p6 scl sda i 2 c bus control micro 4mhz crystal 18p 180n 39n 22k 1n 1n 0.1 v t 22k band inputs output oscillator bcw31 input varicap p3 fig. 4 t ypical application window operating 300 37.5 25 12.5 50 500 1000 1300 1500 vin (mv rms int o 50 ) frequency (mhz) fig. 5 t ypical input sensitivity +30v 47k 10k 10nf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sp5610s tuner p7 p5 p4
sp5610 7 v 3k rf inputs ref v cc charge pump drive output 150 os (o/p disable) rf input loop amplifier port v cc 3k ports p7 p4 reference oscillator v cc crystal q1 crystal q2 v cc 67k 3k scl/sda ack scl and sda input v cc 3k port 12k port p3 fig. 6 input/output interface circuits sda onl y 3k
sp5610 8 0.5 0.2 1 0 +j0.2 +j0.5 +j1 +j2 +j5 2 5 j5 j2 j1 j0.5 j0.2 frequency marker step = 250mhz s 11 :z 0 = 50 fig. 7 t ypical input impedance normalised t o 50 1.25ghz absolute maximum ra tings all voltages are referred to v ee and pin 3 at 0v . parameter pin value units conditions parameter pin min max units conditions supply voltage 12 0.3 7 v rf input voltage 13, 14 2.5 vpp port voltage 610 69 10 0.3 0.3 0.3 14 6 14 v v v port in of f state port in on state port in on state t otal port output current 610 50 ma rf input dc of fset 13, 14 0.3 v cc +0.3 v charge pump dc of fset 1 0.3 v cc +0.3 v drive dc offset 16 0.3 v cc +0.3 v crystal oscillator dc offset 2 0.3 v cc +0.3 v sda,scl input voltage 4, 5 0.3 6 v storage temperature 55 +150 c junction temperature +150 c mp16 thermal resistance, chiptoambient 111 c/w mp16 thermal resistance, chiptocase 41 c/w power consumption at 5.5v 150 mw all ports of f esd protection all 4 kv mil std 883c tm 3015
sp5610 9 application notes a generic set of application notes an168 for designing with synthesisers such as the sp5610 has been written. this covers aspects such as loop filter design, decoupling and i 2 c bus radiation problems. this application note is featured in the media october 1995 ic handbook. a generic test/demo board has been produced which can be used for the sp5610. a circuit diagram and layout for the board is shown in figs. 8 and 9. the board can be used for the following purposes: (a) measuring rf sensitivity performance. (b) indicating port function. (c) synthesising a voltage controlled oscillator . (d) t esting of external reference sources. the programming codes relevant to these tests are shown in t able 6. 116 116 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode select r1 1 3k0 s1 s2 r12 1k0 tp1 data/sda clock/scl address sel enable/ p1 external reference skt2 10nf* *(not fitted) c6 c3 47nf r7 22k c2 220nf x1 4mhz c1 18pf c12 100pf c13 100pf p3 +30v +12v +5v c8 c9 c7/c8/c9 = 100nf c7 r8 22k r9 10k r10 47k c14 10nf var gnd t1 2n3904 c5 1nf c4 1nf c10 1nf r14 22k r13 12k t2 2n3906 p4 r1 4k7 r2 4k7 r3 4k7 r4 4k7 r4 4k7 r5 4k7 r6 d2 d1 d3 d4 d5 d6 pin no: 67 891011 c11 1nf for external reference cap acitor c6 should be fitted and capacit or c1 removed from the test board fig. 8 t est board rf input
sp5610 10 tp1 all surf ace mount components p1 p2 p3 p4 mounted on underside of board tp1 = pin 3 dc bias t op view (ground plane) underside (surface mount components side) notes: circuit schema tic is shown in fig. 8. fig. 9 t est board (layout)
sp5610 11 test modes as explained earlier in the data sheet, the device can be programmed into a number of test modes. these are invoked by programming the following hex codes into byte 4. the most commonly used codes are shown in t able 6 description hex code (byte 4) cp hi mode cp lo mode normal operation, ref div =1024 cc 8c normal operation, ref div = 512 ce 8e charge pump source (down), fl set to 0 e2 a2 charge pump sink (up), fl set to 1 e6 a6 port p7 = f pd /2 ea aa port p7 = f pd ; p6 = f comp ee ae charge pump disable, ref div 512 de 9e varactor line disable, ref div 512 cf 8f charge pump and v aractor line disable, ref div 512 df 9f t able 6 useful test modes. other codes will also apply due to `don't care' conditions, which are assumed to be 1 in the above t able. note: when looking at f pd or f comp signals from ports p7 and p6, byte 4 should be sent twice, firstly to set the desired reference divider ratio, (see t able 6) then secondly to switch on the chosen test mode. the pulses can then be measured by simply connecting an oscilloscope or counter to the relevant output pin on the test board.
sp5610 12 purchase of gec plessey i2c components conveys a licence under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the standard i2c standard specification as defined by philips. 0.35/0.49 9.80/10.01 0.69 (0.027) nom 3.80/4.00 1.27 (0.050) nom 0.41/1.27 0.10/0.25 1.35/1.75 5.80/6.20 0.25/0.51 0.19/0.25 pin 1 pin 1 identifica tion (0.386/0.394) a t 4 places (0.150/0.157) (0.053/0.069) (0.014/0.019) (0.004/0.010)

pin sp acing 16 lead minia ture plastic mp16 (0.228/0.244) headquarters opera tions gec plessey semiconduct ors cheney manor , swindon, wiltshire united kingdom sn2 2qw . t el: (01793) 518000 fax: (01793) 51841 1 gec plessey semiconduct ors p .o. box 660017 1500 green hills road, scotts v alley , california 950670017, united states of america. t el: (408) 438 5576/6231 fax: (408) 438 5576 this publication is issued to provide information only , which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarant ee express or implied is made regarding the capability , performance or suitability of any product or service. the company reserves the right to alter without prior notice the specifi cation, design, or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use w ill be satisfactory in a specific piece of equipment. it is the user 's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result i n significant injury or death to the user . all products and materials are sold and services provided subject to the company's conditions of sale, which are available on request. gec plessey semiconductors 1997 publication no. d.s. 3920 issue no. 3.3 february 1997 technical document a tion not for resale. printed in united kingdom all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. internet: http//www .gpsemi.com cust omer ser vice centres france & benelux les ulis cedex t el: (1) 69 18 90 00 fax: (1) 64 46 06 07 germany munich t el: (089) 3609 06 0 fax: (089) 3609 06 55 ital y milan t el: (02) 6607151 fax: (02) 66040993 japan t okyo t el: (03) 52765501 fax: (03) 52765510 korea seoul tel: (2) 5668141 fax: (2) 5697933 north america scotts v alley , usa t el: (408) 438 2900 fax: (408) 438 7023 south east asia singapore t el: 3827708 fax: 3828872 sweden stockholm t el: (8) 702 97 70 fax: (8) 640 47 36 taiwan , roc t aipei t el: (2) 5461260 fax: (2) 7190260 uk, eire, denmark, finland & nor way swindon t el: (01793) 518527/518566 fax: (01793) 518582 these are supported by agents and distributors in major countries worldwide.
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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