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? applications ? input voltage range : 2.0v ~20v z mobile, cordless phones ? output voltage range : 2.2v ~ 16v z palm top computers, pdast ? oscillation frequency range : 100khz ~ 600khz z portable games ? output current : up to 3a z cameras, digital cameras ? ceramic capacitor compatible z laptops ? msop-8a package ? general description ? features the xc9101/9102 series are step-up multiple current and stable operations via current & voltage multiple feedback voltage feedback dc/dc controller ics. current sense, clock unlimited options for peripheral selection frequencies and amp feedback gain can all be externally regulated. pwm/pfm switching control (xc9102) a stable power supply is possible with output currents of up to 3a and current protection circuit output voltage is selectable in 0.1v steps within a 2.2v - 16.0v low ripple output voltage during light loads (xc9102) (2.5% accuracy) range (internal). further, a type which has a 0.9v ceramic capacitor compatible internal reference voltage and which allows output voltage to be set-up freely via the external components is also available (fb type). switching frequencies can be regulated externally within a range of 100 ~600 khz and therefore frequencies suited to your particular application are selectable. the xc9102 series switches from pwm to current limited pfm control during light loads and the series offers low ripple and high efficiencies from light loads through to large output currents. further, the drive transistor's current limit can be applied via the current sense function and soft-start times can be regulated by the external resistors and capacitors. during shutdown (ce pin =l), consumption current can be reduced to as little as 0.5 a or less. ? pin configuration ? pin assignment 1 pwm controlled, pwm//pfm switchable step-up dc/dc converters pin number pin name 5 8 clk v ss xc9101/02 series sep. 06, 01 ver. iii 3 v in pin number pin name 1 ext cc / gain 4 ce / ss function driver current sense power input ce/soft start 2 isen function clock input phase compensation voltage sense ground 6 v out / fb 7 ext isen v in ce/ss v ss v out cc/gain clk 4 8 7 2 3 1 5 6 0.65 3.0 typ 4.9 typ 3.0 typ height:1.02 typ (units:mm)
? ordering information the standard output voltage of xc9101c series are 2.5v, 3.3v, and 5.0v. the voltage other than listed are semi-custom. ? typical application xc9101c/9102c : output voltage internally set-up xc9101d/9102d : output voltage adjustable externally (fb) ? absolute maximum ratings 2 pwm controlled, pwm//pfm switchable step-up dc/dc converters xc9101/02 series c m v out xc9101 mnopqr soft-start externally set-up d output voltage : for the voltage above 10v, see the example 10=a, 11=b, 12=c, 13=d, 14=e, 15=f, 16=g e.g. vout=2.3v b=2, c=3 vout=13.5v b=d, c=5 fb soft-start externally set-up 20 ~ g0 09 embossed tape. reverse feed fb products adjustable frequency msop-8a embossed tape. standard feed a k r l no p q r ext pin voltage clk pin voltage cc/gain pin voltage vout/fb pin voltage vin pin voltage isen pin voltage ce/ss pin voltage tstg parameter symbol operating ambient temperature ext pin current storate temperature vext visen vin continuous total power dissipation vce -0.3~+22 -0.3~+22 pd 150 iext topr vclk vcc vout -40~+85 -40~+125 ratings -0.3~+22 -0.3~+22 -0.3~+22 100 -0.3~+22 -0.3~+22 v units v v v ta=25 o c ma mw o c o c v v v
? electrical characteristics xc9101c25akr v out =2.5v, fosc=300khz, ta=25 o c vin = 2.0v unless specified *1 : effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2 : soft-start time measuring ce : 0v 3.0v 3 pwm controlled, pwm//pfm switchable step-up dc/dc converters 0.9 frequency input stability frequency temperature fluctuation vin=2.0v~16v v in =2.0v 5 10 xc9101/02 series supply current 1 supply current 2 stand-by current parameter output voltage maximum operating voltage minimum operating voltage ce "low" voltage ext "high" on resistance ext "low" on resistance clk oscillation frequency maximum duty cycle current limiter sense voltage current limiter pfm current limiter maximum duty cycle efficiency soft-start time cc/gain pin output impedance symbol v out v in max v st1 i dd 1 i dd 2 ce "high" voltage i stb f osc ? f osc ? v in ? f osc ? f osc ? t opr ? f osc maxdty ipfm clim v ceh v cel rexth rextl effi tss r ccgain circuits units max. typ. min. conditions i out =300ma 2.438 2.500 2.562 v x 20 2.0 v v a y v out = set output voltage 0.95, ce =v in 130 v out = set output voltage + 0.5, ce=v in 20 khz z v in =20v, ce=v ss 0.3 rt=3.0k ? , ct=270pf 300 a y a y % z % / v z 83 average sense current (xc9102) % \ v out =v ss (max.duty of pwm) 400 operation switches to pwm when exceeding this value. mv ] \ ma % \ rsen : resistance voltage 1 150 \ existance of clk oscillation dissapearance of clk oscillation v \ v ext=v in - 0.5v, v out = v ss ? vin=2.0v, *1 16 85 16 ext=0.5v, v out =set voltage x 1.05 [ ? [ ms ` % x k ? ^ 500 5 ce/ss 240k ? , 0.0047pf connected *2 ipfmdty max.duty of pfm 83
? electrical characteristics xc9101c33akr v out =3.3v, fosc=300khz, ta=25 o c vin = 2.0v unless specified *1 : effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2 : soft-start time measuring ce : 0v 3.0v 4 ms ` cc/gain pin output impedance r ccgain k ? ^ 5 500 pwm controlled, pwm//pfm switchable step-up dc/dc converters 85 soft-start time tss ce/ss 240k ? , 0.0047pf connected *2 % x efficiency effi vin=2.0v, *1 16 ? [ ext "low" on resistance rextl ext=0.5v, v out =set voltage x 1.05 16 ? [ ext "high" on resistance rexth ext=v in - 0.5v, v out = v ss 0.9 v \ ce "low" voltage v cel dissapearance of clk oscillation 1v \ ce "high" voltage v ceh existance of clk oscillation 150 mv ] current limiter sense voltage clim rsen : resistance voltage 83 % \ current limiter maximum duty cycle ipfmdty max.duty of pfm 400 ma \ exceeding this value. current limiter pfm ipfm operation switches to pwm when average sense current (xc9102) maximum duty cycle v out =v ss (max.duty of pwm) 10 83 ? f osc frequency temperature fluctuation z \ ? t opr ? f osc maxdty v in =2.0v % z % frequency input stability vin=2.0v~16v 5 khz ? f osc % / v ? v in ? f osc z clk oscillation frequency f osc rt=3.0k ? , ct=270pf 300 0.3 a y stand-by current i stb v in =20v, ce=v ss 20 a y supply current 2 i dd 2v out = set output voltage + 0.5, ce=v in 130 a y supply current 1 i dd 1 v out = set output voltage 0.95, ce =v in 2.0 v minimum operating voltage v st1 v maximum operating voltage v in max 20 circuits output voltage v out i out =300ma 3.218 3.300 3.383 v x min. typ. max. units parameter symbol conditions xc9101/02 series
? electrical characteristics xc9101c50akr v out =5.0v, fosc=300khz, ta=25 o c vin = 2.0v unless specified *1 : effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2 : soft-start time measuring ce : 0v 3.0v 5 ms 500 ` cc/gain pin output impedance r ccgain k ? ^ soft-start time tss ce/ss 240k ? , 0.0047pf connected *2 83 5 85 16 16 0.9 1 % pwm controlled, pwm//pfm switchable step-up dc/dc converters 10 % z \ % x efficiency effi vin=2.0v, *1 ? [ ext "low" on resistance rextl ext=0.5v, v out =set voltage x 1.05 ? [ ext "high" on resistance rexth ext=v in - 0.5v, v out = v ss v \ ce "low" voltage v cel dissapearance of clk oscillation v \ ce "high" voltage v ceh existance of clk oscillation 150 mv ] current limiter sense voltage clim rsen : resistance voltage 83 % \ current limiter maximum duty cycle ipfmdty max.duty of pfm 400 ma \ exceeding this value. current limiter pfm ipfm operation switches to pwm when average sense current (xc9102) maximum duty cycle v out =v ss (max.duty of pwm) 5 ? f osc frequency input stability ? t opr ? f osc maxdty frequency temperature fluctuation v in =2.0v % / v z ? v in ? f osc vin=2.0v~16v ? f osc 300 khz z clk oscillation frequency f osc rt=3.0k ? , ct=270pf 0.3 a y stand-by current i stb v in =20v, ce=v ss 20 a y supply current 2 i dd 2v out = set output voltage + 0.5, ce=v in 130 a y supply current 1 i dd 1 v out = set output voltage 0.95, ce =v in 2.0 v minimum operating voltage v st1 v maximum operating voltage v in max 20 circuits output voltage v out i out =300ma 4.875 5.000 5.125 v x min. typ. max. units parameter symbol conditions xc9101/02 series
? electrical characteristics xc9101d09akr v out =2.7v, fosc=300khz, ta=25 o c vin = 2.0v unless specified *1 : effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2 : soft-start time measuring ce : 0v 3.0v 6 5 500 soft-start time tss ce/ss 240k ? , 0.0047pf connected *2 85 % _ efficiency effi vin=2.0v, *1 16 ? [ ext "low" on resistance rextl ext=0.5v, v out =set voltage x 1.05 16 ? [ ext "high" on resistance rexth ext=v in - 0.5v, v out = v ss 0.9 v \ ce "low" voltage v cel dissapearance of clk oscillation 1v \ ce "high" voltage v ceh existance of clk oscillation 150 mv ] current limiter sense voltage clim rsen : resistance voltage 83 % \ current limiter maximum duty cycle ipfmdty max.duty of pfm 400 ma \ average sense current (xc9102) current limiter pfm ipfm operation switches to pwm when exceeding this value. 83 % \ maxdty maximum duty cycle v out =v ss (max.duty of pwm) 10 % z ? f osc frequency temperature fluctuation v in =2.0v ? t opr ? f osc 5 % / v z ? f osc frequency input stability vin=2.0v~20v ? v in ? f osc 300 khz z clk oscillation frequency f osc rt=3.0k ? , ct=270pf 0.3 a y stand-by current i stb v in =20v, ce=v ss 20 a y supply current 2 i dd 2v out = set output voltage + 0.5, ce=v in 130 a y supply current 1 i dd 1 v out = set output voltage 0.95, ce =v in 2.0 v minimum operating voltage v st1 v maximum operating voltage v in max 20 circuits fb voltage v out i out =300ma 0.878 0.900 0.923 v _ xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters parameter symbol conditions min. typ. max. units cc/gain pin output impedance r ccgain ms a k ? ^
? test circuits fig. x fig. y fig. z fig. [ fig. \ fig. ] fig. ^ fig. _ fig. ` fig. a 7 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 300pf v 0.047uf 10k ? clk 5 1 ext 2 isen 3 vin 4 ce/ss vout 7 gain 6 vss 8 470pf 22uf rl 100m ? nmos 0.1uf 240k ? 47 h sd v 10k ? 300pf clk 5 1 ext 2 isen 3 vin 4 ce/ss vout/fb7 gain 6 vss 8 0.1uf 10k ? 300pf 0.1uf clk 5 1 ext 2 isen 3 vin 4 ce/ss vout/fb7 gain 6 vss 8 a l h v 10k ? 300pf clk 5 1 ext 2 isen 3 vin 4 ce/ss vout/fb7 gain 6 vss 8 0.1uf a v 10k ? 300pf clk 5 1 ext 2 isen 3 vin 4 ce/ss vout/fb7 gain 6 vss 8 0.1uf v 10k ? 300pf clk 5 1 ext 2 isen 3 vin 4 ce/ss vout 7 gain 6 vss 8 0.1uf v v 300pf 470pf 0.047uf 10k ? clk 5 1 ext 2 isen 3 vin 4 ce/ss vout 7 gain 6 vss 8 22uf rl 100m ? nmos 0.1uf 240k ? sd 47uh v 0.047uf 300pf 470pf 22uf 10k ? clk 5 2 isen 4 ce/ss fb 7 gain 6 vss 8 100m ? nmos 240k ? r2 1 ext 3 vin rl 1000pf 0.1uf r1 47uh sd 300pf v 0.047uf 10k ? clk 5 1 ext 2 isen 3 vin 4 ce/ss fb 7 gain 6 vss 8 470pf 22uf rl 100m ? nmos 1000pf 220uf 240k ? r1 r2 sd 47uh a 10k ? 300pf clk 5 4 ce/ss vout/fb7 gain 6 1 ext 2 isen 3 vin vss 8 0.1uf
? block dia g ram ? operation description 8 the verr amplifier is designed to monitor the output voltage. a fraction of the voltage applied to internal resistors (r1, r2) in the case of a type c controller, and the voltage of the fb pin in the case of a type d controller are fed back and compared with the reference voltage. in response to feedback of a voltage lower than the reference voltage, the output voltage of the verr amplifier increases. the output of the verr amplifier goes directly to the pfm/pwm switch logic and is also led to the mixer via a resistor (rverr). the former signal acts as a voltage sensor in pfm mode. the latter signal works as a pulse width control signal in pwm mode. connecting an external capacitor and resistor makes it possible to set the gain and frequency characteristics of verr amplifier signals (see the section "functional settings" for constants). the ierr amplifier monitors the coil current. the potential difference between the v in and isen pins are sampled each time of switching operation. then the potential difference is amplified or held, as necessary, and input to the mixer. the ierr amplifier outputs a signal ensuring that the greater the potential difference between the v in and isen pins, the smaller the switching current. the gain and frequency characteristics of this amplifier are fixed internally. step-up dc/dc converter controllers of the xc9101/9102 series carry out pulse width modulation (pwm) according to the multiple feedback signals of the output voltage and coil current. the xc9102 series achieves high efficiency within a wide load range, shifting to pulse frequency modulation (pfm) under a light load condition. the internal circuits consist of different blocks that operate at v in or the stabilized power (1.8 v) of the internal regulator. the output setting voltage of type c controller and the fb pin voltage (vref = 0.9 v) of type d controller have been adjusted and set by laser-trimming. with regard to clock pulses, a capacitor and resistor connected to the clk pin generate sawtooth waveforms whose top and bottom are 0.7 v and 0.15 v, respectively. the frequency can be set within a range of 100 to 600 khz by external constants (see the section "functional settings" for constants). the clock pulses are processed to generate a signal used for synchronizing internal sequence circuits. xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters ext isen v in ce/ss v ss v out /fb cc/gain clk + - + - sawtooth wave, internal clk generator chip enable, soft start up ext timing control logic + - + - verr + - pwm + - ierr + - internal voltage regulator current limit protection pfm/pwm switch logic pfm/pwm comp. limitter comp. 1.8v to internal circuit vref generator ce,uvlo to internal circuit 0.9v sampling r1 r2 rverr mix
9 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters the mixer modulates the signal sent from verr by the signal from ierr. the modulated signal enters the pwm comparator for comparison with the sawtooth pulses generated at the clk pin. if the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn on the external switch. the current flowing through the coil is monitored by the limiter comparator via the v in and isen pins. the limiter comparator outputs a signal when the potential difference between the vin and isen pins reaches 150 mv or more. this signal is converted to a logic signal and handled as a dff reset signal for the internal limiter circuit. when a reset signal is input, a signal is output immediately at the ext pin to turn off the mos switch. when the limiter comparator sends a signal to enable data acceptance, a signal to turn on the mos switch is output at the next clock pulse. if at this time the potential difference between the v in and isen pins is great, operation is repeated to turn off the mos switch again. dff operates in synchronization with the clock signal of the clk pin. the soft start function is made available by attaching a capacitor and resistor to the ce/ss pin. the vref voltage applied to the verr amplifier is restricted by the start-up voltage of the ce/ss pin. doing so ensures that the verr amplifier operates with its two inputs in balance, thereby preventing the on-time signal from becoming stronger than necessary. consequently, soft start time needs to be set sufficiently longer than the time set to clk. the start-up time of the ce/ss pin equals the time set for soft start (see the section "functional settings" for constants). the controllers of the xc9102 series switch between pfm and pwm modes automatically. the pfm/pwm comparator monitors the current each time switching occurs. when the current decreases to a certain value or below, a shift from pwm to pfm mode occurs. to be specific, current-limiting pfm is carried out in the pfm mode. when v out (or the fb voltage in the case of type d) decreases below the set value, the verr amplifier sends a signal directly to the logic block to turn on the external mos switch. an on signal is output from the ext pin in synchronization with the clock signal of the clk pin. when the external mos switch is turned on, a current flows through the coil at the same time. the external mos switch is turned off by a current-limit signal of the limiter comparator (set to a different level than the limiter voltage in pwm mode), the leading edge of the next clock signal, or an increase in the output voltage. the logic is programmed for the pfm mode so that a signal is generated in synchronization with the leading edge of the clock signal at clk to turn off the external switch for a fixed period. the controller stops required operation if the output voltage exceeds the set value after a single cycle of switching operation and waits for another drop in the output voltage. if the set value is not exceeded, pulses are output successively. since the current flowing through the coil is limited by the limiter comparator, output voltage ripple is held below a certain value. if the pfm/pwm comparator indicates pwm mode constantly as a result of frequent occurrence of successive pulses, the controller operates in pwm mode continuously. as the pwm mode is active constantly behind the pfm mode, shifting between modes occurs smoothly. clock pulses at the clk pin do not stop even in pfm mode. d clk q /reset pwm/pfm switching signal clk sync signal output signal to ext pin limiter signal pwm/pfm switching signal
? functional settin g s 1. soft start example: set the soft start time to a value sufficiently longer than the period of a clock pulse. > circuit example 1: nch open drain > circuit example 2: cmos logic (low current dissipation) > circuit example 3: cmos logic (low current dissipation), quick off 10 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters ce and soft start (ss) functions are commonly assigned to the ce/ss pin. the soft start function is effective until the voltage at the ce pin reaches approximately 1.55 v rising from 0 v. soft start time is approximated by the equation below according to values of vcont, rss, and css. t = -css x rss x ln((vcont - 1.55)/vcont) when css = 0.1 f, rss = 470 k ? , and vcont = 5 v, t = -0.1 e -6 x 470 e 3 x ln ((5 - 1.55)/5) = 17.44 ms. ce/ss pin [inside ic, xc9101/02] vcont rss css ce, uvlo vref circuit to verr amplifier [inside ic, xc9101/02] ce/ss pin on/off signal rss css vcont on/off signal ce/ss pin [inside ic, xc9101/02] rss css vcont on/off signal ce/ss pin [inside ic, xc9101/02] rss css vcont
2. oscillation frequency example: when cclk = 330 pf and rclk = 5 k ? , f = 1/(-330e - 12 x 5e 3 x ln(0.2)) = 376.56 khz. 3. gain and frequency characteristics of the verr amplifier 4. current limiting example: when rsen = 100 m ? , ilimit = 0.15/0.1 = 1.5 a 11 the gain at output and frequency characteristics of the verr amplifier are adjusted by the values of capacitor and resistor attached to the cc/gain pin. it is generally recommended to attach a cc of 220 to 1,000 pf without an rgain. the greater the cc value, the more stable the phase and the slower the transient response. the current limiting value is approximated by the following equation according to resistor rsen inserted between the v in and isen pins. double function, current fb input and current limiting, is assigned to the isen pin. ilimit = 0.15/rsen the oscillation frequency of the internal clock generator is approximated by the following equation according to the values of capacitor and resistor attached to the clk pin. f = 1/(-cclk x rclk x ln0.2) xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters clk pin [inside ic, xc9101/02] rclk cclk clk generater [inside ic, xc9101/02] isen pin rsen + - v in pin limiter signal comparator with 150-mv offset cc/gain pin [inside ic, xc9101/02] rgain cc vout/fb + - vref verr rverr
5. fb voltage and cfb example: 12 cfb = 1/(2 x x rfb1 x f z fb) when rfb1 = 455 k ? and rfb2 = 100 k ? , v out = 0.9 x (455 k + 100 k)/100 k = 4.995 v and cfb = 1/ ( 2 x x 455 k x 10 k ) = 34.98 p f. with regard to the xc9101d series, the output voltage is set by attaching externally dividing resistors. the output voltage is determined by the equation shown below according to the values of rfb1 and rfb2. in general, the sum of rfb1 and rfb2 should be 1 meg ? or less. v out = 0.9 x (rfb1 + rfb2)/rfb2 the value of cfb (phase compensation capacitor) is approximated by the following equation according to the values of rfb1 and fzfb. the value of fzfb should be 10 khz, as a general rule. xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters fb pin [inside ic, xc9101/02] rfb1 + - rfb2 verr amplifier 0.9 v cfb output voltage verr
? t yp ical a pp lication circuits xc9101c33akr pmos : xp161a1355pr (torex) coil : 22 h (cdrh127 sumida) resistor : 100m ? for isen (npr1 kowa), 20k ? (trimmer) for clk, 240k ? for ss capacitors : 270pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.047 f (any) for ss, 1 f (ceramic) for bypass 47 f (os) or 10 f (ceramic) 2 for cl sd : u3fwj44n (toshiba) xc9101c50akr pmos : xp161a1355pr (torex) coil : 22 h (cdrh127 sumida) resistor : 100m ? for isen (npr1 kowa), 20k ? (trimmer) for clk, 240k ? for ss capacitors : 270pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.047 f (any) for ss, 1 f (ceramic) for bypass 47 f (os) or 10 f (ceramic) 2 for cl sd : u3fwj44n (toshiba) 13 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 47 f(os) or 10 f(ceramic)2 clk 5 1 ext 2 isen 3 v in 4 ce/ss v ss 8 v out 7 cc/gain 6 ~20k ? 270pf 2.0v 470pf 100m ? nmos 22 h 240k ? 0.047 f 1 f sd 3.3v ~1.5a 220 f 22 h sd clk 5 1 ext 2 isen 3 v in 4 ce/ss v ss 8 v out 7 cc/gain 6 ~20k ? 270pf 2.0v 47 f(os) or 10 f(ceramic)2 470pf 100m ? nmos 240k ? 220 f 1 f 5.0v ~1.5a 0.047 f
xc9101d09akr pmos : xp161a1355pr (torex) coil : 22 h (cdrh127 sumida) resistors : 100m ? for isen (npr1 kowa), 20k ? (trimmer) for clk, 240k ? for ss, 330k ? for output voltage, 100k ? (trimmer) for output voltage capacitors : 330pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.047 f (any) for ss, 1 f (ceramic) for bypass 47pf (ceramic) for fb, 47 f (os) or 10mf (ceramic) 2 for cl sd : u3fwj44n (toshiba) xc9101d09akr pmos : xp161a1355pr (torex) coil : 22 h (cdrh127 sumida) resistors : 50m ? for isen (npr1 kowa), 20k ? (trimmer) for clk, 240k ? for ss, 330k ? for output voltage, 100k ? (trimmer) for output voltage capacitors : 330pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.047 f (any) for ss, 1 f (ceramic) for bypass 47pf (ceramic) for fb, 47 f (os) or 10 f (ceramic) 2 for cl sd : u3fwj44n (toshiba) 14 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters clk 5 1 ext 2 isen 3 v in 4 ce/ss v ss 8 fb 7 cc/gain 6 ~20k ? 330pf 2.0v 47 f(os) or 10 f(ceramic)2 470pf 100m ? nmos 22 h 240k ? 0.047 f 1 f sd ~100k ? 330k ? 47pf 2.7v ~1.5a 220 f clk 5 1 ext 2 isen 3 v in 4 ce/ss v ss 8 fb 7 cc/gain 6 ~20k ? 330pf 2.0v 47 f(os) or 10 f(ceramic)2 470pf 50m ? nmos 22 h 240k ? 0.047 f 1 f sd ~100k ? 330k ? 47pf 2.7v ~2a 220 f
? notes on use 1. 2. 3. ? n. b. 15 ensure that the absolute maximum ratings of external components and the xc9101/9102 series are not exceeded. the characteristics of a dc/dc converter depend largely on external components as well as on the characteristics of the xc9101/9102 series. refer to the specifications of each component and take sufficient care when selecting com p onents. place external components in the proximity of the ic. use thick and short connecting wires to reduce wiring impedance. in particular, minimize the distance between the bypass capacitor and the ic. wire the ic to ground sufficiently. variations in ground potential caused by ground current at the time of switching may result in unstable operation of the ic. specifically, provide sufficient ground wiring in the proximity of the vss p in. the xc9101/9102 series are designed for use with a ceramic capacitor as output capacitor. if, however, the potential difference between input and output is too large, a ceramic capacitor may fail to absorb the resulting high switching energy. then the output may present unusual oscillations. if the input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance. the ext pin of an ic of the xc9101/9102 series is designed to minimize the through current that occurs in the internal circuitry. however, the gate drive of external pmos has a low impedance for the sake of speed. therefore, if the input voltage is high and the bypass capacitor is attached away from the ic, the charge/discharge current to the external pmos may cause unstable operation due to switching operation of the ext pin. as a solution to this problem, place the bypass capacitor as close to the ic as possible, so that voltage variations at the v in and vss pins caused by switching are minimized. if this is not effective, insert a resistor of several to several tens of ohms between the ext pin and pmos gate. remember that the insertion of a resistor slows down the switching speed and may result in reduced efficiency. a pnp transistor can be used in place of pmos. in this case, insert a resistor (rb) and capacitor (cb) between the ext pin and the base of the pnp transistor in order to limit the base current without slowing the switching speed. adjust rb in a range of 500 ? to 1 k ? according to the load and hfe of the transistor. use a ceramic capacitor as cb, complying with cb < 1/(2 x x rb x fosc x 0.7), as a rule. xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters ext pin [inside ic, xc9101/02] rb cb v in
? xc9101c33a 180khz (1) output voltage vs. output current topr = 25 o c (2) efficiency vs. output current topr = 25 o c (3) ripple voltage vs. output current topr = 25 o c tr: xp161a1355pr (torex) rsen: 0.1 ? sd: u3fwj44n (toshiba) cdd: 1 f (ceramic capacitor) cin: 220 f (aluminium electrolyic capacitor) cc/gain: 330pf (ceramic capacitor) cl: 10 f 4 (ceramic capacitor) clk: 220pf+20k ? (ceramic capacitor + resistor) l: 22 h (sumida: cdrh127) ce/ss: 0.047 f+240k ? (ceramic capacitor + resistor) 16 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 3.0 3.1 3.2 3.3 3.4 3.5 3.6 1 10 100 1000 output current: i out (ma) output voltage: v out (v) vin=2.5v, 3.0v 40 60 80 100 1 10 100 1000 output current: i out (ma) efficiency: effi (%) vin=2.5v 3.0v 0 50 100 150 200 250 300 1 10 100 1000 output current: i out (ma) ripple: vr (mvp-p) vin=2.5v 3.3v
? xc9101c33a 330khz (1) output voltage vs. output current topr = 25 o c (2) efficiency vs. output current topr = 25 o c (3) ripple voltage vs. output current topr = 25 o c tr: xp161a1355pr (torex) rsen: 0.1 ? sd: u3fwj44n (toshiba) cdd: 1 f (ceramic capacitor) cin: 220 f (aluminium electrolyic capacitor) cc/gain: 330pf (ceramic capacitor) cl: 10 f 4 (ceramic capacitor) clk: 220pf+10k ? (ceramic capacitor + resistor) l: 10 h (sumida: cdrh127) ce/ss: 0.047 f+240k ? (ceramic capacitor + resistor) 17 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 3.0 3.1 3.2 3.3 3.4 3.5 3.6 1 10 100 1000 output current: i out (ma) output voltage: v out (v) vin=2.5v, 3.0v 40 60 80 100 1 10 100 1000 output current: i out (ma) efficiency: effi (%) vin=2.5v 3.0v 0 50 100 150 200 250 300 1 10 100 1000 output current iout (ma) ripple vr: (mvp-p) vin=2.5v 3.0v
? xc9101c50a 180khz (1) output voltage vs. output current topr = 25 o c (2) efficiency vs. output current topr = 25 o c (3) ripple voltage vs. output current topr = 25 o c tr: xp161a1355pr (torex) rsen: 0.1 ? sd: u3fwj44n (toshiba) cdd: 1 f (ceramic capacitor) cin: 220 f (aluminium electrolyic capacitor) cc/gain: 330pf (ceramic capacitor) cl: 10 f 4 (ceramic capacitor) clk: 220pf+20k ? (ceramic capacitor + resistor) l: 22 h (sumida: cdrh127) ce/ss: 0.047 f+240k ? (ceramic capacitor + resistor) 18 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 4.7 4.8 4.9 5.0 5.1 5.2 5.3 1 10 100 1000 output current: i out (ma) output voltage: v out (v) vin=2.5v, 3.0v, 4.2v 40 60 80 100 1 10 100 1000 output current: iout (ma) efficiency: effi (%) vin=2.5v 4.2v 3.3v 0 50 100 150 200 250 300 1 10 100 1000 output current iout (ma) ripple:vr(mvp-p) vin=2.5v 3.3v 4.2v
? xc9101c50a 330khz (1) output voltage vs. output current topr = 25 o c (2) efficiency vs. output current topr = 25 o c (3) ripple voltage vs. output current topr = 25 o c tr: xp161a1355pr (torex) rsen: 0.1 ? sd: u3fwj44n (toshiba) cdd: 1 f (ceramic capacitor) cin: 220 f (aluminium electrolyic capacitor) cc/gain: 330pf (ceramic capacitor) cl: 10 f 4 (ceramic capacitor) clk: 220pf+10k ? (ceramic capacitor + resistor) l: 10 h (sumida: cdrh127) ce/ss: 0.047 f+240k ? (ceramic capacitor + resistor) 19 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 4.7 4.8 4.9 5.0 5.1 5.2 5.3 1 10 100 1000 output current: i out (ma) output voltage: v out (v) vin=2.5v, 3.0v, 4.2v 40 60 80 100 1 10 100 1000 output current: iout (ma) efficiency: effi (%) vin=2.5v 4.2v 3.3v 0 50 100 150 200 250 300 1 10 100 1000 output current iout (ma) ripple: vr (mvp-p) vin=2.5v 3.3v 4.2v
? packaging information (dimensions : mm) msop-8a : 1,000pcs. / reel 20 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 3. 00 0. 10 4. 90 0. 10 3. 00 0. 10 0. 53 0. 13 0 0. 00 0. 20 0. 30 +0. 08 -0.02 1. 02 0. 86 +0. 11 -0.10 +0. 20 -0.21 0. 15 +0. 08 -0.02 (0.65) + + + ~ ~ 6 o +
? recommended pattern layout (dimensions : mm) 21 xc9101/02 series pwm controlled, pwm//pfm switchable step-up dc/dc converters 0. 85 4. 45 0. 65 0. 325 3 3

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