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ccu 3000, ccu 3000-i, ccu 3001, ccu 3001-i, central control unit edition feb. 14, 1995 6251-367-1ds micronas intermetall micronas
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 2 contents page section title 4 1. introduction 4 1.1. features of the ccu 3000, ccu 3000-i, ccu 3001, ccu 3001-i 5 2. functional description 5 2.1. rom 5 2.2. ram 5 2.3. cpu 5 2.4. clock generator 5 2.5. port 1 to port 3, port 6 to port 8 5 2.6. port 4 5 2.7. i/o-lines p50 to p55 6 2.8. special mode of port 7 7 2.8.1. power-down control external memory (special mode p77) 7 2.8.2. r /w output (special mode p76) 7 2.8.3. banking address (special mode p70 to p75) 8 2.9. reset function 8 2.10. control register 10 2.11. interrupt controller 12 2.12. im bus interface 14 2.13. multifunctional timer 19 2.14. watchdog 21 2.15. ir-input 21 2.16. mask options 22 3. definitions 22 3.1. interrupt definitions 22 3.2. memory mappings 22 3.3. i/o definitions 23 4. specifications 23 4.1. outline dimensions 24 4.2. pin configuration 25 4.3. pin connections and short descriptions 28 4.4. pin descriptions 31 4.5. pin circuits 32 4.6. electrical characteristics 32 4.6.1. absolute maximum ratings 32 4.6.2. recommended operating conditions 32 4.6.3. recommended crystal characteristics 33 4.6.4. dc characteristics 34 4.6.5. using external devices 34 4.6.6. ac characteristics 36 4.6.7. im bus waveforms 36 4.6.8. description of the im bus 37 4.6.9. recommended operating conditions of im bus 38 4.6.10. registers 59 5. index 61 6. addendum: ccu 3000, ccu 3000-i emu versions 62 7. addendum: ccu 3000 1 m m version
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 3 contents, continued page section title 62 7.1. electrical characteristics 62 7.1.1. absolute maximum ratings 63 7.1.2. recommended operating conditions 63 7.1.3. recommended crystal characteristics 64 7.1.4. dc characteristics 65 7.1.5. ac characteristics 66 8. addendum: ccu 3000-i specification 66 8.1. changes to ccu3000 66 8.2. definitions 66 8.3. interrupt definitions 66 8.4. memory mappings 66 8.5. i/o definitions 67 8.6. i 2 c and im bus interface 71 8.7. pin connections and short descriptions 73 8.7.1. dc parameters i 2 c bus master interface 74 8.8. list of registers that differ from ccu 3000, ccu 3001 76 9. data sheet history
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 4 1. introduction the ccu 3000, ccu 3000-i, ccu 3001, ccu 3001-i are integrated circuits designed in 1.2 m m cmos technology, with the exception of ccu 3000, tc18 and tc19, which is designed in 1 m m cmos technology. the cpu contained on the chips is a functionally unchanged 65c02-core, which means that for program develop- ment, systems can be used which are on the market; in- cluding high level language compilers. the pin numbers mentioned in this data sheet refer to the 68-pin plcc package unless otherwise designated. the ccu 3000-i is described separately in an adden- dum on page 66. 1.1. features of the ccu 3000, ccu 3000-i, ccu 3001, ccu 3001-i ccu 3000 = rom-less version of the ccu 3001 65c02 cpu with max. 8 mhz clock 32 kbyte internal rom (ccu 3001 only) 1344 internal bytes ram with stand-by option 51 i/o lines (ccu 3001) 26 i/o lines (ccu 3000) clock generator with programmable clock frequency 8 level interrupt controller ccu 3000, ccu 3001: 2 multimaster im bus interfaces ccu 3000-i, ccu 3001-i: 1i 2 c/im bus and 1 multimaster im bus interface (see addendum) ir-input for software-decoded ir-systems on-chip power on, stand-by and clock supervision logic on-chip watchdog 3 multifunctional timers supports memory banking (external 2mbytes) power down signal for external memory mask option: emu mode programs can be written in assembler or in aco ccu 3000 tc 18/19: 1.0 m m cmos technology, (see addendum) application software available cpu p6 p5 p8 p7 timer2 timer1 clock timer3 ir watch dog power on logic stand by logic interrupt controller 3 1 16 1 8 3 68 85 1 11 2 rom ram 32 kbyte (3001 only) 1344 bytes fig. 11: ccu 3000, ccu 3001 block diagram a0 to a15 (p20 to p37) d0 to d7 (p10 to p17) r/w /p40 im 1 im 2
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 5 2. functional description 2.1. rom the chip is equipped with 32 kbyte mask-programmable rom. the rom uses up the address space from 8000h to ffffh. this rom can be supplemented or replaced externally. only the ccu 3001 has an internal rom. 2.2. ram the ram area is split into three parts: page 0 (address 0 to ffh) page 1 (address 100h to 1ffh) page 3, 4, 5, 6 (address 300h to 63fh) page 0 offers a particularly fast access to the 65c02 and is therefore very valuable for fast, compact programs. page 1 contains the stack and must therefore also have ram. the remaining ram-memory follows in pages 3, 4, 5, 6, as page 2 is reserved as i/o address space. the ram can be kept in the stand-by mode via stand-by pin. 2.3. cpu the cpu core is fully compatible with the 65c02 micro- processor. however, not all the pins of the 65c02 proc- essor are accessible for the user outside the chip. one switch in the control register allows the cpu to be switched off, so that an external processor can take over its tasks. this external processor can of course also be an in-circuit emulator, which makes near-hardware emulation possible, even though the status and control lines of the internal cpu are not accessible. if an exter- nal processor is used, all hardware blocks of the chip are as accessible to it as if it were the internal cpu. 2.4. clock generator an integrated two-pin oscillator generates the clock for the microcontroller. the frequency created by the oscil- lator can be programmed to be reduced with a divider by the factor 1 ... 255. this enables the user to decrease the current consumption by the controller by reducing the working frequency as well as to increase the access time for the (slower) external memory. this divider con- tains the value 4 after a reset, so that the system can also start with a slow external memory. if the mask-option osc is set (emu version), a switch in the control regis- ter makes it possible to receive the internal clock f 2 at xtal2. in this case the oscillator must be external and the clock must be fed to the pin xtal1. in this way, the user gets a time reference for internal operations in the microcomputer. this is especially important with the in- terrupt controller. the production version of the ccu does not have this function! 2.5. port 1 to port 3, port 6 to port 8 8 ports belong to the system, of which 5 are 8 bits wide, one 6 bit, one 4 bit and one 1 bit wide. all port lines of ports 1 to 3 and 6 to 8 can be used as inputs or outputs independently from each other. one register per port defines the direction. port1 to port3 have push-pull outputs and port6 to port8 have open drain outputs. even a line defined as output can be read, the pin level being important. this property makes it possible for the software to find desired and undesired short circuits. each port reserves a byte for the direction register and the data in the i/o page. if the corresponding bit in the direction register is set to 0, the output mode is switched on. after a reset, all bits of a direction register are set to 1. the falling edge of bit 7 of port 8 generates inter- rupts if the priority of the corresponding interrupt control- ler source (7) is not set to 0. 2.6. port 4 port 4 consists of only one line (lsb, p40). after a re- set, port 4 operates as an input only. as soon as port 4 is written for the first time, it is switched to output mode (push-pull). later read accesses read the actual level at port 4. if bit 3 in the control word is active, p4 is used as an r/w -line. if the internal cpu is active, r/w is an out- put line, otherwise it is an input. but p4 has another, very important function during reset. the level at p4 during reset decides whether the control word is read from the internal rom (fff9h) or from the external memory. it is therefore important that the desired level during re- set is set at p4. an internal pull-down resistor of ap- prox. 100 k w is integrated in the ccu 3001, which ensur- es that the control word is read by the internal rom. the external control word access is obtained via an external pull-up resistor of approx. 5 k w . the ccu 3000 has an internal pull-up resistor at p4 (external rom access). the further mode of operation of the ccu 3000, ccu 3001 depends only on the control word though. please note that this mode is always necessary for the ccu 3000 since this device does not have inter- nal rom! 2.7. i/o-lines p50 to p55 the 6 additional i/o-lines have a two-fold function: input or output line (open drain output) or fully decoded i/o-select lines (push-pull outputs) as a rule these lines can be used as input or output lines. as soon as ports 1 to 4 are used as system bus, they are lost as i/o-channels. however, a total of 48 port lines (24 inputs and outputs each) can be reconstructed without difficulties (1 housing for 8 lines), if the additional 6 i/o- lines of the ccu 3000, ccu 3001 are switched into the port select mode. they then represent the select lines of the original ports 1 to 3. each line can be defined as i/o or port select line separately. in the i/o-page three bytes are needed.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 6 mode 1 bit 5,4,3,2,1,0 switch i/o port select mode 0... i/o line (default) 1... port select direction 2 bit 5,4,3,2,1,0 direction switch for i/o lines 5 ... 0 1... input (default) 0... output data 3 bit 5 i/o 5 or rdport 1 bit 4 i/o 4 or wrport 1 bit 3 i/o 3 or rdport 2 bit 2 i/o 2 or wrport 2 bit 1 i/o 1 or rdport 3 bit 0 i/o 0 or wrport 3 rd port 1...3 wr port 1...3 d0...d7 data valid fig. 21: timing diagram port 1 in port 1 out port 2 in port 2 out port 3 in port 3 out d0...d7 ccu 3000, p55 p54 p53 p52 p51 p50 fig. 22: external reproduction of ports 1 to 3 e.g. `244 e.g. `374 d0...d7 memory oe p76 r /w ccu 3001 2.8. special mode of port 7 each line of port 7 can be switched independently into a special mode. this mode is selected by the mode con- trol register. after reset this register is set to 0 (= port mode). a a1o in this register turns this line into the special mode. as the control signals are all outputs, the direction for those lines must be defined as outputs (reset condi- tion = inputs) special mode of function p77 p76 p75 ...p70 power-down control for ext. memory r /w output 6 bit banking addresses with common home bank logic all special mode signals have push-pull outputs. (port mode: open drain).
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 7 2.8.1. power-down control external memory (special mode p77) in many applications the power consumption of the con- troller should be reduced when the system goes into standby mode. the programmable clock of the ccu al- lows this, but external memories do not automatically re- duce their power consumptions when the access speed is slower. these devices need a separate control signal for power down. special out of p77 delivers such a sig- nal. it is low for the last two xtal cycles before, and 0.5 cycles after the rising edge of the internal phi2 clock. this guarantees a wake-up and address time of 2 cycles and a maximum active time of 2.5 clock cycles for each phi2 period. at higher speeds the p77 special out stays low. fosc internal f 2 p77 2 cycles 2.5 cycles fig. 23: power-down control please note that during and after reset p77 is a port line (= tristate) until the special mode and the direction regis- ter is set by software. a pull-down resistor on the power- down input of the memory is necessary to allow the ccu the access to the control word and the first instructions. 2.8.2. r /w output (special mode p76) this is the negated r/w -line of the cpu. can be used for ce or oe control on memories. with a pull-down re- sistor on this pin it is active during reset. 2.8.3. banking address (special mode p70 to p 75) banking is done in 32 kbyte banks. the first bank (000h to 7fffh) includes the ram, the i/o-page and rom (all other locations) and is used as a home-bank for the banking controller, interrupt routines, common subrou- tines etc. the second half of the address space (8000h to ffffh) is banked. in the special mode of port 70 to 75 the content of the data register is output as long as the address a15=1. a low level of a15 forces all special outs of p70 to p75 to become `0'. the data register can contain the bank ad- dresses 1 to 63. this bank is used for cpu accesses from 8000h to ffffh. low accesses are always done to bank 0, independent of the data of port 7. note: all upper banks must contain the interrupt vectors. bank 0 must have the control word and reset vector. during and after reset p7 is in the tristate-port-mode. to make sure that the control word and the reset vector can be accessed use high impedance pull-down resis- tors on all special-out p7 lines. the control word and the reset vector are then accessed out from bank 0. the init routine (where p7 will be defined as special out) must be in bank 0. ffffh bank 1 2 3 4 5 bank 63 int vectors in all banks 1 to 63 8000h 7ffdh bank 0 0000h ram i/o ram 7ffch 7ff9h 7fffh home bank reset reset control word rom if pull-down resistors are used for all bank address outputs fig. 24: memory map, up to 2 mbyte ccu memory a0 a0 a14 a15 a14 a15 a16 a17 a18 a19 a20 p70 p71 p72 p73 p74 p75 fig. 25: banking with 32 kbyte banks open
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 8 2.9. reset function the internal reset provides a correct basic setup of the complete hardware on the chip. for this the internal con- trol register is loaded during reset. one reserved byte in the rom is accessed by the reset circuit and its content is copied into the control register. the internal voltage supervision resets the ic if the voltage is too low. the re- set pin is also used as output for internal reset sources (watchdog, power-down detector, clock supervisor). in- ternal resistors limit the maximum current. 2.10. control register (address 201h) this is a combination of control switches in an 8-bit reg- ister. during reset it is loaded with the contents of the ad- dress fff9h, but it can also be read and written via soft- ware. the controller starts operation with the setting dictated by reset. the switches have the following func- tions: bit 0 cpu_disable (low active) bit 1 ram_disable (low active) bit 2 rom_disable (low active) bit 3 r/w -mode p4 (low active) bit 4 bus external (low active) bit 5 to 7 set to 1 the setting at the r/w -pin decides whether the control word is read internally or externally. bit 0 to bit 2 are the switches which can disable ram, rom and cpu. for external access a pull-up resistor must be connected to the r/w pin (ccu 3001). bit 4 switches p1, p2 and p3 into the system bus mode. if the internal cpu is active, the direction of the data bus drivers is automatically set correctly, so that no additional decoding is necessary. bit 3 switches p4 into the r/w mode. if no external write ac- cess is necessary, (ext. eprom), p4 can stay in the port mode. osc prescaler reset + control word logic internal voltage detector 300 k x1 x2 22 p 22 p ccu 3000, ccu 3001 v sup f 2 res d 0 ...d 7 a 0 ...a 15 reset supervision clock watchdog reset clkres resin por resout dogbit fig. 26: oscillator and reset c 1 =c 2 =
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 9 fig. 27: power-on sequence 123 456 = startup time oscillator int. reset fff9 control word (without ext. c) normal operation t osc v sup f osc a 0 ...a 15 d 0 ...d 7 t osc res normal operatio n fig. 28: external reset sequence v sup 123 456 fff 9 control word int. reset f osc a 0 ...a 15 d 0 ...d 7 res 2
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 10 2.11. interrupt controller the most important properties of this controller are: 8 sources 8 freely programmable priorities for every source maximum delay of 3 clock cycles vectorized interrupts, i.e., automatically the correct routine is accessed also to be used for external cpu option: disable after interrupt (resettable by software) running service routines are only interrupted if inter- rupts are enabled and a request of higher priority arrives. all others are stored and executed when interrupts of higher priority have been finished. priority 0 means that the corresponding interrupt is disabled. (priorities 1-7 lead to interrupts). one property of the controller is that the cpu is not modified, but vectorization takes place all the same. thus the use of this controller is also possible for external cpus (emulator!). solely the return from a service program differs slightly in software from the methods normally used for the 65c02. the last command before the artio must be a write operation into the return register of the controller. this tells the controller that the service routine has been completed. apart from this return register the controller occupies further 5 bytes. one of these serves as a con- trol byte, the others incorporate the priorities for 8 sources. the controller therefore needs 6 bytes of the i/o-page. the control byte comprises: bit 0 clear_all_requests (low active) bit 1 allow_one_interrupt (low active) bit 2 disable_interrupts (low active) bit 3 disable_after_int (low active) bit 4 reset_controller (low active) all bits reset to 1 (inactive). clear_all_requests clears all interrupt flags at the same time. allow_one_interrupt is used in connection with the disable_after_int (bit 3), to al- low access to the next interrupt. disable_interrupt does not allow any interrupts, the request flags are set however. with the exception of bits 3 and 2 (dis- able_interrupts, disable_after_int) these are all dynamic signals, that is, the write process itself sends an appropriate signal. this has the same impulse length as the 65c02. each of the 4 priority registers con- tains the priorities for 2 interrupt sources. bit 7, 6, 5, 4 priority for sources 8, 6, 4, 2 bit 3, 2, 1, 0 priority for sources 7, 5, 3, 1 to connect an external cpu (emulator) with the control- ler, only two ics of the 74-family are needed. adb db ctrlq f 2 fig. 29: dynamic control signals interrupt bits 0, 1, 4 adb db ctrlq f fig. 210: static control signals interrupt bits 2, 3 2
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 11 fig. 211: interrupt controller prior. dec. return a=b 1of 8 decod. ab clk comp. comp. pop vector table prior. of int. fffa + fffb a0...a15 clear request int.1 int.2 int.3 int.4 int.5 int.6 int.7 int.8 a>b `0` `1` d0...d7 priority latches push to ir circuit ir clr 1 clr 2 clr 3 clr 4 clr 6 clr 7 clr 8 reset clr clr_8 clr_1 en nmi cpu dis clr clr clr source of int. stack b clr 5
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 12 fig. 212: using an external cpu dq a0 ...a15 rom/ram d0 ...d7 d0 d7 a0 a15 xtal1 xtal2 clk f ext. cpu or emul. rdy ir counter 2 in q clr nmi or clr d 2 1 d0 d7 a0 a15 en ccu 3000, ccu 3001 emu version in 2.12. im bus interface the im bus has been improved in its characteristics for the ccu 3000, ccu 3001. in comparison to the inter- face of the ccu 2000 series it differs in: multimaster ability 3 slave registers (8 bit wide) higher speed possible the multimaster ability permits the use of several ccus on the same im bus without impeding each other. spe- cially in add-on systems or systems with need of high computing power and/or i/o requirements, this offers great advantages. if several ccus are admitted in a sys- tem, it must be ascertained that these can communicate with each other. a slave im bus interface has been in- stalled for this purpose. parallel to the lines of the mas- ter, three completely independent receiver registers have been installed. all of these are constantly alert, whether the master itself is active or not. as all ccus have the same im bus addresses for these registers, the contents of these registers (that is, for all ccus that are in the system) will be the same. the handshake amongst these is realized in software, and one register each is reserved for the device address, the request and the data to be transported. the data rate can now be ad- justed per software. it is possible to attain 1 mbit/s, if the bus participants in question are devised to support this rate. also the actual realization of the bus can forbid such a high data rate. the im bus interface needs exter- nal pull-up resistors. in the i/o-page the im bus interface reserves 8 bytes: 3 bytes slave receiving registers (read) 1 byte master address (write) 2 bytes master data register (read/write) 1 byte control register (read/write) read: bit 0 0... im bus master ready 1... im bus master busy bit 1 1 byte received in slave register 1 (may generate interrupt) bit 2 im-bus 1 control and status (may generate interrupt) bit 3 word 3 received (may generate interrupt)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 13 write: bit 0 1... write 8 bit bit 1 1... write 16 bit bit 2 1... read 8 bit bit 3 1... read 16 bit 1 byte data rate (5 bits) = fosc 4 . n only one of the bits 0 to 3 in the control register should be set. if all bits are set to `0`, a reset of the interface is done, thus deleting telegrams still waiting for access to the bus. the im bus addresses for the slave registers are: slave register im bus address 1 02 h 2 03 h 3 04 h fig. 213: im bus interface int int data rate n master interface transmission completed slave register 1 (im bus mode slave slave slave slave 1 2 3 contr. data addr. rate id data clk 3 4 master ready im bus addresses 2, 3 and 4 interface data rate: 4 n . fosc 4 fosc . f im f im ;n = = cpu data bus address 02h) received data (1 byte)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 14 2.13. multifunctional timer the multifunctional timer for the ccu 3000, ccu 3001 has quite an unusual structure. it can serve as: event counter frequency counter pulse-length meter timer rate multiplier pwm asynchronous, serial interface each timer has a reserved pin and an interrupt. the pin is either input or output, depending on its function. used as an output it has a push-pull structure. the timer con- sists of three main parts: start and stop detector internal time reference accumulator and arithmetic unit the start and stop detector controls the internal pulse generator to synchronize counter and meter operations. the timer itself does not consist of a counter circuit, but of an accumulator and an adder. this configuration works as a counter with adjustable step length, as a shift register, as a pwm and as a rate multiplier. change-over of operation modes can easily be effected. each of the multifunctional timer circuits of the ccu is realized as two 8-bit accumulators. in addition, there is a separate adder register for each of them. both the ac- cumulator and the adder may be accessed by the cpu via data bus. the accumulator has a shadow register the cpu may write to and the adder bus register may be read and written to. while the adder register forms one side of the adder, the other side is either the output of the adder or the content of the accu shadow register. with every accu clock pulse either of these bytes is used. if no aloado signal is ac- tive, the adder output is used. with aloado active, the following accu clock pulse uses the content of the accu shadow register as adder input. the aloado signal is derived from 1 out of 4 sources, selectable with bits 3 and 4 of control byte 3. accu clock is selectable with bits 1 and 2 in control byte 2. instead of the content of the ad- der register, accessible by the cpu, a hard-wired `-1' may be used as input of the other side of the adder (bits 1 and 2 in control byte 3). by adding `-1' to the accu's content, the adder works as a standard down counter. with specific aread latcho signals (control byte 2, bits 3, 4 and 5) and using the adder register as adder input, its content defines the step width of the counter. in addition to its parallel byte connections, the adder reg- isters have serial inputs and outputs. a serial clock shifts its contents. to hit the middle of serial data, the timer's prescaler has a half load feature, controlled with bit 1 in control byte 1. fig. 214 shows a detailed diagram of the high part of the reloadable accumulator and its adder register. for examples of timer applications please refer to aapplica- tion note ccu 3000/3001 timerso.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 15 read bus register (adder) low byte write bus register (adder) low byte latch clock 8-bit latch en en en control reg. 3, bit 2 in out out1 d0 ... d7 d0 ... d7 start bit shadow register wr reloadable accumulator set to `0' during load active (ld = 0) ci accu clock ld 8-bit latch reaccu c co1 co ci wr s 1 1 0 8-bit latch 0 1 fig. 214: reloadable accumulator
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 16 apart from the start values for the counter and adder reg- isters, three control registers shift the timer into the preselected function. registers to control the timer: 2 bytes prescaler high and low byte (read/write) (read: prescaler) (write: prescaler and reload register) 2 bytes accu high and low byte (write) (write: accu and reload register) 2 bytes adder register high and low byte (read/write) 3 bytes control register 1 to 3 (write) q fig. 215: prescaler timer, start/stop logic + d edge d start stop 1/2 load clock d0...d7 d0...d7 ci load ci lsb in msb co co reaccu reaccu a b load lsb in msb + pin stop presc. in presc. out fosc f d 2 pin + clr q q clr clr q + + wr wr
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 17 fig. 216: timer d q clr d0...d7 presc. in presc. out pin load d q clr reg + d0...d7 wr ci ld out in co 1 co 2 reaccu c wr cl out in reaccu d d clr q long inter d0...d7 bus register (adder register) accu_ clk pin stop co 1 co 2 int serial clock latch clock in1 in2 out2 12 11 serial in 2 serial mode serial out serial in rd2 wr2 rd1 wr1 startbit generator from control word pinout co pwm so pin presc.in presc. out open co1 co2 startbit co1 co2 startbit out1 rd latch pin pin pin q reset active pin ld reset active set dq the three control registers control the internal switches of the timer: control register 1 bit 7 serial_2 second serial input level bit 6, 5 clock 00.. pin 01.. fosc. 10.. f 2 11.. disable clock bit 4 stop 0... stop disabled 1... carry out accu bit 3, 2 start 00.. always active 01.. edge 10.. pin 11.. pin bit 1 1/2 load 0... disabled 1... active bit 0 edge detector 0... rising 1... falling control register 2 bit 7, 6 pin_out 00.. open 01.. serial out 10.. pwm out 11.. carry accu d bit 5, 4, 3 read_latch 000. open 001. carry accu c 010. carry accu d 011. pin 100. pin 101. prescaler output 110. prescaler input bit 2, 1 accu clock 00.. prescaler input 01.. prescaler output 10.. pin 11.. pin bit 0 long 0... open 1... carry out accu c carry in accu d
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 18 control register 3 bit 7, 6, 5 inter 000. open 001. pin 010 pin 011. carry accu c 100. carry accu d bit 4, 3 load 00.. open 01.. carry accu c 10.. carry accu d 11.. reg bit 2 11 0... accu c input = bus reg. 1... accu c input = 1 bit 1 12 0... accu d input = bus reg. 1... accu d input = 1 bit 0 serial mode 0... mode off 1... mode on
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 19 2.14. watchdog not active after reset activated when written, cannot be stopped via soft- ware to retrigger, the watchdog period negated bit by bit must be rewritten within the preset space of time (first write event is also counted) triggers reset, the software can identify if reset was generated by watchdog 16 ms to 4 s time-out for 4 mhz system clock this counter circuit offers hardware support for software problems. it is disabled after reset and enabled with the first write of the desired time value into its register. the value to program is calculated by n = t wd * f system / 65536 1 with n = watchdog counter value to be programmed for t wd = the desired watchdog time and f system = system frequency. remarks: a) to prevent the generation of a `reset' by the watch- dog before it could be retriggered by the software, watchdog counter values less than 2 should not be pro- grammed . b) the system clock as input of the watchdog counter is influenced by the system clock prescaler, determining the cpu speed (register addr. 200 h). software can't stop this counter but has to retrigger it by writing the inverted value (one's complement) of the pre- ceding written pattern into its register, which makes un- wanted retrigger loops of disturbed software unlikely. these writes have to occur within the time frame (8 ms to 2 s at 8 mhz system clock), defined with the first write. if no write with the expected pattern occurs within the programmed time period, the watchdog circuit resets the ccu at the end of the time period. there will also be a watchdog reset if another pattern is written instead of the expected one. the software can detect if a reset was generated by the watchdog: bit 0 of the watchdog regis- ter is `0' if the last reset was generated by the watchdog. this bit is reset only with an external reset, e.g. gener- ated by power-on. examples: to set a cycle time of 1 second with 8 mhz system clock the value is 121. this value is calculated as follows: system frequency: 8 mhz watchdog cycle time: 65536 / 8 mhz = 8.192 ms, counter value: 1 s / 8.192 ms = 122.07. the nearest integer value is 122. because a 0 loaded into the counter divides by 1, already, the watchdog counter has to be programmed with 122-1 = 121. with the formula above n = 121 = 1s * 8 mhz/65536 1 the software sequences in assembler could look like this: definitions: ;constants: watchdog_time equ 121 ;ccu i/oaddress: watchdog_address equ 202h ;variable: watchdog_value equ 30h ;(address ; of free ram location) example 1: during initialization the watchdog is filled with the de- sired time-value: lda #watchdog_time sta watchdog_address sta watchdog_value ;memorize ; watchdog pattern in the main loop of the program the watchdog has to be retriggered cyclically: lda watchdog_value eor #ffh ;invert bits sta watchdog_address sta watchdog_value ;memorize new ; watchdog pattern example 2: if an interrupt function occurs cyclically, one value may be programmed in the interrupt service routine, while the other is written in the main loop. so both the continuity of executing the interrupt service and the main loop are checked: during initialization the watchdog shadow variable is filled with the desired time-value: lda #watchdog_time sta watchdog_value ;memorize ; watchdog pattern sequence in the interrupt function: lda watchdog_value cmp #watchdog_time beq skip_irq_wd ; sta watchdog_address eor #$ff sta watchdog_value skip_irq_wd ...
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 20 sequence in the main loop: lda watchdog_value cmp #watchdog_time bne skip_wd ; sta watchdog_address eor #$ff sta watchdog_value skip_wd ... remark: it is important to program the watchdog register with the new value before this value is memorized in the shadow variable, because this procedure could be interrupted by the interrupt, which will program the watchdog with the complementary value. fig. 217: watchdog d d0 = latch = = d0...d7 latch + d f 8bit counter 16bit 2 f 2 clr power down res_dog res_dog_1 en clr clr q r/w swatch reset active swatch r/w q q fig. 218: timing watchdog trigger watchdog is retriggered d0...d7 swatch res_dog_1 f 2 r/w
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 21 2.15. ir-input the ir-interface consists of two parallel edge detectors which trigger the rising and falling edge. the respective state of the rising edge triggered flip-flop can be read from d0 (triggered positively), or d1 (triggered nega- tively). any read event via the cpu deletes both flip- flops. d2 reflects the status of the ir pin, d3 to d7 are set to 0. if the cpu is switched off, the ir-interface is no longer available, as the ir pin is used as output for the interrupt controller. for use as an emulator this function has to be rebuilt externally. the i/o-address designed for the ir- input is treated as an external address when the cpu is switched off, so that the software can remain un- touched. fig. 219: ir input ir clr clr d0 d1 from interrupt controller rd ir cpu dis d2 `1' `0' 2.16. mask options there are two mask options: osc option: if this option is set, x 1 and x 2 can be used as clock input and output or as xtal pins, (depending on control word bit 5) res option: if this option is set, the reset sources power on and clock supervision are disabled with bit 0 of the test register 2ffh. default = enabled). in the production version none of the options is set, in the emu version both are set.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 22 3. definitions 3.1. interrupt definitions interrupt source vector (low, high byte) 0 timer1 fff6, fff7 1 timer2 fff4, fff5 2 timer3 fff2, fff3 3 im-bus1, master fff0, fff1 4 im-bus1, slave ffee, ffef 5 im-bus2, master ffec, ffed 6 im-bus2, slave ffea, ffeb 7 p87 ffe8, ffe9 reset fffc, fffd 3.2. memory mappings ram 0000h to 01ffh page 0, 1 0300h to 063fh page 3, 4, 5, 6 rom 8000h to ffffh (ccu3001 only) control fff9 byte i/o 0200 to 02ff 3.3. i/o definitions address function 200h clock frequency 201h control register 202h watchdog 203h port 1 data 204h direction register port 1 205h port 2 data 206h direction register port 2 207h port 3 data 208h direction register port 3 209h port 4 data 20ah port 5 mode register 20bh port 5 direction register 20ch port 5 data 20dh ir-input 20fh port 7 mode register 210h im-bus 1 control and status 211h im-bus 1 data transfer rate 213h im-bus 1 master address 214h im-bus 1 master data low byte 215h im-bus 1 master data high byte 216h im-bus 1 slave 1, im address 02 218h im-bus 1 slave 2, im-bus address 03 21ah im-bus 1 slave 3, im-bus address 04 21ch interrupt controller control byte 21dh interrupt controller return byte 21eh interrupt controller priorities source 0 & 1 21fh interrupt controller priorities source 2 & 3 220h interrupt controller priorities source 4 & 5 221h interrupt controller priorities source 6 & 7 222h timer 1 control byte 1 223h timer 1 control byte 2 224h timer 1 control byte 3 225h timer 1 prescaler low byte 226h timer 1 prescaler high byte 228h timer 1 accu low byte 229h timer 1 accu high byte 22ah timer 1 adder low byte 22bh timer 1 adder high byte 22ch timer 2 control byte 1 22dh timer 2 control byte 2 22eh timer 2 control byte 3 22fh timer 2 prescaler low byte 230h timer 2 prescaler high byte 232h timer 2 accu low byte 233h timer 2 accu high byte 234h timer 2 adder low byte 235h timer 2 adder high byte 236h timer 3 control byte 1 237h timer 3 control byte 2 238h timer 3 control byte 3 239h timer 3 prescaler low byte 23ah timer 3 prescaler high byte 23ch timer 3 accu low byte 23dh timer 3 accu high byte 23eh timer 3 adder low byte 23fh timer 3 adder high byte 240h port 6 data 241h direction register port 6 242h port 7 data 243h direction register port 7 244h port 8 data 245h direction register port 8 246h im-bus 2 control & status 247h im-bus 2 transfer rate 249h im-bus 2 master address 24ah im-bus 2 master data low 24bh im-bus 2 master data high 24ch im-bus 2 slave 1, im address 02 24eh im-bus 2 slave 2, im address 03 250h im-bus 2 slave 3, im address 04 2e0h external addresses, used for emu boards to 2e7h 2feh reserved, do not use 2ffh reserved for testing purposes
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 23 4. specifications 4.1. outline dimensions 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 2 25 +0.25 43 27 25 +0.25 26 10 9 61 9 44 60 2 1 x 45 0.457 0.2 0.711 1.9 1.5 4.05 0.1 4.75 0.15 1.27 0.1 2.4 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 1 +0.2 2.4 fig. 41: 68-pin plastic leaded chip carrier package (plcc68) weight approximately 4.8 g dimensions in mm fig. 42: pinning of the ccu 3000, ccu 3001 in plcc68 package 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 654321 44 43 42 41 40 68 67 66 65 64 63 62 61 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vsup gnd x2 x1 standby dat_im2 id_im2 clk_im2 timer1 timer2 timer3 ir p10 (d0) p11 (d1) p12 (d2) p13 (d3) p14 (d4) p15 (d5) p16 (d6) p17 (d7) p20 (a0) p21 (a1) p22 (a2) p23 (a3) p24 (a4) p25 (a5) p26 (a6) p27 (a7) p30 (a8) p31 (a9) p32 (a10) p33 (a11) p34 (a12) p35 (a13) p36 (a14) p37 (a15) p50 p51 p52 p53 p54 p55 p70 p71 p72 p73 p74 p75 p76 p77 p80 p81 p82 p83 p87/int p60 p61 p62 p63 p64 p65 p66 p67 res dat _ im1 id_im1 clk_im1 p4 (r/w ) ccu 3000, ccu 3001 v
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 24 57.7 0.1 3.8 0.1 1.29 31 x 1.778 = 55.118 0.1 1 0.05 fig. 43: 64-pin plastic shrink dual inline package (psdip64) 1) weight approximately 9.0 g dimensions in mm 3.2 132 33 64 15 28 4 0.1 0.2 4.8 0.2 0.1 20.1 0.5 0.27 0.1 18 0.1 19.3 0.1 0.457 1.778 0.05 1.9 (1) 58 0.3 4.25 0.15 fig. 44: 64-pin plastic shrink dual inline package (psdip64f) 2) weight approximately 9.0 g dimensions in mm 3.25 132 33 64 0.3 5.2 0.5 20.5 max. 0.25 0.06 17 0.25 19.3 0.1 0.46 0.1 1.778 (0.51 min.) 0.25 m o 1) psdip64 = manufactured in freiburg 2) psdip64f = second source 4.2. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p11 (d1) p10 (d0) p4 (r/ timer3 timer2 timer1 clk_im1 id_im1 dat_im1 res vstand-by x2 gnd vsup p67 p66 p65 p64 p35 (a13) p15 (d5) p20 (a0) p21 (a1) p22 (a2) p24 (a4) p26 (a6) p25 (a5) x1 p34 (a12) p33 (a11) p32 (a10) p30 (a8) p14 (d4) p13 (d3) p23 (a3) ir p31 (a9) p27 (a7) p17 (d7) p16 (d6) p12 (d2) 21 22 23 24 25 26 27 28 29 30 31 32 p62 p61 p87 p82 p81 p80 p77 p76 p75 p74 p60 p63 33 34 35 36 37 38 39 40 41 42 43 44 p51 p54 p55 p70 p72 p73 p50 p37 (a15) p71 p53 p52 p36 (a14) w ) fig. 45: pinning of the ccu 3000, ccu 3001 in psdip64 and psdip64f package
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 25 4.3. pin connections and short descriptions da = im bus data line of external devices id = im bus ident line of external devices cl = im bus clock line of external devices x = obligatory; connections depend on application pin no. con- nection i: input pin name short description 68pin plcc 64pin sdip o: output 1 16 +5v i v sup supply voltage 2 15 gnd i gnd ground 3 14 crystal i/o x2 crystal connector 2 4 13 crystal i x1 crystal connector 1 5 12 +3v to +5v i v stand-by standby supply voltage 6 11 x i/o res reset input/reset output 7 10 da i/o dat_im1 im bus 1 data signal 8 9 id o id_im1 im bus 1 ident signal output 9 8 cl o clk_im1 im bus 1 clock signal output 10 da i/o dat_im2 im bus 2 data signal 11 id o id_im2 im bus 2 ident signal output 12 cl o clk_im2 im bus 2 clock signal output 13 7 x i/o timer1 timer 1 signal 14 6 x i/o timer2 timer 2 signal 15 5 x i/o timer3 timer 3 signal 16 4 external infrared receiver i ir infrared signal input 17 3 x i/o (o) p40 (r/w ) port 4 bit 0 (cpu read/write ) 18 2 x i/o (i/o) p10 (d0) port 1 bit 0 (cpu data bus bit 0) 19 1 x i/o (i/o) p11 (d1) port 1 bit 1 (cpu data bus bit 1) 20 64 x i/o (i/o) p12 (d2) port 1 bit 2 (cpu data bus bit 2) 21 63 x i/o (i/o) p13 (d3) port 1 bit 3 (cpu data bus bit 3) 22 62 x i/o (i/o) p14 (d4) port 1 bit 4 (cpu data bus bit 4) 23 61 x i/o (i/o) p15 (d5) port 1 bit 5 (cpu data bus bit 5)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 26 short description pin name i: input con- nection pin no. o: output con- nection 64pin sdip 68pin plcc 24 60 x i/o (i/o) p16 (d6) port 1 bit 6 (cpu data bus bit 6) 25 59 x i/o (i/o) p17 (d7) port 1 bit 7 (cpu data bus bit 7) 26 58 x i/o (o) p20 (a0) port 2 bit 0 (cpu address bus bit 0) 27 57 x i/o (o) p21 (a1) port 2 bit 1 (cpu address bus bit 1) 28 56 x i/o (o) p22 (a2) port 2 bit 2 (cpu address bus bit 2) 29 55 x i/o (o) p23 (a3) port 2 bit 3 (cpu address bus bit 3) 30 54 x i/o (o) p24 (a4) port 2 bit 4 (cpu address bus bit 4) 31 53 x i/o (o) p25 (a5) port 2 bit 5 (cpu address bus bit 5) 32 52 x i/o (o) p26 (a6) port 2 bit 6 (cpu address bus bit 6) 33 51 x i/o (o) p27 (a7) port 2 bit 7 (cpu address bus bit 7) 34 50 x i/o (o) p30 (a8) port 3 bit 0 (cpu address bus bit 8) 35 49 x i/o (o) p31 (a9) port 3 bit 1 (cpu address bus bit 9) 36 48 x i/o (o) p32 (a10) port 3 bit 2 (cpu address bus bit 10) 37 47 x i/o (o) p33 (a11) port 3 bit 3 (cpu address bus bit 11) 38 46 x i/o (o) p34 (a12) port 3 bit 4 (cpu address bus bit 12) 39 45 x i/o (o) p35 (a13) port 3 bit 5 (cpu address bus bit 13) 40 44 x i/o (o) p36 (a14) port 3 bit 6 (cpu address bus bit 14) 41 43 x i/o (o) p37 (a15) port 3 bit 7 (cpu address bus bit 15) 42 42 x i/o (o) p50 (rd port 1) port 5 bit 0 (ccu read port 1) 43 41 x i/o (o) p51 (wr port 1) port 5 bit 1 (ccu write port 1) 44 40 x i/o (o) p52 (rd port 2) port 5 bit 2 (ccu read port 2) 45 39 x i/o (o) p53 (wr port 2) port 5 bit 3 (ccu write port 2) 46 38 x i/o (o) p54 (rd port 3) port 5 bit 4 (ccu read port 3) 47 37 x i/o (o) p55 (wr port 3) port 5 bit 5 (ccu write port 3) 48 36 x i/o (o) p70 (memory bank address 0) port 7 bit 0 (memory bank address 0) 49 35 x i/o (o) p71 (memory bank address 1) port 7 bit 1 (memory bank address 1) 50 34 x i/o (o) p72 (memory bank address 2) port 7 bit 2 (memory bank address 2) 51 33 x i/o (o) p73 (memory bank address 3) port 7 bit 3 (memory bank address 3)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 27 short description pin name i: input con- nection pin no. o: output con- nection 64pin sdip 68pin plcc 52 32 x i/o (o) p74 (memory bank address 4) port 7 bit 4 (memory bank address 4) 53 31 x i/o (o) p75 (memory bank address 5) port 7 bit 5 (memory bank address 5) 54 30 x i/o (o) p76 (r /w) port 7 bit 6 (cpu read/write) 55 29 x i/o (o) p77 (power-down control) port 7 bit 7 (power-down control) 56 28 x i/o p80 port 8 bit 0 57 27 x i/o p81 port 8 bit 1 58 26 x i/o p82 port 8 bit 2 59 x i/o p83 port 8 bit 3 60 25 x i/o /i p87/int port 8 bit 7 /interrupt input 61 24 x i/o p60 port 6 bit 0 62 23 x i/o p61 port 6 bit 1 63 22 x i/o p62 port 6 bit 2 64 21 x i/o p63 port 6 bit 3 65 20 x i/o p64 port 6 bit 4 66 19 x i/o p65 port 6 bit 5 67 18 x i/o p66 port 6 bit 6 68 17 x i/o p67 port 6 bit 7
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 28 4.4. pin descriptions ccu 3000, ccu 3001 pin descriptions. pin numbers refer to the 68pin plcc housing. the functions of some pins are influenced by bit 4 of the ccu control register (addr. 201h, copied from fff9h at reset: ccu control register bit 4 = `1' switches the ccu in port mode , ccu control register bit 4 = `0' switches the ccu in bus mode . in addition, some port bit functions may be changed be- tween normal mode and special mode by setting the specific bit in its port mode registers. pin 1: v sup : +5v power supply pin 2: gnd: digital ground pin 3: x2: second crystal connector pin 4: x1: first crystal connector pin 5: v standby: +5v standby supply voltage pin 6: res\: ccu reset input / output (open drain) pin 7: dat_im1: im bus 1 data signal (i/o) pin 8: id_im1: im bus 1 ident signal output pin 9: clk_im1: im bus 1 clock signal output pin 10: dat_im2: im bus 2 data signal (i/o) pin 11: id_im2: im bus 2 ident signal output pin 12: clk_im2: im bus 2 clock signal output pin 13: timer1: timer 1 signal (i/o) pin 14: timer2: timer 2 signal (i/o) pin 15: timer3: timer 3 signal (i/o) pin 16: ir: infrared signal input pin 17: p40 or r/w\: in port mode: port 4 bit 0 in bus mode : cpu read/not write output pin 18 : p10 or data bit 0: in port mode: port 1 bit 0 in bus mode : cpu data bit 0 pin 19 : p11 or data bit 1: in port mode: port 1 bit 1 in bus mode : cpu data bit 1 pin 20 : p12 or data bit 2: in port mode: port 1 bit 2 in bus mode : cpu data bit 2 pin 21 : p13 or data bit 3: in port mode: port 1 bit 3 in bus mode : cpu data bit 3 pin 22 : p14 or data bit 4: in port mode: port 1 bit 4 in bus mode : cpu data bit 4 pin 23 : p15 or data bit 5: in port mode: port 1 bit 5 in bus mode : cpu data bit 5 pin 24 : p16 or data bit 6: in port mode: port 1 bit 6 in bus mode : cpu data bit 6 pin 25 : p17 or data bit 7: in port mode: port 1 bit 7 in bus mode : cpu data bit 7 pin 26 : p20 or address bit 0: in port mode: port 2 bit 0 in bus mode : cpu address bit 0 pin 27 : p21 or address bit 1: in port mode: port 2 bit 1 in bus mode : cpu address bit 1 pin 28 : p22 or address bit 2: in port mode: port 2 bit 2 in bus mode : cpu address bit 2 pin 29 : p23 or address bit 3: in port mode: port 2 bit 3 in bus mode : cpu address bit 3 pin 30 : p24 or address bit 4: in port mode: port 2 bit 4 in bus mode : cpu address bit 4 pin 31 : p25 or address bit 5: in port mode: port 2 bit 5 in bus mode : cpu address bit 5 pin 32 : p26 or address bit 6: in port mode: port 2 bit 6 in bus mode : cpu address bit 6 pin 33 : p27 or address bit 7: in port mode: port 2 bit 7 in bus mode : cpu address bit 7 pin 34 : p30 or address bit 8: in port mode: port 3 bit 0 in bus mode : cpu address bit 8 pin 35 : p31 or address bit 9: in port mode: port 3 bit 1 in bus mode : cpu address bit 9
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 29 pin 36 : p32 or address bit 10: in port mode: port 3 bit 2 in bus mode : cpu address bit 10 pin 37 : p33 or address bit 11: in port mode: port 3 bit 3 in bus mode : cpu address bit 11 pin 38 : p34 or address bit 12: in port mode: port 3 bit 4 in bus mode : cpu address bit 12 pin 39 : p35 or address bit 13: in port mode: port 3 bit 5 in bus mode : cpu address bit 13 pin 40 : p36 or address bit 14: in port mode: port 3 bit 6 in bus mode : cpu address bit 14 pin 41 : p37 or address bit 15: in port mode: port 3 bit 7 in bus mode : cpu address bit 15 pin 42 : p50 or rd port1\: in port mode: in normal mode : port 5 bit 0 (open drain output) in special mode : read port 1 (low active) in bus mode : in normal mode : port 5 bit 0 (open drain output) in special mode : read port 1 (low active) pin 43 : p51 or wr port1\: in port mode: in normal mode : port 5 bit 1 (open drain output) in special mode : write port 1 (low active) in bus mode : in normal mode : port 5 bit 1 (open drain output) in special mode : write port 1 (low active) pin 44 : p52 or rd port2\: in port mode: in normal mode : port 5 bit 2 (open drain output) in special mode : read port 2 (low active) in bus mode : in normal mode : port 5 bit 2 (open drain output) in special mode : read port 2 (low active) pin 45 : p53 or wr port2\: in port mode: in normal mode : port 5 bit 3 (open drain output) in special mode : write port 2 (low active) in bus mode : in normal mode : port 5 bit 3 (open drain output) in special mode : write port 2 (low active) pin 46 : p54 or rd port3\: in port mode: in normal mode : port 5 bit 4 (open drain output) in special mode : read port 3 (low active) in bus mode : in normal mode : port 5 bit 4 (open drain output) in special mode : read port 3 (low active) pin 47 : p55 or wr port3\: in port mode: in normal mode : port 5 bit 5 (open drain output) in special mode : write port 3 (low active) in bus mode : in normal mode : port 5 bit 5 (open drain output) in special mode : write port 3 (low active) pin 48 : p70 or memory bank address 0: in port mode: in normal mode : port 7 bit 0 in special mode : memory bank address 0 in bus mode : in normal mode : port 7 bit 0 in special mode : memory bank address 0 pin 49 : p71 or memory bank address 1: in port mode: in normal mode : port 7 bit 1 in special mode : memory bank address 1 in bus mode : in normal mode : port 7 bit 1 in special mode : memory bank address 1 pin 50 : p72 or memory bank address 2: in port mode: in normal mode : port 7 bit 2 in special mode : memory bank address 2 in bus mode : in normal mode : port 7 bit 2 in special mode : memory bank address 2 pin 51 : p73 or memory bank address 3: in port mode: in normal mode : port 7 bit 3 in special mode : memory bank address 3 in bus mode : in normal mode : port 7 bit 3 in special mode : memory bank address 3 pin 52 : p74 or memory bank address 4: in port mode: in normal mode : port 7 bit 4 in special mode : memory bank address 4 in bus mode : in normal mode : port 7 bit 4 in special mode : memory bank address 4
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 30 pin 53 : p75 or memory bank address 5: in port mode: in normal mode : port 7 bit 5 in special mode : memory bank address 5 in bus mode : in normal mode : port 7 bit 5 in special mode : memory bank address 5 pin 54 : p76 or inverted cpu r/w\: in port mode: in normal mode : port 7 bit 6 in special mode : inverted cpu r/w\, i.e.: low active at read in bus mode : in normal mode : port 7 bit 6 in special mode : inverted cpu r/w\, i.e.: low active at read pin 55 : p77 or power-down control: in port mode: in normal mode : port 7 bit 7 in special mode : power-down control external memory (high active) in bus mode : in normal mode : port 7 bit 7 in special mode : power-down control external memory (high active) pin 56 : p80: port 8 bit 0 pin 57 : p81: port 8 bit 1 pin 58 : p82: port 8 bit 2 pin 59 : p83: port 8 bit 3 pin 60 : p87/int: port 8 bit 7 and interrupt input (interrupt controller source 7) pin 61 : p60: port 6 bit 0 pin 62 : p61: port 6 bit 1 pin 63 : p62: port 6 bit 2 pin 64 : p63: port 6 bit 3 pin 65 : p64: port 6 bit 4 pin 66 : p65: port 6 bit 5 pin 67 : p66: port 6 bit 6 pin 68 : p67: port 6 bit 7
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 31 4.5. pin circuits fosc fig. 46: x1, x2 4 3 v sup gnd 6 por, cls, watchdog fig. 47: reset v sup gnd fig. 48: im bus v sup gnd 17 fig. 49: r/w , ccu 3000 v sup gnd fig. 410: p1, p2, p3, timer (1, 2, 3), ir (input only), in special mode: p5, p7, p8 7...12 13...41 in special mode: 42...60 v sup gnd fig. 411: p5, p6, p7, p8 in port mode 42...60 fig. 412: r/w , / p4, ccu 3001 reset v sup gnd 17 reset in port mode
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 32 4.6. electrical characteristics all voltages refer to ground. 4.6.1. absolute maximum ratings symbol parameter pin min. max. unit t a ambient operating temperature 0 65 c t s storage temperature 40 +125 c v sup supply voltage 1 0.5 6 v v i input voltage 4, 6, 16, 13 to 25, 42 to 68 0.3 v v sup +0.3 v p max maximum power dissipation 500 mw the total sum of all the sink currents of all ports together must not exceed 80 ma i outlow and 280 ma i out high at any time. stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. recommended operating conditions at t a = 0 cto 65 c symbol parameter pin min. typ. max. unit v sup supply voltage 1 4.75 5.25 v f clk clock frequency 3, 4 0.5 8 mhz 4.6.3. recommended crystal characteristics at c xtal1 = c xtal2 = 22 pf; c stray 2 pf; c l 13 pf symbol parameter min. typ. max. unit t a ambient operating temperature 20 +85 c f p parallel resonance frequency @ c l = 13 pf 48 mhz r r series resistance 40 [8mhz] 150 [4 mhz] w c 0 shunt capacitance 7.0 pf c 1 motional capacitance 20 ff p rated drive level 0.02 mw f p / f h spurious frequency attenuation 20 db
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 33 4.6.4. dc characteristics at t a = 0 cto 65 c, v sup = 5v, f clk = 8 mhz symbol parameter pin no. min. typ. max. unit comment i sup ccu 3000, ccu 3000-i supply current (no external load) 1 8/16 15/30 ma @ 4/8 mhz i sup ccu 3001 ccu 3001-i supply current (no external load) 1 14/28 20/40 ma @ 4/8 mhz v ilh input low to high trigger level 4,6, 712, 1325, 4268 0.38* v sup 2,05 0.56* v sup v schmitt-trigger inputs v ihl input high to low trigger level 0.2* v sup 1.15 0.29* v sup v schmitt-trigger inputs v ihyst input hysteresis 4,6, 725, 4268 0.1* v sup 0.9 0.27* v sup v schmitt-trigger inputs v boh bus ports and timer output high voltage 1315 1741 2.8 v v bol bus ports and timer output low voltage 0.4 v i boh bus ports and timer output high current 13151 741 2 ma i bol bus ports and timer output low current 5 ma i p5ol p5 output low current 4247 5 ma i p6ol p6 output low current 6168 25 ma i p7ol p7 output low current 4855 5 ma i p8ol p8 output low current 5660 5 ma i ohl output leakage current 4260 1 m a i p5p7oh output high current special mode, p5 to p7 4255 2 ma v p5p7oh output high voltage special mode, p5 to p7 4255 2.8 v v ol output low voltage at i ol = 5 ma 4260 0.4 v v ol output low voltage at i ol = 25 ma 6168 0.55 v v stby stand-by voltage ram 5 3 v i stby stand-by current ram 5 1 m a @ v dd = 0 v, v stby = 5v v pow on power-on voltage 1 4.2 4.75 v bus ports: p1, p2, p3, p4.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 34 4.6.5. using external devices to avoid collision on the data bus during direction changes, the ccu data bus out buffers (active during phi2 = `1' only) are disabled before the address, the r/w and the r /w line changes (t dhw t ah). this guarantees that no collision happens on the bus if the output drives of the external devices (rom, ram, ports) are con- trolled with the r/w or r /w signal and a read cycle fol- lows a write cycle. important: in a write cycle the data-out drivers of the ccu set up the data bus lines. then they leave these lines so that no drivers are active on the data bus. a few ns later the r/w or the p5 select signal latch the data into the external device (port out or write into ram). the same signal is used to enable the output drivers of exter- nal devices for reading so that another few ns later they drive the bus. the data bus is used as data memory for a few ns. this is the only way to make sure that, independent from the loads on the ccu address, data and control lines collisions are avoided and a maxi- mum of access time is available for the memory. if you want to write to external devices the data bus must be in the tristate mode during write operations of the ccu. no pull- up or pull-down resistors are allowed. even in a good layout the capacitive load on the data bus is approx. 20 pf (2* pin capacity and layout). even in the worst case of a 1 m w leakage the time constant is approx. 20 m s. the max. time between disabling the bus drivers and the rising edge of r/w is 20 ns. 4.6.6. ac characteristics at t a = 0 cto 65 c, v sup = 5 v, f clk = 8 mhz, cl = 0 pf external loads: add 0.75 ns/pf for controller output lines symbol parameter pin min. max. unit t cyc cycle time (processor) 3 125 2000 ns t pwl pulse width low 3 60 1000 ns t ah address hold time 2641 10 22 ns t ads address setup time read 15 34 ns t dsr data setup time read 1825 20 ns t mds write data delay 10 29 ns t dhw write data hold time 9 16 ns t dhr read data hold time 10 ns t rwh read/write hold time 17 10 24 ns t wrh read /write hold time (p76 special mode) 17 13 34 ns t p5s delay p1 to p3 select lines on p5 4247 12 26 ns t x1 f 2 delay x1 to internal f 2 4 7 15 ns t f 2x2 delay f 2 internal to x2 3 5 10 ns
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 35 t cyc t pwl t ads t ah a0...a15 t acc t dsr read data t dhr write data t mds t dhw read data write data t rwh r/w f 2 internal t x1 f 2 t p5s t p5s x1 wr port 1 to 3 rd port 1 to 3 select lines fig. 413: ac timing
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 36 4.6.7. im bus waveforms h l h l h l ident clock data 12 34 678910111213 16 or 24 lsb address msb lsb data msb ab c section a section b section c h l data h l clock h l ident address lsb address msb data msb 5 t im1 t im3 t im2 t im7 t im8 t im9 t im4 t im5 t im6 t im10 fig. 414: im bus waveforms 4.6.8. description of the im bus the intermetall bus (im bus for short) was de- signed to control the digit 2000 ics by the ccu central control unit. via this bus the ccu can write data to the ics or read data from them. this means that the ccu acts as a master, whereas all controlled ics have purely slave status. the im bus consists of three lines for the signals ident (id), clock (dl) and data (d). the clock frequency range is 50 hz to 1 mhz. ident and clock are unidirec- tional from the ccu to the slave ics, data is bidirection- al. bidirectionality is achieved by using open-drain out- puts. the 2.5 to 1 kohm pull-up resistor common to all outputs must be connected externally. the timing of a complete im bus transaction is shown in fig. 414. in the non-operative state the signals of all three bus lines are high. to start a transaction the ccu sets the id signal to low level, indicating an address transmission, and sets the cl signal to low level as well as to switch the first bit on the data line. then eight ad- dress bits are transmitted, beginning with the the lsb. data takeover in the slave ics occurs at the positive edge of the clock signal. at the end of the address byte the id signal switches to high, initiating the address comparison in the slave circuits. in the addressed slave the im bus interface switches over to data read or write, because these functions are correlated to the address. also controlled by the address the ccu now transmits eight or sixteen clock pulses, and accordingly one or two bytes of data are written into the addressed ic or read out from it, beginning with the lsb. the completion of the bus transaction is signalled by a short low state pulse of the id signal. this initiates the storing of the transferred data. for future software compatibility, the ccu must write a zero into all bits not currently used. when reading unde- fined or unused bits, the ccu must adopt adon't careo behavior.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 37 4.6.9. recommended operating conditions of im bus symbol parameter pin no. min. typ. max. unit v iml im bus low voltage data 710 0.8 v v imh im bus high voltage 7 , 10 2.4 v r ext external pull-up resistor 1 2.5 k w i imol im bus output low current 5 ma f f i f i im bus clock frequency clock 912 0.05 1000 khz t im1 f i clock delay time after im bus ident 9 , 12 > 0 t im2 f i clock low pulse time 500 ns t im3 f i clock high pulse time 500 ns t im4 f i clock setup time before ident high > 0 0.5 ? t im3 ns t im5 f i clock hold time after ident high 250 0.5 ? t im3 ns t im6 f i clock setup time before ident end-pulse 1 t im2 +t im3 m s t im7 im bus data delay time after f i clock > 0 ns t im8 im bus data setup time before f i clock clock, data 7910 > 0 ns t im9 im bus data hold time after f i clock 7 , 9 , 10 , 12 > 0 ns t im10 im bus ident end-pulse low time ident 8, 11 1 t im2 +t im3 m s
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 38 4.6.10. registers 0200h system clock prescaler bit reset read write 7 to 3 0 x 2 1 x divisor value 1 1 0 x 0 0 x 0201h control register bit reset read write 7 copy from x no function set to `1' (to keep compatibility) 6 addr. fff9h x no function set to `1' (to keep compatibility) 5 x no function set to `1' (to keep compatibility) 4 external bus: `1' = bus on ports 0, 1, 2 disabled bus disable: `1o = disable bus on ports 0, 1, 2 3 r/w signal / port4: `0' = r/w, `1' = p40 r/w signal / port4: `0' = r/w, `1' = p40 2 internal rom: `1' = internal rom enabled rom enable: `1' = enable internal rom 1 internal ram: `1' = internal ram enabled ram enable: `1' = enable internal ram 0 internal cpu: `1' = internal cpu enabled cpu enable: `1' = enable internal cpu 0202h watchdog control and status bit reset read write 7 x x watchdog time value = 6 x x 5 x x 4 x x 3 x x 2 x x 1 x x 0 1/0 `0': last reset was generated by watchdog f system 65536 * twd ) ( 1 = n t wd = (n+1) * 65536 f system (don't use setting n<2!!) with f system = 4 mhz: n = n min = 2 ? t wdmin = 49.152 ms n = n max = 255 ? t wdmax = 4.17792 s min. d n = 1 ? min. d t wd =16.384 ms
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 39 0203h port 1 data register bit reset read write 7 to 0 0 port 1 data port 1 data 0204h port 1 direction register bit reset read write 7 to 0 1 x `1' = input, `0' = output mode 0205h port 2 data register bit reset read write 7 to 0 0 port 2 data port 2 data 0206h port 2 direction register bit reset read write 7 to 0 1 x `1' = input, `0' = output mode 0207h port 3 data register bit reset read write 7 to 0 0 port 3 data port 3 data 0208h port 3 direction register bit reset read write 7 to 0 1 x `1' = input, `0' = output mode 0209h port 4 data register bit reset read write 7 to 1 x x x 0 0 port 4 data (bit 0 only) port 4 data (bit 0, only) 020ah port 5 mode bit reset read write 7 to 6 x x x 5 to 0 x port 4 data (bit 0 only) `1' = port select mode, `0' = port mode
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 40 020bh port 5 direction register bit reset read write 7 to 6 x x x 5 to 0 1 x `1' = input, `0' = output mode 020ch port 5 data register bit reset read write 7 to 6 x x x 5 0 data bit 5 data bit 5 4 0 data bit 4 data bit 4 3 0 data bit 3 data bit 3 2 0 data bit 2 data bit 2 1 0 data bit 1 data bit 1 0 0 data bit 0 data bit 0 020dh ir input bit reset read write 7 to 3 x x x 2 x irpin logic level x 1 x `1' if a falling edge occurred since last read, else `0' x 0 x `1' if a rising edge occurred since last read, else `0' x 020fh port 7 mode register bit reset read write 7 0 x `0' = port mode, `1' = power down control for external memory 6 0 x `0' = port mode, `1' = \r/w output 5 0 x `0' = port mode, `1' = banking addr. bit 5 4 0 x `0' = port mode, `1' = banking addr. bit 4 3 0 x `0' = port mode, `1' = banking addr. bit 3 2 0 x `0' = port mode, `1' = banking addr. bit 2 1 0 x `0' = port mode, `1' = banking addr. bit 1 0 0 x `0' = port mode, `1' = banking addr. bit 0
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 41 0210h im bus 1 control and status register bit reset read write 7 to 4 x x x 3 0 `1' = 1 byte received in slave reg- ister 3 (im bus address 4) `1' = read word via im bus (master) (bits 0 to 3: `0000'= 2 0 `1' = 1 byte received in slave reg- ister 2 (im bus address 3) `1' = read byte via im bus (master) reset im bus interface) 1 0 `1' = 1 byte received in slave reg- ister 1 (im bus address 2) `1' = write word via im bus (master) ) 0 0 `1' = im bus (master) busy `1' = write byte via im bus (master) 0211h im bus 1 data transfer rate register bit reset read write 7 to 6 x x x 5 x x transfer rate bit 5 4 x x transfer rate bit 4 3 x x transfer rate bit 3 2 x x transfer rate bit 2 1 x x transfer rate bit 1 0 x x transfer rate bit 0 0213h im bus 1 master address register bit reset read write 7 x x im bus address bit 7 6 x x im bus address bit 6 5 x x im bus address bit 5 4 x x im bus address bit 4 3 x x im bus address bit 3 2 x x im bus address bit 2 1 x x im bus address bit 1 0 x x im bus address bit 0
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 42 0214h im bus 1 master data register, low byte bit reset read write 7 x im bus data bit 7 im bus data bit 7 6 x im bus data bit 6 im bus data bit 6 5 x im bus data bit 5 im bus data bit 5 4 x im bus data bit 4 im bus data bit 4 3 x im bus data bit 3 im bus data bit 3 2 x im bus data bit 2 im bus data bit 2 1 x im bus data bit 1 im bus data bit 1 0 x im bus data bit 0 (lsb) im bus data bit 0 (lsb) 0215h im bus 1 master data register, high byte bit reset read write 7 x im bus data bit 15 (msb) im bus data bit 15 (msb) 6 x im bus data bit 14 im bus data bit 14 5 x im bus data bit 13 im bus data bit 13 4 x im bus data bit 12 im bus data bit 12 3 x im bus data bit 11 im bus data bit 11 2 x im bus data bit 10 im bus data bit 10 1 x im bus data bit 9 im bus data bit 9 0 x im bus data bit 8 im bus data bit 8 0216h im bus 1 slave 1 register (im bus address 2) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 43 0218h im bus 1 slave 2 register (im bus address 3) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x 021ah im bus 1 slave 3 register (im bus address 4) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x 021ch interrupt controller control register bit reset read write 7 to 5 x x x 4 0 x `0' = reset interrupt controller 3 1 x `0' = disable after interrupt 2 1 x `0' = disable interrupts 1 1 x `0' = allow next interrupt 0 0 x `0' = clear all requests
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 44 021dh interrupt controller return register bit reset read write 7 x x x 6 x x x 5 x x x 4 x x x 3 x x x 2 x x x 1 x x x 0 x x x 021eh interrupt priorities: source 1 = timer 2 and source 0 = timer 1 bit reset read write 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x 021fh interrupt priorities: source 3 = im bus 1 master and source 2 = timer 3 bit reset read write 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x the `write' to this register is the handshake for the interrupt controller that the current interrupt request is served. xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 off low high interrupt priority value for source 1 = timer 2 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority interrupt priority value for source 0 = timer 1 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 off low high interrupt priority value for source 3 = im bus 1 master values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority interrupt priority value for source 2 = timer 3 (1 ms) values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 45 0220h interrupt priorities: source 5 = im bus 2 master and source 4 = im bus 1 slave bit reset read write 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x 0221h interrupt priorities: source 7 = p87 and source 6 = im bus 2 slave bit reset read write 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x 0222h timer 1 control register 1 bit reset read write 7 x x `1' = second serial input level enabled 6 x x clock select, bit 1: `00' = pin, `01' = fosc 5 x x clock select, bit 0: `10' = phi2, `11' = no clock 4 x x counter stop: `0' = disabled, `1' = carry out accu 3 x x start condition, bit 1: `00' = none (always active) 2 x x start condition, bit 0: `01' = edge, `10' = pin, `11' = \ pin 1 x x `1' = half load enabled 0 x x active edge selection: `0' = rising, `1' = falling xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 off low high interrupt priority value for source 5 = im bus 2 master values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority interrupt priority value for source 4 =im bus 1 slave values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 xxxx xxxx 0000 1111 00 00 11 11 00 11 010 1 off low high interrupt priority value for source 7 = p87 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority interrupt priority value for source 4 =im bus 2 slave values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 46 0223h timer 1 control register 2 bit reset read write 7 x x pin output mode, bit 1: 00 = disabled, 01 = serial out 6 x x pin output mode, bit 0: 10 = pwm, 11 = carry accu d 5 x x read latch, bit 2: 000 = disabled, 001 = carry accu c 4 x x read latch, bit 1: `010' = carry accu d, `011' pin 3 x x read latch, bit 0: `100' = \pin, `101' = prescaler out- put, `110' = prescaler input, `111' = undefined 2 x x accu clock, bit 1: `00' = presc. input, `01' = pre.output 1 x x accu clock, bit 0: `10' = pin, `11' = \ pin 0 x x `1' = use accu c with accu d as long one (16bit accu) 0224h timer 1 control register 3 bit reset read write 7 x x interrupt event, bit 2:`000' = none, `001' = pin 6 x x interrupt event, bit 1:`010' = \pin, `011' = carry accu c, 5 x x interrupt event, bit 0:`100' = carry accu d, `101', `110', `111' = undefined 4 x x load event, bit 1: `00': `00' = none, `01' = carry accu c, 3 x x load event, bit 0: `10 = carry accu d, `11' = reg. load 2 x x accu c input: `0' = bus register, `1' = 1 1 x x accu d input: `0' = bus register, `1' = 1 0 x x serial mode enable: `0' = disable, `1' = enable 0225h timer 1 prescaler low byte bit reset read write 7 x x scaler value bit 7 6 x x scaler value bit 6 5 x x scaler value bit 5 4 x x scaler value bit 4 3 x x scaler value bit 3 2 x x scaler value bit 2 1 x x scaler value bit 1 0 x x scaler value bit 0 (lsb)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 47 0226h timer 1 prescaler high byte bit reset read write 7 x x scaler value bit 15 (msb) 6 x x scaler value bit 14 5 x x scaler value bit 13 4 x x scaler value bit 12 3 x x scaler value bit 11 2 x x scaler value bit 10 1 x x scaler value bit 9 0 x x scaler value bit 8 0228h timer 1 accu low byte (accu c) bit reset read write 7 x x accu bit 7 6 x x accu bit 6 5 x x accu bit 5 4 x x accu bit 4 3 x x accu bit 3 2 x x accu bit 2 1 x x accu bit 1 0 x x accu bit 0 (lsb) 0229h timer 1 accu high byte (accu d) bit reset read write 7 x x accu bit 15 (msb) 6 x x accu bit 14 5 x x accu bit 13 4 x x accu bit 12 3 x x accu bit 11 2 x x accu bit 10 1 x x accu bit 9 0 x x accu bit 8
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 48 022ah timer 1 adder low byte bit reset read write 7 x adder bit 7 adder bit 7 6 x adder bit 6 adder bit 6 5 x adder bit 5 adder bit 5 4 x adder bit 4 adder bit 4 3 x adder bit 3 adder bit 3 2 x adder bit 2 adder bit 2 1 x adder bit 1 adder bit 1 0 x adder bit 0 (lsb) adder bit 0 (lsb) 022bh timer 1 adder high byte bit reset read write 7 x adder bit 15 (msb) adder bit 15 (msb) 6 x adder bit 14 adder bit 14 5 x adder bit 13 adder bit 13 4 x adder bit 12 adder bit 12 3 x adder bit 11 adder bit 11 2 x adder bit 10 adder bit 10 1 x adder bit 9 adder bit 9 0 x adder bit 8 adder bit 8 022ch timer 2 control register 1 bit reset read write 7 x x `1' = second serial input level enabled 6 x x clock select, bit 1: `00' = pin, `01' = fosc., 5 x x clock select, bit 0: `10' = phi2, `11' = no clock 4 x x counter stop: `0' = disabled , `1' = carry out accu 3 x x start condition, bit 1: `00'= none (always active), 2 x x start condition, bit 0: `01' = edge, `10' = pin, `11' =\pin 1 x x `1' = half load enabled 0 x x active edge selection: `0' = rising `1' = falling
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 49 022dh timer 2 control register 2 bit reset read write 7 x x pin output mode, bit 1: `00' = disabled, `01' = serial out, 6 x x pin output mode, bit 0: `10' = pwm, `11' = carry accu d 5 x x read latch, bit 2: `000' = disabled, `001' = carry accu c 4 x x read latch, bit 1: `010' = carry accu d, `011' pin 3 x x read latch, bit 0: `100' = \pin, `101' = prescaler out- put, `110' = presc. input, `111' = undefined 2 x x accu clock, bit 1: `00' = presc. input, `01' = presc. output 1 x x accu clock, bit 0: `10' = pin, `11' = \pin 0 x x `1' = use accu c with accu d as long one (16-bit accu) 022eh timer 2 control register 3 bit reset read write 7 x x interrupt event, bit 2: `000' = none, `001' = pin 6 x x interrupt event, bit 1: `010' = \pin, `011' = carry accu c 5 x x interrupt event, bit 0: `100' = carry accu d, `101', `110', `111' = undefined 4 x x load event, bit 1: `00' = none, `01' = carry accu c, 3 x x load event, bit 0: `10' = carry accu d, `11' = register load 2 x x accu c input: `0' = bus register, `1' = 1 1 x x accu d input: `0' = bus register, `1' = 1 0 x x serial mode enable: `0' = disable, `1' = enable
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 50 022fh timer 2 prescaler low byte bit reset read write 7 x x scaler value bit 7 6 x x scaler value bit 6 5 x x scaler value bit 5 4 x x scaler value bit 4 3 x x scaler value bit 3 2 x x scaler value bit 2 1 x x scaler value bit 1 0 x x scaler value bit 0 (lsb) 0230h timer 2 prescaler high byte bit reset read write 7 x x scaler value bit 15 (msb) 6 x x scaler value bit 14 5 x x scaler value bit 13 4 x x scaler value bit 12 3 x x scaler value bit 11 2 x x scaler value bit 10 1 x x scaler value bit 9 0 x x scaler value bit 8 0232h timer 2 accu low byte (accu c) bit reset read write 7 x x accu bit 7 6 x x accu bit 6 5 x x accu bit 5 4 x x accu bit 4 3 x x accu bit 3 2 x x accu bit 2 1 x x accu bit 1 0 x x accu bit 0 (lsb)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 51 0233h timer 2 accu high byte (accu d) bit reset read write 7 x x accu bit 15 (msb) 6 x x accu bit 14 5 x x accu bit 13 4 x x accu bit 12 3 x x accu bit 11 2 x x accu bit 10 1 x x accu bit 9 0 x x accu bit 8 0234h timer 2 adder low byte bit reset read write 7 x adder bit 7 adder bit 7 6 x adder bit 6 adder bit 6 5 x adder bit 5 adder bit 5 4 x adder bit 4 adder bit 4 3 x adder bit 3 adder bit 3 2 x adder bit 2 adder bit 2 1 x adder bit 1 adder bit 1 0 x adder bit 0 (lsb) adder bit 0 (lsb) 0235h timer 2 adder high byte bit reset read write 7 x adder bit 15 (msb) adder bit 15 (msb) 6 x adder bit 14 adder bit 14 5 x adder bit 13 adder bit 13 4 x adder bit 12 adder bit 12 3 x adder bit 11 adder bit 11 2 x adder bit 10 adder bit 10 1 x adder bit 9 adder bit 9 0 x adder bit 8 adder bit 8
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 52 0236h timer 3 control register 1 bit reset read write 7 x x `1' = second serial input level enabled 6 x x clock select, bit 1: `00' = pin, `01' = fosc., 5 x x clock select, bit 0: `10' = phi2, `11' = no clock 4 x x counter stop: `0' = disabled , `1' = carry out accu 3 x x start condition, bit 1: `00'= none (always active), 2 x x start condition, bit 0: `01' = edge, `10' = pin, `11' =\pin 1 x x `1' = half load enabled 0 x x active edge selection: `0' = rising, `1' = falling 0237h timer 3 control register 2 bit reset read write 7 x x pin output mode, bit 1: 00 = disabled, 01 = serial out 6 x x pin output mode, bit 0: 10 = pwm, 11 = carry accu d 5 x x read latch, bit 2: 000 = disabled, 001 = carry accu c 4 x x read latch, bit 1: `010' = carry accu d, `011' pin 3 x x read latch, bit 0: `100' = \pin, `101' = prescaler out- put, `110' = presc. input, `111' = undefined 2 x x accu clock, bit 1: `00' = presc. input, `01' = presc. output 1 x x accu clock, bit 0: `10' = pin, `11' = \pin 0 x x 1 = use acc. c with acc. d as long one (16-bit acc.) 0238h timer 3 control register 3 bit reset read write 7 x x interrupt event, bit 2: `000' = none, `001' = pin 6 x x interrupt event, bit 1: `010' = \pin, 011 = carry accu c 5 x x interrupt event, bit 0: `100' = carry accu d, `101', `110', `111' = undefined 4 x x load event, bit 1: `00' = none, `01' = carry accu c, 3 x x load event, bit 0: 10 = carry accu d, 11 = regist. load 2 x x accu c input: `0' = bus register, `1' = 1 1 x x accu d input: `0' = bus register, `1' = 1 0 x x serial mode enable: `0' = disable, `1' = enable
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 53 0239h timer 3 prescaler low byte bit reset read write 7 x x scaler value bit 7 6 x x scaler value bit 6 5 x x scaler value bit 5 4 x x scaler value bit 4 3 x x scaler value bit 3 2 x x scaler value bit 2 1 x x scaler value bit 1 0 x x scaler value bit 0 (lsb) 023ah timer 3 prescaler high byte bit reset read write 7 x x scaler value bit 15 (msb) 6 x x scaler value bit 14 5 x x scaler value bit 13 4 x x scaler value bit 12 3 x x scaler value bit 11 2 x x scaler value bit 10 1 x x scaler value bit 9 0 x x scaler value bit 8 023ch timer 3 accu low byte (accu c) bit reset read write 7 x x accu bit 7 6 x x accu bit 6 5 x x accu bit 5 4 x x accu bit 4 3 x x accu bit 3 2 x x accu bit 2 1 x x accu bit 1 0 x x accu bit 0 (lsb)
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 54 023dh timer 3 accu high byte (accu d) bit reset read write 7 x x accu bit 15 (msb) 6 x x accu bit 14 5 x x accu bit 13 4 x x accu bit 12 3 x x accu bit 11 2 x x accu bit 10 1 x x accu bit 9 0 x x accu bit 8 023eh timer 3 adder low byte bit reset read write 7 x adder bit 7 adder bit 7 6 x adder bit 6 adder bit 6 5 x adder bit 5 adder bit 5 4 x adder bit 4 adder bit 4 3 x adder bit 3 adder bit 3 2 x adder bit 2 adder bit 2 1 x adder bit 1 adder bit 1 0 x adder bit 0 (lsb) adder bit 0 (lsb) 023fh timer 3 adder high byte bit reset read write 7 x adder bit 15 (msb) adder bit 15 (msb) 6 x adder bit 14 adder bit 14 5 x adder bit 13 adder bit 13 4 x adder bit 12 adder bit 12 3 x adder bit 11 adder bit 11 2 x adder bit 10 adder bit 10 1 x adder bit 9 adder bit 9 0 x adder bit 8 adder bit 8
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 55 0240h port 6 data register bit reset read write 7 to 0 0 port 6 data port 6 data 0241h port 6 direction register bit reset read write 7 to 0 1 x `1' = input, `0' = output mode 0242h port 7 data register bit reset read write 7 to 0 0 port 7 data port 7 data 0243h port 7 direction register bit reset read write 7 to 0 1 x `1' = input, `0' = output mode 0244h port 8 data register bit reset read write 7 0 data bit 7 data bit 7 6 to 4 x x x 3 0 data bit 3 data bit 3 2 0 data bit 2 data bit 2 1 0 data bit 1 data bit 1 0 0 data bit 0 data bit 0
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 56 0245h port 8 direction register bit reset read write 7 1 x `1' = input, `0' = output mode 6 x x x 5 x x x 4 x x x 3 1 x `1' = input, `0' = output mode 2 1 x `1' = input, `0' = output mode 1 1 x `1' = input, `0' = output mode 0 1 x `1' = input, `0' = output mode 0246h im bus 2 control and status register bit reset read write 7 to 4 x x x 3 0 `1' = 1 byte received in slave register 3 (im bus address 4) `1' = read word via im bus (master) (bits 0 ... 3: `0000'= 2 0 `1' = 1 byte received in slave register 2 (im bus address 3) `1' = read byte via im bus (master) reset im bus interface) 1 0 `1' = 1 byte received in slave register 1 (im bus address 2) `1' = write word via im bus (master) ) 0 0 `1' = im bus (master) busy `1' = write byte via im bus (master) 0247h im bus 2 data transfer rate register bit reset read write 7 to 6 x x x 5 x x transfer rate bit 5 4 x x transfer rate bit 4 3 x x transfer rate bit 3 2 x x transfer rate bit 2 1 x x transfer rate bit 1 0 x x transfer rate bit 0
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 57 0249h im bus 2 master address register bit reset read write 7 x x im bus address bit 7 6 x x im bus address bit 6 5 x x im bus address bit 5 4 x x im bus address bit 4 3 x x im bus address bit 3 2 x x im bus address bit 2 1 x x im bus address bit 1 0 x x im bus address bit 0 024ah im bus 2 master data register, low byte bit reset read write 7 x im bus data, low byte, bit 7 im bus data, low byte, bit 7 6 x im bus data, low byte, bit 6 im bus data, low byte, bit 6 5 x im bus data, low byte, bit 5 im bus data, low byte, bit 5 4 x im bus data, low byte, bit 4 im bus data, low byte, bit 4 3 x im bus data, low byte, bit 3 im bus data, low byte, bit 3 2 x im bus data, low byte, bit 2 im bus data, low byte, bit 2 1 x im bus data, low byte, bit 1 im bus data, low byte, bit 1 0 x im bus data, low byte, bit 0 im bus data, low byte, bit 0 024bh im bus 2 master data register, high byte bit reset read write 7 x im bus data, high byte, bit 7 im bus data, high byte, bit 7 6 x im bus data, high byte, bit 6 im bus data, high byte, bit 6 5 x im bus data, high byte, bit 5 im bus data, high byte, bit 5 4 x im bus data, high byte, bit 4 im bus data, high byte, bit 4 3 x im bus data, high byte, bit 3 im bus data, high byte, bit 3 2 x im bus data, high byte, bit 2 im bus data, high byte, bit 2 1 x im bus data, high byte, bit 1 im bus data, high byte, bit 1 0 x im bus data, high byte, bit 0 im bus data, high byte, bit 0
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 58 024ch im bus 2 slave 1 register (im bus address 2) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x 024eh im bus 2 slave 2 register (im bus address 3) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x 0250h im bus 2 slave 3 register (im bus address 4) bit reset read write 7 x im bus data, bit 7 x 6 x im bus data, bit 6 x 5 x im bus data, bit 5 x 4 x im bus data, bit 4 x 3 x im bus data, bit 3 x 2 x im bus data, bit 2 x 1 x im bus data, bit 1 x 0 x im bus data, bit 0 x
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 59 5. index a access time, 5 accu, 16, 17, 18, 22, 66 accumulator, 14, 17 adder, 16, 22, 66 arithmetic unit, 14 asynchronous interface, 14 b bus external bit, 8 c clock, 4, 5, 10, 17, 21, 22, 32, 37, 66 clock supervision, 4, 21 control byte, 10, 22, 66 control register, 5, 8, 12, 13 counter, 14, 16 d data transfer rate, 22 direction register, 5, 6, 22, 66 e emu, 4, 12, 21 event counter, 14 f frequency counter, 14 g generator, 4, 5, 14 h handshake, 12 i i/o lines, 4, 5 i/o page, 5 im bus interface, 4, 12, 13, 36 internal time reference, 14 interrupt, 4, 5, 10 interrupt controller, 4, 5, 10, 11, 21, 22, 66 ir-input, 21, 22, 66 irinput, 4 l lines, 4, 5, 6, 12, 34, 36, 65 m mask-programmed, 5 master, 12, 22, 36, 66 master address, 12, 22 master data, 12, 22 mode register, 22, 66 multimaster ability, 12 o open drain outputs, 5 osc, 5 oscillator, 5, 8 p p4, 5, 8, 31, 33, 34 page 0, 5 f 2, 5 port 1, 5, 6, 22, 34, 35, 65, 66 port 3, 5, 8, 22, 66 port 6, 5 port 8, 5 power on, 4, 21 prescaler, 14, 16, 17 priority, 10 pull-up resistor, 5, 8, 12, 36 pull-up resistor, 12, 37 pulse-length meter, 14 push-pull outputs, 5 pwm, 14, 17 r r/w mode, 8 r/w -line, 5, 34, 65 ram, internal, 4 rate multiplier, 14
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 60 reset, 5, 8, 10, 11, 13, 17, 21, 22, 22, 31, 66 rom, 4 rti, 10 s serial interface, 14 slave registers, 12, 13 speed, 12 stand-by option, 4 start and stop detector, 14 t timer, 14 timers, 4, 14, 17, 22, 66 w watchdog, 4, 19, 22, 66 x x1, 34 x2, 34 xtal1, 5 xtal2, 5
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 61 6. addendum: ccu 3000, ccu 3000-i emu versions the ccu 3000 tcs 10, 12, 16, 1, and ccu 3000-i tcs 1 and 3 are emulator versions (emus). they differ from production versions in the programmability of control register bit 5: if this bit is set to 0, the ccu assumes to have a clock signal at its x1-pin instead of a crystal con- nected at pins x1 and x2. x2, in that case, works as a clock output delivering the inverted processor f 2 output signal. fosc position shown: = 1 xtal-mode fig. 61: x1, x2 f 2 f 2-switch f 2-switch 4 3 0201h control register bit reset read write 7 copy from x no function set to `1' (to keep compatibility) 6 addr. fff9h x no function set to `1' (to keep compatibility) 5 phi2-out: `0' = active, `1' = inactive phi2-out: `0' = active, `1' = inactive 4 external bus: `1' = bus on ports 0, 1, 2 disabled bus disable: `1' = disable bus on ports 0, 1, 2 3 r/w signal / port4: `0' = r/w, `1' = p40 r/w signal / port4: `0' = r/w, `1' = p40 2 internal rom: `1' = internal rom enabled rom enable: `1' = enable internal rom 1 internal ram: `1' = internal ram enabled ram enable: `1' = enable internal ram 0 internal cpu: `1' = internal cpu enabled cpu enable: `1' = enable internal cpu
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 62 7. addendum: ccu 3000 1 m m version as the 1 m m version of the ccu has faster pin signal drivers than the 1.2 m m version, it may be programmed to work in a kind of aslow modeo, i.e.: the current of the pin driver transistors in that mode is limited to 35 to 40%. in this default mode it is compatible with the 1.2 m m version. 020eh fast/slow register bit reset read write 7 to 3 x x x 2 0 x port 6: 0 = slow, 1 = fast 1 0 x ports 5, 7, 8, timers 1, 2, 3, ir, im bus: 0 = slow, 1 = fast 0 0 x ports 1, 2, 3, 4,: 0 = slow, 1 = fast 7.1. electrical characteristics 7.1.1. absolute maximum ratings symbol parameter pin no. min. max. unit test conditions voltages v dd supply voltage 1 0.5 6.5 v v i input voltage on any pin 1 to 68 0.3 v dd +0.3 v currents i dd supply current 1 50 80 ma i stby standby current 5 280 50 ma i i input current 7 to 68 2 2 ma i o output current 7 to 60 5 5 ma (except port 6) i o output current 61 to 68 30 ma (port 6 only) temperatures t a ambient temperature under bias 10 80 c t s storage temperature 40 125 c power p max power dissipation 1210 mw t a 70 c, 68-pin plcc max 800 mw a , t a 70 c, 64-pin sdip stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability.
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 63 7.1.2. recommended operating conditions at v dd = 4.75 v, t amb = 0 cto 70 c symbol parameter pin no. min. typ. max. unit test conditions input voltages v inl input low voltage 34 v ss 0.3 0.8 v v ih input high voltage 3 , 4 , 668 2.8 v dd +0.3 v open drain output voltages v oh output high voltage 6168 v dd +0.3 v (port 6 only) standby voltage v stby 5 3 5.25 v clock input f xtal 4 0.5 8 mhz external clock capacitive load on address, rwq and data pads (port1, port2, port3, port4) c adf 1741 30 pf bus fast mode 020e , bit0=0 c ads 17 41 100 pf bus slow mode 020e , bit0=1 7.1.3. recommended crystal characteristics at c xtal1 = c xtal2 = 22 pf 1p; c stray 2 pf symbol parameter pin no. min. typ. max. unit test conditions quartz (xtal1/xtal2) f p parallel resonance frequency 48 mhz c l= 13 pf r 1 series resistance 40 150 w w 8 mhz 4 mhz c 0 shunt capacitance 7.0 pf c 1 motional capacitance 20 ff p rated drive level 0.02 mw f p / f h spurious frequency attenuation 20 db
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 64 7.1.4. dc characteristics at v dd = 4.75v to 5.25v, t amb = 0 cto 70 c,f xtal = 8 mhz, for 68-pin plcc package symbol parameter pin no. min. typ. max. unit comment i dd supply current (no external load, cmos-levels on in- puts) 1 8/16 15/30 ma @ 4/8 mhz i stby standby current 5 1 m a v dd =0v, v stby =5v v por power-on reset voltage 6 4 4.2 4.75 v inputs (all inputs except xtal1) v ilh schmitt input l h transition voltage 3, 668 0.38 v dd 2.15 0.56 v dd v v ihl schmitt input h l transition voltage 3, 668 0.20 v dd 1.15 0.29 ? v dd v d (v ilh v ihl ) schmitt input hysteresis 0.10 v dd 0.27 ? v dd v i li leakage current 1 1 m a v ss v in v dd outputs (push-pull or push-pull/open-drain switch: p1..5, p7..8, t1..3, ir, xtal2) v ol output low voltage 1760 0.4 v i out =4ma v oh output high voltage v dd 0.4 v i out =4ma outputs (open-drain with weak pull-up: imb_id1, imb_dat1, imb_cl1, imb_id2, imb_dat2, imb_cl2, resq) v ol output low voltage 1760 0.4 v i out = 4 ma v oh output high voltage v dd 0.4 v i out = 2 m a i ohs output high short circuit current 50 m a v out = v ss output data = 1 outputs (open drain, with clamping diode: p6) v ol output low voltage 6168 0.5 v i out = 25 ma
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 65 7.1.5. ac characteristics at t amb = 0 cto 70 c, v dd = 4.75 v to 5.25 v, cl = 0 pf external loads: add 0.75 ns/pf for controller output lines symbol parameter pin min. max. unit t cyc cycle time 3 125 2000 ns t pwl pulse width low 3 60 1000 ns t ah address hold time 2641 10 22 ns t ads address setup time 15 34 ns t dsr data setup time read 1825 20 ns t mds write data delay 10 29 ns t dhw write data hold time 9 16 ns t dhr read data hold time 10 ns t rwh read/write hold time 17 10 24 ns t wrh read /write hold time 17 13 34 ns t p5s delay port1 to port3 select lines 4247 12 26 ns t x1ph2 delay x1 to internal f 2 4 7 15 ns t ph2x2 internal f 2 to x2 output 3 5 10 ns
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 66 8. addendum: ccu 3000-i specification 8.1. changes to ccu3000 instead of the master/slave im bus interface im1 of ccu3000, an i 2 c/im bus master is used. source 3 of the interrupt controller is not connected. its priority has to be set to `0'. source 4 of the interrupt controller is connected with port81 (special input). falling edges of port 8, bit 1 gen- erate interrupts if the priority of this interrupt source is not set to 0. in i 2 c mode it is possible to switch i 2 c_clk from im1_clk_pad to im1_id_pad. therefore two i 2 c busses can be driven (see section 8.6. for details). the ccu 3000-i is available in two different packages, see pages 71 to 73. all other features are the same as in ccu3000. 8.2. definitions 8.3. interrupt definitions interrupt source vector (low, high byte) 0 timer1 fff6, fff7 1 timer2 fff4, fff5 2 timer3 fff2, fff3 3 nc fff0, fff1 4 p81 ffee, ffef 5 im-bus2, master ffec, ffed 6 im-bus2, slave ffea, ffeb 7 p87 ffe8, ffe9 reset fffc, fffd 8.4. memory mappings ram 0000h to 01ffh page 0, 1 0300h to 063fh page 3, 4, 5, 6 rom 8000h to ffffh (ccu3001-i only) control fff9 byte i/o 0200 to 02ff 8.5. i/o definitions address function 200h clock frequency 201h control register 202h watchdog 203h port 1 data 204h direction register port 1 205h port 2 data 206h direction register port 2 207h port 3 data 208h direction register port 3 209h port 4 data 20ah port 5 mode register 20bh port 5 direction register 20ch port 5 data 20dh ir-input 20fh port 7 mode register 21ch interrupt controller control byte 21dh interrupt controller return byte 21eh interrupt controller priorities source 0 & 1 21fh interrupt controller priorities source 2 & 3 220h interrupt controller priorities source 4 & 5 221h interrupt controller priorities source 6 & 7 222h timer 1 control byte 1 223h timer 1 control byte 2 224h timer 1 control byte 3 225h timer 1 prescaler low byte 226h timer 1 prescaler high byte 228h timer 1 accu low byte 229h timer 1 accu high byte 22ah timer 1 adder low byte 22bh timer 1 adder high byte 22ch timer 2 control byte 1 22dh timer 2 control byte 2 22eh timer 2 control byte 3 22fh timer 2 prescaler low byte 230h timer 2 prescaler high byte 232h timer 2 accu low byte 233h timer 2 accu high byte 234h timer 2 adder low byte 235h timer 2 adder high byte 236h timer 3 control byte 1 237h timer 3 control byte 2 238h timer 3 control byte 3 239h timer 3 prescaler low byte 23ah timer 3 prescaler high byte 23ch timer 3 accu low byte 23dh timer 3 accu high byte 23eh timer 3 adder low byte 23fh timer 3 adder high byte 240h port 6 data 241h direction register port 6 242h port 7 data 243h direction register port 7 244h port 8 data 245h direction register port 8 246h im-bus 2 control & status 247h im-bus 2 transfer rate 249h im-bus 2 master address 24ah im-bus 2 master data low 24bh im-bus 2 master data high 24ch im-bus 2 slave 1, im address 02 24eh im-bus 2 slave 2, im address 03 ccu 3000-i, ccu3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 67 250h im-bus 2 slave 3, im address 04 2d0h i 2 c start cycle without generation of ack (ack = `1') 2d1h i 2 c start cycle with generation of ack (ack = `0') 2d2h i 2 c resume cycle without generation of ack (ack = `1') 2d3h i 2 c resume cycle with generation of ack (ack = `0') 2d4h i 2 c termination cycle without generation of ack (ack = `1') 2d5h i 2 c termination cycle with generation of ack (ack = `0') 2d6h i 2 c / im bus data from receive-fifo 2d7h i 2 c / im bus status 2d8h im bus start cycle 2d9h im bus resume cycle 2dah im bus termination cycle 2dbh i 2 c / im bus prescaler 2e0h external addresses, used for emu boards to 2e7h 2feh reserved, do not use 2ffh reserved for testing purposes 8.6. i 2 c and im bus interface the master bus interface can generate two different kinds of format: i 2 c format im format the msbit of the bus prescaler registers (address 2dbh) is used to switch i 2 c_clk between im1_clk_pad and im1_id_pad. the remaining 7 bits can be used to set the bit rate. bit 7 0 = i 2 c_clk at im1_id_pad, 1 = i 2 c_clk at im1_clk_pad (reset state) bit 6 to 0 bit rate f imi2c = f osc / (4 * n) for n>1 where n is the value of bits 0 to 6 and the setting value (0 = reset state means n = 128). a complete telegram is assembled by the software out of individual sections. each section contains an 8-bit data. this data is written into one of the nine possible control-data registers. de- pending on the chosen address, a certain part of an i 2 c or im bus cycle is generated. by means of correspond- ing calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto incre- ment addressing of i 2 c slaves). the software interface contains a 3 byte deep fifo for the control-data registers as well as for the received data. thus all im and most of the i 2 c telegrams can be transmitted to the hardware without the software having to wait for empty space in the fifo. all address and data fields appearing on the bus are constantly read and written into the read-fifo. the software can then check these data in comparison with the scheduled data. if a read instruction is handled, the interface must set the data word ffh so that the re- sponding slave can insert its data. in this case the read- fifo contains the read-in data. if telegrams longer than 3 bytes are received, (1 ad- dress, 2 data bytes), the software must check the filling condition of the control data fifo and, if necessary, fill it up (or read out the read-fifo). a variety of status flags is available for this purpose: the `half-full' flag is set if there are more than two bytes available in the transmit-fifo. bus busy is activated by writing any byte to any one of the data transfer registers. it stays active until the i 2 c or im bus activities are stopped after the stop condition generation. so `busy' becomes inactive af- ter the data that was written in one of the four registers to terminate the bus action is completely shifted out, and the bus-specific stop condition is generated (see fig. 222, 225). moreover, in the i 2 c mode the ack-bit is recorded sepa- rately on the bus lines for the address and the data fields; however, the interface itself can set the address ack=0. in any case the two ack flags show the actual bus condi- tion. these flags remain until the next i 2 c start condition is generated. ccu 3000-i, ccu3001-i ccu 3000-i, ccu 3001-i ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 68 table 21: i 2 c and im bus interface registers address function 2d0h(w) generate i 2 c start condition, transfer data as i 2 c address, and set ack=1 2d1h(w) same as above, ack=0 2d2h(w) output 8 i 2 c data bits, set ack=1 2d3h(w) same as above, set ack=0 2d4h(w) output 8 i 2 c data bits, set ack=1, generate i 2 c stop condition 2d5h(w) same as above, set ack=0 2d6h(r) receive fifo 2d7h(r) status flags: bit 0 not used bit 1 1= receive fifo empty bit 2 1= contr-data- fifo half full bit 3 1= bus busy bit 4 i 2 c data ack bit 5 i 2 c adr ack bit 6 aoroed ack bit 7 not used 2d8h(w) generate im-address field 2d9h(w) generate 8 im-data bits 2dah(w) generate 8 im-data bits and the im-stop condition 2dbh(w) terminal select & speed for example, the software has to work off the following sequence (ack =1) to read a 16-bit word from an i 2 c de- vice address 10h (on condition that the bus is not ac- tive): write 21h to 2d0h write 0ffh to 2d2h write 0ffh to 2d4h read dev. address2d6h read 1. databyte 2d6h read 2. databyte 2d6h the value 21h in the first step results from the device ad- dress in the 7 msbs and the r/w-bit (read=1) in the lsb. if the telegrams are longer, the software has to ensure that neither the control-data-fifo nor the read-fifo can overflow. to write data to this device: write 20h to 2d0h write 1. databyte to 2d2h write 2. databyte to 2d4h the bus activity starts immediately after the first write to the control-data-fifo. in the i 2 c mode the transmis- sion can be synchronized by an artificial extension of the low phase of the clock line. transmission is not contin- ued until the state of the clock line is high once again. thus a slave (software slaves!) can adjust the transmis- sion rate to its own abilities. the i 2 c/ im bus interface is a pure master system, multi- master busses are not realizable. the ident, clock and data terminal pins have open-drain outputs with weak pull-up transistors. ccu 3000-i ccu 3000-i, ccu 3001-i check receive fifo empty flag (bit 1, 2d7h) be- fore read
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 69 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 2 1 4 fig. 220: start condition i 2 c bus fig. 221: single bit on i 2 c bus fig. 222: stop condition i 2 c bus fig. 223: im bus start condition fig. 224: single bit on im bus fig. 225: stop condition im bus 1 1 2 1 4 sd scl 1 sd scl repeated 7 times sd scl 3 4 ident data clock 1 4 1 4 1 4 data clock ident ident 1 on the 8th address bit only clock stays high on the last data bit before stop 1 2 data clock ident 1 2 unit = bit-period ccu 3000-i, ccu 3001-i ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 70 fig. 226: i 2 c/im bus interface address decoder wr_data (chosen address = control info) sr in out transmit fifo 3 x 11 wr d 0 to d 7 control receive fifo 3 x 8 d 0 to d 7 receive logic half full sr q sr q ready transmit logic empty start condition resets ack flags data d 0 to d 7 rd_status (2d7h) dat or adr ack dat_ack adr_ack clock ident ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 71 8.7. pin connections and short descriptions da = im bus data line of external devices id = im bus ident line of external devices cl = im bus clock line of external devices sda = i 2 c bus data line of external devices scl = i 2 c bus clock line of external devices x = obligatory; connections depend on application pin no. con- nection i: input pin name short description 68pin plcc 64pin sdip o: output 1 16 +5v i v sup supply voltage 2 15 gnd i gnd ground 3 14 xtal i/o x2 crystal connector 2 4 13 xtal i x1 crystal connector 1 5 12 +3v to +5v i v standby standby supply voltage 6 11 x i/o res reset input / reset output 7 10 da/sda i/o im1_dat/i 2 c_dat im bus 1 data line/ i 2 c bus data line 8 9 id/scl o im1_id/i 2 c_clk2 im bus 1 ident line/ i 2 c bus clock line 9 8 cl/scl o im1_clk/i 2 c_clk1 im bus 1 clock line/ i 2 c bus clock line 10 da i/o im2_dat im bus 2 data line 11 id o im2_id im bus 2 ident line 12 cl o im2_clk im bus 2 clock line 13 7 x i/o timer1 timer 1 input/output 14 6 x i/o timer2 timer 2 input/output 15 5 x i/o timer3 timer 3 input/output 16 4 external infrared receiver i ir infrared signal input 17 3 x i/o (o) p4 (r/w ) port 4, bit 0 (cpu read/write) 18 2 x i/o (i/o) p10 (d0) port 1, bit 0 (cpu data bus bit 0) 19 1 x i/o (i/o) p11 (d1) port 1, bit 1 (cpu data bus bit 1) 20 64 x i/o (i/o) p12 (d2) port 1, bit 2 (cpu data bus bit 2) 21 63 x i/o (i/o) p13 (d3) port 1, bit 3 (cpu data bus bit 3) 22 62 x i/o (i/o) p14 (d4) port 1, bit 4 (cpu data bus bit 4) ccu 3000-i ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 72 short description pin name i: input con- nection pin no. o: output con- nection 64pin sdip 68pin plcc 23 61 x i/o (i/o) p15 (d5) port 1, bit 5 (cpu data bus bit 5) 24 60 x i/o (i/o) p16 (d6) port 1, bit 6 (cpu data bus bit 6) 25 59 x i/o (i/o) p17 (d7) port 1, bit 7 (cpu data bus bit 7) 26 58 x i/o (o) p20 (a0) port 2, bit 0 (cpu address bit 0) 27 57 x i/o (o) p21 (a1) port 2, bit 1 (cpu address bit 1) 28 56 x i/o (o) p22 (a2) port 2, bit 2 (cpu address bit 2) 29 55 x i/o (o) p23 (a3) port 2, bit 3 (cpu address bit 3) 30 54 x i/o (o) p24 (a4) port 2, bit 4 (cpu address bit 4) 31 53 x i/o (o) p25 (a5) port 2, bit 5 (cpu address bit 5) 32 52 x i/o (o) p26 (a6) port 2, bit 6 (cpu address bit 6) 33 51 x i/o (o) p27 (a7) port 2, bit 7 (cpu address bit 7) 34 50 x i/o (o) p30 (a8) port 3, bit 0 (cpu address bit 8) 35 49 x i/o (o) p31 (a9) port 3, bit 1 (cpu address bit 9) 36 48 x i/o (o) p32 (a10) port 3, bit 2 (cpu address bit 10) 37 47 x i/o (o) p33 (a11) port 3, bit 3 (cpu address bit 11) 38 46 x i/o (o) p34 (a12) port 3, bit 4 (cpu address bit 12) 39 45 x i/o (o) p35 (a13) port 3, bit 5 (cpu address bit 13) 40 44 x i/o (o) p36 (a14) port 3, bit 6 (cpu address bit 14) 41 43 x i/o (o) p37 (a15) port 3, bit 7 (cpu address bit 15) 42 42 x i/o (o) p50 (rd port 1) port 5, bit 0 (ccu read port 1) 43 41 x i/o (o) p51 (wr port 1) port 5, bit 1 (ccu write port 1) 44 40 x i/o (o) p52 (rd port 2) port 5, bit 2 (ccu read port 2) 45 39 x i/o (o) p53 (wr port 2) port 5, bit 3 (ccu write port 2) 46 38 x i/o (o) p54 (rd port 3) port 5, bit 4 (ccu read port 3) 47 37 x i/o (o) p55 (wr port 3) port 5, bit 5 (ccu write port 3) 48 36 x i/o (o) p70 (memory bank address 0) port 7, bit 0 (memory bank address 0) 49 35 x i/o (o) p71 (memory bank address 1) port 7, bit 1 (memory bank address 1) 50 34 x i/o (o) p72 (memory bank address 2) port 7, bit 2 (memory bank address 2) ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 73 short description pin name i: input con- nection pin no. o: output con- nection 64pin sdip 68pin plcc 51 33 x i/o (o) p73 (memory bank address 3) port 7, bit 3 (memory bank address 3) 52 32 x i/o (o) p74 (memory bank address 4) port 7, bit 4 (memory bank address 4) 53 31 x i/o (o) p75 (memory bank address 5) port 7, bit 5 (memory bank address 5) 54 30 x i/o (o) p76 (r /w) port 7, bit 6 (cpu read/write signal) 55 29 x i/o (o) p77 (power-down control) port 7, bit 7 (power-down control) 56 28 x i/o p80 port 8, bit 0 57 27 x i/o /i p81/int port 8, bit 1 / interrupt input 58 26 x i/o p82 port 8, bit 2 59 x i/o p83 port 8, bit 3 60 25 x i/o /i p87/int port 8, bit 7/interrupt input 61 24 x i/o p60 port 6, bit 0 62 23 x i/o p61 port 6, bit 1 63 22 x i/o p62 port 6, bit 2 64 21 x i/o p63 port 6, bit 3 65 20 x i/o p64 port 6, bit 4 66 19 x i/o p65 port 6, bit 5 67 18 x i/o p66 port 6, bit 6 68 17 x i/o p67 port 6, bit 7 8.7.1. dc parameters i 2 c bus master interface the input and output parameters of the i 2 c bus interface (clock and data) are designed according to the inter- metall specification for port and im bus pins (the inter- face can also be operated as im bus interface). the dif- ferences are: symbol meaning intermetall i 2 c specification u il input low voltage max. 1 v max. 1.5 v u ih input high voltage min. 2.8 v min. 3 v u ol output low voltage 0.4 v / 2 ma 0.4 v / 3 ma the intermetall parameters are equivalent to soft- ware i 2 c bus solutions using port-lines for the bus. in ap- plications with series resistors in the clock or data line these differences may become important. ccu 3000-i ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 74 8.8. list of registers that differ from ccu 3000, ccu 3001 the im1 registers of ccu3000 (addr. from 0210h to 021bh) are no longer available. 02d0h i 2 c start cycle without generation of ack (ack = 1) bit reset read write 7 to 0 x x i 2 c-start-data 02d1h i 2 c start cycle with generation of ack (ack=0) bit reset read write 7 to 0 x x i 2 c-start-data 02d2h i 2 c resume cycle without generation of ack (ack = 1) bit reset read write 7 to 0 x x i 2 c-resume-data (set this byte to $ff for a read access) 02d3h i 2 c resume cycle with generation of ack (ack=0) bit reset read write 7 to 0 x x i 2 c-resume-data (set this byte to $ff for a read access) 02d4h i 2 c termination cycle without generation of ack (ack =1) bit reset read write 7 to 0 x x i 2 c-terminate-data (set this byte to $ff for a read access) 02d5h i 2 c termination cycle with generation of ack (ack=0) bit reset read write 7 to 0 x x i 2 c-terminate-data (set this byte to $ff for a read access) 02d6h i 2 c/im bus data from receivefifo bit reset read write 7 to 0 x received data x ccu 3000-i ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 75 02d7h i 2 c/im bus status bit reset read write 7 0 x x 6 0 i 2 c or'd ack x 5 0 i 2 c addrack x 4 0 i 2 c dataack x 3 0 bus busy x 2 0 wr fifo half full x 1 0 rd fifo empty x 0 0 x x 02d8h im bus start cycle bit reset read write 7 to 0 x x im bus start(address)data 02d9h im bus resume cycle bit reset read write 7 to 0 x x im bus resume data 02dah im bus termination cycle bit reset read write 7 to 0 x x im bus terminal data 02dbh i 2 c/im bus prescaler bit reset read write 7 1 x select i 2 c_clk2 on im1_id / select i 2 c_clk1 on im1_clk 6 to 0 0 x f imi2c = f osc / (4*n) for n>1 f imi2c = f osc / 6 for n=1 f imi2c not running for n=0 ccu 3000-i, ccu 3001-i
ccu 3000, ccu 3000-i ccu 3001, ccu 3001-i micronas intermetall 76 9. data sheet history 1. data sheet accu 3000, ccu 3000-i, ccu 3001, ccu 3001-io, feb. 14, 1995, 6251-367-1ds: first release of the data sheet. micronas intermetall gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@intermetall.de internet: http://www.intermetall.de printed in germany by simon druck gmbh & co., freiburg (02/95) order no. 6251-367-1ds all information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas intermetall gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. reprinting is generally permitted, indicating the source. how- ever, our prior consent must be obtained in all cases.
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