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" for more information + ! " mirrorbit? flash memory write buffer programming and page buffer read application note publication number 25539 revision a amendment 0 issue date october 4, 2001
publication# 25539 rev: a amendment/ 0 issue date: october 4, 2001 mirrorbit ? flash memory write buffer programming and page buffer read application note introduction a write buffer is implemented in mirrorbit ? flash mem- ory devices to speed up programming operations. a write buffer is a set of registers used to hold several words that are to be programmed as a group. the buffer is filled with words to be programmed before is- suing the write buffer programming command. the time to program each word is reduced by performing programming overhead operations once for the entire group of words. this results in faster effective word/ byte programming time than the standard ?word/byte? programming algorithms. write buffer programming al- lows the system to write to a maximum of 16 words (32 bytes) in one programming operation. write buffer programming is performed through the use of a few new memory device commands. these are in addition to the commands normally used to con- trol all amd flash devices. please refer to an amd flash datasheet for a review of the full command set, the method for issuing commands, and the method for polling the status of memory during a command opera- tion. write buffer operation write-buffer programming is only available through the ?write to buffer? and ?program buffer to flash? confirm command sequences. the ?write-to-buffer abort re- set? command sequence is used to reset out of the write-buffer-abort state. table 1 lists all software pro- gram sequences associated with the write-buffer. table 1. mirrorbit ? write buffer programming command definitions x8/x16 devices note: the sixth cycle must be repeated to complete the number of buffer writes specified by wc in cycle four. pa = program address of the memory location to be programmed. this can be any address within the target write-buffer-page. pd = program data to be programmed at location pa. sa = sector address containing locations to be programmed. this can be any valid address within the sector. wc = write count is the number of write buffer locations to load minus one. wbl = write buffer location. the address must be within the same write buffer page (32 byte range located on a 32 byte bound- ary) as pa. command sequence interface bus cycles first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data write to buffer word 555 aa 2aa 55 sa 25 sa wc pa pd wbl (note) pd byte aaa 555 program buffer to flash (confirm) both sa 29 write-to-bufferabort reset word 555 aa 2aa 55 xxx f0 byte aaa 555
2 mirrorbit ? flash memory write buffer programming and page buffer read in table 1, the user starts loading data at any location in the target write-buffer-page. subsequent write buffer locations do not need to be loaded in any partic- ular order as long as they reside in the same write- buffer-page. note that the internal write counter decrements for every data load operation, not for each unique write- buffer address location. if the same write-buffer-loca- tion is loaded multiple times, the internal write counter will decrement after each load operation. the last data loaded into a given write-buffer location will be pro- grammed into the device after the ? program buffer to flash ? confirm command. it is the software's respon- sibility to comprehend the ramifications of loading a write-buffer location more than once. when the ? write to buffer ? command programming se- quence has been completed, the ? program buffer to flash ? confirm command must be issued to move the data from the write-buffer into the flash memory array. programming steps table 2. table 2. mirrorbit ? write buffer programming procedure a flowchart for the ? write to buffer ? command se- quence is demonstrated in figure 1. cycle # write buffer program sequence address data comment 1, 2 issue two unlock cycles:unlock 1, unlock 2 refer to ? write-to-buffer ? software command definition for first and second bus cycles 3 issue ? write-buffer-load ? command @ sector address sa 0025h sector address is issued starting with the third bus cycle 4 issue number of write buffer locations to load minus one@ sector address sa wc wc = number of locations to program minus 1wc of 0 = 1 location to pgmwc of 1 = 2 locations to pgm, etc.the word count is issued during the fourth bus cycle 5 load first address/data pair pa pd selects write-buffer-page and loads first address/data pair. the first address location can be any location in the target write-buffer-page.the first address is loaded into the write-buffer during the fifth bus cycle 6 to n load remaining address/data pairs into write buffer wbl pd all addresses must be within the selected write-buffer-page boundaries but do not have to be in any order.number of cycles depends on the cycle count loaded in fourth bus cycle. n + 1 issue write buffer program confirm@ sector address sa 0029h this command must follow the last write buffer location loaded, or the operation will abort. perform data bar polling on last loaded address
mirrorbit ? flash memory write buffer programming and page buffer read 3 figure 1. write buffer programming operation write ?write to buffer? command and sector address write number of locations to program minus 1(wc) and sector address write program buffer to flash confirm, sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 with address = last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when ?sector address? is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written to the device to return the device to read mode. write- buffer-programming-abort-reset if dq1=1, either software reset or write- buffer-programming-abort-reset if dq5=1. (note 2) (note 1)
4 mirrorbit ? flash memory write buffer programming and page buffer read write buffer programming abort a ? write-buffer-page ? is selected by addresses a4- a(max) for x16 or x8/x16 flash memory devices or by addresses a5-a(max) for x8 flash memory devices. the ? write-buffer-page ? addresses must be the same for all addresses loaded during a write buffer program- ming operation. write buffer programming cannot be performed across multiple ? write-buffer-pages ? or across multiple sectors. if the above conditions are vi- olated, the write buffer programming operation will be automatically aborted. listed below are the ways in which the write buffer programming sequence can be automatically aborted: 1. loading a value that is greater than the write buffer size (write-buffer-page) during the ? numbers of lo- cations to program ? step. 2. writing to an address in a sector that is different than the one specified during the ? write-buffer- load ? command. 3. writing an address/data pair to a different write- buffer-page than the one selected by the ? starting address ? during the ? write buffer data loading ? stage of the operation. 4. writing data other than the ? confirm command ? after loading the specified number of write buffer lo- cations. note that the ? write-to-buffer abort ? condition is always indicated by the dq1 ? write-to-buffer abort ? operation status bit. dq1: write-to-buffer abort dq1 is ? 1 ? when a write-to-buffer operation has been aborted. a write-to-buffer-abort-reset command sequence must be issued to return the flash memory device to reading array data. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ? last loaded address ? ), dq6 = tog- gle, dq5=0. this indicates that the write buffer pro- gramming operation was aborted. a ? write-to- buffer-abort reset ? command sequence must be writ- ten to the device to return to read mode. page buffer read introduction whenever the system changes a ? page address ? (or toggles ce# during a read) the device performs a ? ran- dom access ? . during this ? random access ? the read page buffer is loaded in parallel with data within the se- lected read-page boundaries. subsequent ? intra- page ? accesses are 3 to 4 times faster than random ac- cesses because the data are already available in the buffer (please refer to differences between t ce /t acc and t pacc in the am29lvxxxm datasheet). therefore, read performance is significantly improved. read buffer operation for page buffer read operation, the user has to issue a read address, or ? ra ? , for any memory location. during the initial access time (t ce /t acc ) a page of 4 words (8 bytes), located on an 8-byte boundary, is read into the page buffer. if the device is in word mode address bits a1 and a0 can then be used to access any of the four words within the page with a reduced page access time (t pacc ). if the device is in byte mode in a x8/x16 device. a1 through a-1 can be used to access any of the eight bytes in the page. if the device is a x8-only device, a2 through a0 can be used to access any of the eight bytes within the page. the appropriate page is selected by the higher address bits a2-a(max) for x16-only and x8/x16 devices, and a3-a(max) for x8-only devices. fast page mode ac- cesses are obtained by keeping the high-order ? read- page address bits ? constant and changing the ? intra- read page address bits ? addresses: a0 to a1 for x16- only and x8/x16 in word mode; a-1 to a1 for x8/x16 in byte mode; and a0 to a2 for x8-only. this is an asyn- chronous operation with the microprocessor supplying the specific byte or word location. a depiction of the command sequence definition for read accesses is shown in table 3. a depiction of the device bus operation for read ac- cesses is shown in table 4. table 3. read access note: for reading bytes, eight consecutive memory locations can be read, compared to four memory locations for reading words. ? intra-read page ? locations can be accessed in any order. ra = read address rd = read data command sequence interface bus cycles first second third fourth fifth addr data addr data addr data addr data addr data read both ra rd ra rd ra rd ra rd note note
mirrorbit ? flash memory write buffer programming and page buffer read 5 table 4. device bus operation for read access during page buffer read operations, the ce# pin must be kept at voltage level v il during all fast page mode accesses. if the ce# pin toggles or changes state dur- ing a page buffer read operation, the current data trans- fer will automatically be aborted and another initial page access is started. this will result in unnecessary penalty and overhead in read timings. conclusion the write buffer programming feature of amd mirror- bit ? flash memories increases the programming speed by roughly 16 times compared to single byte or word write operations in the same memory for a full write buffer of 16 words or 32 bytes. write buffer pro- gramming performance is roughly two times faster than previous amd low voltage flash memories. write buffer programming is enabled via a simple addition of three commands to the standard amd embedded algo- rithm bus command set. the read page buffer feature of amd mirrorbit flash memories can increase read performance significantly. following each random (inter-page) access all loca- tions of the referenced 8-byte page are available for fast access. when read accesses can be grouped within a page the average read performance can be in- creased by 3 to 4 times. copyright ? 2001 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . operation ce# oe# we# reset# wp#/acc address data read l l h h x a in d out

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