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843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 1 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary g eneral d escription the ics843002i-41 is a member of the hiperclocks? family of high performance clock solutions from ics. the ics843002i-41 is a pll based synchronous clock generator that is optimized for sonet/sdh line card applications where jitter attenuation and frequency translation is needed. the device contains two internal pll stages that are cascaded in series. the first pll stage uses a vcxo which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd pll stage (typically 19.44mhz). the second pll stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise femtoclock? vco. pll multiplication ratios are selected from internal lookup tables using device input selection pins. the device performance and the pll multiplication ratios are optimized to support non-fec (non-forward error correction) sonet/sdh applications with rates up to oc-48 (sonet) or stm-16 (sdh). the vcxo requires the use of an external, inexpensive pullable crystal. vcxo pll uses external passive loop filter components which are used to optimize the pll loop bandwidth and damping characteristics for the given line card application. the ics843002i-41 includes two clock input ports. each one can accept either a single-ended or differential input. each input port also includes an activity detector circuit, which reports input clock activity through the lor0 and lor1 logic output pins. the two input ports feed an input selection mux. ?hitless switching? is accomplished through proper filter tuning. jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. typical ics843002i-41 configuration in sonet/sdh systems: ? vcxo 19.44mhz crystal ? loop bandwidth: 50hz - 250hz ? input reference clock frequency selections: 19.44mhz, 38.88mhz, 77.76mhz, 155.52mhz, 311.04mhz, 622.08mhz ? output clock frequency selections: 19.44mhz, 77.76mhz, 155.52mhz, 311.04mhz, 622.08mhz, hi-z p in a ssignment f eatures ? (2) differential lvpecl outputs ? selectable clkx, nclkx differential input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl or single-ended lvcmos or lvttl levels ? maximum output frequency: 700mhz ? femtoclock vco frequency range: 560mhz - 700mhz ? rms phase jitter @ 155.52mhz, using a 19.44mhz crystal (12khz to 20mhz): 0.81ps (typical) ? full 3.3v or mixed 3.3v core/2.5v output supply voltage ? -40c to 85c ambient operating temperature hiperclocks? ics 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 lor0 lor1 nc v cco _ lvcmos v cco _ lvpecl nqb qb v ee lf1 lf0 iset v cc clk0 nclk0 clk_sel qa_sel2 qa_sel1 qa_sel0 qb_sel2 qb_sel1 qb_sel0 v cca qa nqa nclk1 clk1 v ee r_sel0 r_sel1 r_sel2 xtal_out xtal_in ics843002i-41 32-lead vfqfn 5mm x 5mm x 0.75mm package body k package top view the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 2 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary b lock d iagram note 1: 19.44mhz vcxo crystal shown is typical for sonet/sdh device applications. r divider = 1, 2, 4, 8, 16 or 32 clk1 nclk1 activity detector clk0 nclk0 activity detector lor1 lor0 r_sel2:0 3 iset clk_sel femtoclock pll x32 622.08 mhz v cco_pecl qa nqa cx divider = 1,2,4,8,16,32, hiz or disable qb nqb qb_sel2:0 qa_sel2:0 3 3 vcxo charge pump and loop filter external loop components 19.44 mhz pullable xtal 19.44 mhz xtal_in xtal_out lf1 lf0 divide by 32 divide by 32 vcxo jitter attenuation pll phase detector ics843002-41 110 110 111 111 v cco_lvcmos 1 0 cx divider = 1,2,4,8,16,32, hiz or disable
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 3 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 f l , 1 f l g o l a n a t u p t u o / t u p n i . s n i p e d o n n o i t c e n n o c r e t l i f p o o l 3t e s i g o l a n a t u p t u o / t u p n i . n i p g n i t t e s t n e r r u c p m u p e g r a h c 4v c c r e w o p. n i p y l p p u s r e w o p e r o c 50 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 60 k l c nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v c c . g n i t a o l f t f e l n e h w e g a t l o v s a i b 2 / 7l e s _ k l ct u p n in w o d l l u p . a 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t c e l e s k c o l c t u p n i 82 l e s _ a qt u p n in w o d l l u p . c 3 e l b a t e e s . s t u p t u o a q n / a q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l , 9 0 1 , 1 l e s _ a q 0 l e s _ a q t u p n ip u l l u p . c 3 e l b a t e e s . s t u p t u o a q n / a q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l 1 12 l e s _ b qt u p n in w o d l l u p . c 3 e l b a t e e s . s t u p t u o b q n / b q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l , 2 1 3 1 , 1 l e s _ b q 0 l e s _ b q t u p n ip u l l u p . c 3 e l b a t e e s . s t u p t u o b q n / b q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l 4 1v a c c r e w o p. n i p y l p p u s g o l a n a 6 1 , 5 1a q n , a qt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c o l c l a i t n e r e f f i d 7 2 , 7 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 9 1 , 8 1b q n , b qt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c o l c l a i t n e r e f f i d 0 2v l c e p v l _ o c c r e w o p . b q n , b q d n a a q n , a q r o f n i p y l p p u s r e w o p t u p t u o 1 2v s o m c v l _ o c c r e w o p. 1 r o l d n a 0 r o l r o f n i p y l p p u s r e w o p 2 2c nd e s u n u. t c e n n o c o n 3 21 r o lt u p t u o . 1 k l c r o f e c n e r e f e r f o s s o l , t u p t u o m r a l a . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 20 r o lt u p t u o . 0 k l c r o f e c n e r e f e r f o s s o l , t u p t u o m r a l a . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 21 k l c nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v c c . g n i t a o l f t f e l n e h w e g a t l o v s a i b 2 / 6 21 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n , 8 2 , 9 2 0 3 , 0 l e s _ r , 1 l e s _ r 2 l e s _ r t u p n in w o d l l u p . b 3 e l b a t e e s . e c a f r e t n i l t t v l / s o m c v l . n o i t c e l e s r e d i v i d t u p n i , 1 3 2 3 , t u o _ l a t x n i _ l a t x t u p n i . t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p n i e h t s i n i _ l a t x : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 0 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 0 5k
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 4 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 3a. i nput r eference s election f unction t able s t u p n i l e s _ k l cd e t c e l e s t u p n i 00 k l c 11 k l c t able 3b. i nput r eference d ivider s election f unction t able s t u p n i 0 : 2 l e s _ re t a t s r o e u l a v r e d i v i d r 0 0 01 1 0 02 0 1 04 1 1 08 0 0 16 1 1 0 12 3 0 1 1l l p o x c v s s a p y b 1 1 1s ' l l p ? k c o l c o t m e f d n a o x c v s s a p y b t able 3c. o utput d ivider s election f unction t able s t u p n i 0 : 2 l e s _ x qe t a t s r o e u l a v r e d i v i d t u p t u o 0 0 0z - i h q n d n a q t u p t u o 1 0 02 3 0 1 08 1 1 04 0 0 16 1 1 0 12 0 1 11 1 1 1v l c e p v l t a q t u p t u o l o v l c e p v l t a q n t u p t u o , h o
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 5 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cca = 3.3v5%, v cco_lvcmos , v cco_l vpecl = 3.3v5% or 2.5v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) continuous current 50ma surge current 100ma package thermal impedance, ja 34.8c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v , s o m c v l _ o c c v l c e p v l _ o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 5 7 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = 3.3v5%, v cco_lvcmos = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n ie g a t l o v h g i h2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , 2 l e s _ a q , l e s _ k l c 2 l e s _ r : 0 l e s _ r , 2 l e s _ b q v c c v = n i v 5 6 4 . 3 =0 5 1a 1 : 0 l e s _ b q , 1 : 0 l e s _ a qv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , 2 l e s _ a q , l e s _ k l c 2 l e s _ r : 0 l e s _ r , 2 l e s _ b q v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a 1 : 0 l e s _ b q , 1 : 0 l e s _ a q v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h 1 e t o n ; 1 r o l , 0 r o l v s o m c v l _ o c c v 3 . 3 =6 . 2v v s o m c v l _ o c c v 5 . 2 =8 . 1v v l o t u p t u o e g a t l o v w o l 1 e t o n ; 1 r o l , 0 r o l v s o m c v l _ o c c r o v 3 . 3 = v 5 . 2 5 . 0v note 1: outputs terminated with 50 to v cco_lvcmos /2 .see parameter measurement information section, ?output load test circuit?.
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 6 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 4d. lvpecl dc c haracteristics , v cc = v cca = 3.3v5%, v cco_l vpecl = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t l c e p v l _ o c c , n o i t c e s " n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p " e e s . v 2 - . " t i u c r i c t s e t d a o l t u p t u o " t able 5. c rystal c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n 4 4 . 9 1z h m f t e c n a r e l o t y c n e u q e r f d b t m p p f s y t i l i b a t s y c n e u q e r f d b t m p p e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c c l e c n a t i c a p a c d a o l 2 1f p c o e c n a t i c a p a c t n u h s 4f p c o c / 1 o i t a r y t i l i b a l l u p 0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 l e v e l e v i r d 1w m n o i t a r e p o f o e d o m l a t n e m a d n u f t able 4c. d ifferential dc c haracteristics , v cc = v cca = 3.3v5%, v cco_l vpecl = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c , 0 k l c v n i v = c c v 5 6 4 . 3 = 0 5 1a 1 k l c n , 0 k l c n 0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c , 0 k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a 1 k l c n , 0 k l c nv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 +
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 7 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 6a. ac c haracteristics , v cc = v cca = v cco_lvcmos , v cco_l vpecl = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 4 4 . 9 10 0 7z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i , z h m 2 5 . 5 5 1 z h m 0 2 - z h k 2 1 1 8 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 0 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 9 8s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n t able 6b. ac c haracteristics , v cc = v cca = 3.3v5%, v cco_lvcmos , v cco_l vpecl = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 4 4 . 9 10 0 7z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i , z h m 2 5 . 5 5 1 z h m 0 2 - z h k 2 1 3 8 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 9s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 9s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 8 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t ypical p hase n oise at 155.52mh z 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.81ps (typical) o ffset f requency (h z ) n oise p ower dbc hz ? ? ? 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m filter raw phase noise data phase noise result by adding filter to raw data
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 9 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary p arameter m easurement i nformation o utput s kew 3.3v c ore /2.5v lvpecl o utput l oad ac t est c ircuit 3.3v c ore /3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx lvpecl 2.8v0.04v o utput r ise /f all t ime -0.5v 0.125v t sk(o) nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% qa, qb nqa, nqb v ee v cc , v cca phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power v cco_l vpecl 2v o utput d uty c ycle /p ulse w idth /tp eriod v cmr cross points v pp v ee nclk0, nclk1 nclk0, nclk1 v cc d ifferential i nput l evel p hase j itter scope qx nqx lvpecl -1.3v 0.165v v ee v cc , v cca, v cco_l vpecl 2v
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 10 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary a pplication i nformation d escription of the pll s tages the ics843002i-41 is a two stage device, a vcxo pll followed by a low phase noise femtoclock pll. the vcxo uses an external pullable crystal which can be pulled 100ppm by the vcxo pll circuitry to phase lock it to the input reference frequency. the femtoclock pll is a wide bandwidth pll (about 800khz) which means it will phase track the vcxo pll. most of the reference clock jitter attenuation needs to be accomplished by vcxo pll. by using the bypass femtoclock pll mode (table 3b), the selected input reference clock can be passed directly to the femtoclock pll which will multiply it up by 32 to a higher frequency. a second mode, vcxo and femtoclock bypass, routes the selected input refrence directly to the lvpecl output dividers. vcxo pll l oop r esponse c onsiderations loop response characteristics of the vcxo pll is affected by the vcxo feedback divider value (bandwidth and damp- ing factor), and by the external loop filter components (bandwidth, damping factor, and 2 nd frequency response). a practical range of vcxo pll bandwidth is from about 10hz to about 1khz. the setting of vcxo pll bandwidth and damping factor is covered later in this document. a pc based pll bandwidth calculator is also under devel- opment. for assistance with loop bandwidth suggestions or value calculation, please contact ics applications. s etting the vcxo pll l oop r esponse the vcxo pll loop response is determined both by fixed device characteristics and by other characteristics set by the user. this includes the values of r s , c s , c p and r set as shown in the external vcxo pll components figure on this page. the vcxo pll loop bandwidth is approximated by: w here : r s = value of resistor r s in loop filter in ohms i cp = charge pump current in amps (see table on page 12) k o = vcxo gain in hz/v the above equation calculates the ?normalized? loop bandwidth (denoted as ?nbw?) which is approximately equal to the - 3db bandwidth. nbw does not take into account the effects of damping factor or the second pole imposed by c p . it does, however, provide a useful approximation of filter performance. to prevent jitter on the clock output due to modulation of the vcxo pll by the phase detector frequency, the following general rule should be observed: ? (phase detector) = input frequency (r divider x 32) the pll loop damping factor is determined by: w here : c s = value of capacitor c s in loop filter in farads nbw (vcxo pll) = r s x i cp x k o 32 nbw (vcxo pll) ? (phase detector) 20 df (vclk) = x r s 2 i cp x c s x k o 32
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 11 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary n otes on s etting the v alue of c p as another general rule, the following relationship should be maintained between components c s and c p in the loop filter: c p establishes a second pole in the vcxo pll loop filter. for higher damping factors (> 1), calculate the value of c p based on a c s value that would be used for a damping factor of 1. this will minimize baseband peaking and loop instability that can lead to output jitter. c p also dampens vcxo pll input voltage modulation by the charge pump correction pulses. a c p value that is too low will result in increased output phase noise at the phase detector frequency due to this. in extreme cases where input jitter is high, charge pump current is high, and c p is too small, the vcxo pll input voltage can hit the supply or ground rail resulting in non- linear loop response. the best way to set the value of c p is to use the filter response software under development from ics (please refer to the following section). c p should be increased in value until it just starts affecting the passband peak. l oop f ilter r esponse s oftware online tools to calculate loop filter response (coming soon) at www .icst.com. contact your local sales representative if a tool cannot be found for this product. n otes on e xternal c rystal l oad c apacitors in the loop filter schematic diagram, capacitors are shown be- tween pins 32 to ground and between pins 31 to ground. these are optional crystal load capacitors which can be used to cen- ter tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). note that the addition of external load capacitors will decrease the crystal pull range and the kvco value. c p = c s 20 1 2 3 32 31 lf1 lf0 iset c s r s c p r set the external crystal devices and loop filter components should be kept close to the device. loop filter and crystal pcb connection traces should be kept short and well separated from each other and from other signal traces. other signal traces should not run underneath the device, the loop filter or crystal components. e xternal vcxo pll c omponents in general, the loop damping factor should be 0.7 or greater to ensure output stability. a higher damping factor will create less peaking in the passband. a higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the pll to respond to and therefore compensate for phase noise ingress. the lor0 and lor1 pins are controlled by the internal clock activity monitor circuits. the clock activity monitor circuits are clocked by the vcxo pll phase detector feedback clock. the lor output is asserted high if there are three consecutive feedback clock edges without any reference clock edges (in both cases, either a negative or positive transition is counted l oss of r eference i ndicator (lor0 and lor1) o utput p ins . as an ?edge?). the lor output will otherwise be low. the activity monitor does not flag excessive reference transitions in an phase detector observation interval as an error. the monitor only distinguishes between transitions occurring and no transi- tions occurring.
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 12 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary n otes on s etting c harge p ump c urrent the recommended range for the charge pump current is 50 a to 300 a. below 50 a, loop filter charge leakage, due to pcb or capacitor leakage, can become a problem. this loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. 1e-3 100e-6 10e-6 1k 10k 100 k r set , i cp , amps r t e s i ( t n e r r u c p m u p e g r a h c p c ) k 6 . 7 1a 5 . 2 6 k 8 . 8a 5 2 1 k 4 . 4a 0 5 2 k 2 . 2a 0 0 5 f igure 1. c harge p ump c urrent vs . v alue of r set ( external resistor ) g raph as can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ics, increasing charge pump current (i cp ) increases both bandwidth and damping factor. c harge p ump c urrent , e xample s ettings
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 13 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t ermination for 2.5v lvpecl o utput figure 3a and figure 3b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminat- ing 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 3b can be eliminated and the termination is shown in figure 3c. f igure 3c. 2.5v lvpecl t ermination e xample f igure 3b. 2.5v lvpecl d river t ermination e xample f igure 3a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + - as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843002i-41 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 14 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 15 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary f igure 5c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 5a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 5a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v f igure 5e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 16 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary s ingle e nded c lock i nput i nterface when using a lvcmos or lvttl clock driver, the clock input is connected to the clkx (clk0 or clk1) input pin. the nclkx (nclk0 or nclk1) pin is left unconnected. to help reduce interference with the internal vco circuits, an external resistor can be placed in series with the clock signal right near the clkx input pin. combined with the input pin capacitance, this resistor acts as a low pass signal filter. the typical value for this optional series filter resistor is 100 . this will lower both the amplitude and edge rate of the clock input signal. in the case of a very short clock trace a series termination resistor may not be needed. f igure 6. s ingle -e nded c lock i nput i nterface 3.3v clk nclk 3.3 v (no connection) differential input stage lvttl or lvcmos series termination optional series filter resistor nclkx clkx internal device circuitry external circuitry 50k 50k 50k
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 17 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843002i-41. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843002i-41 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 175ma = 606.375mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 606.375mw + 60mw = 666.38 mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming an air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 34.8c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.666w * 34.8c/w = 108.2c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 32- pin vfqfn, f orced c onvection ja vs. air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 34.8c/w
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 18 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ) * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ) * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 7. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 19 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary r eliability i nformation t ransistor c ount the transistor count for ics843002i-41 is: 5536 t able 8. ja vs . a ir f low t able for a 32 l ead vfqfn ja vs. air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 34.8c/w
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 20 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary p ackage o utline - k s uffix for a 32 l ead vfqfn t able 9. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 0 . 5 2 e 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0
843002aki-41 www.icst.com/products/hiperclocks.html rev. a june 1, 2005 21 integrated circuit systems, inc. ics843002i-41 700mh z , f emto c locks ? vcxo b ased sonet/sdh j itter a ttenuator preliminary t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and f emto c locks are trademarks of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 4 - i k a 2 0 0 3 4 8 s c i1 4 a 2 0 0 3 4 s c in f q f v d a e l 2 3y a r tc 5 8 o t c 0 4 - t 1 4 - i k a 2 0 0 3 4 8 s c i1 4 a 2 0 0 3 4 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 -

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