1 ? HA-2540 400mhz, fast settling operational amplifier the intersil HA-2540 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is 10 or greater. additionally, the HA-2540 has a drive capability of 10v into a 1k ? load. other desirable characteristics include low input voltage noise, low offset voltage, and fast settling time. a 400v/ s slew rate ensures high performance in video and pulse amplification circuits, while the 400mhz gain- bandwidth product is ideally suited for wideband signal amplification. a settling time of 140ns also makes the HA-2540 an excellent selection for high speed data acquisition systems. refer to application note an541 and application note an556 for more information on high speed op amp applications. pinout HA-2540 (cerdip) top view features ? very high slew rate . . . . . . . . . . . . . . . . . . . . . . 400v/ s ? fast settling time . . . . . . . . . . . . . . . . . . . . . . . . . . 140ns ? wide gain bandwidth (a v 10). . . . . . . . . . . . . . 400mhz ? power bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mhz ? low offset voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mv ? input voltage noise . . . . . . . . . . . . . . . . . . . . . . . 6nv/ hz ? output voltage swing . . . . . . . . . . . . . . . . . . . . . . . 10v ? monolithic bipolar construction applications ? pulse and video amplifiers ? wideband amplifiers ? high speed sample-hold circuits ? fast, precise d/a converters for a lower power version of this product, please see the ha-2850 datasheet. nc nc nc -in +in v- nc nc nc nc v+ output nc nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - ordering information part number temp. range ( o c) package pkg. dwg. # ha1-2540-5 0 to 75 14 ld cerdip f14.3 data sheet july 2003 fn2897.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum rati ngs thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . 35v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v output current . . . . . . . . . . . . . . 33ma rms continuous, 50ma peak operating conditions temperature range HA-2540-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 2) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 75 20 maximum internal power dissipation (note 1) maximum junction temperature (ceramic package) . . . . . . 175 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. maximum power dissipation with load co nditions must be designed to maintain t he maximum junction temperature below 175 o c for the ceramic package, and below 150 o c for the plastic package. by using a pplication note an556 on safe operati ng area equations, along with the thermal resistances, proper load conditi ons can be determined. heat sinking is recommended above 75 o c. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications v supply = 15v, r l = 1k ? , c l < 10pf, unless otherwise specified parameter temp ( o c) min typ max units input characteristics offset voltage 25 - 8 15 mv full - 13 20 mv average offset voltage drift full - 20 - v/ o c bias current 25 - 5 20 a full - - 25 a offset current 25 - 1 6 a full - - 8 a input resistance 25 - 10 - k ? input capacitance 25 - 1 - pf common mode range full 10 - - v input noise current (f = 1khz, r source = 0 ? )25-6-pa/ hz input noise voltage (f = 1khz, r source = 0 ? )25-6-nv/ hz transfer characteristics large signal voltage gain (note 3) 25 10 15 - kv/v full 5 - - kv/v common-mode rejection ratio (note 4) full 60 72 - db minimum stable gain 25 10 - - v/v gain bandwidth product (notes 5, 6) 25 - 400 - mhz output characteristics output voltage swing (notes 3, 10) full 10 - - v output current (note 3) 25 10 20 - ma output resistance 25 - 30 - ? full power bandwidth (notes 3, 7) 25 5.5 6 - mhz transient response (note 8) rise time 25 - 14 - ns overshoot 25 - 5 - % slew rate 25 320 400 - v/ s settling time: 10v step to 0.1% 25 - 140 - ns HA-2540
3 power requirements supply current full - 20 25 ma power supply rejection ratio (note 9) full 60 70 - db notes: 3. r l = 1k ? , v o = 10v. 4. v cm = 10v. 5. v o = 90mv. 6. a v = 10. 7. full power bandwidth guaranteed based on slew rate measurement using: . 8. refer to test circuits section of the data sheet. 9. v supply = +5v, -15v and +15v, -5v. 10. guaranteed range for output voltage is 10v. functional operation outside of this range is not guaranteed. electrical specifications v supply = 15v, r l = 1k ? , c l < 10pf, unless otherwise specified (continued) parameter temp ( o c) min typ max units fpbw slew rate 2 v peak --------------------------- = test circuits and waveforms figure 1. large and small signal response test circuit large signal response small signal response figure 2. settling time test circuit v in 900 100 v out - + notes: 11. a v = +10. 12. c l 10pf. a b vertical scale: a = 0.5v/div., b = 5.0v/div. horizontal scale: 50ns/div. vertical scale: input = 10mv/div.; output = 50mv/div. horizontal scale: 20ns/div. 0.001 f 1 f 0.001 f 1 f 2k ? 5k ? 500 ? 200 ? v+ v- - + probe monitor output input settle point notes: 13. a v = -10. 14. load capacitance should be less than 10pf. turn on time delay typically 4ns. 15. it is recommended that resistors be carbon composition and the feedback and summing network ratios be matched to 0.1%. 16. settle point (summing node) capacitance should be less than 10pf. for optimum settling time results, it is recommended that the test circuit be construct ed directly onto the device pins. a tektronix 568 sampling oscill oscope with s-3a sampling heads is recommended as a settle point monitor. HA-2540
4 schematic diagram output r 3 r 24 r 13 q p28 q p18 q p19 q p17 q p22 q p6 q p5 q p25 q p3 q p4 r 6 r 7 r 8 r 9 q n1 q n2 r 11 r 12 r 14 r 25 v+ r 10 q n14 q n20 q n15 q n25 q n29 v+ r 21 r 22 q p23 q n21 + input - input z 1 d z1 d z2 q p8 q n9 q n7 q n10 q n13 r 4 r5 c 2 v+ r 19 r 18 q n16 q n12 r 17 r 16 r 15 q p11 c 1 r c2 v- v- v- r 23 r 1 r 2 typical applications figure 3. wideband signal splitter figure 4. bootstrapping for more output current and voltage swing refer to application note an541 for further application information. HA-2540 + 200 v+ v- 2k 2k offset adjust - note: with one HA-2540 and two low capacitance switching diodes, signals exceeding 10mhz can be separated. this circuit is most useful for full wave rectification, am detectors or sync generation. notes: 17. used for experimental purposes. c f ? 3pf. 18. c 1 is optional (0.001 f 0.01 f ceramic). 19. r 5 is optional and can be utilized to reduce input signal amplitude and/or balance input conditions. r 5 = 500 ? to 1k ? . HA-2540 v+ v- c f (note 17) c 1 (note 18) 1k 1k r 5 10k r 1 4k r 2 4k signal out 0.1 f r 3 4k r 4 4k (note 19) - + HA-2540
5 typical performance curves figure 5. closed loop frequency response f igure 6. output voltag e swing vs frequency figure 7. output voltage swin g vs load resistance figure 8. normalized ac parameters vs temperature figure 9. settling time for various output step voltages figure 10. power supply current vs temperature frequency (hz) closed loop gain (db) 100 1k 10k 100k 1m 10m 100m -10 10 30 40 50 60 70 80 90 100 0 20 frequency (hz) output voltage swing (v p-p ) 1k 10k 100k 1m 10m 100m 0 4 8 12 16 20 24 28 v s = 15v v s = 10v v s = 5v output voltage swing (v p-p ) resistance ( ? ) 0 200 400 600 800 1k 1.2k 0 4 8 12 16 24 28 20 temperature ( o c) normalized parameters referred to values at 25 o c -80 -40 0 40 80 120 160 slew rate bandwidth 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 settling time (ns) output voltage step (v) 080 40 120 160 200 240 -10 -8 -6 -4 -2 2 4 6 8 10 10mv 1mv 10mv 1mv 0 temperature ( o c) -80 -40 0 40 80 120 160 0 4 8 12 16 24 28 20 supply current (ma) v s = 15v v s = 5v HA-2540
6 figure 11. input offset voltage and bias current vs temperature figure 12. input noise voltage and noise current vs frequency figure 13. broadband noise (0.1hz to 1mhz) figure 14. common mode rejection ratio vs frequency figure 15. power supply rejectio n ratio vs frequency figure 16. open loop gain/phase vs frequency typical performance curves (continued) temperature ( o c) -80 -40 0 40 80 120 160 0 2 4 6 8 12 14 10 input bias current ( a) bias current offset voltage 0 1 2 3 4 6 7 5 |v io | offset voltage (mv) 0 5 10 15 20 25 100 1k 10k 100k 10 0 10 20 30 40 50 noise voltage (nv/ hz ) noise current (pa/ hz ) voltage current noise r source = 0 ? , v s = 15 noise frequency (hz) +40 v +20 v +10 v 0 v -10 v -20 v -30 v -40 v +30 v vertical scale: 10mv/div. horizontal scale: 50ms/div. frequency (hz) 1k 10k 100k 1m 10m 0 20 40 60 80 100 120 v s = 15, r l = 1k cmrr (db) frequency (hz) 1k 10k 100k 1m psrr (db) 0 20 40 60 80 100 positive supply negative supply 10m frequency (hz) 100 10k 100k 1m 10m 100m 1k -10 0 20 40 60 80 100 open loop gain (db) 225 180 135 90 45 0 gain phase phase (degrees) HA-2540
7 die characteristics die dimensions: 62 mils x 76 mils x 19 mils 1575 mx 1930 m x 483 m metallization: type: al, 1% cu thickness: 16k ? 2k ? passivation: type: nitride (si 3 n 4 ) over silox (sio 2 , 5% phos.) silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1.5k ? substrate potential (powered up): v- transistor count: 30 process: bipolar dielectric isolation metallization mask layout HA-2540 v+ output v- +in -in - in + in HA-2540
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HA-2540 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94
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