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CXA1166K
8-bit 250 MSPS Flash A/D Converter For the availability of this product, please contact the sales office.
Description The CXA1166K is an 8-bit ultrahigh-speed flash A/D converter IC capable of digitizing analog signals at a maximum rate of 250 MSPS. The digital I/O level of this A/D converter is compatible with the ECL 100K/10KH/10K. This IC is pin-compatible with the conventional CXA1076AK/CXA1176K/CXA1176AK, and can replace the conventional models easily. Compared with the conventional models, the CXA1166K has a greatly improved performance because of the new circuit design and carefully considered layout. Features * Differential linearity error: 0.5 LSB or less * Integral linearity error: 0.5 LSB or less * Built-in integral linearity compensation circuit * Ultrahigh-speed operation with maximum conversion rate of 250 MSPS * Low input capacitance: 18pF * Wide analog input bandwidth: 250MHz (full-scale input, standard) * Single power supply: -5.2V * Low power consumption: 1.4W (Typ.) * Low error rate * Good temperature characteristics * Capable of driving 50 loads 68 pin LCC (Ceramic)
Structure Bipolar silicon monolithic IC Applications * Digital oscilloscopes * Other apparatus requiring ultrahigh-speed A/D conversion
Pin Configuration (Top View) Pins without name are NC pins (not connected internally).
AGND VIN1 VIN1 AGND VRM AGND VIN2 VIN2 AGND AVEE
AGND AVEE VRT VRTS AVEE AVEE LINV OR OR D0 D0 D1 D1 DVEE 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 AGND AVEE VRB VRBS AVEE AVEE CLK CLK MINV D7 D7 D6 D6 DVEE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
D2 D2 D3 D3 DGND2 DGND2 DGND1 D4 D4 D5 D5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
-1-
E90406-ST
CXA1166K
Absolute Maximum Ratings (Ta = 25C) * Supply voltage AVEE, DVEE * Analog input voltage VIN * Reference input voltage VRT, VRB, VRM | VRT - VRB | * Digital input voltage MINV, LINV, CLK, CLK | CLK - CLK | * VRM pin input current IVRM * Digital output current ID0 to ID7, IOR, ID0 to ID7, IOR * Storage temperature Tstg Operating Conditions * Supply voltage Min. -5.5 -0.05 -0.05 -0.1 -2.2 VRB -20
-7 to +0.5 -2.7 to +0.5 -2.7 to +0.5 2.5 -4 to +0.5 2.7 -3 to +3 -30 to 0 -65 to +150 Typ. -5.2 0 0 0 -2.0 Max. -4.95 0.05 0.05 0.1 -1.8 VRT 100
V V V V V V mA mA C Unit V V V V V C
* Reference input voltage * Analog input voltage * Operating temperature
AVEE, DVEE AVEE - DVEE AGND - DGND VRT VRB VIN Tc
-2-
CXA1166K
Block Diagram
MINV 33 r1 VRT 64 r/2 r2 VRTS 65 r r r 0 1 2 * * * 63 64 r 65 * * * 126 127 128 129 * * * 191 192 r r r4 VRBS 39 r5 VRB 40 r r/2 193 * * * 254 255 31 D7 (MSB) 32 D7 29 D6 30 D6 21 D5 22 D5 2 OR 3 OR Comparator
VIN1 54
r
55
r r r3 VRM 52 r r
ENCODE LOGIC
OUTPUT
19 D4 20 D4 14 D3 15 D3 12 D2 13 D2 6 D1 7 D1 4 D0 (LSB) 5 D0
r r VIN2 49
50
CLK 35 CLK 34
CLOCK DRIVER
1 LINV
-3-
CXA1166K
Pin Description Pin No. Symbol I/O
Standard voltage level
DGND1 18
Equivalent circuit
Description Polarity selection other than MSB and overrange. (Refer to the table of input voltage vs. Digital output) Low level is maintained with left open.
-1.3V
1
LINV
I
ECL
LINV or 1
r r r
33 MINV
33
MINV
I
ECL
DVEE 8 28
r
Polarity selection for MSB (Refer to the table of input voltage vs. Digital output) Low level is maintained with left open. Reference voltage (Top) (0V typ.) Reference voltage sense (Top)
64
VRT
I
0V
VRT 64 r2 VRTS 65
r1 r2
65
VRTS
O
0V
r3
r
52
VRM
I
VRB/2
VRM 25
r
To Comparator
Reference voltage mid-point. Can be used for linearity compensation. Reference voltage sense (Bottom) Reference voltage (Bottom)
39
VRBS
O
-2V
r4 VRBS 39
r r 2 r5 VRB 40 43, 48, 51, 53, 56, 61 AGND
40
VRB
I
-2V
VIN1
54 55
VIN1 I VRTS to VRBS
54 55 49 50 VIN2 To Comp 0 to 127 128 to 255
49 50
Analog input. Pins 49, 50 and Pins 54, 55 should be connected externally.
VIN2
DGND1
35
CLK
I
ECL
18 r r CLK 35 CLK 34 r r
CLK input
34
CLK
I
ECL
DVEE 8 28 r r
Complementary CLK input. ECL threshold potential (-1.3V) is maintained with left open. The complementary input is recommended for stable operation at high speed though the operation only with the CLK input is possible when the CLK input is left open.
-4-
CXA1166K
Pin No. 31 32 29 30 21 22 19 20 14 15 12 13 6 7 4 5
Symbol D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
I/O O O O O O
Standard voltage level
Equivalent circuit
Description MSB and complementary MSB output
DGND2 16 17
Di Di
D1 to D6: Output D1 to D6: Complementary output
ECL O O
DVEE
8 28
O
LSB and complementary LSB output Overrange output; Low level for overrange. Overrange complementary output; High level for overrange.
2 3
OR OR
O
37, 38, 42, 58, AVEE 62, 66, 67 43, 48, 51, 53, AGND 56, 61 8 28 18 16 17 DVEE
AGND
-5.2V
61 48 53 DGND1 43 51 56 18
DGND2 16 17
Analog supply. Internally connected with DVEE (resistance: 4 to 6).
0V
Internal Analog Circuit
Internal Digital Circuit Di Di
Analog ground. Separated from DGND. Digital supply. Internally connected with AVEE (resistance: 4 to 6). Digital ground Digital ground for output drive No connected. It is recommended to connect these pins to AGND.
-5.2V
4 to 6 42 37 58 8 28 DVEE
DGND1 DGND2
0V 0V
62 38 66 67 AVEE
41, 44, 45, 46, 47, 57, NC 59, 60, 63 9, 10, 11, 23, 24, 25, NC 26, 27, 36, 68
--
--
No connected. It is recommended to connect these pins to DGND.
For stable operation, all of these pins must be connected on the corresponding PCB pattern. -5-
CXA1166K
Electrical Characteristics Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Input bias current Reference inputs Reference resistance Residual resistance1 r1 r2 r3 r4 r5 Digital inputs Logic High level Logic Low level Logic High current Logic Low current Input capacitance Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Output delay Clock High pulse width Clock Low pulse width Digital output Logic High level Logic Low level Output rise time Output fall time Dynamic characteristics Input bandwidth SNR EIL EDL CIN RIN IIN RREF r1 r2 r3 r4 r5 VIH VIL IIH IIL Symbol
(AVEE = DVEE = -5.2V, VRT, VRTS = 0V, VRB, VRBS = -2V, Ta = 25C) Condition Min. Typ. 8 0.5 0.5 VIN = -1V + 0.07Vrms VIN = -1V VIN = -1V 18 120 450 125 0.6 500 2.0 500 0.6 182 2.0 700 5.0 700 2.0 Max. Unit bits LSB LSB pF k A V V A A pF MSPS ps ns ns ns ns V V ns ns MHz dB dB 10-9 TPS2
50 20 83 0.1 300 0.5 300 0.1 -1.13
VIH = -0.8V VIL = -1.6V
0 -50 4
-1.50 70 50
Fc Taj Tds Tdo TPW1 TPW0 VOH VOL Tr Tf
250 0.4 1.8 1.8 1.8 -1.00 0.6 0.6 200 44 30 -1.60 1.5 1.5 9 1.4 2.5 2.4 3.2
RL = 50 to -2V
} TPW1 + TPW0 = 4.0ns
RL = 50 to -2V RL = 50 to -2V RL = 50 to -2V RL = 50 to -2V VIN=2Vp-p Input = 1kHz, FS Clock = 250MHz Input = 62.499MHz, FS Clock = 250MHz Input = 49.999MHz, FS Error > 16LSB Clock = 200MHz Input = 62.499MHz, FS Error > 16LSB Clock = 250MHz NTSC 40IRE mod. ramp, Fc = 250MSPS
SNR
{ {
46 35
Error rate
{ {
DG DP IEE Pd
10-8
10-6
TPS2
Differential gain error Differential phase error Power supply Supply current Power consumption3 1 See Block Diagram. 2 TPS: Times Per Sample 2 3 Pd = IEE * VEE + (VRT - VRB) RREF
}
1.0 0.5 -360 -270 1.4
% deg mA W
1.9
-6-
CXA1166K
Input Voltage vs. Digital Output VIN Step 0 0 1 1 1 MINV LINV OR D7 0V 1 1 D0 OR D7 0 1 1 0 1 D0 OR D7 0 1 1 1 0 D0 OR D7 0 1 1 0 0 D0
0 0 0 ...... 0 0 0 0 0 ...... 0 0 0 0 0 ...... 0 1 : : 0 1 1 ...... 1 1 1 0 0 ...... 0 0 : : 1 1 1 ...... 1 0 1 1 1 ...... 1 1 1 1 1 ...... 1 1
1 0 0 ...... 0 0 1 0 0 ...... 0 0 1 0 0 ...... 0 1 : : 1 1 1 ...... 1 1 0 0 0 ...... 0 0 : : 0 1 1 ...... 1 0 0 1 1 ...... 1 1 0 1 1 ...... 1 1
0 1 1 ...... 1 1 0 1 1 ...... 1 1 0 1 1 ...... 1 0 : : 0 0 0 ...... 0 0 1 1 1 ...... 1 1 : : 1 0 0 ...... 0 1 1 0 0 ...... 0 0 1 0 0 ...... 0 0
1 1 1 ...... 1 1 1 1 1 ...... 1 1 1 1 1 ...... 1 0 : : 1 0 0 ...... 0 0 0 1 1 ...... 1 1 : : 0 0 0 ...... 0 1 0 0 0 ...... 0 0 0 0 0 ...... 0 0
-1V
127 128
254 255 -2V
1 1 : : 1 1 1
1 1 : : 1 1 1
1 1 : : 1 1 1
1 1 : : 1 1 1
VRT = VRTS = 0V, VRM = -1V or Open, VRB = VRBS = -2V
Timing Diagram
Tds
N Analog input
N+1
N+2 Tpw1 CLK CLK Tpw0
Digital output Td
N-1
20%
80%
N
80%
N+1 20% Tf
Tr
-7-
CXA1166K
Electrical Characteristics Measurement Circuit Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit
+V S2 S1:ON when AB
S1
-V AB Comparator VIN DUT CXA1166K 8 A8 to A1 A0 "0" DVM Controller B8 to B1 B0 "1 " 000***00 to 111***10 8 Buffer
Sampling Delay Measurement circuit Aperture Jitter Measurement circuit
60MHz Amp OSC1 :Variable VIN fr CLK OSC2 ECL Buffer 60MHz 1024 samples CXA1166K 8 Logic Analizer
Aperture Jitter Measurement Method
0V VIN -1V -2V
CLK t VIN 129 128 127 126 125
t
(LSB)
CLK
Sampling timing fluctuation ( = aperture jitter)
When the distribution of the output codes is (unit: LSB) If the maximum slew rate point is sampled with the clock signal having the same frequency as that of the analog input signal, Aperture jitter (Taj) is defined as follows: Taj = / 256 = / ( x 2f ) t 2
-8-
CXA1166K
Error Rate Measurement Circuit
Signal Source Vin 8 ECL Latch + ECL Latch A B Comparator ACXA1166K CLK CLK
fCLK - 1kHz 4 2Vp - p Sine Wave
DATA 16 Signal Source fCLK 116
Differential Gain Error Measurement Circuit Differential Phase Error Measurement Circuit
(CX20202A - 1) NTSC Signal Source
Amp
DUT CXA1166K CLK CLK
8
ECL Latch
8
10bit DA
SG (CW) 50 VBB
Decimator
Vector Scope
Power Supply Current Measurement Circuit Analog Input Bias Current Measurement Circuit
IIN
A
- 1V
60 61
44 43 - 2V
1
CXA1166K
9
10
27 26
A IEE
- 5.2V
-9-
CXA1166K
Notes on Operation * The CXA1166K is an ultra-high speed A/D converter featuring ECL level of input/output for the logic block. In order to derive the most from its high-speed performance, the characteristic impedance should be matched properly. * The outputs are designed to drive a load terminated to -2V at 50. An excellent transmission characteristic can be yielded by designing the printed circuit board with a 50 characteristic impedance. Yielding its top performance is difficult on the printed circuit board with a characteristic impedance of 100 or more. * The power supply and ground pattern greatly affect the characteristics of the converter. The higher the frequency, the more important these connections become. The general precautions are as follows. - Make the pattern of the power supply and ground as wide as possible. Using a ground plane inner layer by using a multilayer printed circuit board is recommended. - lsolate the AGND, DGND pins and the AVEE, DVEE from one another on the pattern in order to safeguard against interaction. Connect the AGND and DGND pins at one place using a ferrite-bead filter to prevent DC offset. The same processing is requited for the AVEE and DVEE pins. * When mounting the A/D converter on the socket, use the one of shortest leads. The QFP socket, the type name IC61-0684-048, manufactured by YAMAICHI ELECTRONICS CO., LTD. is recommended. * The VIN analog input pins have somewhat large input capacitance (approximately 18pF) for high-frequency circuits. In order to drive them with an excellent frequency response, it is necessary to safeguard against any deterioration in performance resulting from parasitic capacitance and parasitic inductance by using a highcapacity drive circuit, keeping the wiring as short as possible, and using chip parts as resistors and capacitors, for instance. The drive circuit shown in the Application Circuit has a virtually flat frequency response up to approximately 170MHz. C89, R11 and C15 have been inserted mainly to expand the bandwidth, while R10 has been inserted mainly to suppress operational amplifier oscillation and block peaking of the frequency response. Since the optimal values of these elements differ depending on the printed circuit board pattern and mounting condition of the A/D converter socket used, they must be determined on the basis of experimentation. * Connect all four VIN pins directly and as short as possible. Unlike the CXA1176, it is not necessary to insert resistance of several ohms for each pin. * The voltage at the VRT and VRB reference voltage pins and the reference voltage inside these pins differ slightly due to residual resistance. VRTS and VRBS are provided to detect the reference voltage inside the pins. The overrange reference voltage is 1/2 LSB down from VRTS; the lowest input voltage at which the output code changes is 1/2 LSB up from VRBS. * Provide adequate by-pass capacitors for VRT and VRB to protect them from high-frequency noise. Normally, VRT is connected to AGND of an inner layer of the printed circuit board. Using a chip capacitor (approximately 0.1F), make the by-pass from VRB to AGND as short as possible. C22 (1F), in the Application Circuit is for suppressing the oscillation of the reference voltage generation circuit.
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CXA1166K
* Unlike the CXA1176, VRTS and VRBS are connected to the reference resistors via resistors of approximately 500. Since these resistors may be eliminated in the future improved versions of this converter, use a reference voltage generation circuit which is adaptable to their elimination. The reference voltage generation circuit (the section composed of IC12_2, etc.) in the Application Circuit is recommended. * Although VRM is provided to compensate for the integral linearity error, there is no need for such compensation. It is recommended that it is kept open. * OR and OR are output pins for indicating that the input is over range. They are not inverted by MINV or LINV. * Noise in MINV and LINV results in misoperation, the cause of which is extremely difficult to track down. Keep these pins open in cases where low level setting voltage alone is sufficient. When high level voltage input is required, provide the shortest possible by-pass from them to DGND using chip capacitors (approximately 0.1F). Input voltages of -0.5V to -1.0V for high level and -1.6V to -2.5V for low level are recommend. Do not make the direct connection to DGND when high level voltage is input. * Inputting differential signals is recommended for the CLK and CLK clock input pins. Although operation is possible by driving only the CLK pin, doing so involves the risk that the characteristics may become unstable near the maximum speed. This is because the internal operation of the A/D converter depends on both clock rise and fall. * When the CLK pin is not used, by-pass it to DGND using a capacitor (approximately 0.1F). At this time, approximately -1.3V voltage will be generated at this pin. However, the driving capacity is too weak for this to be used as the VBB threshold voltage. It cannot drive even one ECL input load. * This converter is designed to be used at the clock duty cycle of 50%. The deviation from this condition will subtly affect the performance of the A/D converter but the degree of the affection is not so great as to require adjustment. The "Error rate vs. Clock duty cycle characteristics" graph shows an example of these changes in the converter's performance. * Increasing chip temperature will cause the supply current and also the error rate to rise. Adding to these reasons, in order to prolong the converter's service life, provide an adequate means of cooling. See the "Maximum conversion frequency vs. Temperature characteristics" and "Supply current vs. Temperature characteristics" graphs. The reference data for thermal resistance is shown in the "Thermal resistance of the converter mounted on a board" graph. Note that the actual thermal resistance will differ greatly depending on the mounting conditions. * Since the CXA1166K is a high-speed IC, take adequate measures to prevent electrostatic breakdown. For further details on these measures, refer to "Precautions for IC Application" in Sony's Data book. * Sony's SPECL series is used as the logic ICs in the Application Circuit to investigate the maximum performance of the CXA1166K. For normal applications, lower speed logic ICs can be used according to the applied frequency.
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CXA1166K
Example of Representative Characteristics
Thermal resistance at on-board condition
50 Socket for YAMAICHI ELECTRONICS IC61-0684-048 Socket for AMP173061-5 (without heat sink) Socket for AMP173257-3 (with heat sink) 25
VIN pin input capacitance vs. Voltage characteristics
ja -- Thermal resistance [C/W]
40
CIN -- Input capacitance [pF]
20
30
15
0
1.0
2.0 Air velocity [m/s]
3.0
10
-2
-1.5
-1
-0.5
0
VIN -- Input voltage [V]
VIN pin input resistance vs. Voltage characteristics
150 200
VIN pin input current vs. Voltage characteristics
Analog input resistance [k]
IIN [A]
125
100
100
0 -2.0
-1.5
-1.0
-0.5
0
VIN -- Input voltage [V]
-2.0
-1.5
-1.0
-0.5
0
VIN -- Input voltage [V]
- 12 -
CXA1166K
VIN pin input current vs. Temperature characteristics
200
VIN -- Input current [A]
150
100
50
0 -50
0
50 Tc -- Case temperature [C]
100
150
Resistor string current vs. Temperature characteristics
-12
-14
Resistor string current [mA]
-16
-18
-20
-22 -24 -50
0
50 Tc -- Case temperature [C]
100
150
CLK open voltage vs. Temperature characteristics
-1.25
-1.3
CLK open voltage [V]
-1.35
-1.4
-1.45 -50
0
50 Tc -- Case temperature [C]
100
150
- 13 -
CXA1166K
VOH vs. Temperature characteristics
-0.7
-0.8
VOH [V]
-0.9
-1.0
-1.1 -50
0
50 Tc -- Case temperature [C]
100
150
VOL vs. Temperature characteristics
-1.7
-1.8
VOL [V]
-1.9
-2.0
-2.1 -50
0
50 Tc -- Case temperature [C]
100
150
SNR vs. Input frequency response characteristics
50
45
SNR [dB]
40
35
30
25 1 10 Input frequency [MHz] 100
- 14 -
CXA1166K
Harmonic distortion vs. Input frequency response characteristics
Clock frequency : 250MHz -30 2nd harmonic distortion 3rd harmonic distortion
Harmonic distortion [dB]
-40
-50
-60
-70
-80 0.1 1 10 Input frequency [MHz] 100 1000
Maximum conversion rate vs. Temperature characteristics 300
250
CLK [MHz]
200
Error rate = 10-8TPS Input frequency = CLK frequency/4 - 1kHz 16LSB or more error
150
-25
25
75
125
Ta -- Ambient temperature [C]
- 15 -
CXA1166K
Error rate vs. Conversion rate
Input frequency = CLK frequency/4-1kHz 16LSB or more error 10-7
Error rate vs. Clock duty cycle
Error rate [TPS]
10-7 10-8
Error rate [TPS]
10-8
10-9
10-10
Input frequency = 125MHz, full-scale Clock frequency = 250MHz 16LSB or more error 200 250 300 10-9 25 30 35 40 45 50 55 60 65 70
CLK frequency [MHz]
CLK duty cycle [%]
Supply current vs. Temperature characteristics
-200
Supply current [mA]
-250
-300
-350 -50
0
50 Tc -- Case temperature [C]
100
150
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CXA1166K
8-bit, 250 MSPS ADC Evaluation Board The CXA1166K PCB is a tool for customers to evaluate the performance of the CXA1166K (8-bit, 250MHz, high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this tool equips the input voltage offset generator, clock decimator, output date latches, 10-bit high-speed DAC, and 20-pin cable connector for digital outputs. This evaluation board is designed to facilitate evaluation. Features * Resolution: 8 bits * Maximum conversion rate: 250 MSPS * Supply voltage: -5.2V, -4.5V, -2.0V, +5.0V * Clock level converter: Sine wave to ECL level signal * Reference voltage adjustment circuit for A/D converter * Built-in clock frequency decimation circuit: 1/1 to 1/128
Fig. 1. Block Diagram
VR2 (2k)
VRB - 2V
H VR3 (2k) SW4
L
VR1 (2k)
Vin OFFSET J1
SW5
DIGITAL OUT (CONNECTOR) 8 (D7 to D0)
LINV MINV VRB VIN CXA1166K CLK
8 (D7 to D0)
AMP.IN 53
X (- 2)
DATA 8 (D7 to D0) LATCH CLK
2 (CLK.CLK) 8 (D7 to D0) D/A OUT H INV L SW6
SW2 DELAY SW1 0.1 CLK 51 SW3 1/1 to 1/128 DECIMATOR
D/A CONVERTER CLK
+ 5V (A)
- 5.2V (A)
AGND
DGND
- 5.2V (D)
- 2V (D)
- 4.5V (D)
- 17 -
CXA1166K
Supply Current Item -5.2V +5.0V -4.5V -2.0 Min. Typ. 0.65 17 0.9 0.7 Max. 0.9 40 1.1 0.9 Unit A mA A A
Analog Input (AMP. IN) Item Input voltage (AMP.IN) Input impedance Min. -2.0 50 Typ. Max. 0 Unit V
( Adjustable with VR1)
Clock input (CLK) Item Input voltage (Peak to Peak) Input impedance Min. Typ. 2.0 50 Max. Unit Vp-p
Digital output (Digital OUT) ECL level Output Code Table MINV (SW5) LINV (SW4) 0V : : : : : : : : -2V 0 0 1 1 1 ...... 1 1 1 1 1 ...... 1 0 : : 1 0 0 ...... 0 0 0 1 1 ...... 1 1 : : 0 0 0 ...... 0 1 0 0 0 ...... 0 0 0 1 1 0 0 ...... 0 0 1 0 0 ...... 0 1 : : 1 1 1 ...... 1 1 0 0 0 ...... 0 0 : : 0 1 1 ...... 1 0 0 1 1 ...... 1 1 1: ECL High level, 0: ECL Low level 1 0 0 1 1 ...... 1 1 0 1 1 ...... 1 0 : : 0 0 0 ...... 0 0 1 1 1 ...... 1 1 : : 1 0 0 ...... 0 1 1 0 0 ...... 0 0 1 1 0 0 0 ...... 0 0 0 0 0 ...... 0 1 : : 0 1 1 ...... 1 1 1 0 0 ...... 0 0 : : 1 1 1 ...... 1 0 1 1 1 ...... 1 1
VIN
- 18 -
CXA1166K
Fig. 2. Timing Diagram
N A/D input pin (AMP. IN) Vin N+1 N+2
PCB input pin
CLK
CLK A/D clock CLK
D7 to D0 A/D output D7 to D0 N -1 N
PCB output pin (For 1/1 decimation)
D7 to D0
N -2 Tdh 1.8ns (Typ)
N -1
N
CLKN PCB output pin (For 1/1 decimation) CLK
PCB output pin (For 1/2 decimation)
D7 to D0
N -4
N -2 Tdh 1.8ns (Typ)
N
CLKN PCB output pin (For 1/2 decimation) CLK
Adjustment Methods and Notes on Operation 1) VIN Offset (VR1) The volume to adjust the AMP. IN signal range (0V center assumed) with the A/D converter input range. 2) A/D Full Scale (VR2) The volume to adjust A/D converter VRB voltage (-2V typ.). 3) Linearity (VR3) The volume to adjust the VRM (linearity) voltage by shorting the J1. - 19 -
CXA1166K
4) D/A Full Scale (VR4) The volume to adjust the bottom of D/A output full scale voltage (-1V typ.) 5) SW1 and SW2 Selection switches to adjust the clock delay. These switches enable clock delay to be stepped to any one of 128 settings (binary code of "0000000" to "1111111") through binary input. Approximately 163ps is delayed per one step. Normal evaluation requires the binary code of "0000000" (all of OFF), so that these switches are not mounted for shipment. 6) SW3 (Decimation) The switch to select clock frequency decimation. Selection settings are as follows. SW3 3 L L L L H H H H 2 L L H H L L H H Decimation ratio 1 L H L H L H L H 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128
H = ECL High level ; L = ECL Low level 7) SW4 The switch for LINV High/Low. 8) SW5 The switch for MINV High/Low. 9) SW6 (D/A INV) The switch for D/A converter output inversion.
- 20 -
CXA1166K
10) The waveform monitoring pins P6 through P39 are designed to make connection to GND easily in order to reduce distortion when monitoring the waveform with an oscilloscope. As shown in the diagram below, the distance between the measuring point and GND is 300mil, and each is equipped with a through hole of 1.2mm. When a Tektronix ground chip (part No. 013-1185-00) is mounted on the tip of a probe, the signal - GND positions match.
1.2mm GND Monitoring point
Fig. 3.
11) D/A converter (IC9) input data (waveform monitoring pins P28 to P35) are the negative logic signals of the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction (rise/fall) of reproduced waveform can agree with the A/D input signal's. 12) In order to maintain the accuracy of the reproduced waveform (waveform from A/D to D/A), set the decimator such that the clock frequency of the D/A converter (IC9: CX20201A-1) is less than 100MHz. 13) The input bandwidth weighs with the design of this PCB analog input circuit. Therefore, the SNR (signal-tonoise ratio) should be less significant. The input circuit example to improve the SNR is shown in Fig.4. See the measured data in Fig.s 6 to 8 for the SNR and the input circuit characteristics. 14) The part number of the digital output connector mounted on the PCB is KEL 8830E-020-170S. A corresponding connector and cable assembly is JUNKOSHA KB0020MCG50B1.
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CXA1166K
From offset circuit 560 5pF VIN2 VIN2 2 3pF 68 CLC409 3 120 VIN1 VIN1 AGND AGND VRB (- 2V) 6 30
240 AMP. IN
Fig. 4. Example of SNR Improvement Circuit
- 22 -
Fig. 5. Schematic Diagram
VRBS D6 P24 - 2V DGND (D) P25 P26 P27 C40 0.1 D6N D7 D7N P5 C39 0.1 R13 51 Linearity AVEE - 5.2V CLKA 18 17 16 15 14 Q1 Q2 12 Q2M 11 VCCA 10 VCC 9 Q3 8 Q3M 7 D3N D4 D4N Q4N Q4 DGND 1 3 5 7 R33 R34 R35 R36 51 51 51 51 R37 R38 R39 R40 51 51 51 51 - 2V DGND (D) C42 0.1 9 11 13 15 CLKB D2 D1 D2N D1N Q1 Q1N P39 19 CA Q2 12 20 CB Q2M 11 VCCA 10 VCC 9 Q3 8 D3N D4 D4N Q4N Q4 Q3M 7 4 3 5 6 DGND DGND IC8 CXB1109Q 21 VEE 22 VCCA 23 VBB D3 24 MR 1 2 18 17 16 15 14 13 17 19 CLK DGND CLKN DGND 18 20 Digital OUT D0 DGND (LSB) D1 D2 D3 D4 D5 D6 D7 DGND DGND DGND DGND DGND DGND DGND 2 4 6 8 10 12 14 16 5 6 R44 51 R42 R43 51 51 - 2V DGND (D) 16 15 14 13 IC5_3 R59 51 SW2 DELAY ADJ. 16 11 10 C6 C5 C26 0.1 C4 9 C3 8 C2 7 C1 6 IC3 CXB1159Q C0 5 F5 4 F4 3 F3 2 F2 1 DIN VEE VEE F0 F1 DINB - 2V (D) SW1 DELAY ADJ. DGND DOUT DGND GND GND 15 14 13 12 2 1 R60 51 C49 0.1 - 2V DGND (D) D0 P35 D1 P34 D2 P33 D3 P32 D4 P31 D5 P30 D6 P29 D7 P28 1 D1 AGND 28 R63 1k 2 D2 VREF 27 VR4 2k C50 0.1 3 D3 AVEE 26 C57 C58 C59 0.1 0.1 1 4 D4 DGND C51 0.1 - 2V (D) 13 12 11 10 VCC QON VCCA COUT C33 0.1 QO Q7 9 DGND 18 DOH 19 DOG 20 DOF 21 DOE 22 DOD 23 DOC 24 DOB 25 DOA C30 0.1 S0 S1 S2 VEE IC4 CXB1144Q Q6 8 Q5 7 Q4 6 IC2 CXB1136Q Q3 5 DGND Q2 4 Q1 3 Q0 2 CIMN 1 DGND S1 S2 C32 0.1 17 MR COUTN 16 15 14 VCCA VCC 13 DGND NC 25 - 5.2V (A) 5 D5 NC 24 C64 33 AGND C63 33 DGND R64 270 AGND TL431CP IC10 VTT P40 DVEE P41 ( - 4.5) DGND - 4.5V (D) C62 33 DGND C61 33 DGND AGND - 5.2V (A) IC5_4 8 7 C43 0.1 Q1N D1N D1 D2 19 CA 20 CB 21 VEE 22 VCCA 23 VBB 24 MR 1 2 3 4 D3 IC7 CXB1109Q D2N 13 P1 P4 VRT C21 0.1 FERRITE BEAD 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 NC VRB NC CLK D7 AVEE VRBS AVEE AVEE CLKN MINV DVEE NC 44 NC DGND D4 P20 P21 P22 P23 D4N D5 D5N 45 NC 46 NC 47 NC J1 C15 10p 50 VIN2 51 AGND 52 VRM R11 10 53 AGND DGND2 17 DGND2 16 D3N 15 D3 14 D2N 13 D2 12 NC 11 NC LINV NC AVEE AVEE D0 D0N D1 D1N NC 10 NC DGND C37 1 C36 0.1 P8 DGND D0 P12 P13 P14 P15 D0N D1 D1N - 5.2V (D) DGND - 5.2V (D) DVEE P9 9 VRTS ORN VRT OR DVEE DGND P16 P17 P18 P19 54 VIN1 55 VIN1 56 AGND 57 NC 58 AVEE 59 NC AGND AVEE 60 NC C18 1 61 62 63 64 65 66 67 68 1 C34 C19 0.1 0.1 2 3 7 4 8 5 6 R61 51 - 2V (D) C46 0.1 - 4.5V DGND (D) C47 0.1 D2 D2N D3 D3N C41 0.1 IC6 CXA1166K DGND1 18 D4 19 D4N 20 49 VIN2 D5 21 48 AGND D5N 22 NC 23 NC 24 NC 26 NC 25 D7N D6N D6 C70 0.1 C38 0.1 C22 1 C23 0.1 AGND AGND P6 P7 CLK CLKN R29 R30 R31 R32 51 51 51 51
- 5V (A) AGND
C10 0.1
IC13 TL431CP VR3 1k AGND R12 51 GND - 2V (D) L2
6
8
Q1 2SA970
VR1 2k
R3 510
VR2 2k
Full Scale
7
5
4
Offset
TL4558 IC12_2
R5 240
R6 1.3k
AGND
R2 11k
- 5.2V AGND R4 (A) 22k
C9 0.1
AGND - 5.2V (A)
R62 P38 51 - 2V (D) C44 0.1 - 4.5V DGND (D) C45 0.1
2 3 C11 1 C12 0.1
8
1
R8 1k
+ 5.2V (A) AGND AGND
4 TL4558 IC12_1
C7 0.1
C8 3.3
AGND
AGND AGND
R9 560
AMP. IN
R1 68
R7 240
C89 3P
2 3
7
6
R10 4 CLC404AJP 24 IC11 C13 1 C14 0.1
AGND
AGND
- 5.2V AGND AGND (A)
- 5.2V AGND (A) AGND
P2
L1 FERRITE BEAD
R28 51 - 2V (D) DGND IC5_2 INV NORM SW4 SW5 IC5_1 23 24 11 12 20 19 - 2V DGND (D) 18 17 LINV MINV C35 0.1 C48 R55 R56 0.1 51 51 R57 R58 51 51
R41 51
CXA1166K EVALUATION BOARD P10 OR ORN R27 P11 51
DOUTB
C1 0.1 VREF 26 27 30 C24 0.1 - 5.2V (D) DGND 28 29 31 32
VCC
VCCA
VEE
VBB
NC
QI
MR
VCCA
QIN
- 4.5V DGND (D) 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 CN VBB C VEE VCCA
17 NC
LEN2
VCC
VCCA
VEE
VBB
VCCA
NC
NC
- 23 -
DGND C16 1000p GND 18 DOUTPB 17 CAP GND 21 RBIAS 22 MR 23 SW 24 DINP 25 DINPB C17 19 DOUTP 0.01 20 CBIAS R45 51 R46 51 R47 51 R48 51 R49 51 R50 51 R51 51 R52 51 16 DGND 15 14 GND 12 11 10 9 LEN1 DIH 8 DIG 7 DGND DIF 6 DIE 5 DID 4 DIC 3 DIB 2 DIA 1 R65 51 R54 51 CLKN P37 R66 51 INV SW6 NORM INV C60 0.1 R14 51 R15 51 R16 51 R17 51 R18 51 R19 51 R20 51 26 27 30 3 4 R22 51 28 29 31 32 IC1_3 5 6 R24 51 26 27 28 29 30 R21 51 IC1_4 24 12 23 R25 51 C28 0.1 C27 0.1 - 2V GND (D) C29 0.1 DGND 11 R26 51 31 32 C31 0.1 - 4.5V DGND (D) SW3 DECIMATION IC5_5 3 6 4 5 R53 51 CLK P36 C52 0.1 - 2V DGND (D) R23 C26 51 0.1 C25 0.1 - 2V GND - 4.5V DGND GND (D) (D)
+ 5V P42 C65 33 AGND + 5V (A)
AGND
- 5.2V (D)
R8 51
2
8
DGND
CLK
1
7 IC1_1
DGND
IC1 CXB1103Q
- 2V (D)
- 2V (D)
9
10
21 22
18
16
17
C2 0.1
15 IC1_2
6 D6
NC 23
C3 0.1
7 D7 IC9 CXA20201 8 D8
NC 22
NC 21
IC5 CXB1103Q
9 D9
OUT 20
D/A OUT
10 LSB
NC 19
AGND 11 NC AGND 18 AGND 12 NC DGND 17 DGND 13 CLKN INV 16 C55 0.1 14 CLK DVEE 15 DGND
9
10
21 22
C5 0.1
C4 0.1
- 4.5V DGND (D)
: CHIP CAPACITOR
C53 0.1
C54 1 DGND DGND - 5.2V (D)
CXA1166K
CXA1166K
Characteristics
2 0 -2
Fig.6. Gain vs. Input frequency
Gain [dB]
-4 -6 -8 Fig.5. CXA1166K PCB Schematic Diagram Fig.4. Example of SNR Improvement Circuit - 10 - 12 5
10 Input frequency [MHz]
100
300
Fig.7. SNR vs. Input frequency
50
45
SNR [dB]
40
35 Fig.5. CXA1166K PCB Schematic Diagram Fig.4. Example of SNR Improvement Circuit 30
25
1
10 Input frequency [MHz]
100
200
- 20
Fig.8. 2nd, 3rd Harmonic distortion vs. Input frequency
Fig.5. Schematic Diagram (2nd Harmonic distortion) Fig.5. Schematic Diagram (3rd Harmonic distortion) Fig.4. Example of SNR Improvement Circuit (2nd Harmonic distortion) Fig.4. Example of SNR Improvement Circuit (3rd Harmonic distortion)
2nd, 3rd Harmonic distortion [dB]
- 30
- 40
- 50
- 60
- 70
- 80
1
10 Input frequency [MHz]
100
200
- 24 -
CXA1166K
Parts Layout
Component side
Soldering side - 25 -
CXA1166K
Printed Pattern
Component side
Soldering side - 26 -
CXA1166K
GND layer (inner layer)
VEE layer (inner layer) - 27 -
CXA1166K
Package Outline
Unit: mm
68PIN LCC (CERAMIC)
21.59 0.2 1.27 0.2
+ 0.38 24.13 - 0.25
1.27 0.1
C 1
15.85 0.2
1.65 0.18
0.3
1.27 0.915 0.07 R0.2 PIN NO.1 INDEX 2.16 0.25
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LCC-68C-01 QFN068-C-S950-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 3.7g CERAMIC GOLD PLATING
- 28 -
1.95 0.25
1.9 0.25
20.32 0.1

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