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SK70720 and SK70721
Multi-Rate DSL Data Pump Chip Set
Datasheet
The Multi-Rate DSL Data Pump is a complete, variable-rate transceiver that provides full duplex communication on two wires using echo-canceller-with-hybrid and 2B1Q line coding technology. It provides symmetrical line rates from 272 to 784 kbps. Performance specifications are defined at the 272, 400, 528, and 784 kbps data rates which provide a payload of 4, 6, 8, or 12 64 kbps channels with a 16 kbps overhead channel. The MDSL Data Pump also supports applications where the payload is unchannellized. The MDSL Data Pump chip set consists of two devices: s SK70720 MDSL Digital Signal Processor (MDSP) s SK70721 Integrated Analog Front-End (IAFE)
The IAFE is a fully integrated CMOS analog front-end IC which includes transmitter line drivers, filters, and 2B1Q encoding functions along with the receiver hybrid, AGC, A-to-D converter modulator and VCXO functions. The MDSP incorporates all digital signal processing required for A/D conversion, echo-cancellation, data scrambling and adaptive equalization as well as transceiver activation state machine control.
Applications
s s s
High speed residential Internet access Extended Range fractional T1/E1 transport 4 to 12-channel digital pair-gain
s s s
Wireless base station to switch access WAN access for LAN routers Video Conferencing
As of January 15, 2001, this document replaces the Level One document SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set.
Order Number: 249209-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The SK70720 and SK70721 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Contents
1.0 2.0 3.0 Features ......................................................................................................................... 7 Pin Assignment and Signal Descriptions ........................................................ 9 Functional Description...........................................................................................16
3.1 Framing ...............................................................................................................16 3.1.1 Fixed Data Rate Mode ...........................................................................17 3.1.2 Variable Data Rate Mode .......................................................................18 Component Description.......................................................................................19 3.2.1 Integrated Analog Front End (IAFE).......................................................19 3.2.2 MDSL Digital Signal Processor (MDSP) ................................................19 3.2.3 MDSP/IAFE Interface .............................................................................20 Line Interface.......................................................................................................21 MDSL Data Interface...........................................................................................22 3.4.1 Clock Distribution ...................................................................................22 3.4.2 Fixed Data Rate Operation.....................................................................22 3.4.3 Variable Data Rate Operation ................................................................23 3.4.4 Data Interface Timing .............................................................................24 3.4.5 Loopbacks ..............................................................................................24 Microprocessor Interface (MDSP) .......................................................................25 3.5.1 Control Pins............................................................................................26 3.5.2 Register Definitions ................................................................................26 3.5.3 Register Access .....................................................................................26 Activation.............................................................................................................27 3.6.1 Master Mode Activation Sequence.........................................................27 3.6.2 Slave Mode Activation Sequence...........................................................29 3.6.3 Synchronization State Machine..............................................................31 PCB Layout .........................................................................................................33 4.1.1 Digital Section ........................................................................................33 4.1.2 Analog Section .......................................................................................33
3.2
3.3 3.4
3.5
3.6
4.0
Application Information.........................................................................................33
4.1
5.0 6.0
Test Specifications ..................................................................................................40 Register Definitions.................................................................................................52
6.0.1 6.0.2 6.0.3 6.0.4 6.0.5 6.0.6 6.0.7 6.0.8 6.0.9 WR0--Main Control Register .................................................................52 WR2--Interrupt Mask Register ..............................................................53 WR3--Read Coefficient Select Register ................................................53 RD0--Main Status Register ...................................................................54 RD1--Receiver Gain Word Register ......................................................55 RD2--Noise Margin Register .................................................................55 RD3 (LSB), RD4 (MSB)--Coefficient Read Register .............................56 RD5--Activation Status Register ...........................................................57 RD6--Receive Step Gain Register ........................................................57
Datasheet
3
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
7.0
Mechanical Specifications ................................................................................... 59
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SK70720 and SK70721 Block Diagram ................................................................ 8 SK70721 IAFE Pin Locations................................................................................ 9 SK70720 MDSP Pin Assignments ...................................................................... 11 MDSL System Data Transport ............................................................................ 17 MDSL Frame....................................................................................................... 17 Variable Data Rate Mode Framing...................................................................... 18 MDSP/IAFE Interface - Relative Timing ............................................................. 22 MDSL Clock Distribution In Master and Slave Modes ........................................ 23 MDSP Digital Data Interface Timing ................................................................... 25 Master Mode Activation State Machine............................................................... 29 Slave Mode Activation State Machine................................................................. 30 MDSL Synchronization State Machine................................................................ 32 PCB Layout Guidelines ....................................................................................... 35 Typical Application for Master Mode Operation (Microprocessor Interface Mode) . 36 Typical Application for Slave Mode Operation .................................................... 37 MDSP Control and Status Signals (Stand-alone Mode) ..................................... 39 IAFE Normalized Pulse Amplitude Transmit Template ....................................... 41 Transmit Power Spectral Density--Upper Bound ............................................... 42 IAFE Receiver Syntax and Timing ...................................................................... 43 Typical Performance vs. Line Rate and Cable Gauge (Metric) ........................... 44 Typical Performance vs. Line Rate and Cable Gauge (English) ......................... 45 MDSL Data Interface Timing............................................................................... 48 RESET and INTERRUPT Timing (mP Control Mode) ........................................ 50 Parallel Data Channel Timing ............................................................................. 51 Data Pump Package Specifications .................................................................... 59
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 SK70721 IAFE Pin Assignments/Signal Descriptions ......................................... 10 SK70720 MDSP Pin Assignments/Signal Descriptions ...................................... 12 Data Rate and Frame Length Examples............................................................. 18 Minimum and Maximum Data Rate/Frame Time Examples................................ 20 IAFE Transmit Control......................................................................................... 20 MDSP/IAFE Serial Port Word Bit Definitions (Figure 7) ...................................... 21 State Machine Timer Durations (Figure 10 and Figure 11) ................................. 28 Data Pump Activation States .............................................................................. 30 Activation and Synchronization States................................................................ 31 Components for Suggested Circuitry (Figure 14 and Figure 15) ........................ 36 Transformer Specifications (Figure 14 and Figure 15, Reference T1)38 Crystal Specifications (Figure 14 and Figure 15, Reference Y1)38 IAFE Absolute Maximum Ratings ....................................................................... 40 IAFE Recommended Operating Conditions ........................................................ 40
4
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
IAFE DC Electrical Characteristics (Over Recommended Range)......................40 IAFE Transmitter Electrical Parameters (Over Recommended Range)..............41 IAFE Receiver Electrical Parameters (Over Recommended Range) ..................42 MDSP Absolute Maximum Ratings .....................................................................45 MDSP Recommended Operating Conditions......................................................45 MDSP DC Electrical Characteristics (Over Recommended Range) ...................46 MDSL Data Interface Timing Specifications (Figure 22) .....................................46 MDSP/Microprocessor Interface Timing Specifications (Figure 19 & Figure 20) 49 General System and Hardware Mode Timing .....................................................49 Register Summary...............................................................................................52 Main Control Register WR0.................................................................................52 Interrupt Mask Register WR2 ..............................................................................53 Read Coefficient Select Register WR3 ...............................................................54 Main Status Register RD0...................................................................................54 Receiver Gain Word Register..............................................................................55 Noise Margin Register RD2 (Noise Margin Coding)55 Coefficient Read Register ...................................................................................57 Activation Status Register RD5 ...........................................................................57 Receiver AGC and FFE Step Gain Register RD6 ...............................................58
Datasheet
5
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Revision History
Revision Date Description
6
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
1.0
Features
* Fully integrated, 2-chip transceiver * Compliant with the following standards:
-- ITU G.991.1 -- ANSI Committee T1E1 .4-TR28 (T1E1.4/96-006) -- ETSI ETR -152
* Integrated line drivers, filters and hybrid circuits reduce the number of external components
required
* Self-contained activation/start-up control eliminates an external microprocessor in many
applications
* Parallel interface for processor control or monitoring * Single +5V supply * Typical power dissipation less than 500 mW--good for applications with remote power
feeding
* Supports transparent repeater applications without an external processor or glue-logic * Supports processor directed rate selection driven by receive signal level and noise margin * Continuously adaptive echo canceller and equalizers maintain excellent transmission
performance with changing noise and line characteristics
* Typical noise-free transmission range*:
272 kbps 25.3 kft (7.7 km) on #24 AWG (0.5 mm) cable 17.1 kft (5.2 km) on #26 AWG (0.4 mm) cable 784 kbps 19.8 kft (6.0 km) on #24 AWG (0.5 mm) cable 13.7 kft (4.2 km) on #26 AWG (0.4 mm) cable * Refer to AN76 or SK70725/21 data sheet for details.
Datasheet
7
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 1. SK70720 and SK70721 Block Diagram
MDSP
TX_CK
IAFE
Line Driver TSGN TMAG
SLAVE_CK TDATA TFP RDATA RFP BIT_CK MODE ACTIVE MSTR_CK DATA ADDR CTRL
Back End
Scrambler Control Logic DFE Activation Control
2B1Q Encoder
Tx Filter
TTIP TRING
Echo Canceller
VREF
A/D Modulator
AD1
AGC_SET
Phase Detector
VCO_CK
RX_CK
SER_CTL
8
o
Decision Circuit
FFE DAGC AGC Tap
Decimation Filter
AD0
RTIP
AGC
BRING RRING BTIP XI XO VPLL
VCO Serial I/F To Various Blocks
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
2.0
Pin Assignment and Signal Descriptions
The IAFE is packaged in a 28-pin PLCC. Figure 2 shows the IAFE pin locations and Table 1 lists signal descriptions. The MDSP device is packaged in a 44-pin PLCC. Figure 3 shows MDSP pin designations and Table 2 lists signal descriptions.
Figure 2. SK70721 IAFE Pin Locations
SER_CTL
AGC_SET
RX_CK
TX_CK
4 VCO_CK DGND XO XI VPLL PGND IBIAS 5 6 7 8 9 10 11
3
2
1 28 27 26 25 24 23 TSGN DVCC TVCC TRING TTIP TGND n/c
Part # LOT # FPO #
SK70721PE XX XXXXXX XXXXXXXX
Rev # 22
TMAG 21 20 19 n/c
AD0
12 13 14 15 16 17 18 RGND RRING BRING RVCC RTIP BTIP
Package Topside Markings Marking Part # Rev # Lot # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Definition
Datasheet
AD1
9
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
FPO #
Identifies the Finish Process Order.
Table 1.
Group
SK70721 IAFE Pin Assignments/Signal Descriptions
Pin # 13 14 16 Symbol RTIP RRING BTIP BRING TTIP TRING XO XI VPLL PGND RVCC TVCC DVCC DGND RGND TGND RX_CK SER_CTL VCO_CK TX_CK AGC_SET AD1 AD0 TSGN TMAG IBIAS n/c I/O1 AI Receive Tip and Ring. Receiver differential inputs. AI AI Receive Balance Tip and Ring. Receiver hybrid balance inputs. 17 21 22 7 AI AO Transmit Tip and Ring. Line driver outputs. AO AO AI AO S S S S S S S DI DI DO DI DO DO DO DI DI AI Crystal Oscillator Input and Output. Connect a pullable crystal whose frequency is 32 times the bit rate between these two pins. Refer to the Applications Section for crystal specifications. PLL Control Voltage. Control signal for the VCXO. PLL Ground. 0 V. Receive Power Supply. +5 VDC ( 5%). Transmit Power Supply. +5 VDC ( 5%). Digital Power Supply. +5 VDC ( 5%). DVCC Ground. 0 V. RVCC Ground. 0 V. TVCC Ground. 0 V. Receive Baud Rate Clock Input. Serial Control Input. MDSL Reference Clock Output. Used as the receive timing reference for the MDSP. Transmit Symbol Clock Input. 16 times the transmit symbol rate. AGC Adjust Output. A-to-D Converter Data Line 1. A-to-D Converter Data Line 0. Transmit Quat Sign Input. Transmit Quat Magnitude. Input Bias. This input sets internal bias currents. Not Connected. No internal connection Description
Line
PLL
8 9 10 12 23
Power
24 6 15 20 3 4
Clock and Control
5 27 28
Data Input and Output
1 2 25 26
Analog Input No Connects
11 18 19
1. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S = Supply.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 3. SK70720 MDSP Pin Assignments
ADDR1(ACTREQ)
ADDR2(LOOPID)
ADDR0(QUIET)
D6(RCLKU)
D7(TXTST)
D5(BELB)
6 RFP RDATA ADDR3(ACTVNG) RDATA_ST TDATA TFP MSTR_CK SLAVE_CK CK_EN MODE BIT_CK 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 D3(RPTR) D2(ILMT) D1(DEACTVTD) D0(LOS) READ WRITE CHIPSEL INT(TMR_EXP) TEST ACTIVE n/c
Part # LOT # FPO #
SK70720PE XX XXXXXX XXXXXXXX
Rev #
D4(FELB) 34 33 32 31 30 29 GND3
GND2
GND1
VCC1 AD1
18 19 20 VCO_CK SER_CTL RESET
21 22 23 24 25 26 27 28 RX_CK AD0 AGC_SET TX_CK TMAG TSGN
NOTE: Pin Functions in Hardware Control Mode are shown in parentheses.
Package Topside Markings Marking Part # Rev # Lot # FPO # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Definition
Datasheet
VCC2
11
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 2.
Group
SK70720 MDSP Pin Assignments/Signal Descriptions
Pin # 1 44 Symbol VCC1 VCC2 GND1 GND2 GND3 n/c TEST RESET RDATA_ST I/O4 S S S S S - DI DI
1 1
Description Logic Power Supply. (Refer to Table 17). I/O Power Supply. +5 VDC ( 5%). Ground 1. 0 V. Ground 2. 0 V. Ground 3. 0 V. No internal connection. Test. Reserved for factory testing. Tie High for normal operation. Reset. Pulse Low to initialize internal circuits. Receive Data Strobe. RDATA_ST goes High for 18 consecutive BIT_CK periods to indicate four stuffing bits (b4703 - 4706) and 14 frame bits (b114) on RDATA. Mode Select. When MODE is High, the Data Pump operates in Master mode so that it is the link timing source and initiates activation. When MODE is Low, the Data Pump operates in Slave mode. Tied to internal pullup device. The MDSP must be reset after the MODE is changed. Bit Rate Clock. This clock transfers data into and out of the MDSL data interface at the bit rate. MSTR_CK is the source of BIT_CK in Master Mode. VCO_CK is the source of BIT_CK in Slave Mode. Link Active Indicator. ACTIVE goes Low upon the receipt of two consecutive frame sync words. ACTIVE goes High when the frame sync word is not detected in six consecutive frames. MDSL Receive Data Output. When ACTIVE is Low, the receive data including frame sync and stuff bits are output on RDATA. RDATA is High when ACTIVE is High. Receive Frame Pulse. Low for one BIT_CK cycle during the last bit of the current MDSL receive frame on RDATA, either b4702 or b4706. RFP is valid when ACTIVE is Low. MDSL Transmit Data Stream. When ACTIVE is Low, the Data Pump samples data on TDATA except during frame sync and stuff bits. Transmit Frame Pulse. TFP should be Low for one BIT_CK cycle the during last bit of the current MDSL frame on TDATA. If TFP is pulled Low and is Low again three BIT_CK cycles later, RDATA, RFP, RDATA_ST, BIT_CK, CK_EN, and ACTIVE will tri-state until the device is reset. Tied to an internal pull-up device.
Power
2 3 28 29
Misc
31 18 10
DO
16
MODE
DI
17
BIT_CK
DO
30 User Port2 8
ACTIVE
DO
RDATA
DO
7
RFP
DO DI1
11
TDATA
12
TFP
DI1
1. 2. 3. 4.
This input is a Schmidt Triggered circuit and includes an internal pull-up device. The frame period is 2351 or 2353 baud times. See "Framing" on page 16. This input is a Schmidt Triggered circuit and includes an internal pull-down device. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S = Supply.
12
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 2.
Group
SK70720 MDSP Pin Assignments/Signal Descriptions (Continued)
Pin # 4 Symbol QUIET I/O4 DI3 DI3 Description Quiet Mode Enable. Set High to force the MDSP into the Deactivated State. Set Low to enable activation requests (see ACTREQ). Activation Request (Master mode) (no function in Slave mode). Tie this pin Low in Slave mode. When QUIET is Low, a rising edge on this pin initiates activation. The signal is ignored after activation (see QUIET). Loop Number Input (Master mode) or Loop Number Indicator (Slave mode). This indicator is transmitted from the link Master to the slave and can be used for loop identification in systems that multiplex data onto multiple MDSL lines. In Slave mode LOOPID is valid only when ACTIVE is Low. Activating State Indication. ACTVNG goes High when the MDSP is in the Activating State. Timer Expiration Indicator. TMR_EXP goes High to indicate the expiration of the activation timer. Chip Select Write Pulse Read Pulse Assert these three pins Low to activate Hardware Control Mode. When any of them is High, the MDSP reverts immediately to Software Control Mode.
5
ACTREQ
6
LOOPID
DI /O
3
9 32 33 34 Hardware Interface (Hardware Control Mode) 36 35
ACTVNG TMR_EXP CHIPSEL WRITE READ
DO DO DI3 DI
3
DI3
LOS (Master)
DO
Loss of Signal Indicator. In Master mode, LOS goes High when the Data Pump enters the Inactive State. When the Data Pump reaches the Deactivated State from Active-1 or Active-2, it starts the Loss of Signal (LOS) timer after Slave transmission stops. When the LOS timer expires, the Data Pump goes to the Inactive State. When the Data Pump transitions from the Activating State directly to the Deactivated State, it may immediately enter the Inactive State without waiting for Slave transmission to cease (Figure 10). Loss of Signal Indicator. In Slave mode, LOS goes High immediately when loss of signal energy is detected and the data pump enters the Inactive State (Figure 11). Deactivation Indicator. DEACTVTD goes High when the Deactivation timer expires and the data pump goes from the Pending Deactivation state to the Deactivated state. Insertion Loss Measurement Test. Set High to transmit a framed & scrambled, "all 1s", 2B1Q pulse sequence. Pulse sequence will have a valid sync word. In the Slave configuration, when the ILMT mode is selected, the Data Pump may begin activation. Repeater Mode Enable. When in Master mode, setting RPTR High configures the data pump to derive timing from the MSTR_CK output of an adjacent device for transparent repeater applications. The BIT_CK output phase is aligned to the TFP input pulse width. RPTR is ignored in Slave mode.
LOS (Slave)
DO
37
DEACTVTD
DO
38
ILMT
DI1
39
RPTR
DI1
1. 2. 3. 4.
This input is a Schmidt Triggered circuit and includes an internal pull-up device. The frame period is 2351 or 2353 baud times. See "Framing" on page 16. This input is a Schmidt Triggered circuit and includes an internal pull-down device. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S = Supply.
Datasheet
13
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 2.
Group
SK70720 MDSP Pin Assignments/Signal Descriptions (Continued)
Pin # Symbol I/O4 Description Front-End Loopback (Master only). In the Inactive State, set High to cause the IAFE to loopback. The returned signal activates the MDSP which receives its own transmitted data. The chip set ignores incoming data from the Slave during loopback. Back-End Loopback. In the Active-1 or Active-2 states, setting BELB High forces an internal, transparent loopback with RDATA connected to TDATA and RFP connected to TFP. Receive Baud Rate Clock. Aligned with BIT_CK in Slave mode, phase synchronous with receive pulse stream, However, during Activating State, the clocks may not be aligned. In the Master mode RCLKU has a constant, arbitrary, phase relationship with BIT_CK in Active State. Transmit Test. Set high to enable isolated transmit pulse generation. TDATA controls the sign and TFP controls the magnitude of the transmitted quat pulses according to the 2B1Q encoding rules. In the Slave configuration, when the TXTST mode is selected, the Data Pump may begin activation. Data bit 0. Eight-bit, parallel data bus. Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Address bit 0. Four-bit address, selects read or write register. Address bit 1 Address bit 2 Address bit 3 Interrupt Output. Open drain output. Requires an external 10 k pull up resistor. Goes Low on interrupt. Chip Select. Pull Low to read or write to registers. Write Pulse. Pull Low to write to registers. Read Pulse. Pull Low to read from registers.
40
FELB
DI
1
Hardware Interface (Hardware Control Mode) -cont'd
41
BELB
DI1
42
RCLKU
DO
43
TXTST
DI
1
36 37 38 39 40 41 Processor Interface (Software Control Mode) 42 43 4 5 6 9 32 33 34 35 1. 2. 3. 4.
D0 D1 D2 D3 D4 D5 D6 D7 ADDR0 ADDR1 ADDR2 ADDR3 INT CHIPSEL WRITE READ
DI1/O DI1/O DI1/O DI1/O DI1/O DI1/O DI1/O DI1/O DI
3
DI3 DI3 DI3 DO DI3 DI
3
DI3
This input is a Schmidt Triggered circuit and includes an internal pull-up device. The frame period is 2351 or 2353 baud times. See "Framing" on page 16. This input is a Schmidt Triggered circuit and includes an internal pull-down device. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S = Supply.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 2.
Group
SK70720 MDSP Pin Assignments/Signal Descriptions (Continued)
Pin # 14 Symbol SLAVE_CK I/O4 DI3 Description Slave Mode Reference Clock. Mandatory in Slave mode. Tie High or Low in Master Mode. Clock input requires 32 ppm accuracy. Slave Mode Reference Clock Enable. Active High enable for the SLAVE_CK clock. In slave mode, this pin goes Low to indicate the PLL is tracking the input signal from the master. Not used in master mode. 16x MDSL Reference Clock. In Master Mode, this clock generates transmit and receive timing and must have 32 ppm accuracy. In Slave Mode, this output is derived by dividing VCO_CK by two so that it may drive the MSTR_CK input of another data pump configured for Master mode as a repeater (with RPTR High). 32x Receive Clock Input. Serial Control Output. Receive Baud Rate Clock. Derived from VCO_CK. Analog to Digital Converter Data Line 0. Analog to Digital Converter Data Line 1. AGC Adjust Input. Transmit Symbol Clock Output. Transmit Quat Magnitude Bit. Transmit Quat Sign Bit.
15
CK_EN
DO
DI1 13 MSTR_CK DO Clock and Control 19 20 21 22 23 24 25 26 27 1. 2. 3. 4. VCO_CK SER_CTL RX_CK AD0 AD1 AGC_SET TX_CK TMAG TSGN DI DO DO DI DI DI DO DO DO
This input is a Schmidt Triggered circuit and includes an internal pull-up device. The frame period is 2351 or 2353 baud times. See "Framing" on page 16. This input is a Schmidt Triggered circuit and includes an internal pull-down device. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S = Supply.
Datasheet
15
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
3.0
Functional Description
The MDSL Data Pump (MDP) provides synchronous, full duplex transmission on a single pair of wires using 2B1Q line coding and echo cancellation. The Data Pump supports symmetrical line rates from 272 to 784 kbps and provides complete start up and operation without an external processor. The MDP may be used to transport framed or unframed data which is synchronous, asynchronous, or near-synchronous to the clock rate of the data pump. This section provides an overview of how the MDP data interface functions to support these applications. For a detailed explanation on the how to configure the MDP for a specific application refer to the section entitled "MDSL Data Interface." Figure 4 illustrates data transport using the MDSL system. Data is clocked into a transmitter, sent over the line, and clocked out of the receiver of the far-end transceiver. Data is transmitted simultaneously in both directions.
3.1
Framing
The MDP embeds a 14-bit frame synchronization word (FSW) in the data stream that divides the data into 4702-bit MDSL frames as shown in Figure 5. The framing signal serves three purposes: 1. It allows automatic activation and deactivation based on receiver frame sync word detection. 2. It allows the average data rate in each direction of transmission to be adjusted while maintaining a constant line rate. 3. It provides an MDSL frame position indicator that may be used in unframed time-divisionmultiplexed systems to relate time slots in the MDSL frame to those in an application frame. (See Note below) Note: The MDP frame sync word format and frame length are fully compatible with those defined for 784 kbps HDSL applications in ITU G.991.1, ANSI Committee T1E1.4-TR28 (T1E1.4/96-006), and ETSI ETR-152 standards. The MDP is fully transparent to all data except the frame sync word. It does not provide any other framing functions defined for HDSL. Each frame contains 4688 payload data bits, and there are no restrictions on the data patterns which can be transmitted in the payload data. The application synchronizes data to the MDP framing by generating a pulse on the transmit frame pulse input, TFP. The transmitter sends the FSW in the first 14 bits following the rising edge of TFP. Application data is not transmitted or buffered during the transmission of the FSW.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 4. MDSL System Data Transport
BIT_CK BIT_CK TDATA TFP Scrambled 2B1Q Signal
b4701 b4702 XXX X XXXXX b15 b16
RDATA RDATA_ST RFP
b4701
b4702
b15
b16
TDATA TFP BIT_CK RFP RDATA RDATA_ST
RDATA RDATA_ST RFP BIT_CK
TDATA TFP
Master Data Pump
Slave Data Pump
Figure 5. MDSL Frame
MDSL Frame
1
0
1
0
1
0
0
0
0
0
1
0
0
0 b15 b16 b17 b18 b19
...
b4701 b4702
Frame Sync Word
Transparent Payload Data
The MDP receiver detects the incoming FSW and provides a blanking signal (RDATA_ST) at its output to indicate that payload data is not present during the FSW. The RDATA_ST signal can also be used to gate the receiver clock signal (BIT_CK) so that clock transitions are present only when payload data is available. The resulting gapped clock is similar to that found in many other data transport systems. The MDP has two modes of operation: Fixed Data Rate and Variable Data Rate.
3.1.1
Fixed Data Rate Mode
In Fixed Data Rate Mode, the MDP transports one data bit for each cycle of the bit clock (BIT_CK) except during the 14-bit FSW at the start of each frame. Data may be either synchronous (one data bit per available clock cycle) or asynchronous (data sent only when available). In both cases, the transmitter samples the transmit data signal (TDATA) on the rising edge of BIT_CK and reproduces that signal at the output of the receiver (RDATA) so that it is valid on the rising edge of the receiver BIT_CK. An external frame counter is required to provide a transmit frame pulse every 4702 BIT_CK cycles to synchronize the Data Pump frame position to the gapped data. In applications where the data is formatted into logical frames or packets there is no requirement for a fixed mapping between the application frames and MDSL frames since the data contains the framing information required to give it meaning. Unless the application frame size divides evenly into the MDSL frame size, it is best to embed application framing information with the data rather
Datasheet
17
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
than to create a fixed mapping between specific time slots in the MDSL and application frames. With unframed, time-division multiplexed data defined relative to an application frame pulse it is necessary to establish a fixed mapping between application frame and MDSL frame boundaries. Table 3 shows the payload data rate and frame length for some common values of line rates.
.
Table 3.
Data Rate and Frame Length Examples
Line Rate (kbps) 272 400 528 784 Payload Data Rate (kbps) 271.190 398.809 526.428 781.666 Frame Length (ms) 17.287 11.755 8.905 5.997
3.1.2
Variable Data Rate Mode
Some applications require that data be transported at a rate which is externally controlled and varies a small amount from a nominal payload data rate. The MDP has a variable rate operating mode which allows the application to modify the payload data rate without changing the line rate so that each of the payload bits contains a valid data bit. To operate in this mode, the MDP uses a mechanism known as stuffing. By properly choosing the line rate of the MDSL system and using the stuffing mechanism, the application can transmit data at slightly different rates in both directions simultaneously while still using a common, fixed MDSL line rate. When stuffing is employed, the application inserts an additional four bits not carrying payload data in the data stream between the end of the 4688 payload bits and the beginning of the next FSW as shown in Figure 6. This is accomplished by delaying the TFP pulse by four BIT_CK periods from its normal position. The MDP receiver detects this four bit change in the location of the FSW and adjusts its payload data strobe indicator (RDATA_ST) to indicate that the four additional bits do not contain payload data and should be suppressed along with the FSW which follows them. This mode of operation is frequently used in the transport of T1 signals where the upstream data rate is not identical to the downstream data rate.
Figure 6. Variable Data Rate Mode Framing
Short Frame 1 0 1 0 1 0 0 0 0 0 1 0 0 0 b15 b16 b17 b18 b19
...
b4701 b4702
Frame Sync Word
Long Frame 1 0 1 0 1 0 0 0 0 0 1 0 0
Transparent Payload Data
0 b15 b16 b17 b18 b19
...
b4701 b4702 b4703 b4704 b4705 b4706
Frame Sync Word
Transparent Payload Data
Stuff Bits
Table 4 provides the minimum and maximum data rates and frame times for several line rates. Although the MDP can only transport data at either of these two instantaneous rates, it can support any average data rate between them by adjusting the ratio of frames with stuffing to those without stuffing. When 50% stuffing is used the MDP will transport data at the nominal rate shown below. If necessary, a PLL tracking the receive frame pulse output (RFP) can be used to create a continuous (i.e., not gapped) clock whose frequency follows the average receive data rate.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
3.2
Component Description
The following paragraphs describe the chip set components individually with reference to internal functions and the interfaces between Data Pump components.
3.2.1
Integrated Analog Front End (IAFE)
The IAFE incorporates the following analog functions:
* * * *
the transmit driver transmit and receive filters Phase-Locked Loop (PLL) hybrid circuitry analog-to-digital converter
The IAFE provides the complete analog front end for the MDSL Data Pump. It includes transmit pulse shaping, line driver, receive A/D modulator, and the VCO portion of the receiver PLL function. Transmit and receive controls are implemented through the serial port. The IAFE line interface uses a single twisted pair line for both transmit and receive. Table 5 lists the IAFE pin descriptions. Refer to Test Specifications for IAFE electrical and timing specifications.
3.2.1.1
IAFE Transmitter
The IAFE performs the pulse shaping and driving functions. The IAFE transmitter generates a 4level output defined by TMAG and TSGN. Table 5 lists 2B1Q pulse coding parameters. Refer to Test Specifications for frequency and voltage templates.
3.2.1.2
IAFE Receiver
The IAFE receiver is a sophisticated sigma-delta converter. It sums the differential signal at RTIP/ RRING minus the signal at BTIP/BRING. The first A/D signal comes out of AD0 at the rate of 64 times the 2B1Q symbol rate. The second stage of the A/D samples the noise of the first and generates the AD1 bit stream at the rate of 64 times the symbol rate. Receiver gain is controlled by the MDSP via the AGC2-0 bits in the SER_CTL serial control stream. The AGC_SET output from the IAFE is normally Low. It goes High when the signal level in the sigma delta A/D is approaching its clipping level, signaling the MDSP to lower the gain. The VCO is part of a phase-locked loop (PLL) locked to the receive data. The VCO frequency is varied by pulling an external crystal with varactor diodes that are biased by the VPLL output. The VPLL output is, in turn, controlled by the serial port PLL bits.
3.2.2
MDSL Digital Signal Processor (MDSP)
The MDSP incorporates the following digital functions:
* bit-rate transmit and receive signal-processing * adaptive Echo-Cancelling (EC) * adaptive decision feedback-equalization (DFE) using the receive quat stream and the internal
error signal
Datasheet
19
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
* fixed and adaptive digital-filtering functions * activation/start-up control and the microprocessor interface
The MDSP also provides the digital data interface. A simple, parallel 8-bit microprocessor interface on the MDSP allows high-speed access to control, status and filter coefficient words. Table 6 lists the MDSP pin descriptions. Refer to Test Specifications for MDSP electrical and timing specifications. The microprocessor interface on the MDSP provides bit flags for signal presence, synchronization, activation completion. Single-byte words representing receive signal level and the noise margin of the transceiver are also available on the microprocessor interface. One control bit allows the user to start the Data Pump activation sequence. The MDSP controls the complete activation/start-up sequence. Table 4.
Line Rate (kbps) 272 400 528 784
Minimum and Maximum Data Rate/Frame Time Examples
Frame Length (ms) 4706 bit Frame 17.301 11.765 8.913 6.003 Min. Payload Data Rate (kbps) 270.960 398.470 525.980 781.001 Nominal Rate (kbps) (50% stuffing) 271.075 398.640 526.204 781.333 Max. Payload Data Rate (kbps) 271.190 398.809 526.428 781.666
Frame Length (ms) 4702 bit Frame 17.287 11.755 8.905 5.997
Table 5.
IAFE Transmit Control
TSGN 1 1 0 0 TMAG 0 1 1 0 Output Symbol (quat) +3 +1 -1 -3
3.2.3
MDSP/IAFE Interface
The IAFE provides the receiver recovered clock, VCO_CK, to the MDSP. The serial control stream framing signal RX_CK is sampled inside the IAFE with the VCO_CK rising edge. The serial control stream, SER_CTL, is sampled inside the IAFE by the rising edge of an internally-generated clock at f(VCO_CK)/2. This IAFE internal clock has the same phase relationship with a similar clock inside the MDSP, as established by the RX_CK signal. In the MDSP, the half-rate clock VCO_CK/2 and RX_CK transition on the rising edge of VCO_CK, and SER_CTL transitions coincide with the falling edge of VCO_CK/2. The output MSTR_CK in Slave Mode is equal to VCO_CK/2. A/D converter outputs (AD0 and AD1) are clocked out of the IAFE with VCO_CK, having transitions coincident with the rising edge of VCO_CK/2. The MDSP samples AD0 and AD1 with the falling edge of its internal VCO_CK/2. Transmit data, represented by TSGN and TMAG, is clocked from the MDSP using the falling edge of TX_CK, the transmit clock. The IAFE uses the rising edge of TX_CK to sample TSGN and TMAG. TSGN and TMAG change state at the baud rate, or every 8 cycles of TX_CK. Figure 7 shows relative timing for the MDSP/IAFE interface.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
3.2.3.1
MDSP/IAFE Serial Port
The MDSP continually writes to the IAFE serial port. This serial stream consists of two 16-bit words as shown in Table 6. The data flows from the MDSP to the IAFE at a rate of f(VCO_CK)/2. Refer to the Test Specifications section for serial port timing relationships and electrical parameters.
3.3
Line Interface
The Data Pump line interface consists of three differential pairs. The transmit outputs TTIP and TRING, receive inputs RTIP and RRING, and the balance inputs BTIP and BRING, all connect through a common transformer to a single twisted-pair line (Figure 14 and Figure 15). The transmit outputs require resistors in series with the transformer. A passive prefilter is required for the receive inputs. The balance inputs feed the transmit signals back to the Data Pump providing passive echo cancellation. Protection circuitry should be inserted between all Data Pump line interface pins and the transformer. Refer to the Applications section for typical schematics.
Table 6.
MDSP/IAFE Serial Port Word Bit Definitions (Figure 7)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word A (on SER_CTL) INIT n/a n/a TXOFF TXDIS TXTST AGC2 AGC1 AGC0 FELB n/a PTR4 PTR3 PTR2 PTR1 PTR0 Word B (on SER_CTL) COR4 COR3 COR2 COR1 COR0 VCO2 VCO1 VCO0 PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0
Datasheet
21
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 7. MDSP/IAFE Interface - Relative Timing
VCO_CK TX_CK VCO_CK/2 RX_CK AD0 AD1 SER_CTL B1 B0 A15 A14 A13 A1 A0 B15
3.4
MDSL Data Interface
This section provides detailed information on the operation of the data interface and how it is configured to support variable data rate and fixed data rate applications.
3.4.1
Clock Distribution
Figure 8 shows an MDSL link between a master and slave transceiver. This figure illustrates the clock/timing architecture of the data pump in both modes. Link activation is initiated by the master mode device which also operates as the MDSL timing source. The slave mode device responds to an activation request and is "loop-timed" (i.e., it recovers the MDSL clock from the master and uses this clock to transmit upstream). In the master mode, the data pump derives its line transmit clock and data interface BIT_CK by dividing the clock supplied at the MSTR_CK input by 16. MSTR_CK also provides a 32 ppm accurate local training reference for the receiver clock recovery VCXO before activation. When active, the master data pump uses this VCXO in a PLL for data recovery from the line, but an internal FIFO is provided so that the receive data can be clocked out using the BIT_CK divided down from the MSTR_CK. In the slave mode after activation, the data pump derives its line transmit clock and data interface BIT_CK from the receiver PLL. In this mode, the clock supplied at the SLAVE_CK input is only used to train the VCXO frequency within 32 ppm before activation. To minimize switching noise, the SLAVE_CK can be turned off when CK_EN is Low. To select the clock and crystal frequencies required for a specific application, the required line rate must first be calculated from the specified payload data rate. This process is outlined below for fixed data rate and variable data rate configurations.
3.4.2
Fixed Data Rate Operation
For fixed data rate operation, the line rate is calculated from the payload data rate as follows: line_rate = data_rate (4702/4688). The time required to transmit a complete frame is: frame_time = 4702 / line_rate.
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Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
The Master transceiver requires a clock frequency of: MSTR_CK = 16 (line_rate). The slave transceiver requires a clock frequency of: SLAVE_CK = 16 (line_rate). Both transceivers require a VCXO crystal frequency of: fxtal = 32 (line_rate). Figure 8. MDSL Clock Distribution In Master and Slave Modes
MASTER SLAVE SLAVE_CK Clock (16 x bit rate, +/- 32 ppm) MSTR_CK 1/32 1/16 FIFO
RD WR
Clock (16 x bit rate, +/- 32 ppm)
VCXO
1/64
1/32
BIT_CK VCXO
BIT_CK
3.4.3
Variable Data Rate Operation
For variable data rate operation, the line rate is calculated from the payload data rate as shown below: line_rate = average_data_rate (4704/4688). At this line rate the data pump will transport data at the specified average data rate when 50% stuffing is used, however it will always operate at one of the instantaneous data rates given by the following two equations. By adjusting the number of BIT_CK cycles between TFP pulses an external controller may adjust the frame length to control the average data rate between the minimum and maximum instantaneous rates: max_data_rate = line_rate (4688/4702), and min_data_rate = line_rate (4688/4706). The time required to transmit a complete frame is: frame_time (min) = 4702 / line_rate, or frame_time (max) = 4706 / line_rate. The Master transceiver requires a clock frequency of: MSTR_CK = 16 (line_rate). The slave transceiver requires a clock frequency of: SLAVE_CK = 16 (line_rate).
Datasheet
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SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Both transceivers require a VCXO crystal frequency of: fxtal = 32 (line_rate).
3.4.4
Data Interface Timing
The MDSL data interface provides for the transfer of binary data to and from the transceiver using the 272 to 784 kHz clock, BIT_CK, generated by data pump. Figure 9 shows the timing for the data interface. In the receive direction, the binary data output on RDATA contains the 14-bit frame sync word (b1-b14), the transparent payload data (b15-b4702) and optional stuff bits (b4703-b4706). During the activation process, RDATA is held High until ACTIVE goes Low to indicate link activation has been completed and recovered data is available. The data strobe signal RDATA_ST is High during the frame sync word and stuff bits and Low during payload data. RDATA_ST can be used to create a gapped receive payload data clock by suppressing BIT_CK cycles when RDATA_ST is High. RFP is the receive frame sync output that goes Low during the first bit of every MDSL frame. In variable data rate applications the original data timing can be recovered from RFP using a synthesizer PLL. In the transmit direction, payload data is sampled from TDATA during bits b15-b4702 of each frame. Frame sync word bits (b1-b14) are internally generated in the MDSP and not sampled from TDATA, so any data supplied during b1-b14 is ignored. During the activation process, transmit data is internally generated by the MDSP and TDATA is not sampled until ACTIVE goes Low to indicate link activation has been completed. For fixed data rate applications an external counter is used to generate a one BIT_CK cycle long Low pulse for the TFP input. This frame sync pulse establishes the start of an MDSL frame and is needed to establish a gap in the payload data during the time the data pump internally generates the frame sync word. In variable rate applications stuffing control logic adjusts the time between TFP pulses to match the average data rate transmitted by the data pump to the rate at which it is supplied by the external source. In both cases, the TFP signal should be valid prior to an activation request for the Master Data Pump. A valid TFP signal should be generated after power-up, before or immediately after LOS goes Low for the Slave Data Pump. During initialization and anytime thereafter TFP must not be held low for more than 2 BIT_CK cycles or the data interface output signals will be disabled. Also, if the TFP signal is inactive (always High or unconnected) when activation starts, then the Data Pump may activate but will inject stuff bits in the TDATA stream in every other frame and sync bits in every frame. Since the Data Pump will not be synchronized to the data source these internally generated bits will overwrite payload data. If the phase of TFP jumps the Data Pump will immediately reset the transmit frame alignment, typically causing loss of alignment at the other end.
3.4.5
Loopbacks
The data pump provides data loopbacks toward the line and toward the digital interface. Front End Loopback (FELB) is the loopback toward the digital interface inside the IAFE and is available only in Master mode. FELB is initiated by bringing the FELB and ACTREQ signals High in hardware mode, or by setting the FELB and ACTREQ bits to 1 in the processor control mode. In FELB the data pump receiver activates with its own transmit data and ignores a signal at the IAFE receiver analog line interface. Data is transmitted on the line during FELB. Back End Loopback (BELB) is a data loopback toward the analog line interface inside the MDSP. BELB is available in both Master and Slave modes after activation is complete. BELB is initiated by bringing the BELB signal High in hardware mode, or by setting the BELB bit to 1 in the processor control mode. In BELB the data pump receive data and frame pulse signals are supplied to the transmitter which ignores the TDATA and TFP inputs. Receive Data is output on RDATA during BELB.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 9. MDSP Digital Data Interface Timing
A) Transmit Timing-Without Stuff Bits BIT_CK TFP
b4699 b4701 b1 b4700 b4702 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
TDATA
b1-b14 are the frame sync word generated by the MDSP (not sampled from TDATA)
B) Transmit Timing-With Stuff Bits BIT_CK TFP
b4703 b4705 b1 b4704 b4706 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
TDATA
b4703-b14 are the stuff bits and frame sync word generated by the MDSP (not sampled from TDATA)
C) Receive Timing-Without Stuff Bits BIT_CK RFP
b4701
RDATA
b4702
b15 b16
RDATA_ST D) Receive Timing-With Stuff Bits BIT_CK RFP
b4702 b4704 b4706 b15 b16 b4703 b4705
RDATA RDATA_ST
3.5
Microprocessor Interface (MDSP)
Three primary control pins, CHIPSEL (Chip Select), READ and WRITE, select the Software Mode which also uses an interrupt output pin to report status changes. Four additional pins are used for the parallel bus addressing and eight pins for data I/O. Refer to Test Specifications for microprocessor interface timing in Software Mode.
Datasheet
25
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
3.5.1
Control Pins
Chip Select: The Chip Select (CHIPSEL) pin requires an active Low signal to enable Data Pump read or write transfers over the data bus. To enable Hardware Mode hold this pin Low, along with READ and WRITE. Data Read: The Data Read pin (READ) requires an active Low pulse to enable a read transfer on the data bus. When READ is pulled Low, the Data Pump data bus lines go from tristate to active and output the data from the register addressed by ADDR0-ADDR3. To avoid reading data during register updates, reads should be synchronized to the falling edge of RX_CK. Alternatively, each read should be repeated until the same data is read twice within one baud time. Data Write: The Data Write pin (WRITE) requires an active Low pulse to enable a write transfer on the data bus. Data transfer is triggered by the rising edge of the WRITE pulse. To ensure data is written to the register addressed by ADDR0-ADDR3, valid data must be present on the MDSP data bus lines before WRITE goes High. Interrupt: The Interrupt pin (INT) is an open drain output requiring an external pull-up resistor. The INT output is pulled active Low when an internal interrupt condition occurs. INT is latched and held until Main Status Register RD0 is read. An internal interruption results from a Low-toHigh transition in any of four status indicators: ACTIVE, ACTIVE, DEACTVTD or TMR_EXP. Any transition on LOS will also generate an interrupt. If an interrupt mask bit in register WR2 is set, any transition of the corresponding status bit will not trigger the INT output.
3.5.2
Register Definitions
Refer to "Register Definitions" on page 52 for detailed description of the data pump register set.
3.5.3
3.5.3.1
Register Access
Write
To write to an MDSP register, proceed as follows: 1. Drive CHIPSEL Low. 2. Drive an address (0000, 0010, or 0011) onto ADDR0-ADDR3. 3. Observe address setup time. 4. Set 8-bit input data word on D0-D7. 5. Pull WRITE Low, observing minimum pulse width. 6. Pull WRITE High, observing hold time for data and address lines.
3.5.3.2
Read
Procedures for reading the MDSP registers vary according to the particular register. Accessing registers RD0, RD1, RD2, RD5 and RD6 is relatively simple. Reading registers RD3 and RD4 is more complex. Unless parallel port reads are synchronized with the falling edge of RX_CK, all read operations should be repeated until the same data is read twice within one baud time. To read register RD0, RD1, RD2, RD5 or RD6 proceed as follows:
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
1. Drive CHIPSEL Low. 2. Drive the desired address onto ADDR0-ADDR3. 3. Pull READ Low, observing minimum pulse width. 4. Pull READ High to complete the read cycle. Registers RD3 and RD4 hold the coefficient values from the DFE, EC, FFE and AGC as shown in Table 27. Register RD3 holds the lower byte value and register RD4 holds the upper byte value. To reconstruct the complete 16-bit word, concatenate the least significant and most significant bytes. To read registers RD3 and RD4 proceed as follows: 1. Select the desired coefficient by writing the appropriate code from Table 27 to register WR3. 2. Enable the Coefficient Read Register by writing a 1 to bit b0 (CRD1) in register WR2. 3. Perform standard register read procedure listed in steps 1 through 6 above to read the lower byte from RD3 and the upper byte from RD4. 4. Concatenate the RD3 and RD4 to obtain the complete 16-bit word.
3.6
Activation
The MDSL Data Pump integrates all logic required to manage link activation and deactivation. Figure 10 illustrates the Activation State Machine for the Master mode. Figure 11 illustrates the Slave mode state machine. In software mode, the STn bits in Read Register 6 (ADDR 0110) show the current status of the state machine.
3.6.1
Master Mode Activation Sequence
When the Master Data Pump is powered up and reset is applied, the chip set is in the Inactive State as shown at the top of Figure 10. Starting at the Inactive State, the device progresses in a clockwise direction through the Activating, Active-1, Active-2, Pending Deactivation and Deactivated States. In the hardware mode when the Data Pump is in the Inactive State and the QUIET pin is Low, a Low-to-High transition on the ACTREQ pin initiates activation of the link (Table 7). In the software mode when the Data Pump is in the Inactive State and the QUIET bit is set to 0, setting the ACTREQ bit to 1 initiates activation of the link. Because the ACTREQ control bit is level sensing, to generate a single request, ACTREQ should be set to 1 and then reset to 0 again before the Activation Timer period elapses. During the Activating State, the echo canceller, equalizers and timing recovery circuits are all adapting during the simultaneous transmission and reception of the framed, scrambled-ones data transmitted first as a two-level code (S0) and then as a four-level code (S1). If the receive frame sync word is not detected in two consecutive frames before the activation timer expires the device moves to the Deactivated State and ceases transmission. After reaching the Deactivated state this way, it will then immediately transition to the Inactive State (setting LOS regardless of whether Slave transmission ended). The next activation request should not be generated for one activation timer period to allow the Slave to time-out, detect LOS and move from the Deactivated to the Inactive State. Microprocessor-based systems may reduce this time by resetting the Slave data pump from the Activating State when no Master signal is present.
Datasheet
27
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Successful detection of the sync word drives the State machine to the Active-1 State. This is indicated by a 0-to-1 transition of the ACTIVE bit or High to Low transition of the ACTIVE pin. If the Master Data Pump remains locked to the sync word until the activation timer expires, the device transitions to the Active-2 (fully active) State. If sync is lost, as indicated by a 0-to-1 transition on the ACTIVE pin, the Master Data Pump transitions to the Pending Deactivation State. In Pending Deactivation, the Master Data Pump progresses to the Deactivated and Inactive States with the expiration of the respective timers. If the sync word is detected before the Pending Deactivation timer expires, the Master Data Pump returns to either Active-1 or Active-2. (The Master Data Pump returns to which ever state it occupied before transitioning to Pending Deactivation.) The Master Data Pump will exit the Active-2 State in one of two ways. A Low-to-High transition on the QUIET pin (Hardware Mode) or the QUIET bit (Software Mode), forces the Master Data Pump directly to the Deactivated State. The only other means of exiting the Active State is through a loss of receive sync word. ACTIVE goes Low when six consecutive frames occur without a sync word match sending the Master Data Pump into the Pending Deactivation State. The Master Data Pump remains in the Pending Deactivation State for a maximum of two seconds. If a sync word is detected within the time limit, the Master Data Pump re-enters the Active State. If not, DEACTVTD goes High and the chip set goes to the Deactivated State. When the Deactivated State is reached from Pending Deactivation, the Master Data Pump returns to the Inactive State and declares LOS when it detects no signal from the Slave for one second. The Data Pump waits in the Inactive State before another activation attempt (Table 7). Table 7.
Timer
State Machine Timer Durations (Figure 10 and Figure 11)
Nominal Timer Duration (seconds) 272 kbps 400 kbps 528 kbps Description 784 kbps Master Mode: Starts with an activation request. Restarts when a signal is detected from the Slave. Slave Mode: Starts when a signal is detected from the Master. Starts due to Loss of Sync Word for 6 consecutive frames, triggering the Pending Deactivation state. Master Mode: Starts in Deactivated state once the Slave is quiet. Slave Mode: not used. The amount of time the Master must be in the Inactive state before another activation request can be made after the Data Pump deactivates directly from the Activating State.
Activation Timer1
86.5
59.0
44.5
30.0
Deactivation Timer2,
3
6.0
4.0
3.0
2.0
LOS Timer4
3.0
2.0
1.5
1.0
Delay required before next activation request 1. 2. 3. 4.
86.5
59.0
44.5
30.0
If time elapses and data pump has not moved to Active-1 state, the data pump enters the Deactivated State. Pending Deactivation can be reached from either Active-1 or Active-2 states, if loss of sync word occurs for 6 frames. If sync word detection does not occur before time elapses, the data pump deactivates. When the data pump fails to activate in the Activating state, there is no waiting period in the Deactivated state; the data pump immediately goes Inactive.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 10. Master Mode Activation State Machine
Deactivated TX Off (1, 0, 1) DEACTVTD 0 1
LOS 0 Activation Timer Expiration 1 Inactive TX Off (0, 0, 0)
Power On
ACTREQ 0 1
Pending Deactivation TX On (1, 0, 0) ACTIVE 1 0 ACTIVE 0 1 Active-2 TX On (0, 1, 1)
ACTIVE 1 0
ACTIVE 0 1
Activating TX On (S0,S1) (0, 0, 1)
ACTIVE 1
0
Active-1 Actvation Timer Expiration TX On (0, 1, 0)
NOTE: (n, n, n) indicates the status of bits ST2, ST1 and ST0 respectively.
3.6.2
Slave Mode Activation Sequence
Figure 11 and Figure 12 represent the Slave Data Pump Activation State Machine and the Slave MDSL Framer State Machine. The activation state machines for Slave and Master devices are similar. Both Data Pump machines start at the Inactive State and progress clockwise through the Activating, Active-1, Active-2, Pending Deactivation, and Deactivated States. One difference between them is in the initial condition required to exit from the Inactive State. The Master Data Pump responds to the Activation Request (ACTREQ) signal. The Slave device responds only to the presence of signal energy on the link. Thus, only an active Master device can bring up the link. Once the Master begins transmitting, the Slave device will automatically activate and attempt synchronization. The other difference between the Data Pump state machines is the impetus for the change from the Deactivated to the Inactive State. In the Master Data Pump, expiration of a one-second loss of signal timer (after far end signal energy ceases) will cause the transition. In the Slave the transition occurs immediately on Loss of Signal (LOS).
Datasheet
29
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 8.
Data Pump Activation States
ST2 0 0 0 0 1 1 1 1 ST1 0 0 1 1 0 0 1 1 ST0 0 1 0 1 0 1 0 1 Data Pump State Inactive Activating - Activation timer running Active - Activation timer running (Active-1)1 Active - Activation timer expired (Active-2)1 Pending Deactivation1 Deactivated unused unused
1. The data pump samples the TDATA input for all transmit data except the 14 sync bits at the start of each frame during states 010, 011 and 100.
Figure 11. Slave Mode Activation State Machine
1-sec Timer Deactivated TX Off (1, 0, 1) DEACTVTD 0 1 LOS 0 Activation Timer Expiration 1 Inactive TX Off (0, 0, 0) LOS 1 0
Power On
Pending Deactivation TX On (1, 0, 0) ACTIVE 1 0 ACTIVE 0 1 Active-2 TX On (0, 1, 1)
ACTIVE 1 0
ACTIVE 0 1
Activating TX On (S0,S1) (0, 0, 1)
ACTIVE 1
0
Active-1 Actvation Timer Expiration TX On (0, 1, 0)
NOTE: (n, n, n) indicates the status of bits ST2, ST1 and ST0 respectively.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
3.6.3
Synchronization State Machine
Figure 12 shows the MDSL Synchronization State Machine incorporated in the MDSP. It applies to both Master and Slave devices. Table 9 lists the correspondence between the Synchronization states and Activation states. The Sync state machine is clocked by the receive signal framing. Starting at the initial Out-of-Sync condition (State 0), the device progresses in a clockwise direction through State 1 until Sync is declared in State 2. Two consecutive frame sync word matches are required to achieve synchronization. Once the In-Sync condition is declared, six consecutive frame sync mismatches will cause the device to transition through States 3 through 7 and declare an Out-of-Sync condition in State 8. From State 8, the device will return either to State 2 or to State 0. If the Pending Deactivation timer expires without re-establishing frame sync or if the receive signal energy is no longer detected, the device returns directly to State 0. If frame sync is re-established, the device will return to the In-Sync condition (State 2) through State 9 if two consecutive frames are received without any change of frame alignment (COFA = 0). If a change of frame alignment does occur (COFA = 1), two consecutive matches are required to transition through State 10 back to State 2.
Table 9.
Activation and Synchronization States
Activation State Inactive Activating Active Pending Deactivation Synchronization States State 0 State 1 States 2, 3, 4, 5, 6, and 7 States 8, 9, and 10
Datasheet
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SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 12. MDSL Synchronization State Machine
No Sync Sync Initial "Out-of-Sync" State 0
ACTIVE = 0 LOS = 1
Sync 1
No Sync Sync with No Change Of Frame Alignment Sync (COFA = 0) 9 In Sync State 2
ACTIVE = 1
Sync Sync
LOS = 1 or DEACTVTD = 1
No Sync Out of Sync No Sync State 8
ACTIVE = 0 LOS = 0
LOS = 0
Sync
No Sync
7 No Sync No Sync No Sync Sync with Change Of Frame Alignment
6 No Sync
5 No Sync
4 No Sync
3
10 COFA = 1
Sync COFA = 1
NOTES: 1. "Sync" = Frame Sync Word Match. "No Sync" = Frame Sync Word Mismatch. 2. A 0-to-1 transition on QUIET will set the Sync State Machine from any State to State 0. 3. Expiration of the Activation Timer will set the Sync State Machine from State 1 to State 0.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
4.0
4.1
Application Information
PCB Layout
Refer to Figure 13, Figure 14 and Figure 15, and Table 10. The following are general considerations for PCB layout using the MDSL Data Pump chip set: 1. Use a four-layer or more PCB layout, with embedded power and ground planes 2. Bring the digital power and ground planes down to include pins 1-6 and 24-28 of the IAFE 3. Break up the power and ground planes into the following regions. Tie these regions together at the common point where power connects to the circuit: -- Digital Region -- Analog Region -- VCXO subregion -- IAFE, Line I/F, and IBIAS subregion 4. Use larger feedthroughs ("vias") and tracks for connecting the power and ground planes to the power and ground pins of the ICs than for signal connection 5. Place the decoupling capacitors right at the feed-through power/ground plane ties or on the tracks to the IC power/ground pins as close to the pins as possible 6. On the User Interface Connector, route digital signals to avoid proximity to the TIP, RING, and CT lines 7. Provide at least 100 F or more of bulk power supply decoupling at the point where power is connected to the Data Pump circuit
4.1.1
Digital Section
The following are considerations for PCB layout of digital signals: 1. Keep all digital traces separated from the analog region of the Data Pump layout 2. Provide high frequency decoupling capacitors (0.01 F ceramic or monolithic) around the MDSP as shown in Figure 14 and Figure 15. 3. The capacitor on the MDSP VCC1 pin (pin 1) should be on the IC side of the diode 4. It is possible to replace the NAND gate (shown in Figure 14) with an AND gate
4.1.2
Analog Section
The analog section of the PCB consists of the following subsections:
* * * *
IAFE and power supply decoupling capacitors. Bias Current Generator. Voltage Controlled Crystal Oscillator. Line Interface Circuit.
Datasheet
33
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
The following are considerations for PCB layout of analog signals: 1. Route digital signals AD0, AD1, RX_CK, SER_CTL, TSGN, TMAG, TX_CK, and AGC_SET on the solder side of the PCB 2. route all analog signals on the component side as much as possible 3. Route the following signal pairs as adjacent traces, but keep the pairs separated from each other as much as possible: TTIP/TRING BTIP/BRING RTIP/RRING 4. Do not run the analog ground plane under the transformer line side to maximize high voltage isolation 5. The IAFE should be placed such that pin 1 is near pin 23 of the MDSP 6. pins 12-18 are near the edge of the PCB, with the line transformer and connector
34
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 13. PCB Layout Guidelines
6 7
1 44
40 39
MDSP SK70720
RESET2
AGCKIK
TCK3M
CK25M
30 TMAG GND3 TSGN
DTR
AD0 2
18 19 20 21 22 23 24 25 26 27 28
FS
17
4 5
3
1 28 27 26 25 DVCC 24
AD1
VCC
GND
D2 R4 D1 R3 C7 C3 C4 Y1
6 DGND 7 8 9 RVCC 10 11 RTIP
Digital GND and VCC Planes Analog GND and VCC Planes
IAFE SK70721
RRING RGND BTIP
TVCC 23 22 21
TGND
BRING
20 19
12 13
14 15 16 17 18
C5 R5 R6
C6 R11
C1
C2
R1
R2
R10
R9
n/c
R7
R8
No GND and VCC Planes this side
R12 R13
TIP
RING
NOTE: The VCC and GND planes for Digital and Analog sides should be connected at a single point.
Datasheet
35
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 14. Typical Application for Master Mode Operation (Microprocessor Interface Mode)
+5V
+ C8
C12 D3* C9 C10 J1 C11 C13
2
1 44 3 28
20 23 24 12 15 6
TGND
RVCC DVCC
GND1
GND2
GND3
TVCC
RGND
DGND
VCC1
VCC2
7 10 8 17 12 11 MDSL DATA I/F 4 5 6 9 36..43 35 34 33 32 PROCESSOR I/F CMOS CLOCK OSCILLATOR 16x BIT_CK (+/- 32 PPM)
RFP RDATA_ST RDATA BIT_CK TFP TDATA U1 SK70720 MDSP
TSGN TMAG TX_CK
27 26 25
25 26 27
TSGN TMAG TX_CK
RTIP 13 C5 RRING 14
R5
R6
AGC_SET
24 23 22 21 20 19
28 1 2 3 4 5
AGC_SET AD1 AD0 RX_CK SER_CTL VCO_CK U2 SK70721 IAFE
BTIP 16 C6 BRING 17 TTIP 21 R9 R11 R10 R7 4 6 R12 R13 2 IBIAS 11 R2
+5V
AD1 AD0 RX_CK
ADDR0 ADDR1 ADDR2 ADDR3 D0..D7 READ
SER_CTL VCO_CK
TRING
22
R8 10 T1 1:1.8
PGND
WRITE CHIPSEL INT
TEST
31 18
C7
VPLL
XO
XI
+5V RESET-
SLAVE_CK
NOTES: 1. Diode D3 is optional. 2. The MDSP and IAFE should have independent ground planes connected at a single point near pin 5 of the IAFE. 3. Refer to AN76 or SK70725/SK70721 Data Sheet for improved line interface circuit.
Table 10. Components for Suggested Circuitry (Figure 14 and Figure 15)
Ref C1, 9, 10 C2 C3, 4 Description 0.01 F, ceramic, 10% 100 F, electrolytic, 20% low leakage 5 A @ 25 C 1000 pF, ceramic, 20% Ref R1 R2 R3, 4 R5, 6 Description 5.11 k, 1% R12, 13 35.7 k, 1% 20.0 k, 1% 499 , 1% D1, 2 D3 Ref Description 5.6 , line feed fuse resistor (ALFR-2-5.6-1 IRC) Varicap diode (Motorola MV209) Silicon rectifier diode (1N4001)
1. R7, R8 should be 20 , when R12 and R13 (the 5.6 fuse links) are not used.
MSTR_CK
RESET
9 C3
8 Y1
7
10
13 14 15 16 NC R14 C1 R1
CK_EN
MODE
C2
R3
C4 R4 D1 D2
+5V
36
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 10. Components for Suggested Circuitry (Figure 14 and Figure 15) (Continued)
Ref C5, 6 Description 470 pF, COG or mica, 10% Ref R7, 81 Description 18.2 , 1% 806 , 1% Y1 Ref Description Pullable Crystal 784 kbps: 25.088 MHz (pn:80546/1) 528 kbps: 16.896 MHz (pn:81522/1) 400 kbps: 12.800 MHz (pn:80546/5) 272 kbps: 8.704 MHz (pn:81523/1) (Hy-Q International) 1:1.8 Transformer 400 kbps: Midcom 671-7376 or Pulse Engineering PE-68614 < 400 kbps: Midcom 50109
C7, 11-13
0.1 F, ceramic, 10%
R9, 10
C8
100 F, electrolytic, 20%
R11
2.49 k, 1%
T1
1. R7, R8 should be 20 , when R12 and R13 (the 5.6 fuse links) are not used.
Figure 15. Typical Application for Slave Mode Operation
+5V
+ C8
C12 D3* C9 C10 J1 C11 C13
2
1 44 3 28
20 23 24 12 15 6
TGND
RVCC DVCC
GND1
GND2
GND3
TVCC
RGND
DGND
VCC1
VCC2
7 10 8 17 12 11 MDSL DATA I/F 4 5 6 9 36..43 35 34 33 32 PROCESSOR I/F
TSGN RFP RDATA_ST RDATA BIT_CK TFP TDATA AD1 AD0 U1 ADDR0 SK70720 RX_CK MDSP ADDR1 SER_CTL ADDR2 VCO_CK ADDR3 D0..D7 READ AGC_SET TMAG TX_CK
27 26 25
25 TSGN 26 TMAG 27 TX_CK
RTIP
13 C5
R5
RRING 14 24 23 22 21 20 19 28 1 2 3 4 5 AGC_SET AD1 AD0 RX_CK SER_CTL VCO_CK IBIAS 11 R2 U2 SK70721 IAFE BTIP 16 C6 BRING 17 TTIP 21
R6
R9 R11 R10 R7 4 6 R12 R13 2
+5V
TRING
22
R8 10 T1 1:1.8
PGND
VPLL
WRITE CHIPSEL INT
TEST
31 18
C7
+5V RESET-
XO
XI
SLAVE_CK
MSTR_CK
RESET
9 C3
8 Y1
7
10
13 14 15 16 R4 CMOS CLOCK OSCILLATOR 16x BIT_CK (+/- 32 PPM) C1 R1 D1
NOTES: 1. Diode D3 is optional. 2. The MDSP and IAFE should have independent ground planes connected at a single point near pin 5 of the IAFE. 3. Refer to AN76 or SK70725/SK70721 Data Sheet for improved line interface circuit.
CK_EN
MODE
C2
R3
C4 D2
Datasheet
37
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 11. Transformer Specifications (Figure 14 and Figure 15, Reference T1)
Measure Turns Ratio (IC:Line) Line Side Inductance 400 kbps < 400 kbps Leakage Inductance Interwinding Capacitance THD Longitudinal Balance Return Loss Isolation Primary DC Resistance Secondary DC Resistance Operating Temperature Value 1:1.8 2.8 mH 11.7 mH Tolerance 1% 10% 5-196 kHz 40-200 kHz -
50 H 70 pF -70 dB 50 dB 20 dB
1500 VRMS
3.2 6.0
-40 to +85 C
Table 12. Crystal Specifications (Figure 14 and Figure 15, Reference Y1)
Measure Frequency @CL = 20 pF Mode Pullability (CL = 24 pF O 16 pF) Operating Temperature Temperature Drift Aging Drift Series Resistance Drive Level Value 8.704 to 25.088 MHz Offset -0, +40 ppm
Fundamental, Parallel Resonance
+160 ppm
-40 to +85 C
-
30 ppm 5 ppm/year 15
0.5 mW
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 16. MDSP Control and Status Signals (Stand-alone Mode)
5 4 6 9 32 37 36 38 43 39 40 41 nc 42 33 34 35
ACTREQ QUIET LOOPID ACTVNG TMR_EXP DEACTVTD LOS ILMT TXTST RPTR FELB BELB RCLKU CHIPSEL WRITE READ U1 SK70720 MDSP
NOTE: This figure illustrates the MDSP control and status signals in stand-alone mode. All other MDSP and IAFE signals are connected as shown in Figure 14 and Figure 15.
Datasheet
39
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
5.0
Note:
Test Specifications
The minimum and maximum values in Table 13 through Table 23 and Figure 17 through Figure 24 represent the performance specifications of the Data Pump and are guaranteed by test, except where noted by design.
Table 13. IAFE Absolute Maximum Ratings
Parameter Supply voltage1 (reference to ground2) Input voltage
2, 3
Symbol TVCC, RVCC, DVCC TVCC, RVCC, DVCC - TSTOR
Min -0.3 - 0.3V - -65
Max +6.0 VCC + 0.3 25 +150
Unit
V V mA C
, any input pin
Continuous output current, any output pin Storage temperature
Caution:
Operations at the limits shown may result in permanent damage to the Integrated Analog Front End. Normal operation at these limits is neither implied nor guaranteed.
1. No supply input may have a maximum potential of more than 0.3 V from any other supply input. 2. TGND = 0V; RGND = 0V; DGND = 0V. 3. TVCC = RVCC = DVCC = VCC.
Table 14. IAFE Recommended Operating Conditions
Parameter DC supply Ambient operating temperature Symbol TVCC, DVCC, RVCC TA Min 4.75 -40 Typ 5.0 +25 Max 5.25 +85 Unit V C
Table 15. IAFE DC Electrical Characteristics (Over Recommended Range)
Parameter Supply current (full operation) Input low voltage Input high voltage Output low voltage
2 3 4
Sym ICC VIL VIH VOL VOH IIL CIN CLREF
Min - - 4.5 - 4.5 - - -
Typ1 80 - - - - - 12 -
Max 120 0.5 - 0.2 - 50 - 20
Unit mA V V V V
Test Conditions 83 resistor across TTIP and TRING
IOL < 1.6 mA IOH < 40 A 0 < VIN < VCC
Output high voltage
Input leakage current
A
pF pF
Input capacitance (individual pins) Load capacitance (MSTR_CK output) 1. 2. 3. 4.
Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. IOL is sinking current. IOH is sourcing current. Applies to pins 3, 4, 25, 26 and 27.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 16. IAFE Transmitter Electrical Parameters (Over Recommended Range)
Parameters Sym - Isolated pulse height at TTIP, TRING - - - Setup time (TSGN, TMAG) Hold time (TSGN, TMAG) tTSMSU tTSMH Min +2.455 -2.825 +0.818 -0.941 5 12 Typ +2.640 -2.640 +0.880 -0.880 - - Max +2.825 -2.455 +0.941 -0.818 - - Unit Vp Vp Vp Vp ns ns Test Conditions TDATA High, TFP Low (+3) TDATA Low, TFP Low (-3) TDATA High, TFP High (+1) TDATA Low, TFP High (-1)
1. Pulse amplitude measured across a 135 resistor on the line side of the transformer using the application circuit shown in Figure 14 and Table 11.
Figure 17. IAFE Normalized Pulse Amplitude Transmit Template
-0.4 T B = 1.07 C = 1.00 D = 0.93
0.4 T
Normalized Levels A B C D E F G H .01 1.07 1.00 0.93 0.03 -0.01 -0.16 -0.05
Quaternary Symbols (values in Volts) +3 0.0264 2.8248 2.6400 2.4552 0.0792 -0.0264 -0.4224 -0.1320 +1 0.0088 0.9416 0.8800 0.8184 0.0264 -0.0088 -0.1408 -0.0440 -1 -0.0088 -0.9416 -0.8800 -0.8184 -0.0264 0.0088 0.1408 0.0440 -3 -0.0264 -2.8248 -2.6400 -2.4552 -0.0792 0.0264 0.4224 0.1320
T = 7.35 s, 5.00 s, 3.79 s, 2.55 s (@ 272, 400, 528 & 784 kbps)
A = 0.01 F = -0.01 -1.2 T -0.6 T G = -0.16 0.5 T
1.25 T E = 0.03
14 T
50 T A = 0.01 F = -0.01 H = -0.05
NOTE: Pulse amplitude measured across a 135 resistor on the line side of the transformer using the application circuit shown in Figure 14 and Table 11.
Datasheet
41
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 18. Transmit Power Spectral Density--Upper Bound
-20 -32 dBm/Hz @ 68 kHz -34 dBm/Hz @ 100 kHz -35 dBm/Hz @ 132 kHz -37 dBm/Hz @ 196 kHz
-40
-60
272 kbps 400 kbps 528 kbps 784 kbps
dBm/Hz
-80 -95 dBm/HZ -100
-120
-117 dBm/Hz @ 1.96 MHz
-140 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
Table 17.
IAFE Receiver Electrical Parameters (Over Recommended Range)
Sym tADD - - Min - - - Typ - -80 1.0 Max 25 - 1.01 Unit ns dB V/V V(RTIP, RRING) = 3 Vpp @ 50 kHz Test Conditions
Parameter Propagation delay (AD0, AD1) Total harmonic distortion RTIP, RRING, to BTIP, BRING gain ratio
42
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 19. IAFE Receiver Syntax and Timing
A) Receiver Syntax B) Receiver Timing
VCO_CK
VCO_CK
PROP DELAY
VCO_CK/2 (INTERNAL)
AD0, AD1 AGC_SET
RX_CK
AD0
AD1
AGC_SET
Datasheet
43
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 20. Typical Performance vs. Line Rate and Cable Gauge (Metric)
Typical performance
8,000 7,500 7,000 6,500 6,000 Reach (Meter) 5,500 5,000 4,500 4,000 3,500 3,000 2,500 2,000 272 ETSI - 0dB, 26 AWG ETSI - 0dB, 24 AWG Noise Free, 26 AWG Noise Free, 24 AWG
336
400
464
528 Line Rate
592
656
720
784
NOTES: 1. Noise-free range is specified with a Bit Error Rate (BER) less than or equal to 1.0 x 10-7. 2. The range with ETSI shaped noise corresponds to a 0 dB margin with a BER less than or equal to 1.0 x 10-7. The power spectral density for ETSI standard noise is defined in ETSI ETR-152 section 6.3.3.1. 3. Refer to AN76 or SK70725/SK70721 Data Sheet for improved line interface circuit.
44
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 21. Typical Performance vs. Line Rate and Cable Gauge (English)
Typical performance
30,000
25,000
20,000 Reach (ft)
15,000
10,000 SNEXT - 6dB, 26 AWG SNEXT - 6 dB, 24 AWG 5,000 Noise Free, 26 AWG Noise Free, 24 AWG 0 272
336
400
464
528 Line Rate
592
656
720
784
NOTES: 1. Noise-free range is specified with a Bit Error Rate (BER) less than or equal to 1.0 x 10-7. 2. There are no generally accepted noise models for MDSL systems. Performance simulations using ANSI Near End Cross Talk (NEXT) noise models indicate worst case performance degradation should be less than 2 kft (0.6 km) from the noisefree performance. 3. Refer to AN76 or SK70725/SK70721 Data Sheet for improved line interface circuit.
Table 18. MDSP Absolute Maximum Ratings
Parameter Supply voltage (reference to ground ) Input voltage , any input pin Continuous output current, any output pin Storage temperature
2 1 2
Symbol VCC2, VCC1 - - TSTOR
Min -0.3 - 0.3 - -65
Max +6.0 VCC2 + 0.3 25 +150
Unit V V mA C
Table 19. MDSP Recommended Operating Conditions
Parameter Symbol VCC12 DC supply
1
Min 3.95 4.75 -0.25 -40
Typ 5.0 5.0 -
Max 5.25 5.25 +0.9 +85
Unit V V V C
VCC2 VCC2-VCC1
Ambient operating temperature
SK70720PE
TA
1. To derive this supply, a 1N4001 (or equivalent) diode may be connected between VCC2 and VCC1 as shown in Figure 14 and Figure 15. 2. If a diode is used, it should be selected to meet VCC1 minimum specifications.
Datasheet
45
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 20. MDSP DC Electrical Characteristics (Over Recommended Range)
Parameter 272 kbps 400 kbps 528 kbps 784 kbps Sym Min - - - - - 4.0 - VCC2 - 0.5 - - - - Typ1 35 48 62 100 - - - - - - 12 - Max 45 60 80 135 0.5 - GND +0.3 - 50 30 - 15 Unit Test Conditions
Supply current
ICC
mA
Input low voltage Input high voltage Output low voltage2 Output high voltage
3 4 5
VIL VIH VOL VOH IIL ITOL CIN CLREF
V V V V IOL < 1.6 mA IOH < 40 A 0 < VIN < VCC2 0 < V < VCC2
Input leakage current
A A
pF pF
Tristate leakage current
Input capacitance (individual pins) Load capacitance (MSTR_CK output) 1. 2. 3. 4.
Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. IOL is sinking current. IOH is sourcing current. Applies to pins 4, 5, 11, 12, 14, 16, 18, 19, 22, 23, 24, 29, 31, 33, 34 and 35. Applies to pins 5, 6, 9, 13, and 36-43, when configured as inputs. 5. Applies to pins 7, 8, 10, 15, 17, 30, 32 and 36-43, when tristated.
Table 21. MDSL Data Interface Timing Specifications (Figure 22)
Parameter BIT_CK frequency MSTR_CK frequency MSTR_CK frequency tolerance (Master Mode) SLAVE_CK frequency tolerance (Slave Mode)2 BIT_CK pulse width high 272 kbps 400 kbps 528 kbps 784 kbps Transition time on any digital output3 Transition time on any digital input TDATA, TFP setup time to BIT_CK rising edge TDATA, TFP hold time from BIT_CK rising edge RDATA, RFP, RDATA_ST delay from BIT_CK falling edge 1. 2. 3. 4. 5. 6. Symbol fBIT_CK fREFCK tolRCK tolSLAVE_C K Min 272 4.352 -32 -32 - - tIPW tTO tTI tTSU tTH tTD - - - - 100 100 0 Typ1 - - 0 0 1.840 1.250 0.950 0.638 5 - - - - Max 784 12.544 +32 +32 - - - - 10 25 - - 150 ns ns ns ns ns Unit kHz MHz ppm ppm
Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. SLAVE_CK must meet this tolerance about a frequency of 16 times the BIT_CK frequency in slave mode. Measured with 15 pF load. These parameters apply only to the master mode data pump programmed for repeater applications as shown in Figure 22. The values are for minimum line rate 272 Kbps. The values are for minimum line rate 784 Kbps.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 21. MDSL Data Interface Timing Specifications (Figure 22) (Continued)
Parameter TFP pulse width4 TFP falling edge to BIT_CK rising edge
4
Symbol tTFPW tTFIR tTSUR
Min 36775 1838 25
5
Typ1 - - -
Max 12766 638 -
6
Unit ns ns ns
TFP set-up time to MSTR_CK rising edge 1. 2. 3. 4. 5. 6.
Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. SLAVE_CK must meet this tolerance about a frequency of 16 times the BIT_CK frequency in slave mode. Measured with 15 pF load. These parameters apply only to the master mode data pump programmed for repeater applications as shown in Figure 22. The values are for minimum line rate 272 Kbps. The values are for minimum line rate 784 Kbps.
Datasheet
47
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 22. MDSL Data Interface Timing
A) Non-Repeater Mode
1
f BIT_CK
t
IPW
BIT_CK tTH TDATA, TFP tTD RATA, RFP, RDATA_ST
B) Repeater Mode
VOH VOL
tTSU
tTI
VIH VIL
tTO
VOH VOL
TFP
1
VIH VIL
f BIT_CK
tIPW
tTFPW tTFIR
tTI
BIT_CK tTH TDATA tTO tTSU
VOH VOL
tTH
VIH VIL
tTD RATA, RFP, RDATA_ST
C) Repeater Mode
VOH VOL
MSTR_CK
VIH VIL
TFP
VIH VIL
tTSUR
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 22. MDSP/Microprocessor Interface Timing Specifications (Figure 19 & Figure 20)
Parameter RESET pulse width Low RESET to INT clear (10 k resistor from INT to VCC2) RESET to data tristate on D0-7 CHIPSEL pulse width Low CHIPSEL Low to data active on D0-7 CHIPSEL High to data tristate on D0-7 READ pulse width Low READ Low to data active READ High to data tristate Address to Valid Data Address setup to WRITE rising edge Address hold from WRITE rising edge WRITE pulse width Low Data setup to WRITE rising edge Data hold from WRITE rising edge READ High to INT clear when reading register RD0 Symbol tRPWL tINTH tDTHZ tCSPWL tCDLZ tCDHZ tRSPWL tRDLZ tRDHZ tPRD tASUW tAHW tWPWL tDSUW tDHW tINTR Min 0.1 - - 200 - - 100 - - - 20 10 100 20 10 - Typ - - - - - - - - - - - - - - - - Max 5 300 100 - 80 80 - 80 80 80 - - - - - 400 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Timing for all outputs assumes a maximum load of 30 pF. 2. "Address" refers to input signals CHIPSEL, A0, A1, A2, and A3. "Data" refers to I/O signals D0, D1, D2, D3, D4, D5, D6, and D7.
Table 23. General System and Hardware Mode Timing
Parameter TDATA to TTIP/TRING 272 kbps 400 kbps 528 kbps 784 kbps Throughput delay RTIP/RRING to RDATA 272 kbps 400 kbps 528 kbps 784 kbps "ACTREQ" input transitional pulse width (High or Low) Hardware Mode "QUIET" transitional pulse width (High-to-Low) 5 - - - - - - 5 154 105 79.6 53.6 - 206 140 106 72 - - - - - 29.4 20.0 15.2 10.2 36.8 25.0 18.9 12.5 Min Typ1 Max Unit
s
s
s s
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
49
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Figure 23. RESET and INTERRUPT Timing (P Control Mode)
A) Reset Timing
tRPWL
VIH VIL
RESET
tINTH
VOH
INT
VOL
tDTHZ D<0:7> (Output)
VOH VOL
B) Interrupt Timing
READ
VIH VIL
CHIPSEL
VIH VIL
ADDR<0:3>
VIH VIL
t INTR
VOH
INT
VOL
50
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Figure 24. Parallel Data Channel Timing
A) Chip Select Timing
tCSPWL
VIH
CHIPSEL (READ = 0) tCDLZ
VIL
tCDHZ
VOH
D<0:7>
(Output)
B) Data Read Timing
VOL
CHIPSEL ADDR<0:3> tRSPWL
VIH VIL
VIH
READ
(WRITE = 1) VIL
tRDLZ D<0:7>
(Output)
C) Data Write Timing
tPRD
tRDHZ
VOH VOL
tASUW CHIPSEL ADDR<0:3> tAHW tWPWL WRITE
(READ = 1)
tTI
VIH VIL
VIH VIL
tDSUW D<0:7>
(Input)
tDHW
VIH VIL
Datasheet
51
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
6.0
Register Definitions
Three write registers and seven read registers are available to the user. Table 24 lists these registers and the following paragraphs describe them in greater detail. Some of the registers contain reserved bits. Software must deal correctly with reserved fields. For reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. In some cases, software must program reserved bit positions to a particular value. This value is defined in the individual bit descriptions. After asserting the RESET signal, the Data Pump initializes its registers to the default value.
Table 24. Register Summary
Address A3-A0 0000 0001 0010 0011 0100 0101 0110 0111-1001 WR# WR0 WR2 WR3 Write Registers Name Main Control reserved Interrupt Mask Read Coefficient Select reserved reserved reserved reserved Table 25 26 27 RD# RD0 RD1 RD2 RD3 RD4 RD5 RD6 Main Status Receiver Gain Word Noise Margin Coefficient Read Register (lower byte) Coefficient Read Register (upper byte) Activation Status Receiver AGC and FFE Step Gain reserved Read Registers Name Table
28
29 30 31 31 32 33 -
6.0.1
WR0--Main Control Register
Address: Default: Attributes: A<3:0> = 0000 00h Write Only
Control Register bits serve the same purpose in Software Mode as the like-named individual pins in Hardware Mode. Table 25 lists bit assignments for the WR0 register. Table 25. Main Control Register WR0
Bit Description Transmit Test Pattern Enable (TXTST). Set TXTST to 1 to enable isolated transmit pulse generation. One symbol is output every 4702 or 4706 BIT_CK cycles. TDATA controls the sign and TFP controls the magnitude of the transmitted symbols according to the 2B1Q encoding rules. In the Slave mode when the TXTST mode is selected, the Data Pump may begin activation. Back-End Loop Back (BELB). In the Active State, set BELB to 1 to enable an internal, transparent loopback of the MDSP RDATA to TDATA and RFP to TFP. Front End Loop Back (FELB). In the Master mode with the Data Pump in the Inactive State, set FELB to 1 to enable an IAFE front-end loopback. The Data Pump will begin activation and transmission on the line, but will ignore any signal from the Slave instead synchronizing to its own transmit signal. 4 Repeater Mode (RPTR). The RPTR bit is set to 1 and the MODE pin is pulled High to program the Data Pump for operation on the side of the MDSL repeater driving a remote slave. RPTR is set to 0 and the Master pin is tied Low to program the Data Pump for operation on the side of the repeater driven by the Master.
7
6
5
52
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 25. Main Control Register WR0 (Continued)
Bit 3 Description Loop Number (LOOPID). In two loop MDSL applications, LOOPID is set at the Master end of the loop to select the frame sync word format to encode the loop number. Insertion Loss Measurement Test (ILMT). Set ILMT to 1 to enable transmission of a scrambled all ones insertion loss measurement test pattern. In the Slave configuration when the ILMT mode is selected, the Data Pump may begin activation. Quiet Mode (QUIET). Set QUIET to 1 to force the Data Pump into the Deactivated State with the transmitter silent. Setting QUIET to 0 will not cause the Data Pump to reactivate. In the Slave mode, the Data Pump will not respond to a signal from the Master when QUIET is set to 1, but may activate after QUIET is set to 0 even if the Master transmission has already ceased. Activation Request (ACTREQ). In the Master mode when the Data Pump is in the Inactive State and Quiet is set to 0, setting the ACTREQ bit to 1 will initiate an activation sequence. Because ACTREQ is a level- rather than an edgetriggered signal, it should be reset to 0 again within approximately 25 seconds to prevent the immediate start of another activation cycle if the current activation attempt fails. If an activation attempt fails, the processor should allow the Data Pump to remain in the Inactive State where the transmitter is silent for the Activation Timer duration (Table 7) before generating another activation request. This delay will allow the Slave to return to the Inactive State. It is possible to shorten this quiet period following a failed activation by implementing additional algorithms described in the section entitled "Activation State Machines."
2
1
0
6.0.2
WR2--Interrupt Mask Register
Address: Default: Attributes: A<3:0> = 0010 00h Write Only
Table 26 shows the various interrupt masks provided in register WR2. Table 26. Interrupt Mask Register WR2
Bit 7:6 5 4 3 2 1 0 Reserved. Must be set to 0. LOSMSK. 1=Masked. 0=Not Masked. Interrupt mask for the LOS condition. DEACTMSK. 1=Masked. 0=Not Masked. Interrupt mask for the DEACTVTD condition. ACTBMSK. 1=Masked. 0=Not Masked. Interrupt mask for the ACTIVE condition. ACTMSK. 1=Masked. 0=Not Masked. Interrupt mask for the TMR_EXP condition and the ACTIVE condition. Reserved. Must be set to 0. Enable coefficient read register (CRD1). 1=Enable. 0=Disable. Used in conjunction with WR3 for reading coefficient values. Description
6.0.3
WR3--Read Coefficient Select Register
Address: Default: Attributes: A<3:0> = 0011 00h Write Only
Table 27 lists the bit maps used to select the coefficient read from the MDSP.
Datasheet
53
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 27. Read Coefficient Select Register WR3
Hex Value Selected Registers Description
00-07 08-0F 10-15 16-19 1A 1B-FF
DFE1-DFE8 EC1-EC8 FFE1-FFE6 reserved AGC Tap reserved
DFE coefficients Echo Cancellation FFE coefficients 1-6 - AGC Tap -
6.0.4
RD0--Main Status Register
Address: Default: Attributes: A<3:0> = 0000 xxh (x = undefined) Read Only
Status Register bits serve the same purpose in Software Mode as the like-named individual pins in Hardware mode. Table 28 lists the bit assignments in this register. Table 28. Main Status Register RD0
Bit 7 6 5 4 Active Description Timer Expiry (TMR_EXP). Set to 1 to indicate Activation timer expiration. * Causes interrupt on changing from 0 to 1; masked by ACTMSK = 1 * Latched event; reset on read, with persistence while in the Active State TIP/RING polarity reversed (INVERT). 0 = polarity reversal. Valid only in Active-1 or Active-2 states. Change Of Frame Alignment (COFA). Indicates that re-acquisition of frame sync is in a different position with respect to the last frame position. Does not cause interrupt. Latched event; reset on read. Loss Of Signal (Slave). 1 = loss of line signal energy detected and entry into the Inactive state. Loss of Signal (Master). 1 = loss of signal for 1 second on entering Inactive State. * Causes interrupt on transitions from 0 to 1 or 1 to 0 that are masked by LOSMSK = 1 * LOS/LOS is not a latched event 3 Loop Number Control (LOOPID). 0 = loop 1; 1 = loop 2. Valid only in Active States, 0 in all others. Deactivation Indicator (DEACTVTD). 1 = expiration of the Deactivation timer and the transition from the Pending Deactivation state to the Deactivated state. * Causes interrupt on changing from 0 to 1; masked when DEACTMSK = 1 * Latched event; reset on read; with persistence while in the Deactivated State Link Active Indicator, (ACTIVE), active Low. 1 = entry into the Pending Deactivation state. * Causes interrupt on changing from 0 to 1; masked by ACTBMSK = 1 * Latched event; reset on read; with persistence while in the Pending Deactivation State Link Active Indicator, (ACTIVE), active High. 1 = Completion of layer 1 activation and entry into the Active-1 state. * Causes interrupt on changing from 0 to 1; masked by ACTMSK = 1 * Latched event; reset on read with persistence if still in the Active State
2
1
0
54
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
6.0.5
RD1--Receiver Gain Word Register
Address: Default: Attributes: A<3:0> = 0001 xxh (x = undefined) Read Only
The 8-bit word in this register is the eight most significant bits of the main FFE AGC tap, which, along with the AGC and DAGC values (RD6), represent the receiver gain required to compensate for line loss, and to normalize the receive 2B1Q pulses to a fixed threshold. Bit b7 (sign bit, always 0) is the MSB with bit b0 the LSB. The AGC tap value is determined as follows: Table 29. Receiver Gain Word Register
Bit 7:0 Description FFE AGC Tap Value (eight most significant bits).
6.0.6
RD2--Noise Margin Register
Address: Default: Attributes: A<3:0> = 0010 xxh (x = undefined) Read Only
The noise margin of the received signal is an input to the MDSL framer's Activation State Machine. The noise margin must reach a threshold level before the MDSL framer can transition to the fully Active State. The MDSP provides a calculated, logarithmic noise margin value used by the MDSL framer. This eight-bit word, stored in register RD2, is available every baud, although updated only every 64 baud. Table 30 shows the noise margin coding. To calculate the SNR, use this equation: SNR =Noise Margin + 21.5 dB. Error propagation in the DFE and de-scrambler may introduce some fractional errors in this formula, however, the relationship between the SNR and the noise margin remains valid as long as the noise follows a Gaussian distribution. Since the average period of the calculation is very short (64 bauds), the recommended procedure for evaluating transmission quality is to average at least 1000 samples. Table 30. Noise Margin Register RD2 (Noise Margin Coding)
MSB 7 0 0 0 0 0 6 0 0 0 0 0 5 1 1 1 1 1 4 1 0 0 0 0 Bit 3 0 1 1 1 0 2 1 1 0 0 1 1 0 1 1 0 1 LSB 0 1 1 1 1 1 Noise Margin1 +26.5 +23.5 +21.5 +20.5 +19.5
0
0
1
0
0
1
0
1
+18.5
1. Accuracy of noise margin is 1 dB.
Datasheet
55
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 30. Noise Margin Register RD2 (Continued) (Noise Margin Coding)
MSB 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 5 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 4 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit 3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 2 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Noise Margin1 +18.0 +17.0 +16.0 +15.0 +14.0 +13.0 +12.0 +11.0 +10.0 +9.0 +8.0 +7.0 +6.0 +5.0 +4.0 +3.0 +2.0 +1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0
1. Accuracy of noise margin is 1 dB.
6.0.7
RD3 (LSB), RD4 (MSB)--Coefficient Read Register
Address: Default: Attributes: RD3 (A<3:0> = 0011) RD4 (A<3:0> = 0100) xxh (x = undefined) Read Only
Coefficient Read Word (read from the MDSP) comes from the location configured in the Read Coefficient Select Register (WR3, Address A<3:0> = 0011). The MDSP updates this word on the rising edge of the receive clock, RX_CK. Read register RD3 is the lower byte, and RD4 is the upper byte.
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Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
Table 31. Coefficient Read Register
Bit 7:0 Description Coefficient Word Value. RD3 contains the lower byte; RD4 the upper byte.
6.0.8
RD5--Activation Status Register
Address: Default: Attributes: A<3:0> = 0101 xxh (x = undefined) Read Only
The ACT bits indicate the current state of the MDSP transceiver during the Activating State as listed in Table 32. For any state other than the Activating State, the ACT bits will be "0000." Table 32. Activation Status Register RD5
ACT Bits 3:0 0000 0001 0010 0011 0100 0101 0110 0111 1000 State in Master Mode Inactive Pre-AGC Pre-EC SIGDET AAGC EC PLL 4LVLDET FRMDET State in Slave Mode Inactive Wait AAGC EC PLL1 PLL2 4LVLDET FRMDET -
6.0.9
RD6--Receive Step Gain Register
Address: Default: Attributes: A<3:0> = 0110 xxh (x = undefined) Read Only
This 8-bit register represents AGC and FFE gain coefficients (GAGC and GFFE, respectively). Bit assignments are listed in Table 33. The approximate line loss (LL) can be determined using these values in the following equation: LL = 20log10 (GFFE * AGC tap) + GAGC + 28 dB. GFFE corresponds to DAGC in the MDSP and GAGC is from the IAFE. Bits ST0-ST2 indicate the Data Pump activation states as shown in Figure 10, Figure 11, and Table 8.
Datasheet
57
SK70720 and SK70721 -- Multi-Rate DSL Data Pump Chip Set
Table 33. Receiver AGC and FFE Step Gain Register RD6
Bit 7 6 ST2. Data Pump Activation State-bit 2. ST1. Data Pump Activation State-bit 1. GFFE1, GFFE0. Digital Gain Word-bit 1 and Digital Gain Word-bit 0. Bits <5:4>GFFE Value 5:4 00 = 20 = 1 01 = 21 = 2 10 = 22 = 4 11 = 23 = 8 3 ST0. Data Pump Activation State-bit 0. GAGC2-GAGC0. Analog Gain Word-bit 2,1 and 0. Bits <2:0>GAGC Value (dB) 000 = -12 001 = -10 2:0 010 = -8 011 = -6 100 = -4 101 = -2 110 = 0 111 = +2 Description
58
Datasheet
Multi-Rate DSL Data Pump Chip Set -- SK70720 and SK70721
7.0
Mechanical Specifications
Figure 25. Data Pump Package Specifications
Integrated Analog Front End (IAFE) * 28-pin PLCC * P/N SK70721PE * Extended Temperature Range (-40 to + 85 C) MDSL Digital Transceiver (MDSP) * 44-pin PLCC * P/N SK70720PE * Extended Temperature Range (-40 to + 85 C)
C L
C L
C
C
B
B
D1 D
D1 D
D A2 A1 F A
A1 A2
D A F
Inches Dim Min A A1 A2 B C D D1 F 0.165 0.090 0.062
1
Millimeters Dim Max 0.180 0.120 0.083 Min 4.191 2.286 1.575
1
Inches Min A A1 A2 B C D D1 F 0.165 0.090 0.062
1
Millimeters Max 0.180 0.120 0.083 Min 4.191 2.286 1.575
1
Max 4.572 3.048 2.108
Max 4.572 3.048 2.108
.050 BSC (nominal) 0.026 0.485 0.450 0.013 0.032 0.495 0.456 0.021
1.27 BSC (nominal) 0.660 12.319 11.430 0.330 0.813 12.573 11.582 0.533
.050 BSC (nominal) 0.026 0.685 0.650 0.013 0.032 0.695 0.656 0.021
1.27 BSC (nominal) 0.660 17.399 16.510 0.330 0.813 17.653 16.662 0.533
1. BSC--Basic Spacing between Centers.
1. BSC--Basic Spacing between Centers.
Datasheet
59

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