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| DATASHEET 0.11 m Processor System for ARM926EJ-STM cw001200_agflxr_2_0 February 2005 Preliminary (R) DB08-000261-01 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using production parts. This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. Purchase of I2C components of LSI Logic Corporation, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C standard Specification as defined by Philips. Document DB08-000261-01, February 2005 This document describes LSI Logic Corporation's 0.11 m Processor System for ARM926EJ-S cw001200_agflxr_2_0 and will remain the official reference source for all revisions/releases of this product until rescinded by an update. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT LSI Logic, the LSI Logic logo design, CoreWare, Gflx, GigaBlaze, HyperPHY, RapidChip, RapidReady, and RapidWorx are trademarks or registered trademarks of LSI Logic Corporation. ARM and Multi-ICE are registered trademarks and ARM926EJ-S and EmbeddedICE are trademarks of ARM Ltd., used under license. All other brand and product names may be trademarks of their respective companies. JSS To receive product literature, visit us at http://www.rapidchip.com. For a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/index.html ii Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Preface The 0.11 m Processor System for ARM926EJ-STM (cw001200_agflxr_2_0) is compatible with the RapidWorx(R) design tools and design methodology and based on 0.11 m process technology. Audience This document is intended for software engineers, hardware engineers, system architects, platform ASIC designers, engineering managers, and marketing managers who are evaluating the Processor System for ARM926EJ-S. This document assumes that you have some familiarity with microprocessors and related support devices. The people who benefit from this book are: * * Organization Engineers and managers who are evaluating the processor for possible use in a system Engineers who are designing the processor into a system This document contains the following chapters: * Chapter 1, Introduction, defines the RapidChip(R) system, introduces its main CoreWare components, and provides an overview of RapidChip Platform ASIC, CoreWare IP, and the Processor System for ARM926EJ-S. Chapter 2, Architectural Description, describes the Processor System for ARM926EJ-S architecture. Chapter 3, Registers, describes the Processor System for ARM926EJ-S programming model. * * 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. iii * * Chapter 4, Signal Summary, describes the signals used by the Processor System for ARM926EJ-S. Chapter 5, Specifications, describes the specifications required by the Processor System for ARM926EJ-S. Related Publications The following LSI Logic publications are related to this document: * * * * 0.11 m Processor System for ARM926EJ-S Technical Manual, DB14-000299-01 0.11 m Processor System for ARM926EJ-S Integration Guide, DB09-000147-02 0.11 m Processor System for ARM926EJ-S Release Notes 0.11 m Processor System for ARM926EJ-S Errata Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active LOW end in an "n." Hexadecimal numbers are indicated by the prefix "0x"--for example, 0x32CF. Binary numbers are indicated by the prefix "0b"--for example, 0b0011.0010.1100.1111. iv Preface Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Contents Chapter 1 Introduction 1.1 RapidChip Technology Overview 1.1.1 RapidChip Platform ASICs 1.1.2 CoreWare IP Program 1.1.3 RapidReadyTM Certification 1.1.4 RapidWorx Processor System for ARM926EJ-S Product Description 1.2.1 Processor System for ARM926EJ-S Overview 1.2.2 Processor System for ARM926EJ-S Features and Benefits 1.2.3 Processor System for ARM926EJ-S Options 1.2.4 Processor System for ARM926EJ-S Deliverables Required Platform ASIC Resources Required Cores 1-1 1-1 1-2 1-2 1-2 1-3 1-3 1-4 1-5 1-6 1-6 1-7 1.2 1.3 1.4 Chapter 2 Architectural Description 2.1 Processor System for ARM926EJ-S Block Diagram 2.2 ARM926EJ-S Processor Block Description 2.3 Instruction AHB Bus Block Description 2.4 Data AHB Bus Block Description 2.5 APB Bus Block Description 2.6 Interrupts Chapter 3 Registers 3.1 Register Summary 3.1.1 External SRAM Registers 2-1 2-2 2-3 2-3 2-4 2-5 3-1 3-1 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. v 3.2 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 System 3.2.1 3.2.2 GPIO Registers UART Registers APB Timer Registers Ethernet Controller Registers ApI2c Registers ApVic Registers Remap Register Memory Map System Boot Settings Memory Map and Addressing 3-1 3-3 3-4 3-4 3-6 3-9 3-10 3-10 3-10 3-11 Chapter 4 Signal Summary 4.1 4.2 Chapter 5 Specifications 5.1 5.2 5.3 Physical Specifications Operating Conditions AC Electrical Specifications 5.3.1 Input Timing 5.3.2 Output Timing 5.3.3 Pass-Through Timing 5-1 5-1 5-2 5-3 5-7 5-12 System Interfaces Interface Signals 4-1 4-4 vi Contents Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Figures 2.1 4.1 5.1 Processor System for ARM926EJ-S Block Diagram System Interfaces AC Specifications 2-2 4-2 5-2 vii Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. viii Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Tables 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 5.1 5.2 5.3 5.4 5.5 Chip Select Control Register Summary GPIO Register Summary UART Register Summary APB Timer Register Summary Ethernet Controller Register Summary ApI2c Register Summary ApVic Register Summary Chip Select Control Register Summary System Boot Setting: BRBOOTSEL=0 System Boot Setting: BRBOOTSEL=1 Address Map for Instruction AHB Bus--TCMs Disabled Address Map for Instruction AHB Bus--TCMs Enabled Address Map for Data AHB Bus--TCMs Disabled Address Map for Data AHB Bus--TCMs Enabled Address Map for APB Bus Peripherals (TCMs Enabled or Disabled) Clock Generation Signals Reset Signals ARM926EJ-S Signals AHB Master Expansion Port Signals Ethernet Signals ApVic Signals ApI2c Signals UART Signals GPIO Signals Timer Signals SRAM, Flash, ROM Port Signals Instruction AHB Multiport Memory Controller Port Signals Data AHB Multiport Memory Controller Port Signals AHB Slave Expansion Port Signals JTAG Signals Processor System for ARM926EJ-S Timing Conditions Maximum Clock Frequency Input Timing in the CLK Domain Input Timing in the HCLK Domain Input Timing in the HOST_CLK Domain 3-1 3-2 3-3 3-4 3-4 3-7 3-9 3-10 3-11 3-11 3-12 3-13 3-14 3-15 3-16 4-4 4-5 4-5 4-6 4-6 4-8 4-8 4-9 4-10 4-10 4-10 4-11 4-11 4-12 4-13 5-2 5-3 5-4 5-4 5-5 ix Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 Input Timing in the MII_RXCLK Domain Input Timing in the MII_TXCLK Domain Input Timing in the PCLK Domain Input Timing in the TCK Domain Output Timing in the CLK Domain Output Timing in the HCLK Domain Output Timing in the HOST_CLK Domain Output Timing in the MII_RXCLK Domain Output Timing in the MI_TXCLK Domain Output Timing in the PCLK Domain Pass-Through Paths in the HCLK Domain 5-6 5-6 5-6 5-7 5-8 5-8 5-10 5-10 5-11 5-11 5-13 x Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Chapter 1 Introduction The 0.11 m Processor System for ARM926EJ-STM is compatible with the RapidWorx(R) design tools and design methodology and ready to integrate into the RapidChip(R) Platform ASIC families. This chapter contains the following sections: * * Section 1.1, "RapidChip Technology Overview" Section 1.2, "Processor System for ARM926EJ-S Product Description" 1.1 RapidChip Technology Overview RapidChip Platform ASICs, RapidWorx design methodology, and RapidWorx design tools are all based on RapidChip Technology. This section briefly explains these concepts. For more information about RapidChip Technology, go to http://www.rapidchip.com. 1.1.1 RapidChip Platform ASICs RapidChip Technology allows you to customize the metal layers of a partially manufactured semiconductor wafer that contains multiple copies of a predefined platform ASIC. The silicon layers of a platform ASIC have diffused IP resources that are later connected with user-specific metallization patterns. Because platform ASICs are available as partially manufactured devices, customers benefit from dramatically reduced lead times for prototypes and production units as well as lower inventory costs. The broad range of resources available in platform ASICs meets the needs of many different systems and applications. 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 1-1 Each platform ASIC incorporates diffused memory blocks, PLLs, and IP blocks from our extensive CoreWare(R) library. In addition, each platform ASIC has a transistor fabric region and an I/O ring, which are both userconfigurable. 1.1.2 CoreWare IP Program The LSI Logic CoreWare IP library provides the industry's most comprehensive set of IP solutions that work seamlessly in the cell-based ASIC design flow and the RapidWorx Design Kit. Customers can leverage CoreWare IP solutions to significantly reduce the risk and turnaround times associated with complex System on a Chip (SoC) designs. CoreWare IP includes: * * * * * * * * GigaBlaze(R) and HyperPHY(R) high-speed, standards-compliant SerDes High-performance ARM(R) and MIPS processors and associated systems and reference designs Processor peripherals and AMBA on-chip-bus structures DSP cores USB cores Memory PHYs and controllers Ethernet MAC and PHY cores PCI Express, XGXS, SPI4.2, and other protocol layer IP 1.1.3 RapidReadyTM Certification CoreWare IP can have RapidReady certification, which means it meets the highest level of compatibility with the RapidWorx design methodology and design tools and is ready to be integrated into RapidChip Platform ASICs. For more information about RapidReady certification refer to http://www.rapidchip.com. 1.1.4 RapidWorx The RapidWorx design tools and design methodology are used to customize a RapidChip Platform ASIC, creating a unique metallized device, called an instance. 1-2 Introduction Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. RapidWorx design tools help you create design structures for implementing a custom IC design. Based on user inputs, these tools automatically generate clock, memory, test, and I/O structures, relieving the design team of more mundane design tasks. This dramatically reduces the overall manpower resource required to design custom highperformance ICs. Additionally, these structures are "correct by construction" and optimized to ensure ease of implementation during the physical design phase. RapidWorx design methodology is compatible with best-in-class thirdparty EDA tools. Rules and constraints guide designers throughout the design process to ensure predictable results and reduced design times when compared to fully optimized ASICs. 1.2 Processor System for ARM926EJ-S Product Description This section provides an overview of the Processor System for ARM926EJ-S, including its features and benefits, product options, and product deliverables. 1.2.1 Processor System for ARM926EJ-S Overview The 0.11 m Processor System for ARM926EJ-S is a general purpose microprocessor typically used in the following applications: * * * * * Portable communications Hand-held computing Multimedia Digital consumer Embedded solutions 0.11 m Processor System for ARM926EJ-S 0.11 Micron Firm IP GflxTM-r Product Name Process Technology IP Type Library CoreWare IP Number cw001200_agflxr_2_0 Processor System for ARM926EJ-S Product Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 1-3 1.2.2 Processor System for ARM926EJ-S Features and Benefits The Processor System for ARM926EJ-S offers the following features and benefits: * * ARM926EJ-S processor Two AHB slave ports for connecting a multiport memory controller or other AHB slave to the ARM926EJ-S 32-bit instruction and data buses APB peripheral set: UARTs, GPIO, timers, and I2C bus controllers. Industry standard AMBA 2.0 Bus family - - Advanced High-Performance Bus (AHB) Advanced Peripheral Bus (APB) * * * * * * Supports little endian systems only JTAG debug port Clocking system supports integer-multiple bus frequencies for AHB and APB buses External SRAM, flash, and ROM memory controller - - - - 32-bit external data bus 32-bit external address bus Assembles and disassembles 8-bit, 16-bit, and 32-bit AHB requests to external 8-bit, 16-bit, and 32-bit devices Programmable wait state control (1-16) that supports external flash memory * * * * * * AHB Arbiter Vectored Interrupt Controller (ApVic) I-AHB and D-AHB can access external SRAM, flash, and ROM memory controller 10/100 Mbit/s Ethernet Controller (ApE110) with AMBA Master DMA interface 32-bit AHB Master Expansion Port I-AHB and D-AHB can access 32-bit AHB to AHB synchronous Segmentation Bridge for external AHB slaves 1-4 Introduction Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 1.2.3 Processor System for ARM926EJ-S Options Configuration options for the Processor System for ARM926EJ-S are as follows: * Compile-Time Options The Processor System for ARM926EJ-S has no compile time options. * Programmable Options Programmable options are customer selectable options. The programmable options are peripheral dependent and are captured by the peripheral register section. * Strappable Options Strap pins are options available at the system boundary. These strappable pins must be held HIGH or LOW to enable or disable the particular feature. The following table lists the options. Interface Signal Strapping LOW: Processor boots from SRAM, Flash, ROM port HIGH: Processor boots from AHB Slave Expansion Port Clock Select pin Chip Select 7 Data Select Width defines the data path width Data TCM size; set internally by TCM configuration process Decoding Logic BRBOOTSEL ApE110 ApSramCtlr ARM926EJ-S ApE110 ApE110 ARM926EJ-S ARM926EJ-S ARM926EJ-S CLKS CS7WIDTH DRSIZE E110RX_RAM_SIZE Receive FIFO RAM size E110TX_RAM_SIZE Transmit FIFO RAM size INITRAM IRSIZE VINITHI Enables Instruction TCM at reset Instruction TCM size; set internally by TCM configuration process LOW: Exception vectors start at 0x00000000 HIGH: Exception vectors start at 0xFFFF0000 Processor System for ARM926EJ-S Product Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 1-5 1.2.4 Processor System for ARM926EJ-S Deliverables Typical Firm IP Deliverables: Deliverable Encrypted or Behavioral Verilog to support the following simulators: Mentor Graphics Modelsim, Cadence NCVerilog, and Synopsys VCS Verilog gate level netlist Verilog test wrapper to support automated test insertion flow Abstracted Timing (estimated) and LEF models to support chip level RTL analysis Timing constraints for synthesis and physical layout RapidWorx data files Simulation testbench, run control scripts, and test stimuli Datasheet Technical Manual Integration Guide Release Notes Errata Yes/No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.3 Required Platform ASIC Resources This Processor System for ARM926EJ-S requires the ARM926EJ-S processor identified below: Compatible CoreWare IP cw001124_1_0 Description ARM926EJ-S processor, rev r0p4 Format Hard R-Cell 1-6 Introduction Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. The table below identifies the platform ASIC resources for the Processor System for ARM926EJ-S: Resource Memory Description Ethernet memories are external to the cw001200; you can choose the memory size using strap pin settings and how to implement the memory (R-Cell, diffused memory in slice, and so on) Requires the ARM926EJ-S processor core No special I/O requirements, however some signals (SRAM, GPIO, UART, I2C, and so on) require them No special PLL requirement other than you must generate the CLK, HCLK, PCLK, HOST_CLK, and so on R-Cells I/O Buffers PLLs 1.4 Required Cores The following table identifies the physical requirements of the Processor System for ARM926EJ-S: Requirement Type (Firm) Memory Requirements * Encrypted RTL * Test ready netlist * * * * Description Data TCM--Single Port SRAM, size determined by customer Instruction TCM--Single Port SRAM, size determined by customer Ethernet Receive FIFO--Dual Port SRAM, size determined by customer Ethernet Transmit FIFO--Dual Port SRAM, size determined by customer Clocks Required Reset Scheme * Six clocks required * Up to three clock enables depending on clock frequencies * Asynchronous with de-assertion synchronous * Three resets required Required Cores Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 1-7 1-8 Introduction Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Chapter 2 Architectural Description The 0.11 m Processor System for ARM926EJ-S, part of the CoreWare IP library, easily integrates with the RapidChip Platform ASIC design flow. This fully integrated, general purpose system is built from existing LSI Logic CoreWare IP blocks and delivered as a Fixed IP block. Expansion ports let you add external features and application-specific hardware to the subsystem. This chapter contains the following sections: * * * * * * Section 2.1, "Processor System for ARM926EJ-S Block Diagram" Section 2.2, "ARM926EJ-S Processor Block Description" Section 2.3, "Instruction AHB Bus Block Description" Section 2.4, "Data AHB Bus Block Description" Section 2.5, "APB Bus Block Description" Section 2.6, "Interrupts" 2.1 Processor System for ARM926EJ-S Block Diagram The Processor System for ARM926EJ-S is intended as the primary processor in a larger AMBA system. Other system processors are expected to be Slaves for startup and system control functions. Because the Processor System for ARM926EJ-S serves as the main communication protocol control processor for a larger AMBA system, the Processor System for ARM926EJ-S includes a 10/100 Ethernet Controller (ApE110). Additional IP blocks, such as USB interfaces and PCI interfaces, can be added to the system using the AHB Slave Expansion Port, the AHB Master Expansion Port, and the Multiport Memory Controller ports. 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 2-1 The processor system includes an ARM926EJ-S microprocessor and commonly required system peripherals, such as timers, UARTs, a vectored interrupt controller, an Ethernet controller, and controllers for SRAM, flash, and ROM memories. Figure 2.1 shows the Processor System for ARM926EJ-S block diagram. Figure 2.1 Processor System for ARM926EJ-S Block Diagram External AHB Master Ethernet Rx/Tx Interrupts Expansion Port FIFOs MII Processor System for ARM926EJ-S ApVic JTAG Port MiceSync D-AHB Bus Block ApE110 APB Bus Block ApGpio APB Bridge ApUart1 ApUart2 APB D$ D-TCM ARM926EJ-S Processor D-AHB I-AHB ApI2c1 ApI2c2 ApTimer I$ I-TCM Segmentation ApSramCtlr Bridge Remap Key Separate CoreWare IP Configurable Block Bus Block AHB Slave Expansion Port SRAM Multiport Memory Controller I-AHB Bus Block Flash ROM 2.2 ARM926EJ-S Processor Block Description The ARM926EJ-S processor is a separate CoreWare IP component. This block consists of the ARM926EJ-S soft macro, memories to create the data and instruction tightly coupled memories (TCMs), if supported by the Processor System for ARM926EJ-S component, and the processor. 2-2 Architectural Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 2.3 Instruction AHB Bus Block Description The instruction AHB bus is based on the AMBA 2.0 AHB standard from ARM Ltd. This ARM926EJ-S AHB Master bus includes the following Slave devices: * * * External SRAM Controller (ApSramCtlr) AHB-lite port to an external Multiport Memory Controller Segmentation Bridge to an expansion AHB-lite bus The Bus Matrix boots the subsystem from either the External SRAM Controller or Segmentation Bridge which are aliased at both 0x0 and 0xF000.0000. The boot device is controlled by the BTBOOTSEL strap pin. Booting HIGH or LOW is controlled by the VINITHI strap pin. The AHB-lite port lets you connect to a memory controller, for example the LSI Logic DDR SDRAM controller. 2.4 Data AHB Bus Block Description The data AHB bus is based on the AMBA 2.0 AHB standard from ARM Ltd. This AHB bus has three masters: * * * 10/100 Mbit/s Ethernet Controller (ApE110) ARM926EJ-S Processor Expansion Master Port The three masters are controlled by a priority arbiter. The highest priority master is the Ethernet controller (ApE110), the intermediate level master is the ARM926EJ-S, and the lowest priority master is the Expansion Master Port. The Expansion Master Port is an AHB port to allow an external Master access to peripherals on the data AHB bus. This port lets you add additional IP to the system. Instruction AHB Bus Block Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 2-3 The data AHB bus has the following Slave devices: * * * * * External SRAM Controller (ApSramCtlr) AHB-lite port to an external Multiport Memory Controller Vectored Interrupt Controller (ApVic and ApVicBridge) APB Bridge Segmentation Bridge to an expansion AHB-lite bus The Expansion Master Port, AHB expansion bus port, and the AHB-lite port, for an external Multiport Memory Controller, lets you add additional IP to the system. The AHB-lite port is provided to allow connection to memory controller, such as the LSI Logic DDR SDRAM controller. The APB bridge allows all data AHB Masters to access peripherals on the APB bus. 2.5 APB Bus Block Description The APB is a Slave bus based on the AMBA 2.0 APB standard from ARM Ltd. The APB includes the following peripherals: * * * * * * Two UART (16550 type) instantiations A 32-bit GPIO block Two I2C Bus Controller instantiations Timer block (two timers) Ethernet Controller Configuration port Remap block 2-4 Architectural Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 2.6 Interrupts The 32-bit input interrupt channel to the Vectored Interrupt Controller, ApVic, is brought to the top interface of the system as an input. You must connect the peripheral interrupt outputs to the appropriate ApVic interrupt channels. There are no interrupts connected to the ApVic internally. Interrupts for all the instantiated system peripherals are brought to the top interface of the system as outputs. These include: * * * * * One interrupt for the Ethernet Controller One interrupt for each I2C instantiation One interrupt for each UART instantiation Six interrupts for the Timer block Four interrupts for the GPIO block Interrupts Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 2-5 2-6 Architectural Description Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Chapter 3 Registers This chapter summarizes the Processor System for ARM926EJ-S registers. This chapter contains the following sections: * * Section 3.1, "Register Summary" Section 3.2, "System Memory Map" 3.1 Register Summary This section summarizes the system registers. 3.1.1 External SRAM Registers Eight Chip Select Control registers control the AHB address chip select decoding. Chip Select 7 has the highest priority, Chip Select 0 the lowest. The registers are accessed through the AHB from the D-AHB bus. The peripheral register set consists of the registers summarized in Table 3.1. Table 3.1 Chip Select Control Register Summary R/W Function Register Name Chip Select Control Register 0/1/2/3/4/5/6/7 R/W Controls the chip select decoding of the AHB address 3.1.2 GPIO Registers The GPIO registers set the external GPIO bits for use as General-Purpose Input/Output. Each GPIO bit can be configured as an 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-1 input or output through the Direction register. The GPIO also can generate interrupts to the processor's FIQ/IRQ interrupt system. Each register set defines a particular behavior for all of the external GPIO pins. There is one bit for each GPIO pin. This definition is the same for all register sets. For example: * * * * GPIO Data Direction Register 1, bit 7 controls the direction for external GPIO bit 7. GPIO Data Direction Register 1, bit 0 controls the direction for external GPIO bit 0. GPIO Data Direction Register 2, bit 7 controls the direction for external GPIO bit 15. GPIO Data Direction Register 2, bit 0 controls the direction for external GPIO bit 8. The GPIO register set is summarized in Table 3.2. Table 3.2 GPIO Register Summary R/W Function Register Name GPIO Data Direction 1/2/3/4 GPIO Data In 1/2/3/4 GPIO Data Out 1/2/3/4 GPIO Edge 1/2/3/4 GPIO Enable Clear 1/2/3/4 GPIO Enable Set 1/2/3/4 GPIO Polarity 1/2/3/4 R/W Sets the direction of the corresponding GPIO bits R W Reads the data value for the corresponding GPIO bit Writes the data value for the corresponding GPIO bit R/W Selects whether an edge or level signal on the GPIO generates an interrupt R/W Clears the enables for the GPIO interrupts R/W Sets the enables for the GPIO interrupts R/W Selects whether the GPIO interrupt is active HIGH or LOW (edge bit = level), or, if edge triggered (edge bit = edge), on the falling or rising edge R/W Reads the raw (premasked) interrupt status of the GPIO interrupts; on writes, a 1 in a bit position clears the corresponding interrupt bit R/W Selects whether the GPIO inputs are resynchronized to the internal clock when configured as an input R Reads the (postmasked) interrupt status of the GPIO interrupts GPIO Raw Status 1/2/3/4 GPIO Resync 1/2/3/4 GPIO Status 1/2/3/4 3-2 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3.1.3 UART Registers The registers are accessed through the APB. The Divisor Latch Access Bit (DLAB) is set and cleared by writing to bit 7 of the Line Control Register (LCR). The UART register set consists of 17 registers, summarized in Table 3.3. Table 3.3 UART Register Summary R/W Description Register Name Divisor Latch Low/High (DLL/DLH) FIFO Control (FCR) Interrupt Enable (IER) Interrupt Identification (IIR) Line Control (LCR) Line Status (LSR) Modem Control (MCR) Modem Status (MSR) Receiver Buffer (RBR) Scratch Speedsense Complete (SCR) Speedsense Value Low/Med/High (SVL/SVM/SVH) Start Speedsense (SSR) Transmit Holding (THR) R/W Stores the divisor for a baud generator in a 16-bit binary format W R Provides control for both the receive and transmit FIFOs Stores the four levels of prioritized interrupts and indicates the highest priority pending interrupt when read R/W Enables the five types of UART interrupts R/W Specifies the format of the asynchronous data communications exchange and set the DLAB R Provides data transfer status information R/W Provides control functions R/W Provides modem status information R R R Provides temporary storage for receive data Determines whether the Speedsense process is complete (1) or not complete (0) Matches the baudrate of the UART to that of the other modem device; reflects the low, middle, or high byte of the Speedsense value Triggers the Speedsense function when any value to the register is written Provides temporary storage for transmit data R/W Provides a place where software can store data temporarily W W Register Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-3 3.1.4 APB Timer Registers The Timer register set consists of 13 registers, summarized in Table 3.4, which are accessed through the APB. Table 3.4 APB Timer Register Summary R/W Description Register Name Timer 1/2 Timer Control 1/2 R/W Returns the current value of the Timer on reads; updates the Timer at the next rising edge of the Timer 1/2 clock on writes R/W Controls specific Timer functions including freezing, up/down count, interval or periodic mode, and trigger point register selection R/W Contains the value controlling the unit of time that each tick of the Timer represents when combined with the input Timer 1/2 clock R/W Selects between Timer 1 and Timer 2 to compare against the value held in each of the Timer Trigger Point registers R/W Defines when an interrupt is generated Timer Prescaler 1/2 Timer Trigger Control Timer Trigger Point 1/2/3/4/5/6 3.1.5 Ethernet Controller Registers All Ethernet Control registers are accessed over the APB. The Ethernet Control register summary is shown in Table 3.5. Table 3.5 Ethernet Controller Register Summary R/W Description Register Name Carrier Loss Counter Collisions Counter: x (1-15) or More Back-to-Back DMAC Configuration DMAC Interrupt Enable DMAC Interrupt Status Ethernet Back-to-Back IPG Ethernet Interrupt Active Ethernet Interrupt Diagnostic R/W Contains the number of times the carrier is lost in the middle of a Transmit frame since the last time the counter was read R/W Contains the number of packets that collided x (1-15) or more times before being transmitted R/W Configures the AHB-Master DMA controller R/W Enables the interrupts to the processor used to control the DMA R/W Provides status of the interrupts to the processor used to control the DMA R/W Programmable Transmit IPG for back-to-back transmissions R Asserts the E110_INT signal R/W Generates an unconditional interrupt for test purposes; initializes the Transmit and Receive FIFOs for gate-level simulation 3-4 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 3.5 Ethernet Controller Register Summary (Cont.) R/W Description Register Name Ethernet Interrupt Enable Ethernet Interrupt Status Ethernet IPG Part 1 Ethernet IPG Part 2 Ethernet MAC Address (Bytes 1-4) Ethernet MAC Address (Bytes 5-6) Ethernet Main Control Ethernet MII Control Status Ethernet MII Read Ethernet MII Write Ethernet Receive Control Ethernet RNG Seed Ethernet Transmit Control R/W Enables individual interrupt types selectively R/W Can be used to poll the interrupt flags; contains interrupt status and is unaffected by interrupt enables R/W Programmable transmit IPG Part 1 for non back-to-back transmissions R/W Programmable transmit IPG Part 2 for non back-to-back transmissions R/W Address of the Ethernet device R/W Address of the Ethernet device R/W Lets you reset the MAC, determine retransmission delay retries and wait times, and set full- or half-duplex mode R/W Status information and control of MIIM functions to the MII PHY R Contains Status Register data read from the addressed MII PHY R/W PHY and register address and write data for MII PHY register accesses R/W Controls Receive functions such as Virtual LAN protocol, Multicase block, Broadcase block, and Promiscuous Mode R/W Seed value to generate random number sequence used in collision backoff timing R/W Controls transmit functions such as packet padding, preamble, maximum packet size that can be transmitted, and CRC insertion R/W Contains the number of receive overruns since last read R/W Contains the number of packets received since last read R/W Enables transmit flow control when PAUSE frames are received; provides false carrier sense in half-duplex mode R/W Contains the number of packets received that are less than 64 octets in length (excluding framing bits, but including FCS octets) and have either a bad FCS or a nonintegral number of octets (Alignment Error) R/W Contains the number of packets received that are greater than 1518 octets for non-VLAN packets or if VLAN is disabled or greater than 1522 octets if VLAN is enabled and the packet is a VLAN packet (excluding framing bits, but including FCS octets), and have either a bad FCS or a nonintegral number of octets (Alignment Error) Events Dropped Counter FCS/Alignment Errors Counter Flow Control Fragment Packets Counter Jabber Counter Register Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-5 Table 3.5 Ethernet Controller Register Summary (Cont.) R/W Description Register Name Late Collisions Counter R/W Contains the number of late collisions that occurred since it was last read regardless of whether the Multiple Collisions (COL) interrupt is enabled R/W Contains the number of packets received that are greater than 1518 octets for non-VLAN packets or if VLAN is disabled or greater than 1522 octets if VLAN is enabled and the packet is a VLAN packet (excluding framing bits, but including FCS octets) and are otherwise well-formed R Resets the peripheral R/W Contains the number of packets received that are less than 64 octets in length (excluding framing bits, but including FCS octets) and are otherwise well-formed R R Determines whether data is transferred to and from the Receive FIFO--for test purposes only Provides current state of match, receive and transmit state machines Oversize Packets Counter Peripheral Reset Runt Packets Counter Receive Pointers State Transmit Underruns Counter Transmit and Receive BMD Pointer Transmit Pointers Transmit Poll Timer Transmit Threshold R/W Contains the number of transmit underruns that occurred since it was last read R/W Contains the upper address of the first Transmit/Receive Buffer Memory Descriptors (BMDs) in the lists R Determines whether data is transferred to and from the Transmit FIFO--for test purposes only R/W Contains the number of clock cycles the transmit section must wait before polling a BMD with the valid bit cleared R/W Controls how much data is required in the Transmit FIFO before the E-100 MAC starts transmitting 3.1.6 ApI2c Registers The ApI2c interface allows access for up to 64 addressable 16-bit registers aligned on 32-bit boundaries. The registers are used to control I2C Master and Slave access to the I2C bus. Reserved registers or fields are read-only and return all zeros when read. 3-6 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. The ApI2c registers are summarized in Table 3.6. Table 3.6 ApI2c Register Summary R/W Description Register Name Global Control I2C Monitor IBML tLOW:MEXT Control IBML tLOW:SEXT Control IBML tTIMEOUT Control Interrupt Enable R/W Enables or disables the Master and Slave units independently; enables and disables the IBML time-out timers globally R/W Lets the host manually read and control the SCL and SDA I2C bus signals R/W Measures the time the SCL signal is extended LOW by the Master controller during data byte transmission or reception R/W Measures the time the SCL signal is extended LOW by the Slave controller during message transmission or reception R/W Measures the time the SCL signal is detected LOW R/W Enables/disables interrupt status reporting for the Master and Slave interrupt sources in the corresponding Interrupt Status Register bit and external interrupt signal R/W Reports the Master and Slave interrupt source status R/W Sent as the first byte in the address phase of an I2C transaction R/W Sent as the second byte in the address phase of an I2C transaction if ten-bit addressing is enabled R/W Issues commands to the Master state machine R/W Writes data into the Master Transmit FIFO, reads get data from the top of the Master Receive FIFO R/W Enables/disables the individual Master interrupts; bits correspond to the Master Interrupt Status register bits R R R Records the status results of the last command issued Tracks the number of successfully received (acknowledged) data bytes Indicates the number of data bytes currently in the Master Receive FIFO Interrupt Status Master Address Register 1 Master Address Register 2 Master Command Master Data Master Interrupt Enable Master Interrupt Status Master Receive Bytes Transferred Master Receive FIFO Status Master Receive Transfer Length R/W Determines the number of bytes transferred during receive transfers Master Transmit Bytes Transferred Master Transmit FIFO Status Master Transmit Transfer Length SCL High Period R R Tracks the number of successfully transmitted (acknowledged) data bytes Indicates the number of data bytes currently in the Master Transmit FIFO R/W Determines the number of data bytes sent during transmit transfers R/W Determines the high period for the SCL clock generated by I2C Master Register Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-7 Table 3.6 ApI2c Register Summary (Cont.) R/W Description Register Name SCL Low Period SDA Hold Time SDA Setup Time Slave Address 1 Slave Address 2 Slave Address Decode Control Slave Data Slave Interrupt Enable Slave Interrupt Status Slave Read Dummy Byte R/W Determines the low period for the SCL clock generated by the I2C Master R/W Controls the data hold time whenever the core controls SDA (Master or Slave) R/W Controls the data setup time when the Master is driving SCL and SDA R/W Contains the first I2C Slave address R/W Contains the second I2C Slave address R/W Enables/disables the two Slave address decoders and the General Call Address decode R/W Provides access to Slave read or write data R/W Enables/disables the individual Slave interrupts; bits correspond to the Slave Interrupt Status register bits R Contains status information for Slave operations R/W Provides a data byte for an I2C Master read transaction if the I2C Slave state machine has not received a data byte in the Slave Data register before the SCL timer expires R Provides access to the Receive Status FIFO which provides the status word for the data at the top of the Receive FIFO Slave Receive FIFO Status Slave Receive Control Soft Reset Spike Filter Length Timer Clock Divider Control Wait Timer Control R/W Controls the acknowledge cycle response during the data phase of a Slave write transfer R/W Lets the host independently clear the I2C interface R/W Controls the spike filter for SCL and SDA; filter stages determine the maximum size of the spike the filter suppresses R/W Divides the APB clock frequency for use by all timers R/W Controls the Master/Slave Wait Timer; times the different I2C transactions and causes the appropriate state machine to take action when time-out occurs 3-8 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3.1.7 ApVic Registers The ApVic contains registers, summarized in Table 3.7, that initialize and control interrupts within the system. Table 3.7 ApVic Register Summary R/W Description Register Name Edge Select FIQ Current Priority Level (CPR) FIQ Enable Clear FIQ Enable Set FIQ Index R/W Determines whether the interrupts are edge- or level-sensitive R/W Sets the current priority level for the FIQ interrupts W Clears the corresponding bit in the FIQ Enable register when writing a 1; writing a 0 has no effect R/W Sets up the mask for each interrupt that generates an interrupt into the nFIQ signal of the processor R/W On reads this register contains the FIQ channel index location with the highest service priority; on writes it loads a hardware jump table R/W Contains the starting address vector of the ISR for the FIQ interrupt with the highest service priority R Returns the last priority level for the FIQ interrupts R/W Contains the premasked interrupts on reads; on writes, it clears active interrupts R Contains postmasked interrupts ORed together to form the FIQ interrupt FIQ Interrupt Service Routine (ISR) Vector FIQ Last Priority Level (LPR) FIQ Raw Status/Clear FIQ Status IRQ Current Priority Level (CPR) IRQ Enable Clear IRQ Enable Set IRQ Index R/W Sets the current priority level for the IRQ interrupts W Clears the corresponding bit in the IRQ Enable register when writing a 1; writing a 0 has no effect R/W Sets up the mask for each interrupt that can generate an interrupt to the processor nIRQ output R/W On Reads this register contains the IRQ channel index location with the highest service priority; on Writes it loads a hardware jump table R/W Contains the starting address vector of the ISR for the IRQ interrupt with the highest service priority R Returns the last priority level for the IRQ interrupts R/W Contains the premasked interrupts when read; on writes, the Clear register clears active interrupts R Contains postmasked interrupts ORed together to form the IRQ interrupt IRQ Interrupt Service Routine (ISR) Vector IRQ Last Priority Level (LPR) IRQ Raw Status/Clear IRQ Status IRQ/FIQ Soft Interrupt R/W Sets a software interrupt Register Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-9 Table 3.7 ApVic Register Summary (Cont.) R/W Description Register Name Polarity Select Priority Table Channel x Resync Select R/W Determines whether a HIGH or LOW state on each INTERRUPTS[31:0] input causes an interrupt R/W Sets channel priorities; there are 32 Priority Table Channel registers, one for each interrupt channel R/W Determines whether or not the external interrupts are resynced internally 3.1.8 Remap Register The remap peripheral located on the APB bus has only one register located at offset 0x0 from the remap base address. Table 3.8 Chip Select Control Register Summary R/W Description Register Name Remap Register R/W Lets you change the address map after reset when writing to the Remap bit (Remap register bit 0); read this register to determine the address map currently used by the system decoding logic 3.2 System Memory Map This section summarizes the system boot settings and memory maps. 3.2.1 System Boot Settings The boot method is selected by using the strap pins BRBOOTSEL, VINITHI, and INITRAM. These three pins determine which device and which address location the ARM926EJ-S processor uses. Possible boot devices are the External SRAM, an external slave connected to the AHB Slave Expansion Port using the Segmentation Bridge, or the Instruction TCM, if the Processor System for ARM926EJ-S supports the use of TCMs. Check the ARM926EJ-S processor datasheet. 3-10 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. The system memory maps and decoding support the boot methods shown in Table 3.9 and Table 3.10. Table 3.9 System Boot Setting: BRBOOTSEL=0 BRBOOTSEL = 0 Address 0x0000.0000-0x0FFF.FFFF 0x1000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF VINITHI = 0 INITRAM = 0 External SRAM -- -- VINITHI = 1 INITRAM = 0 -- -- External SRAM VINITHI = 0 INITRAM = 1 Instruction TCM -- -- VINITHI = 1 INITRAM = 1 -- -- External SRAM Table 3.10 System Boot Setting: BRBOOTSEL=1 BRBOOTSEL = 1 Address 0x0000.0000-0x0FFF.FFFF 0x1000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF VINITHI = 0 INITRAM = 0 Segmentation Bridge -- -- VINITHI = 1 INITRAM = 0 -- -- Segmentation Bridge VINITHI = 0 INITRAM = 1 Instruction TCM -- -- VINITHI = 1 INITRAM = 1 -- -- Segmentation Bridge 3.2.2 Memory Map and Addressing Table 3.11, Table 3.12, Table 3.13, and Table 3.14 show the I-AHB and D-AHB memory maps. Table 3.15 provides an address map for the APB peripherals. Together, these maps specify the memory addresses for every peripheral in the system. System Memory Map Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-11 Table 3.11 Address Map for Instruction AHB Bus--TCMs Disabled1 BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset After Remap Memory Space Device on Instruction AHB Bus Instruction TCM (1 Mbyte max) ARM926EJ-S TCMs & External Memory Data TCM (1 Mbyte max) External SRAM Segmentation Bridge (AHB Slave Expansion Port) Multiport Memory Controller Port with select pin IHSEL After Reset After Remap 0x0000.0000- 0x0FFF.FFFF 0x0000.0000- 0x0FFF.FFFF 256 Mbytes 0x0000.0000- 0x0FFF.FFFF 0x0000.0000- 0x0FFF.FFFF 1.75 Gbytes 1.5 Gbytes Multiport Memory Controller Port with select pin IHSEL Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) 1. 0x1000.0000-0x7FFF.FFFF 0x8000.0000-0xDFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF 0xF000.0000-0xFFFF.FFFF 256 Mbytes 256 Mbytes TCMs Disabled: INITRAM = 0 at boot and TCMs are not enabled later. 3-12 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 3.12 Address Map for Instruction AHB Bus--TCMs Enabled1 BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset After Remap Memory Space Device on Instruction AHB Bus Instruction TCM (1 Mbyte max) ARM926EJ-S TCMs & External Memory Data TCM (1 Mbyte max) External SRAM Segmentation Bridge (AHB Slave Expansion Port) Multiport Memory Controller Port with select pin IHSEL After Reset After Remap 0x0000.0000-0x001F.FFFF 0x0020.0000-0x003F.FFFF 0x0040.0000- 0x0FFF.FFFF 0x0040.0000- 0x0FFF.FFFF 256 Mbytes 0x0040.0000- 0x0FFF.FFFF 0x0040.0000- 0x0FFF.FFFF Multiport Memory Controller Port with select pin IHSEL Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) 1. 0x1000.0000-0x7FFF.FFFF 1.75 Gbytes 1.5 Gbytes 0x8000.0000-0xDFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF 0xF000.0000-0xFFFF.FFFF 256 Mbytes 256 Mbytes TCMs Enabled: INITRAM = 1 at boot or when TCMs are enabled later. System Memory Map Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-13 Table 3.13 Address Map for Data AHB Bus--TCMs Disabled1 BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset After Remap Memory Space Device on Data AHB Bus Instruction TCM (1 Mbyte max) ARM926EJ-S TCMs, & External Memory Data TCM (1 Mbyte max) External SRAM Segmentation Bridge (AHB Slave Expansion Port) Multiport Memory Controller Port with select pin DHSEL After Reset After Remap 0x0000.0000- 0x0FFF.FFFF 0x0000.0000- 0x0FFF.FFFF 0x0000.0000- 0x0FFF.FFFF 0x1000.0000-0x7FFF.FFFF 0x8000.0000-0x83FF.FFFF 0x8400.0000-0x87FF.FFFF 0x8800.0000-0x8FFF.FFFF 0x0000.0000- 0x0FFF.FFFF 256 Mbytes Multiport Memory Controller Port with select pin DHSEL ApVic External SRAM configuration registers Multiport Memory Controller Port configuration registers with select pin DHSELCFG APB Bridge (see Table 3.15 for detailed APB address map) Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) External SRAM Segmentation Bridge (AHB Slave Expansion Port) 1. 1.75 Gbytes 64 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 1.0 Gbytes 256 Mbytes 256 Mbytes 0x9000.0000-0x9FFF.FFFF 0xA000.0000-0xDFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF 0xF000.0000-0xFFFF.FFFF TCMs Disabled: INITRAM = 0 at boot and TCMs are not enabled later. 3-14 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 3.14 Address Map for Data AHB Bus--TCMs Enabled1 BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset After Remap Memory Space Device on Data AHB Bus Instruction TCM (1 Mbyte max) ARM926EJ-S TCMs, & External Memory Data TCM (1 Mbyte max) External SRAM Segmentation Bridge (AHB Slave Expansion Port) Multiport Memory Controller Port with select pin DHSEL After Reset After Remap 0x0000.0000-0x001F.FFFF 0x0020.0000-0x003F.FFFF 0x0040.0000- 0x0FFF.FFFF 0x0040.0000- 0x0FFF.FFFF 0x0040.0000- 0x0FFF.FFFF 0x1000.0000-0x7FFF.FFFF 0x8000.0000-0x83FF.FFFF 0x8400.0000-0x87FF.FFFF 0x0040.0000- 0x0FFF.FFFF 1.75 Gbytes 64 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes Multiport Memory Controller Port with select pin DHSEL ApVic External SRAM configuration registers Multiport Memory Controller Port configuration registers with select pin DHSELCFG APB Bridge (see Table 3.15 for detailed APB address map) Segmentation Bridge (AHB Slave Expansion Port) (Sheet 1 of 2) 0x8800.0000-0x8FFF.FFFF 0x9000.0000-0x9FFFF.FFFF 256 Mbytes 1.0 Gbytes 0xA000.0000-0xDFFF.FFFF System Memory Map Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-15 Table 3.14 Address Map for Data AHB Bus--TCMs Enabled1 (Cont.) BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset After Remap Memory Space 256 Mbytes 256 Mbytes Device on Data AHB Bus External SRAM Segmentation Bridge (AHB Slave Expansion Port) External SRAM (Sheet 2 of 2) 1. After Reset After Remap 0xE000.0000-0xEFFF.FFFF 0xE000.0000-0xEFFF.FFFF 0xF000.0000-0xFFFF.FFFF TCMs Enabled: INITRAM = 1 at boot or when TCMs are enabled later. Table 3.15 Address Map for APB Bus Peripherals (TCMs Enabled1 or Disabled2) BRBOOTSEL State BRBOOTSEL = 0 (SRAM, Flash, ROM Port) BRBOOTSEL = 1 (AHB Slave Exp Port) After Reset 3 Device on APB Bus GPIO Timers UART (instance 0) UART (instance 1) I I 2C 2C After Reset After Remap After Remap Memory Space 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes ~255 Mbytes 0x9**0.0000-0x9**0.FFFF3 0x9**1.0000-0x9**1.FFFF 0x9**3.0000-0x9**3.FFFF 0x9**2.0000-0x9**2.FFFF3 3 (instance 0) (instance 1) 0x9**4.0000-0x9**4.FFFF3 0x9**5.0000-0x9**5.FFFF3 0x9**6.0000-0x9**6.FFFF3 0x9**7.0000-0x9**7.FFFF 0x9**8.0000-0x9**F.FFFF 3 3 ApE110 Remap Unused 1. 2. 3. TCMs Enabled: INITRAM = 1 at boot or when TCMs are enabled later. TCMs Disabled: INITRAM = 0 at boot and TCMs are not enabled later. Indicates that address bits [27:20] are not decoded by any of the system logic, which allows the peripherals to be aliased within this region. The APB peripheral addresses are set up so software can define the peripherals within a 1 Mbyte region. This feature allows you to manage all APB peripherals with a single locked down entry in the ARM926EJ-S Translation Lookaside Buffer (TLB). 3-16 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. The ARM926EJ-S Instruction TCM (I-TCM) and Data TCM (D-TCM) can be placed anywhere in the physical address space. The locations shown in Table 3.12 and Table 3.14 are examples. In these examples, the TCMs are overlaying the External SRAM controller, Segmentation Bridge, and Multiport Memory Controller Ports at address 0x0. Typically, this is done so the exception vectors at location 0x0 can be contained in the I-TCM, improving performance. You must not overlay the TCMs on peripheral address space, such as the ApVic or APB peripheral spaces. You must also configure the I-TCM and D-TCM size to match the system configuration. The I-TCM and D-TCM sizes are configured after releasing the reset by writing the ARM926EJ-S system control coprocessor (CP15) registers; the SVE initialization code provides some examples. If the Processor System for ARM926EJ-S supports TCMs, the 0.11 m Processor System for ARM926EJ-S Integration Guide contains information about configuring the TCMs. System Memory Map Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 3-17 3-18 Registers Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Chapter 4 Signal Summary This chapter summarizes the Processor System for ARM926EJ-S external interface signals in these sections: * * Section 4.1, "System Interfaces" Section 4.2, "Interface Signals" 4.1 System Interfaces Figure 4.1 is a block diagram showing the Processor System for ARM926EJ-S external signals. The signals are grouped by function and listed alphabetically within each group. 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-1 Figure 4.1 System Interfaces BRHCLKEN CLK HCLK HCLKEN HOST_CLK MII_RXCLK MII_TXCLK PCLK PCLKEN HRESETn PRESETn Processor System CoreWare IP for ARM926EJ-S IHADDR[31:0] IHBURST[2:0] IHMASTLOCK IHPROT[3:0] IHRDATAEXT[31:0] IHREADY IHREADYOUTEXT IHRESPEXT[1:0] IHSEL IHSIZE[2:0] IHTRANS[1:0] IHWRITE DHADDR[31:0] DHBURST[2:0] DHMASTLOCK DHPROT[3:0] DHRDATAEXT[31:0] DHRDATACFG[31:0] DHREADY DHREADYOUTEXT DHREADYOUTCFG DHRESPEXT[1:0] DHRESPCFG[1:0] DHSEL DHSELCFG DHSIZE[2:0] DHTRANS[1:0] DHWDATA[31:0] DHWRITE I2CINTR0 SCL0_I SDA0_I SCL0_O_n SDA0_O_n I2CINTR1 SCL1_I SDA1_I SCL1_O_n SDA1_O_n GPIODataDir[31:0] GPIODataIn[31:0] GPIODataOut[31:0] GPIOINTS[3:0] DBGACK EDBGRQ INITRAM STANDBYWFI VINITHI Clock Generation Signals Inputs: 9 Outputs: 0 Instruction AHB Multiport Memory Controller Port Signals Inputs: 35 Outputs: 48 Reset Signals Inputs: 2 Outputs: 0 Ethernet Signals Inputs: 32 Outputs: 78 CLKS E110_INT E110RX_AADR[10:0] E110RX_BADR[10:0] E110RX_DIB[8:0] E110RX_DOA[8:0] E110RX_ENA E110RX_ENB E110RX_RAM_SIZE[1:0] E110RX_WEB E110TX_AADR[10:0] E110TX_BADR[10:0] E110TX_DIB[8:0] E110TX_DOA[8:0] E110TX_ENA E110TX_ENB E110TX_RAM_SIZE[1:0] E110TX_WEB MII_COL MII_CRS MII_MDC MII_MDI MII_MDO MII_MDOEN_n MII_RXD[3:0] MII_RXDV MII_RXER MII_TXD[3:0] MII_TXEN MII_TXER TTP1MATCH TTP2MATCH TTP3MATCH TTP4MATCH TTP5MATCH TTP6MATCH Data AHB Multiport Memory Controller Port Signals Inputs: 70 Outputs: 81 I 2C Instance 0 Signals Inputs: 2 Outputs: 3 I2C Instance 1 Signals Inputs: 2 Outputs: 3 GPIO Signals Inputs: 32 Outputs: 68 ARM926EJ-S Signals Inputs: 3 Outputs: 2 Timer Signals Inputs: 0 Outputs: 6 4-2 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Figure 4.1 System Interfaces (Cont.) UART Instance 0 Signals Inputs: 5 Outputs: 8 CTSn0 DCDn0 DSRn0 DTRn0 OUT1n0 OUT2n0 RIn0 RTSn0 RXRDYn0 SIN0 SOUT0 TXRDYn0 UARTINTR0 CTSn1 DCDn1 DSRn1 DTRn1 OUT1n1 OUT2n1 RIn1 RTSn1 RXRDYn1 SIN1 SOUT1 TXRDYn1 UARTINTR1 CS7WIDTH[1:0] SRAMADDR[31:0] nSRAMCS[7:0] nSRAMDOE[3:0] nSRAMOE SRAMRDATA[31:0] SRAMWDATA[31:0] nSRAMWE[3:0] Processor System CoreWare IP for ARM926EJ-S BRBOOTSEL BRHADDR[31:0] BRHBURST[2:0] BRHMASTLOCK BRHPROT[3:0] BRHRDATA[31:0] BRHREADY BRHRESP[1:0] BRHSIZE[2:0] BRHTRANS[1:0] BRHWDATA[31:0] BRHWRITE AHB Slave Expansion Port Signals Inputs: 36 Outputs: 78 UART Instance 1 Signals Inputs: 5 Outputs: 8 MHADDR[31:0] MHBURST[2:0] MHBUSREQ MHGRANT MHLOCK MHPROT[3:0] MHRDATA[31:0] MHREADY MHRESP[1:0] MHSIZE[2:0] MHTRANS[1:0] MHWDATA[31:0] MHWRITE RTCK TCK TDI TDO nTDOEN TMS nTRST INTERRUPTS[31:0] AHB Master Expansion Port Signals Inputs: 79 Outputs: 36 SRAM Flash ROM Port Signals Inputs: 34 Outputs: 81 JTAG Signals Inputs: 4 Outputs: 3 ApVic Signals Inputs: 32 Outputs: 0 System Interfaces Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-3 4.2 Interface Signals Table 4.1 through Table 4.15 briefly describe the Processor System for ARM926EJ-S signals, grouped by function. * * * * * * * * * * * * * * * Table 4.1 Clock Generation Signals Reset Signals ARM926EJ-S Signals AHB Master Expansion Port Signals Ethernet Signals ApVic Signals ApI2c Signals UART Signals GPIO Signals Timer Signals SRAM, Flash, ROM Port Signals Instruction AHB Multiport Memory Controller Port Signals Data AHB Multiport Memory Controller Port Signals AHB Slave Expansion Port Signals JTAG Signals Clock Generation Signals Signal Function Segmentation Bridge AHB Clock Enable--Describes the relationship between HCLK and the external AHB-lite bus clock Processor Clock System AHB Clock--AHB bus clock for the I-AHB and D-AHB System AHB Clock Enable--Describes the relationship between the processor clock and the AHB Clock Host Clock--Derives the MII_MDC clock Ethernet Receive Nibble or Symbol Clock--Continuous clock providing a timing reference for transferring the MII_RXDV, MII_RXD[3:0], and MII_RXER signals from the PHY to the Ethernet Core I/O Input Input Input Input Input Input Signal Mnemonic BRHCLKEN CLK HCLK HCLKEN HOST_CLK MII_RXCLK 4-4 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 4.1 Clock Generation Signals (Cont.) Signal Function Ethernet Transmit Nibble or Symbol Clock--Continuous clock providing a timing reference for transferring the MII_TXER signals from the Ethernet Core to the PHY System APB Clock--AMBA peripheral bus (APB) clock System APB Clock Enable--Describes the relationship between the AHB Clock and the APB Clock I/O Input Signal Mnemonic MII_TXCLK PCLK PCLKEN Input Input Table 4.2 Reset Signals Signal Function AHB Clock System Reset--Carries a chip reset from an external source; asynchronously asserted and synchronously deasserted to AHB Clock APB Clock System Reset--Carries a chip reset from an external source; asynchronously asserted and synchronously deasserted to APB Clock I/O Input Signal Mnemonic HRESETn PRESETn Input Table 4.3 ARM926EJ-S Signals Signal Function Debug Acknowledge--When HIGH, this signal indicates that the processor is in the debug state External Debug Request--When asserted, it causes the processor to enter the debug state Tightly-Coupled Memory Enable--When HIGH, the instruction TCM is enabled during reset, when LOW, the TCM is disabled during reset Stand By-Wait For Interrupt--When HIGH, this signal indicates that the processor is in "wait for interrupt" mode Exception Vector Location at Reset--Determines the reset location of the exception vectors for the processor I/O Output Input Input Output Input Signal Mnemonic DBGACK EDBGRQ INITRAM STANDBYWFI VINITHI Interface Signals Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-5 Table 4.4 AHB Master Expansion Port Signals Signal Function AHB Address Bus--32-bit system address bus AHB Burst Type--Indicates whether the transfer is part of a burst and the burst type AHB Bus Request--When asserted, indicates that the bus Master requires the bus AHB Bus Grant--Indicates the expansion Master is currently the highest priority Master AHB Locked Transfer--When HIGH, indicates that the Master requires locked access to the bus, and that no other Masters can be granted the bus until it goes LOW AHB Protection Control--Provides information about the bus access level of protection AHB Read Data Bus--Transfers data from bus Slaves to the bus Master during read operations AHB Transfer Done--Indicates the existing transfer on the bus is being completed and a new transfer is starting AHB Transfer Response--Provides additional information about the transfer status AHB Transfer Size--Indicates the size of the transfer AHB Transfer Response--Provides additional information on the transfer status AHB Write Data Bus--Transfers data from the Master to the bus Slaves during write operations AHB Transfer Direction--Indicates a write transfer when asserted or a read transfer when deasserted I/O Input Input Input Output Input Signal Mnemonic MHADDR[31:0] MHBURST[2:0] MHBUSREQ MHGRANT MHLOCK MHPROT[3:0] MHRDATA[31:0] MHREADY MHRESP[1:0] MHSIZE[2:0] MHTRANS[1:0] MHWDATA[31:0] MHWRITE Input Output Output Output Input Input Input Input Table 4.5 Ethernet Signals Signal Function Clock Select--Determines the relationship between MII_MDC and the HOST_CLK clock frequencies Ethernet Interrupt--Interrupt line from the peripheral Receive FIFO Read Address--Read address bus to the Receive FIFO Receive FIFO Write Address--Write address bus to the Receive FIFO I/O Input Output Output Output Signal Mnemonic CLKS E110_INT E110RX_AADR[10:0] E110RX_BADR[10:0] 4-6 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 4.5 Ethernet Signals (Cont.) Signal Function Receive Data into FIFO Port B--Carries receive data written into the Receive FIFO by the E-110 MAC Receive Data out of FIFO Port A--Carries receive data read from the Receive FIFO by the ApE110 DMAC Receive Enable Port A--Output enable to the Receive FIFO RAM read port Receive Enable Port B--Enable to the Receive FIFO RAM write port I/O Output Input Output Output Input Output Output Output Output Input Output Output Input Output Input Signal Mnemonic E110RX_DIB[8:0] E110RX_DOA[8:0] E110RX_ENA E110RX_ENB E110RX_RAM_SIZE[1:0] Receive FIFO RAM Size--Strap these inputs to define the Receive FIFO RAM size E110RX_WEB E110TX_AADR[10:0] E110TX_BADR[10:0] E110TX_DIB[8:0] E110TX_DOA[8:0] E110TX_ENA E110TX_ENB Receive Write Enable Port B--Write enable from the E-110 MAC to strobe data into the Receive FIFO Transmit FIFO Read Address--Read address bus to the Transmit FIFO Transmit FIFO Write Address--Write address bus to the Transmit FIFO Transmit Data into FIFO Port B--Carry transmit data the ApE110 DMAC wrote into the Transmit FIFO Transmit Data out of FIFO Port A--Carry transmit data the E-110 MAC read from the Transmit FIFO Transmit Enable Port A--Output enable to the Transmit FIFO RAM read port Transmit Enable Port B--Enable to the Transmit FIFO RAM write port E110TX_RAM_SIZE[1:0] Transmit FIFO RAM Size--Strap these inputs to define the Transmit FIFO RAM size E110TX_WEB MII_COL Transmit Write Enable Port B--Write enable from the ApE110 DMAC to strobe data into the Transmit FIFO Ethernet Collision Detected--When the Ethernet PHY detects a collision, it asserts the MII_COL signal asynchronously with minimum delay from the start of collision on the media Ethernet Carrier Sense--When a non-idle medium is detected, the Ethernet PHY asserts the MII_CRS signal asynchronously with minimum delay Ethernet Management Data Clock--The Ethernet PHY uses MII_MDC as a timing reference for the transfer of information on the MII_MDI and MII_MDO signal lines Ethernet Management Data In--The Ethernet PHY device places the Ethernet control information on MII_MDI, and MII_MDC clocks it synchronously MII_CRS Input MII_MDC Output MII_MDI Input Interface Signals Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-7 Table 4.5 Ethernet Signals (Cont.) Signal Function Ethernet Management Data Out--Transfers Ethernet control information on the MII_MDO signal to the Ethernet PHY device Ethernet Management Data Output Enable--Provides the 3-state enable for MII_MDO when MII_MDO and MII_MDI are combined into a bidirectional line (MII_MDIO) outside the Ethernet peripheral Ethernet Receive Nibble Data--Consists of four data signals that the Ethernet PHY drives synchronously to the rising edge of MII_RXCLK Ethernet Receive Data Valid--The Ethernet PHY asserts MII_RXDV to indicate that the Ethernet PHY is presenting recovered and decoded nibbles on the MII_RXD[3:0] signals, and that MII_RXCLK is synchronous to the recovered data Ethernet Receive Error--The Ethernet PHY asserts MII_RXER to indicate to the Ethernet core that a media error (for example, a coding error) was detected somewhere in the frame being transferred to the Ethernet PHY Ethernet Transmit Nibble Data--Consists of four data signals that are synchronous to the rising edge of MII_TXCLK Ethernet Transmit Enable--Indicates that the Ethernet core is presenting MII_TXD[3:0] nibbles on the MII for transmission Ethernet Transmit Coding Error--Causes the Ethernet PHY to transmit one or more symbols not part of the frame to indicate there has been a transmitter coding error I/O Output Output Signal Mnemonic MII_MDO MII_MDOEN_n MII_RXD[3:0] Input MII_RXDV Input MII_RXER Input MII_TXD[3:0] MII_TXEN MII_TXER Output Output Output Table 4.6 ApVic Signals Signal Function System External Interrupt--External interrupt inputs to the Vectored Interrupt Controller I/O Input Signal Mnemonic INTERRUPTS[31:0] Table 4.7 ApI2c Signals Signal Function I Interrupt--Indicates an internal interrupt is pending from one of the Master or Slave sources I2C Bus SCL In--SCL input clock signal 2C Signal Mnemonic I2CINTR# SCL#_I I/O Output Input 4-8 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 4.7 ApI2c Signals (Cont.) Signal Function 2 2 Signal Mnemonic SCL#_O_n SDA#_I SDA#_O_n I/O I C Bus SCL Output--ApI2c output signal drives the I C bus SCL clock Output signal I2C Bus SDA In--SDA serial data input signal I2C Bus SDA Output--ApI2c output signal drives the I2C bus SDA data signal Input Output Table 4.8 UART Signals Signal Function Clear to Send--Indicates the modem or data set is ready to exchange data Data Carrier Detect--Indicates the data carrier has been detected by the modem or data set Data Set Ready--Indicates the modem or data set is ready to establish communications with the UART Data Terminal Ready--Informs the modem or data set the UART is ready to establish communications User Controlled Output--User-designated output User Controlled Output--User-designated output Ring Indicator--Indicates a telephone ringing signal has been received by the modem or data set Request to Send--Informs the modem or data set the UART is ready to exchange data Receiver Ready--Receiver DMA signaling is available Serial Input--Serial data input from the communications link Serial Output--Composite serial data output to the communications link Transmitter Ready--Transmitter DMA signaling is available UART Interrupt--Goes HIGH when one of the interrupt types has an active HIGH condition I/O Input Input Input Output Output Output Input Output Output Input Output Output Output Signal Mnemonic CTSn# DCDn# DSRn# DTRn# OUT1n# OUT2n# RIn# RTSn# RXRDYn# SIN# SOUT# TXRDYn# UARTINTR# Interface Signals Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-9 Table 4.9 GPIO Signals Signal Function General-Purpose I/O Data Direction--Reflects the contents of the GPIO Data Direction Registers and indicates whether a GPIO bit is an input or output GPIO Data In--Inputs to the GPIO peripheral GPIO Data Out --Outputs from the GPIO peripheral Interrupt Vector--Indicates an interrupt was detected in GPIO (n+1) I/O Output Signal Mnemonic GPIODataDir[31:0] GPIODataIn[31:0] GPIODataOut[31:0] GPIOINTS[3:0] Input Output Output Table 4.10 Timer Signals Signal Function Timer Trigger Point 1 Match--Indicates a match between the Trigger Point 1 value and selected timer value Timer Trigger Point 2 Match--Indicates a match between the Trigger Point 2 value and selected timer value Timer Trigger Point 3 Match--Indicates a match between the Trigger Point 3 value and selected timer value Timer Trigger Point 4 Match--Indicates a match between the Trigger Point 4 value and selected timer value Timer Trigger Point 5 Match--Indicates a match between the Trigger Point 5 value and selected timer value Timer Trigger Point 6 Match--Indicates a match between the Trigger Point 6 value and selected timer value I/O Output Output Output Output Output Output Signal Mnemonic TTP1MATCH TTP2MATCH TTP3MATCH TTP4MATCH TTP5MATCH TTP6MATCH Table 4.11 SRAM, Flash, ROM Port Signals Signal Function Chip Select 7 Data Width Select--Provides the reset value of the Chip Select 7 Control Register Width field External SRAM Chip Selects--Controls the chip select signals for the external SRAM SRAM Data Output Enable--Controls the direction of the data for the external SRAM controller External SRAM Output Enable--Enables the SRAM outputs External SRAM Write Enables--Indicates valid write operations to the SRAM I/O Input Output Output Output Output Signal Mnemonic CS7WIDTH[1:0] nSRAMCS[7:0] nSRAMDOE[3:0] nSRAMOE nSRAMWE[3:0] 4-10 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 4.11 SRAM, Flash, ROM Port Signals (Cont.) Signal Function External SRAM Address--External SRAM address bus SRAM Read Data--Carries the data read out from the SRAM SRAM Write Data--Carries the data written to the SRAM I/O Output Input Output Signal Mnemonic SRAMADDR[31:0] SRAMRDATA[31:0] SRAMWDATA[31:0] Table 4.12 Instruction AHB Multiport Memory Controller Port Signals Signal Function AHB Address Bus--32-bit system address bus AHB Burst Type--Indicates whether the transfer is part of a burst and the burst type AHB Locked Sequence--Indicates the current Master is performing a locked transfer sequence I/O Output Output Output Signal Mnemonic IHADDR[31:0] IHBURST[2:0] IHMASTLOCK IHPROT[3:0] IHRDATAEXT[31:0] IHREADY IHREADYOUTEXT IHRESPEXT[1:0] IHSEL IHSIZE[2:0] IHTRANS[1:0] IHWRITE AHB Protection Control--Provides information about protection level of Output a bus access AHB Read Data Bus--Transfers data from bus Slaves to the bus Master during read operations AHB Transfer Done--Indicates the existing transfer on the bus is complete and a new transfer is starting AHB Transfer Done--Indicates that a transfer has finished on the bus AHB Transfer Response--Provides additional information on the transfer status AHB Slave Select to Memory--Combinational address bus decode AHB Transfer Size--Indicates the transfer size AHB Transfer Type--Current transfer type AHB Transfer Direction--Indicates a write transfer when asserted or a read transfer when deasserted Input Output Input Input Output Output Output Output Table 4.13 Data AHB Multiport Memory Controller Port Signals Signal Function AHB Address Bus--32-bit system address bus AHB Burst Type--Indicates whether the transfer is part of a burst and the burst type AHB Locked Sequence--Indicates the current Master is performing a locked transfer sequence I/O Output Output Output Signal Mnemonic DHADDR[31:0] DHBURST[2:0] DHMASTLOCK Interface Signals Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-11 Table 4.13 Data AHB Multiport Memory Controller Port Signals (Cont.) Signal Function I/O Signal Mnemonic DHPROT[3:0] AHB Protection Control--Provides information about protection level of Output a bus access Input Input Output Input Input Input Input Output Output Output Output DHRDATACFG[31:0] AHB Configuration Port Read Data Bus--Transfers data from bus Slaves to the bus Master during read operations DHRDATAEXT[31:0] DHREADY DHREADYOUTCFG DHREADYOUTEXT DHRESPCFG[1:0] DHRESPEXT[1:0] DHSEL DHSELCFG DHSIZE[2:0] DHTRANS[1:0] DHWDATA[31:0] DHWRITE AHB Memory Port Read Data Bus--Transfers data from bus Slaves to the bus Master during read operations AHB Transfer Done--Indicates the existing transfer on the bus is complete and a new transfer is starting AHB Configuration Port Transfer Done--Indicates that a configuration port bus transfer is complete AHB Memory Port Transfer Done--Indicates that a memory port bus transfer is complete AHB Configuration Port Transfer Response--Provides additional information about the configuration port transfer status AHB Memory Port Transfer Response--Provides additional information about the memory port transfer status AHB Slave Select to Memory--Indicates memory accesses to a DDR SDRAM controller AHB Slave Select to Register Configuration--Indicates register configuration accesses to a DDR SDRAM controller AHB Transfer Size AHB Transfer Type--Current transfer type AHB Write Data Bus--Transfers data from the Master to the bus Slaves Output during write operations AHB Transfer Direction--Indicates a write transfer when asserted or a read transfer when deasserted Output Table 4.14 AHB Slave Expansion Port Signals Signal Function Bridge Boot Select--Indicates from which port the processor will boot AHB Address Bus--32-bit system address bus AHB Burst Type--Indicates whether the transfer is part of a burst and the burst type AHB Master Lock--Indicates whether the Master requires locked access on the external bus I/O Input Output Output Output Signal Mnemonic BRBOOTSEL BRHADDR[31:0] BRHBURST[2:0] BRHMASTLOCK 4-12 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 4.14 AHB Slave Expansion Port Signals (Cont.) Signal Function I/O Signal Mnemonic BRHPROT[3:0] BRHRDATA[31:0] BRHREADY BRHRESP[1:0] BRHSIZE[2:0] BRHTRANS[1:0] BRHWDATA[31:0] BRHWRITE AHB Protection Control--Provides information about protection level of Output a bus access AHB Read Data Bus--Transfers data from the Slave(s) on the external bus during read operations AHB Transfer Done--Indicates whether a transfer has finished on the external bus AHB Transfer Response--Provides additional information on the transfer status AHB Transfer Size AHB Transfer Type AHB Write Data Bus--Transfers data from the bridge to the Slave(s) on the external bus during write operations AHB Transfer Direction--Indicates a write transfer when asserted or a read transfer when deasserted Input Input Input Output Output Output Output Table 4.15 JTAG Signals Signal Function JTAG Test Data Output Enable--Enables test data output JTAG Test Reset--Used to reset ARM926EJ-S debug logic including the EmbeddedICETM logic, TAP controller, and boundary scan cells; does not reset the entire processor system JTAG Returned Test Clock--Returned TCK that can be used by ARM Multi-ICE(R) debug tools with adaptive clocking to synchronize to the JTAG port JTAG Test Clock--Used as a data enable in the synchronizing logic included in the processor system JTAG Test Data Input--Test data input signal JTAG Test Data Output--Test data output signal JTAG Test Mode Select I/O Output Input Signal Mnemonic nTDOEN nTRST RTCK Output TCK TDI TDO TMS Input Input Output Input Interface Signals Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 4-13 4-14 Signal Summary Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Chapter 5 Specifications This chapter summarizes the Processor System for ARM926EJ-S physical specifications. This chapter contains the following sections: * * * Section 5.1, "Physical Specifications" Section 5.2, "Operating Conditions" Section 5.3, "AC Electrical Specifications" 5.1 Physical Specifications The physical specifications of the Processor System for ARM926EJ-S are shown below: Process Technology 0.11 m (Gflx-r) Gate Count Metal Stack 164,0001 N/A 1. Excluding the ARM926EJ-S and its TCMs 5.2 Operating Conditions The core is characterized for: * * Setup times: Worst Case Industrial (wcind) Hold times: N/A 0.11 m Processor System for ARM926EJ-S Datasheet Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-1 Table 5.1 shows the Processor System for ARM926EJ-S timing conditions. Table 5.1 Processor System for ARM926EJ-S Timing Conditions Process 0.81 1.32 VDD (V) 1.26 1.08 Junction Temperature (oC) -40 125 AC Timing Best Case, Industrial Worst Case, Industrial 5.3 AC Electrical Specifications All AC timing values are referenced to an ideal system clock input to the Processor System for ARM926EJ-S. Input setup time is measured from the time the signal is valid to the rising edge of an ideal clock and includes the sink flip-flop setup time. Input hold time is measured from the rising edge of the ideal clock to the time the signal goes invalid. For input setup times, the driver must drive the signal valid before any receivers need it. For input hold times, the driver must hold the signal valid longer than needed by any receiver. The maximum delay times for outputs are measured from the rising edge of ideal clock, and include CP->Q of the source flip-flop. Figure 5.1 shows how AC timing is measured. Figure 5.1 AC Specifications Clock Period CLK Setup Hold Input Signal Max Delay Output Signal Min Delay 5-2 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. The maximum frequency for each clock of the Processor System for ARM926EJ-S in each technology is shown in Table 5.2: Table 5.2 Maximum Clock Frequency Maximum frequency (MHz) (cw001200_agflxr_2_0) 200 100 50 25-33 2.5 or 25 2.5 or 25 Clock CLK HCLK PCLK HOST_CLK MII_RXCLK MII_TXCLK Maximum frequency is heavily dependent on the system. The maximum clock frequency estimate assumes input and output delays as a function of the clock period. The Processor System for ARM926EJ-S is a Firm core that delivers a netlist without placement information. Therefore hold time values are not precise enough to be useful and are not reported in this document. This design has been rated using static timing analysis for a 50/50 duty cycle. The design is nearly independent of duty cycle because it is fully synchronous other than the lock-up latches for scan. 5.3.1 Input Timing Table 5.3, Table 5.4, Table 5.6, Table 5.7, Table 5.8, and Table 5.9 show the AC timing values for the Processor System for ARM926EJ-S input pins. The input value is a percentage of the maximum clock frequency for a given technology. Because the IP is delivered as a Firm netlist, the AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-3 input times represented are only estimates and are valid for all technologies. Table 5.3 Input Timing in the CLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 35% 15% 15% Input Pin EDBGRQ INITRAM VINITHI Table 5.4 Input Timing in the HCLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 40% 20% 5% 20% 20% 10% 25% 25% 40% 40% 40% 40% 20% 15% 10% Input Pin BRBOOTSEL BRHCLKEN BRHRDATA[*] BRHREADY BRHRESP[*] CS7WIDTH[*] DHRDATACFG[*] DHRDATAEXT[*] DHREADYOUTCFG DHREADYOUTEXT DHRESPCFG[*] DHRESPEXT[*] E110RX_DOA[*] E110RX_RAM_SIZE[*] E110TX_RAM_SIZE[*] 5-4 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.4 Input Timing in the HCLK Domain (Cont.) Input Setup cw001200_agflxr_2_0 with cw001124_1_0 20% 10% 25% 15% 55% 50% 30% 5% 10% 20% 25% 40% 30% 35% 5% Input Pin HCLKEN IHRDATAEXT IHREADYOUTEXT IHRESPEXT[*] INTERRUPTS[*] MHADDR[*] MHBURST[*] MHBUSREQ MHLOCK MHPROT[*] MHSIZE[*] MHTRANS[*] MHWDATA[*] MHWRITE SRAMRDATA[*] Table 5.5 Input Timing in the HOST_CLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 10% Input Pin CLKS AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-5 Table 5.6 Input Timing in the MII_RXCLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 10% 10% 5% Input Pin MII_RXD[*] MII_RXDV MII_RXER Table 5.7 Input Timing in the MII_TXCLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 10% 5% 5% Input Pin E110TX_DOA[*] MII_COL MII_CRS Table 5.8 Input Timing in the PCLK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 5% 5% 5% 5% 5% 5% 10% 25% Input Pin CTSn0 CTSn1 DCDn0 DCDn1 DSRn0 DSRn1 GPIODataIn[*] PCLKEN 5-6 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.8 Input Timing in the PCLK Domain (Cont.) Input Setup cw001200_agflxr_2_0 with cw001124_1_0 5% 5% 5% 5% 5% 5% 5% 5% Input Pin RIn0 RIn1 SCL0_I SCL1_I SDA0_I SDA1_I SIN0 SIN1 Table 5.9 Input Timing in the TCK Domain Input Setup cw001200_agflxr_2_0 with cw001124_1_0 10% 10% Input Pin TDI TMS 5.3.2 Output Timing Table 5.10, Table 5.11, Table 5.12, Table 5.13, Table 5.14, and Table 5.15 show the AC timing values for the Processor System for ARM926EJ-S output pins as a percentage of the maximum clock frequency in a given AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-7 technology. Because the IP is delivered as a Firm netlist, the output times represented are only estimates, and are valid for all technologies. Table 5.10 Output Timing in the CLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 50% 30% 15% 20% 40% Output Pin DBGACK nTDOEN RTCK STANDBYWFI TDO Table 5.11 Output Timing in the HCLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 10% 10% 10% 10% 10% 10% 10% 10% 30% 25% 10% 25% 35% Output Pin BRHADDR[*] BRHBURST[*] BRHMASTLOCK BRHPROT[*] BRHSIZE[*] BRHTRANS[*] BRHWDATA[*] BRHWRITE DHADDR[*] DHBURST[*] DHMASTLOCK DHPROT[*] DHREADY 5-8 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.11 Output Timing in the HCLK Domain (Cont.) Output Valid cw001200_agflxr_2_0 with cw001124_1_0 40% 40% 25% 30% 20% 25% 15% 15% 10% 10% 30% 20% 15% 20% 15% 10% 15% 30% 20% 20% 10% 10% 30% 40% Output Pin DHSEL DHSELCFG DHSIZE[*] DHTRANS[*] DHWDATA[*] DHWRITE E110_INT E110RX_AADR[*] E110RX_ENA E110TX_BADR[*] E110TX_DIB[*] E110TX_ENB E110TX_WEB IHADDR[*] IHBURST[*] IHMASTLOCK IHPROT[*] IHREADY IHSEL IHSIZE[*] IHTRANS[*] IHWRITE MHGRANT MHRDATA[*] AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-9 Table 5.11 Output Timing in the HCLK Domain (Cont.) Output Valid cw001200_agflxr_2_0 with cw001124_1_0 35% 35% 10% 10% 10% 10% 10% 10% Output Pin MHREADY MHRESP[*] nSRAMCS[*] nSRAMDOE[*] nSRAMOE nSRAMWE[*] SRAMADDR[*] SRAMWDATA[*] Table 5.12 Output Timing in the HOST_CLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 5% 5% 5% Output Pin MII_MDC MII_MDO MII_MDOEN_n Table 5.13 Output Timing in the MII_RXCLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 5% 10% 10% 10% Output Pin E110RX_BADR[*] E110RX_DIB[*] E110RX_ENB E110RX_WEB 5-10 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.14 Output Timing in the MI_TXCLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 5% 10% 5% 5% 5% Output Pin E110TX_AADR[*] E110TX_ENA MII_TXD[*] MII_TXEN MII_TXER Table 5.15 Output Timing in the PCLK Domain Output Valid cw001200_agflxr_2_0 with cw001124_1_0 30% 30% 10% 10% 15% 10% 10% 30% 30% 30% 30% 30% 30% 10% Output Pin DTRn0 DTRn1 GPIODataDir[*] GPIODataOut[*] GPIOINTS[*] I2CINTR0 I2CINTR1 OUT1n0 OUT1n1 OUT2n0 OUT2n1 RTSn0 RTSn1 RXRDYn0 AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-11 Table 5.15 Output Timing in the PCLK Domain (Cont.) Output Valid cw001200_agflxr_2_0 with cw001124_1_0 10% 10% 10% 10% 10% 15% 15% 15% 10% 10% 10% 10% Output Pin RXRDYn1 SCL0_O_n SCL1_O_n SDA0_O_n SDA1_O_n SOUT0 SOUT1 TTPxMATCH TXRDYn0 TXRDYn1 UARTINTR0 UARTINTR1 5.3.3 Pass-Through Timing The Processor System for ARM926EJ-S, when analyzed individually, contains several pass-through paths. These paths are defined in two ways: The port to and from an internal register; and the port to another port. In Section 5.3.1, "Input Timing," the percentage of the clock for input setup of the input port to an internal register is reported. Likewise in Section 5.3.2, "Output Timing," the percentage of clock for output valid for an internal register to the output port is reported. In this section the AC timing value of the input port to the output port is reported. The rest of the clock period must be shared by the logic connected to the input and output ports. Table 5.16 shows the AC timing values for the Processor System for ARM926EJ-S pass-through pins as a percentage of the maximum clock frequency in a given technology. Because the IP is delivered as a Firm netlist, the times represented are only estimates, and are valid for all 5-12 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. technologies. The 0.11 m Processor System for ARM926EJ-S Integration Application Note contains more information about these paths. Table 5.16 Pass-Through Paths in the HCLK Domain Pass-Through Time cw001200_agflxr_2_0 with cw001124_1_0 10% 15% 20% 15% 20% 15% 15% 15% 10% 15% 15% 10% 20% 20% 10% 10% Input Pin Output Pin DHRDATACFG[*] DHRDATAEXT[*] DHREADYOUTCFG DHREADYOUTCFG DHREADYOUTEXT DHREADYOUTEXT DHRESPCFG[*] DHRESPEXT[*] GPIODataIn[*] GPIODataIn[*] IHREADYOUTEXT MHADDR[*] MHADDR[*] MHADDR[*] MHBURST[*] MHPROT[*] MHRDATA[*] MHRDATA[*] DHREADY MHREADY DHREADY MHREADY MHRESP[*] MHRESP[*] GPIOINTS[*] MHRDATA[*] IHREADY DHADDR[*] DHSEL DHSELCFG DHBURST[*] DHPROT[*] AC Electrical Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-13 Table 5.16 Pass-Through Paths in the HCLK Domain (Cont.) Pass-Through Time cw001200_agflxr_2_0 with cw001124_1_0 10% 10% 10% 10% 10% 10% Input Pin Output Pin MHSIZE[*] MHTRANS[*] MHWDATA[*] MHWRITE PCLKEN PCLKEN DHSIZE[*] DHTRANS[*] DHWDATA[*] DHWRITE DHREADY MHREADY 5-14 Specifications Copyright (c) 2004, 2005 by LSI Logic Corporation. All rights reserved. |
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