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EDI8F82048C
2 Megx8 SRAM Module
2 Megabits x 8 Static RAM CMOS, Module
Features
2 Meg x 8 bit CMOS Static Random Access Memory * Access Times 70 thru 100ns * Data Retention Function (EDI8F82048LP ) * TTL Compatible Inputs and Outputs * Fully Static, No Clocks High Density Packaging * 36 Pin SIP, No. 136 * 36 Pin Flat SIP, No. 335 Single +5V (10%) Supply Operation
The EDI8F82048C is a 16 megabit CMOS Static RAM based on sixteen 128Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate. A low power version with data retention (EDI8F82048LP) is also available. The EDI8F82048C is offered in a double sided, 36 pin singlein-line package (SIP), which provides a cost effective solution to very high packing density. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI8F82048C requires no clocks or refreshing for operation.
Pin Configurations and Block Diagram
A19 VCC W DQ2 DQ3 DQO A1 A2 A3 A4 VSS DQ5 A10 A11 A5 A13 A14 A20 E A15 A16 A12 A18 A6 DQ1 VSS AO A7 A8 A9 DQ7 DQ4 DQ6 A17 VCC G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Names
AO-A20 E W G DQO-DQ7 VCC VSS NC
AO-A16 W G DQO-DQ7
Address Inputs Chip Enable Write Enable Output Enable Common Data Input/Output Power (+5V10%) Ground No Connection
A20 A19 A18 A17 E
DECODER DECODER
DECODER DECODER
Electronic Designs Incorporated * One Research Drive * Westborough, MA 01581USA * 508-366-5151 * FAX 508-836-4850 * Electronic Designs Europe Ltd. * Shelley House, The Avenue * Lightwater, Surrey GU18 5RF United Kingdom * 01276 472637 * FAX: 01276 473748
1 EDI8F82048C Rev. 4.0 4/96 ECO#7470
Absolute Maximum Ratings*
Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. -0.5V to 7.0V 0C to +70C -40C to +85C -55C to +125C 1 Watt 20 mA
Recommended DC Operating Conditions
Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --Max Units 5.5 V 0 V 6.0 V 0.8 V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
VSS to 3.0V 5ns 1.5V TTL, CL =100pF
DC Electrical Characteristics
Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
*Typical: TA = 25C, VCC = 5.0V
Sym ICC1 ICC2 ICC3
ILI ILO VOH VOL
Conditions W, E = VIL, II/O = 0mA, Min Cycle E VIH, VIN VIL VIN VIH E VCC-0.2V VIN VCC-0.2V or VIN 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH =-1.0mA IOL = 2.1mA
Min --C LP ----2.4 --
Typ*
Max 210 135 20 500
Units mA mA mA A A A V V
-----
20 20 -0.4
Truth Table
G X H L X E H L L L W X H H L Mode Standby Output Deselect Read Write Output High Z High Z DOUT DIN Power ICC2, ICC3 ICC1 ICC1 ICC1
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter Sym Max 110 130 20 Unit pF pF pF
Address Lines CI Data Lines CD/Q Chip Enable and A17-A20 Lines CC
These parameters are sampled, not 100% tested.
EDI8F82048C
2Megx8 SRAM Module
2 EDI8F82048C Rev. 4.0 4/96 ECO#7470
EDI8F82048C
2 Megx8 SRAM Module
AC Characteristics Read Cycle
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1)
Note 1: Parameter guaranteed, but not tested.
Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ
70ns Min Max 70 70 70 5 30 3 40 0 30
85ns Min Max 85 85 85 5 35 3 45 0 35
100ns Min Max 100 100 100 5 40 3 50 0 40
Units ns ns ns ns ns ns ns ns ns
Read Cycle 1 - W High, G, E Low
TAVAV A ADDRESS 1 TAVQV Q ADDRESS 2 TAVQX DATA 1 DATA 2
Read Cycle 2 - W High
TAVAV A TAVQV E TELQV TELQX G TGLQV TGLQX Q TGHQZ TEHQZ
3 EDI8F82048C Rev. 4.0 4/96 ECO#7470
AC Characteristics Write Cycle
Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
Symbol JEDEC Alt. TAVAV TWC TELWH TCW TELEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TWLEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ
70ns Min Max 70 65 65 0 0 65 65 65 65 0 0 0 0 0 30 30 30 5
85ns Min Max 85 70 70 0 0 70 70 70 70 0 0 0 0 0 35 35 35 5
100ns Min Max 100 80 80 0 0 80 80 80 80 0 0 0 0 0 40 40 40 5
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle 1 - W Controlled
TAVAV A E TELWH TAVWH TWLWH W TAVWL D TWLQZ Q HIGH Z TDVWH DATA VALID TWHQX TWHDX TWHAX
EDI8F82048C
2Megx8 SRAM Module
4 EDI8F82048C Rev. 4.0 4/96 ECO#7470
EDI8F82048C
2 Megx8 SRAM Module
Write Cycle 2 - E Controlled
TAVAV A TAVEL E TAVEH TWLEH W TDVEH D Q HIGH Z DATA VALID TEHDX TEHAX TELEH
Data Retention Characteristics
Characteristic Data Retention Voltage Data Retention Quiescent Current Sym VDD ICCDR Test Conditions VDD Min 2 -0 TAVAV* Typ --
LP Version Only
Max 70C 85C --300 450 400 550 ----Unit V A A ns ns
Chip Disable to Data Retention Time(1) TCDR Operation Recovery Time (1) TR
Note 1: Parameter guaranteed, but not tested. * Read Cycle Time
E VDD -0.2V VIN VDD -0.2V or VIN 0.2V
2V 3V
---
Data Retention - E Controlled
Data Retention Mode VCC TCDR 4.5V VDD 4.5V
TR
E
EVDD -0.2V
5 EDI8F82048C Rev. 4.0 4/96 ECO#7470
Ordering Information
Standard Power EDI8F82048C70BSC EDI8F82048C85BSC EDI8F82048C100BSC EDI8F82048C70BFC EDI8F82048C85BFC EDI8F82048C100BFC Low Power with Data Retention EDI8F82048LP70BSC EDI8F82048LP85BSC EDI8F82048LP100BSC EDI8F82048LP70BFC EDI8F82048LP85BFC EDI8F82048LP100BFC Speed (ns) 70 85 100 70 85 100 Package No. 136 136 136 335 335 335
Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, eg. EDI8F82048C70BSC becomes EDI8F82048C70BSI.
Package Description Package No. 136 36 Pin Single-in-line Package
4.040 Max 0.200 Max
0.855 Max 0.175 0.125
0.020 0.016
35 x 0.100 =3.500
Package No. 335 36 Pin Flat SIP
4.040 MAX.
.200 MAX
.830 MAX P1
.100 TYP.
35 X .100 3.500 REF.
Electronic Designs Incorporated * One Research Drive * Westborough, MA 01581USA * 508-366-5151 * FAX 508-836-4850 * Electronic Designs Europe Ltd. * Shelley House, The Avenue * Lightwater, Surrey GU18 5RF United Kingdom * 01276 472637 * FAX: 01276 473748 Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301
EDI8F82048C
2Megx8 SRAM Module
6 EDI8F82048C Rev. 4.0 4/96 ECO#7470

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