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| 10BIT 30MSPS ADC GENERAL DESCRIPTION The BW1217X is a CMOS 10-bit A/D converter for video applications. It is a three-step pipelined A/D converter which consists of sample & hold, two multiplying DACs, and three 4-bit flash ADCs. The maximum conversion rate of BW1217X is 30MSPS and supply voltage is 3.3V single. BW1217X FEATURES Resolution : 10Bit Differential Linearity Error : 1.0 LSB Integral Linearity Error : 2.0 LSB Maximum Conversion Rate : 30MSPS Sample & Hold Function Implemented Low Power Consumption : 82.5mW(Typ) Power Supply : 3.3V Single Operation Temperature Range : 0C ~70C TYPICAL APPLICATIONS - PC or computer based video signal processing such as multi-media, scanner, etc. - General Purpose video applications including camcorder, digital video, broad-casting and studio equipments. - Medical electronics such as digital scope, transit recorder, radar. FUNCTIONAL BLOCK DIAGRAM VDDA VSSA VBBA VDDD VSSD VBBD FLASH 1 FLASH 2 FLASH 3 OVF UDF DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] AINT AINC REFTOP REFBOT SHA MDAC 1 MDAC 2 REFMID CML CML GEN. ITEST STBY CKIN MAIN BIAS CLOCK GEN. DIGITAL LOGIC Ver 1.1 (Feb. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice 10BIT 30MSPS ADC CORE PIN DESCRIPTION NAME AINT AINC REFMID REFTOP REFBOT VDDA VSSA VBBA ITEST STBY CKIN CML DO[9:0] OVF UDF VBBD VSSD VDDD BW1217X I/O TYPE AI AI AB AI AI AP AG AG AB DI DI AB DO DO DO DG DG DP I/O PAD piar50_bb piar50_bb pia_bb pia_bb pia_bb vdda vssa vbba pia_bb picc_bb picc_bb pia_bb pot2_bb pot2_bb pot2_bb vbba vssd vddd PIN DESCRIPTION Analog Input + (Input Range : 0.5V ~ 2.5V) Analog Input : (DC=1.5V) Reference Mid Point (Test Pin) Reference Top (2.0V) Reference Bottom(1.0V) Analog Power ( 3.3V ) Analog Ground Analog Sub Bias open=use internal bias point high=power saving standby mode (normally = gnd) Sampling Clock Input Internal Bias Point(Test Pin) Digital Output Overflow Underflow Digital Sub Bias Digital Ground Digital Power I/O TYPE ABBR. AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground CORE CONFIGURATION VDDA VSSA VDDD VBBD VBBA VSSD AINT AINC OVF UDF DO[9:0] REFTOP REFBOT CKIN STBY BW1217X REFMID ITEST CML SEC ASIC 2 / 11 ANALOG 10BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Storage Temperature Range BW1217X Symbol VDD AIN CLK VOH, VOL Tstg 4.5 Value Unit V V V V C VSS to VDD VSS to VDD VSS to VDD -45 to 125 NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5K resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Supply Voltage Supply Voltage Difference Reference Input Voltage(Externally) Analog Input Voltage (+) Analog Input Voltage (-) Operating Temperature Symbol VDDA - VSSA VDDD - VSSD VDDA - VDDD REFTOP REFBOT AINT AINC Topr Min 3.15 -0.1 0.5 Typ 3.3 0.0 2.0 1.0 1.5 Max 3.45 0.1 2.5 Unit V V V V V 0 - 70 C NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 11 ANALOG 10BIT 30MSPS ADC BW1217X DC ELECTRICAL CHARACTERISTICS Characteristics Resolution Reference Current Differential Linearity Error Integral Linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Symbol IREF DLE ILE EOB EOT Min - Typ 2 - Max 10 3 1.0 2.0 20 20 Unit Bits mA LSB LSB LSB LSB - Conditions AINT : 0.5 ~ 2.5V (Ramp Input) Fck : 1MHz NOTES 1. Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=GND VSSD=GND Ta=25C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Symbol fc Min 30 Typ - Max - Unit MSPS Conditions AINT : 1MHz Sine Signal (source resolution > 12bit) fc=30MHz (without system load) AINT = 1MHz fc = 30MHz Dynamic Supply Current Ivdd - 25 30 mA Signal - to - Noise Ratio SNR 48 52 - dB SEC ASIC 4 / 11 ANALOG 10BIT 30MSPS ADC TIMING DIAGRAM( Main Function ) BW1217X AIN CLOCK SHA hold track hold track hold track hold track hold track ref sample FLASH1 amplify precharge latch track latch encoding input sample residue amplify MDAC1 input sample residue amplify ref sample FLASH2 amplify precharge latch track latch encoding input sample residue amplify MDAC2 input sample residue amplify ref sample FLASH3 amplify precharge latch track latch encoding DATA DATA SEC ASIC 5 / 11 ANALOG 10BIT 30MSPS ADC FUNCTIONAL DESCRIPTION 1. BW1217X is a three step A/D Converter comprising three 4-bit flash ADC and two multiplying DAC. The N-bit flash ADC is composed of 2(n-1) latching comparators, and multiplying DAC is composed of 2*(N+2) capacitors and two fully-differential amplifier. BW1217X bias to protect interruption of any other circuit. SAH amp is designed that open-loop dc gain is higher than 70dB, phase margin is higher than 60degree. Its input block is designed to be the rail-to-rail architecture using complementary differential pair. 2. FLASH The 4-bit flash converter compares analog signal(SAH output) with reference voltage, and that result transfers to MDAC and digital correction logic block. It is realized fully differential comparators of 15EA. Considering self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the reference voltage at the sampling capacitors before transferred SAH output. Q2 works this process and Q1 discharges this sampling capacitors. That is, the comparators compare relative different values dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P. 3. MDAC MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of amp1,amp2, selection logic and capacitor array(c_array). C_array's compositions are the capacitors to charge the analog input and the reference voltage, Switches to control the path. Selection logic controls the c_array internal switches. If Q1 is high, selection's output is all low, the switches of tsw1 are off, the switches of tsw2 are all on. Therefore the capacitors of c_array charges analog input values held at SAH. If Q2 is high, it is reversed and final MDAC output voltage is described the following equation. Vout = (AIN - Vref)*8-Vref/2 AIN=AINT-1.5V 2. BW1217X operates as follows. During the first "L" cycle of external clock the analog input data is tracked and sampled, and the input is held from the rising edge of the external clock, which is fed to the first 4-bit flash ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 4-bit ADC's output, and finally amplifies a residue voltage by 23. The second 4-bit flash ADC, and MDAC are worked as same manner, finally amplifiers a residue voltage, which is the difference between first MDAC's output and reconstructed voltage by 22. The third 4-bit flash ADC, and MDAC are worked as previous stages. 3. BW1217X has the error correction scheme, which handles the output from mismatch in the first, second and third flash ADC. MAIN BLOCK DESCRIPTION 1. SAH SAH(track and hold) is the circuit that samples the analog input signal and holds that value until next sample-time. It is good as small as its different value between analog input signal and output signal. SAH amp gain must be higher than 66dB at least for less than 1/2LSB of SAH error voltage at 10bit ADC and its conversion frequency is 30MHz, its settling-time must be shorten than 12ns. This SAH is consist of fully differential op amp, switching tr. and sampling capacitor. The sampling clock are non-overlapping clocks(Q1,Q2) and sampling capacitor value is 1.2pF. SAH uses independent SEC ASIC 6 / 11 ANALOG 10BIT 30MSPS ADC CORE EVALUATION GUIDE BW1217X 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor divider. 2.0V 1.0V NOTES : 10uF Electronic Capacitor unless Otherwise Specified : 0.1uF Ceramic Capacitor unless Otherwise Specified REFTOP STBY REFBOT DO[9:0] DO[9:0] Power Used :VDDA,VDDD,VBBD VSSA,VSSD,VBBA Digital Mux OVF UDF AINT AINC CKIN ITEST REFMID CML BW1217X HOST DSP CORE DO[9:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input) SEC ASIC 7 / 11 ANALOG 10BIT 30MSPS ADC PACKAGE CONFIGURATION BW1217X NOTES 1. You can test ADC function by checking external bidirectional pad connected to internal signal path. 2. ESD (Electro Static Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 3. NC denotes "No Connection". 2.0V 1.0V Reference Reference Top Bottom 3.3V Digital Power GND 48 VDDD 47 VDDD 46 VSSD 45 VSSD 4 3 2 1 3.3V Analog Power NC REFBOT REFTOP NC 5 6 7 8 CML VDDA VDDA VBBA VSSA VSSA AINT NC AINC VBBD NC NC NC NC NC OVF 44 43 42 41 40 39 38 37 36 35 Digital Output Bits 2 Through 9 GND Video-In (Input Range:0.5~2.5V) 9 10 11 12 DC 1.5V 13 14 15 16 17 REFMID NC ITEST STBY VDDR VSSR CKIN bw1217l_top BW1217X TRISTATE 25 UDF D<9> D<8> D<7> 34 D<6> 33 D<5> 32 D<4> 31 D<3> 30 D<2> 29 D<0> 27 D<1> 28 3.3V PAD Power 18 19 20 NC 21 NC 22 NC 23 NC 24 NC 26 Clock Signal Digital Output Bits 0 and 1 NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED SEC ASIC 8 / 11 ANALOG 10BIT 30MSPS ADC PACKAGE PIN DESCRIPTION NAME REFTOP REFBOT CML VDDA VBBA VSSA AINT BW1217X PIN NO. 2 3 5 6,7 8 9,10 11 I/O TYPE AI AI AB AP AG AG AI PIN DESCRIPTION External Reference Top Bias.(2.0V) External Reference Bottom Bias.(1.0V) Internal Bias Point ( Test Pin ) 3.3V Analog Power Analog Sub Bias Analog Ground Analog Input (+) Input Range : 0.5~2.5V Analog Input. (-) DC 1.5V Reference Mid Point ( Test Pin ) open=use internal bias point High = power saving standby mode (normally gnd) Ouput Driver Power(3.3V) Output Driver Ground Sampling Clock Input high = high impedance digital output (normally gnd) Digital Output Underflow Overflow Digital Substrate Bias Digital Ground Digital Power(3.3V) AINC REFMID ITEST STBY VDDR VSSR CKIN TRISTATE DO[9:0] UDF OVF VBBD VSSD VDDD 13 14 16 17 18 19 20 25 27~36 37 38 44 45,46 47,48 AI AB AB DI PP PG DI DI DO DO DO DG DG DP NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. SEC ASIC 9 / 11 ANALOG 10BIT 30MSPS ADC USER GUIDE BW1217X 1. Resolution Control. - Modular structure is the most important feature of BW1217X. - You can get any resolution you want by combining each primary module (MDAC + FLASH) without major circuit change. - It means you don't have to redesign the most difficult analog block for another resolution. - But this simple resolution control method has a limit up to 10bits, otherwise the internal op-amp must be redesigned. module ain sha mdac1 mdac2 flash1 flash2 flash3 dclogic 10bit 2. Speed Up - The initial target speed of BW1217X was 30MHz, but it proved to operate well at 35MHz or more due to a lot of design margin. 3. Input Range Variation. - The default of the input of this ADC is differential -1.0V ~ +1.0V. - The bias voltages of both AINT and AINC are 0.5V~2.5V, and their offset is 1.5V. - In order to change to another input voltage range, alter the voltage values of AINT and AINC after setting Reftop and Refbot to the maximum value of input range. - If you want single ended input, fix AINC to 1.5V as a ground and the internal input voltage level is V(aint)-1.5V. 4. Verilog Modeling - Verilog modeling needs 64bits for only one analog real signal. SEC ASIC 10 / 11 ANALOG 10BIT 30MSPS ADC FEEDBACK REQUEST BW1217X It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic cheking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise Ratio Pipeline Delay Digital Output Format (Provide detailed description & timing diagram) Min Typ Max Unit V V Bit V Vpp C LSB LSB mV mV MSPS mA mW dB CLK Remarks 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 11 / 11 ANALOG |
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