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| 10BIT 30MSPS ADC GENERAL DESCRIPTION The ADC1230X is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A converters (DACs), and subranging flash ADCs. The maximum conversion rate of ADC1230 is 30MSPS and supply voltage is 2.5V single. ADC1230X FEATURES Resolution : 10Bit Differential Linearity Error : 1.0 LSB Integral Linearity Error : 2.0 LSB Maximum Conversion Rate : 30MSPS Sample & Hold Function Implemented Low Power Consumption : 62.5mW(Typ) Power Supply : 2.5V Single Operation Temperature Range : 0~70C TYPICAL APPLICATIONS - CCD imaging processors Camcorders, scanners, and security cameras. - Read channel LSI HDD, DVD, and CD-ROM drives - IF and baseband signal digitizers FUNCTIONAL BLOCK DIAGRAM VDD25A1 VDD25A2 VBB25A1 VBB25A2 MDAC3 Flash3 VSS25A1 VSS25A2 AINT SHA AINC MDAC1 MDAC2 REFTOP REFBOT Flash1 Flash2 Flash4 STC Digital Correction Logic (DCL) EOC DO[9:0] ITEST STBY SPEEDUP Bias Current Generator Clock Generator CML Level Generator Ver 1.2 (Apr. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD CKIN CML 10BIT 30MSPS ADC CORE PIN DESCRIPTION NAME AINT AINC REFTOP REFBOT VDD25A1 VSS25A1 VBB25A1 ITEST STBY STC SPEEDUP CKIN CML DO[9:0] EOC VBB25A2 VSS25A2 VDD25A2 ADC1230X I/O TYPE AI AI AI AI AP AG AG AB DI DI DI DI AB DO DO DG DG DP I/O PAD piar50_abb piar50_abb pia_abb pia_abb vdd1t_abb vss1t_abb vbb_abb pia_abb picc_abb picc_abb picc_abb picc_abb pia_abb poa_abb poa_abb vbb_abb vdd1t_abb vss1t_abb PIN DESCRIPTION AAnalog Input + (Input Range : 0.7V ~ 1.9V) Analog Input : (DC=1.3V) Reference Top (1.6V) Reference Bottom(1.0V) Analog Power (2.5V) Analog Ground Analog Sub Bias Open=use internal bias point High=power saving standby mode (normally, gnd) Start of conversion signal (normally, high) Speed test pin (normally, gnd) Sampling Clock Input Internal Bias Point(Test Pin) Digital Output End of conversion signal Digital Sub Bias Digital Ground Digital Power I/O TYPE ABBR. AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground CORE CONFIGURATION VDD25A1 VDD25A2 VBB25A1 VBB25A2 VSS25A1 VSS25A2 EOC AINT ADC1230X AINC CKIN DO[9:0] SEC ASIC 2 / 12 SPEEDUP REFTOP REFBOT ITEST STBY CML STC ANALOG 10BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Storage Temperature Range ADC1230X Symbol VDD AIN CLK VOH, VOL Tstg 3.3 Value Unit V V V V C VSS to VDD VSS to VDD VSS to VDD -45 to 125 NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5K resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Supply Voltage Supply Voltage Difference Reference Input Voltage(Externally) Analog Input Voltage (+) Analog Input Voltage (-) Operating Temperature Symbol VDD25A1 - VSS25A1 VDD25A2 - VSS25A2 VDD25A1 - VDD25A2 REFTOP REFBOT AINT AINC Topr Min 2.3 -0.1 0.7 Typ 2.5 0.0 1.6 1.0 1.3 Max 2.7 0.1 1.9 Unit V V V V V 0 - 70 C NOTES 1. It is strongly recommended that all the supply pins (VDD25A1, VDD25A2) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 12 ANALOG 10BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Resolution Reference Current Differential Linearity Error Integral Linearity Error Bottom Offset Voltage Error Top Offset Voltage Error ADC1230X Symbol IREF DLE ILE EOB EOT Min - Typ 10 2 - Max 3 1.0 2.0 20 20 Unit Bits mA LSB LSB LSB LSB Conditions AINT : 0.7V~1.9V (Ramp Input) fc : 1MHz NOTES 1. Converter Specifications (unless otherwise specified) VDD25A1=2.5V VDD25A2=2.5V VSS25A1=GND VSS25A2=GND Ta=25C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Dynamic Supply Current Symbol fc Ivdd Min Typ 25 Max 30 30 Unit MSPS mA fc=30MHz (without system load) AINT = 1MHz fc = 30MHz Conditions Signal - to - Noise Ratio SNR 48 52 - dB SEC ASIC 4 / 12 ANALOG 10BIT 30MSPS ADC I/O CHART Index 0 1 2 *** 511 512 513 *** 1021 1022 1023 AINT Input (V) 0.7000 ~ 0.7012 0.7012 ~ 0.7023 0.7023 ~ 0.7035 *** 1.2988 ~ 1.3000 1.3000 ~ 1.3012 1.3012 ~ 1.3023 *** 1.8965 ~ 1.8977 1.8977 ~ 1.8988 1.8988 ~ 1.9000 1.3 1.3 1.3 1.3 1.3 1.3 AINC Input (V) 1.3 1.3 1.3 Digital Output 0000000000 0000000001 0000000010 *** 0111111111 1000000000 1000000001 *** 1111111101 1111111110 1111111111 ADC1230X 1LSB=1.172mV REFTOP=1.6V REFBOT=1.0V SEC ASIC 5 / 12 ANALOG 10BIT 30MSPS ADC TIMING DIAGRAM 1. Main Waveform A1 A2 A4 A6 ADC1230X AINT STC Pipeline Delay EOC DO[9:0] D1 D2 D4 D6 Output code of DO[9:0] is generated during STC (Start of Conversion) signal is just "HIGH". Otherwise, it keeps the current states. After STC goes "HIGH", the A/D converter requires the pipeline delay of 3 clock period to generate EOC signal and DO[9:0]. 2. STC and CKIN 8ns CKIN Tsafe 4ns 8ns Tsafe 4ns STC The STC signal is rising-edge triggered, and it should be changed during "Tsafe" region on CKIN . SEC ASIC 6 / 12 ANALOG 10BIT 30MSPS ADC CORE EVALUATION GUIDE ADC1230X 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor divider. Analog Input Clock Input AINC AINT GND CKIN SEC ASIC 1.6V 1.0V Reference Reference Top Bottom STC Input or 2.5V ADC1230X 2.5V REFTOP REFBOT VDD25A1 VSS25A1 GND VBB25A1 CML ITEST STBY STC GND GND GND BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing 2.5V VDD25A2 VSS25A2 DO[9:0] GND EOC VBB25A2 SPEEDUP 10-bit Digital Output NOTES : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 10uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED DIGITAL MUX CORE HOST DSP 7 / 12 ANALOG 10BIT 30MSPS ADC PACKAGE CONFIGURATION ADC1230X 1.6V 10u 10u 1.0V 0.1u 2.5V 10u 0.1u 0.1u 0.1u 1 2 3 4 5 6 7 8 9 0.1u 10 11 REFTOP REFTOP REFBOT REFBOT CML VDD25A1 VDD25A1 VBB25A1 VSS25A1 VSS25A1 AINT NC AINC NC SPEEDUP ITEST STBY VDD25A3 VSS25A3 CKIN NC NC NC NC VDD25A2 VDD25A2 VSS25A2 VSS25A2 VBB25A2 STC EOC NC NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 TRISTATE in 10-b ADC output STC in EOC out 0.1u 10u 2.5V Analog input 50 1K 0.1u 12 13 14 15 ADC1230X_top NC DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] NC 0.1u 2.5V 10u 0.1u 16 17 18 19 20 Clock in 50 21 22 23 24 TRISTATE : Test Pin No bias forcing, Remain floating NOTES 1. This information is for testing the provided test-chips of ADC1230X. SEC ASIC 8 / 12 ANALOG 10BIT 30MSPS ADC PACKAGE PIN DESCRIPTION NAME REFTOP REFBOT CML VDD25A1 VBB25A1 VSS25A1 AINT ADC1230X PIN NO. 1,2 3,4 5 6,7 8 9,10 11 I/O TYPE AI AI AB AP AG AG AI PIN DESCRIPTION External Reference Top Bias (1.6V) External Reference Bottom Bias (1.0V) Internal Bias Point (Test Pin) 2.5V Analog Power Analog Sub Bias Analog Ground Analog Input (+) Input Range : 0.7~1.9V Analog Input. (-) DC 1.3V Speed test pin. Tie to gnd (VSSA) open=use internal bias point High = power saving standby mode (normally gnd) Ouput Driver Power (2.5V) Output Driver Ground Sampling Clock Input high = high impedance digital output (normally gnd) 10bit Digitized Output End of conversion signal Start of conversion signal Digital Substrate Bias Digital Ground Digital Power (2.5V) AINC SPEEDUP ITEST STBY VDD25A3 VSS25A3 CKIN TRISTATE DO[9:0] EOC STC VBB25A2 VSS25A2 VDD25A2 13 15 16 17 18 19 20 25 27~36 42 43 44 45,46 47,48 AI DI AB DI PP PG DI DI DO DO DI DG DG DP NOTES 1. This information is for testing the provided test-chips of ADC1230X. 2.. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. SEC ASIC 9 / 12 ANALOG 10BIT 30MSPS ADC USER GUIDE 1. Input Range - If you want to using the single-ended input, you should use he input range as below. AINT : 0.7V ~ 1.9V AINC : 1.3V - If you want to using the differential input, you should use the input range as below. AINT : 1.0V ~ 1.6V AINC : 1.6V ~ 1.0V ADC1230X SEC ASIC 10 / 12 ANALOG 10BIT 30MSPS ADC PHANTOM CELL INFORMATION ADC1230X - Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user. VBB25A1 CKIN VBB25A2 VDD25A2 VDD25A2 VSS25A2 VBB25A2 DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] EOC STC VSS25A1 VBB25A1 VDD25A1 ADC1230X 10bit 30MSPS ADC SEC ASIC VDD25A1 VSS25A1 VBB25A1 VDD25A1 AINC AINT REFBOT CML REFTOP ITEST STBY SPEEDUP Pin Name VDD25A1 VSS25A1 VBB25A1 VDD25A2 VSS25A2 VBB25A2 AINT AINC CKIN REFTOP REFBOT CML ITEST STBY STC SPEEDUP EOC DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] Pin Usage External External External External External External External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal Pin Layout Guide - Maintain the large width of lines as far as the pads. - place the port positions to minimize the length of power lines. - Do not merge the analog powers with anoter power from other blocks. - Use good power and ground source on board. - Do not overlap with digtal lines. - Maintain the shotest path to pads. - Separate from all other analog signals - Maintain the larger width and the shorter length as far as the pads. - Separate from all other digital lines. - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um. 11 / 12 ANALOG 10BIT 30MSPS ADC FEEDBACK REQUEST ADC1230X It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise Ratio Pipeline Delay Digital Output Format (Provide detailed description & timing diagram) Min Typ Max Unit V V Bit V Vpp C LSB LSB mV mV MSPS mA mW dB CLK Remarks 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 12 / 12 ANALOG 10BIT 30MSPS ADC HISTORY CARD ADC1230X Version ver 1.0 ver 1.1 ver 1.2 Date 98.12.1 99.12.13 00.4.17 Original version published Pin/Port name change - STCB -> STC Modified Items Comments The operation is not changed Add the PHANTOM CELL INFORMATION (11/12) SEC ASIC ANALOG |
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