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ADS901
AD S 901 E
SBAS054A - MAY 2001
10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
q LOW POWER: 48mW at +3V q SUPPLY RANGE: +2.7V to +3.7V q ADJUSTABLE FULL SCALE RANGE WITH EXTERNAL REFERENCES q NO MISSING CODES q WIDEBAND TRACK/HOLD: 350MHz q POWER DOWN: 15mW q SSOP-28 PACKAGE
DESCRIPTION
The ADS901 is a high-speed pipelined analog-to-digital converter that operates from a +3V power supply. This complete converter includes a wide bandwidth track/hold and a 10-bit quantizer. The full scale input range is set by external references. The ADS901 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. The ADS901 is available in an SSOP-28 package.
APPLICATIONS
q q q q q BATTERY POWERED EQUIPMENT CAMCORDERS DIGITAL CAMERAS COMPUTER SCANNERS COMMUNICATIONS
ADS901
CLK
LVDD
Timing Circuitry
IN
T/H
Pipeline A/D
Error Correction Logic
3-State Outputs
10-Bit Digital Data
Reference Ladder
REFT CM REFB
Pwrdn
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V Logic VDD ............................................................................................. +6V Analog Input ............................................................................... +VS +0.3V Logic Input ................................................................................. +VS +0.3V Case Temperature ......................................................................... +100C Junction Temperature .................................................................... +150C Storage Temperature ..................................................................... +125C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 324 324 SPECIFIED TEMPERATURE RANGE -40C to +85C -40C to +85C PACKAGE MARKING ADS901E ADS901E ORDERING NUMBER(1) ADS901E ADS901E/1K TRANSPORT MEDIA Rail Tape and Reel
PRODUCT ADS901E ADS901E
PACKAGE SSOP-28 SSOP-28
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of "ADS901E/1K" will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
At TA = +25C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. ADS901E PARAMETER Resolution Specified Temperature Range ANALOG INPUT Specified Full Scale Input Range(1) Common-Mode Voltage (Midscale) Analog Input Bias Current Input Impedance DIGITAL INPUT Logic Family Convert Command (Start Conversion) CONVERSION CHARACTERISTICS Sample Rate Data Latency CONDITIONS TEMP MIN TYP 10 Ambient Air -40 1Vp-p 1.5 1 1.25 || 5 CMOS Compatible Rising Edge of Convert Clock Full 10k 5 20M Samples/s Clk Cyc +85 MAX UNITS Bits C V V A M || pF
Start Conversion
2
ADS901
SBAS054A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. ADS901E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz f = 9MHz No Missing Codes Integral Nonlinearity Error, f = 500kHz Spurious Free Dynamic Range(2) f = 500kHz (-1dBFS(3) input) f = 9MHz (-1dBFS input) Signal-to-Noise Ratio (SNR) Referred to Sinewave Input Signal f = 500kHz (-1dBFS input) f = 9MHz (-1dBFS input) Maximum SNR Referred to DC Full Scale Input Signal f = 9MHz (-1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (-1dBFS input) f = 3.58MHz (-1dBFS input) f = 9MHz (-1dBFS input) Effective Number of Bits(4) fIN = 3.58MHz Differential Gain Error NTSC, PAL Differential Phase Error NTSC, PAL Output Noise Input Grounded Aperture Delay Time Aperture Jitter Analog Input Bandwidth Small Signal -20dBFS Input Full Power 0dBFS Input Overvoltage Recovery Time(5) DIGITAL OUTPUTS Logic Family Logic Coding High Output Voltage, VOH Low Output Voltage, VOL 3-State Enable Time 3-State Disable Time Internal Pull-Down to Gnd Power-Down Enable Time Power-Down Disable Time Internal Pull-Down to Gnd ACCURACY Gain Error Input Offset(6) Power Supply Rejection (Gain) Power Supply Rejection (Offset) External REFT Voltage Range External REFB Voltage Range Reference Input Resistance POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Power Dissipation (Power Down) Thermal Resistance, JA 28-Lead SSOP CL = 15pF
Full Full Full Full Full Full Full Full
0.8 0.9 Guaranteed 3.5 50 49 53 53 62
1.0
LSB LSB LSB dBFS(3) dBFS dB dB dB dB dB dB Bits % degrees LSB rms ns ps rms MHz MHz ns
45
48
Full Full Full
45
50 50 49 8.0 2.3 1.0 0.2 3 7 350 100 2 CMOS Compatible Straight Offset Binary
+2.4 OE = L OE = H Pwrdn = L Pwrdn = H fS = 2.5MHz VS = +10% Full Full Full Full Full Full 2.5 0.4 56 68 2 1 4 +3.0 16 49 15 89 20 18 50 133 18 50
LVDD +0.4 40 10
V V ns ns k ns ns k %FS %FS dB dB V V k V mA mW mW C/W
REFB +0.5 0.8
VS-0.8 REFT -0.5
Operating Operating Operating Operating
Full Full Full Full
+2.7
+3.7 60
NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS is dB relative to full scale. (4) Based on (SINAD - 1.76)/6.02. (5) No "Rollover" of bits. (6) Offset Deviation from Ideal Negative Full Scale.
ADS901
SBAS054A
3
PIN CONFIGURATION
TOP VIEW SSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESIGNATOR +VS LVDD Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GND GND CLK OE Pwrdn +VS GND GND LpBy REFT NC REFB LnBy CM IN +VS DESCRIPTION Analog Supply Output Logic Driver Supply Voltage Data Bit 10 (D0) (LSB) Data Bit 9 (D1) Data Bit 8 (D2) Data Bit 7 (D3) Data Bit 6 (D4) Data Bit 5 (D5) Data Bit 4 (D6) Data Bit 3 (D7) Data Bit 2 (D8) Data Bit 1 (D9) (MSB) Analog Ground Analog Ground Convert Clock Input Output Enable, Active Low Power Down Pin Analog Supply Analog Ground Analog Ground Positive Ladder Bypass Top Reference Input No Connection Bottom Reference Input Negative Ladder Bypass Common-Mode Voltage Output Analog Input Analog Supply
+VS LVDD (LSB) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (MSB) Bit 1 GND GND
1 2 3 4 5 6 7 ADS901 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
+VS IN CM LnBy REFB NC REFT LpBy GND GND +VS Pwrdn OE CLK
TIMING DIAGRAM
N+1 Analog In N tD Clock tCONV
N+2 N+3
N+4 N+5 tL tH N+6
N+7
5 Clock Cycles t2 Data Out N-5 N-4 N-3 N-2 N-1 N t1 N+1 N+2
Data Invalid
SYMBOL tCONV tL tH tD t1 t2
DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max
MIN 50 24 24 3.9
TYP
MAX 100s
UNITS ns ns ns ns ns ns
25 25 3 12
4
ADS901
SBAS054A
TYPICAL CHARACTERISTICS
At TA = +25C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
SPECTRAL PERFORMANCE 0 fIN = 500kHz -20
Amplitude (dB) Amplitude (dB)
SPECTRAL PERFORMANCE 0 fIN = 3.58MHz -20
-40
-40
-60
-60
-80
-80
-100 0 2 4 6 8 10 Frequency (MHz)
-100 0 2 4 6 8 10 Frequency (MHz)
SPECTRAL PERFORMANCE 0 fIN = 9MHz -20
Amplitude (dB)
TWO-TONE INTERMODULATION 0 f1 = 4.5MHz f2 = 5.0MHz
-20
-40
Amplitude (dB)
0 2 4 6 8 10
-40
-60
-60
-80
-80
-100 Frequency (MHz)
-100 0 2.5 5 Frequency (MHz) 7.5 10
DIFFERENTIAL LINEARITY ERROR 2 fIN = 500kHz 1 1
DLE (LSB)
DIFFERENTIAL LINEARITY ERROR 2 fIN = 9MHz
DLE (LSB)
0
0
-1
-1
-2 0 256 512 Output Code 768 1024
-2 0 256 512 Output Code 768 1024
ADS901
SBAS054A
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
INTEGRAL LINEARITY ERROR 10 fIN = 500kHz
SWEPT POWER SFDR 100
80
SFDR (dBc, dBFS)
5
dBFS 60
ILE (LSB)
0
40
-5
20
dBc
-10 0 256 512 Output Code 768 1024
0 -60 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY 54 SNR 53
Amplitude (dB)
UNDERSAMPLING 0 -20 -40 -60 -80 -100 fIN = 20MHz fS = 16MHz
SFDR (dBFS), SNR (dB)
52 SFDR 51
50 0.1 1 Frequency (MHz) 10
-120 0 16.2 32.4 48.6 64.8 81.0 Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.9 fIN = 9MHz 54 SFDR (dBFS) DLE (LSB) 0.8 56
SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE
fIN = 500kHz
52 fIN = 9MHz 50
0.7 fIN = 500kHz 0.6 -50 -25 0 25 50 75 100 Temperature (C)
48 -50 -25 0 25 50 75 100 Temperature (C)
6
ADS901
SBAS054A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS, Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
SIGNAL-TO-NOISE RATIO vs TEMPERATURE 55 50
POWER DISSIPATION vs TEMPERATURE
fIN = 500kHz 54
SNR (dB)
Power Dissipation (mW)
49
48
fIN = 9MHz 53
47
46
52 -50 -25 0 25 50 75 100 Temperature (C)
45 -50 -25 0 25 50 75 100 Temperature (C)
GAIN ERROR vs TEMPERATURE 2.8
OFFSET ERROR vs TEMPERATURE 0.6
Offset Error (% FS)
-50 -25 0 25 50 75 100
2.7
Gain Error (%FS)
0.5
2.6
0.4
2.5
2.4 Temperature (C)
0.3 -50 -25 0 25 50 75 100 Temperature (C)
OUTPUT NOISE HISTOGRAM (DC Input) 8 55
POWER DISSIPATION vs SAMPLING FREQUENCY
6
Counts (x105)
Power Dissipation (mW)
50
4
45
2
40
0 N-2 N-1 N Output Code N+1 N+2
35 1 10 Frequency (MHz) 100
ADS901
SBAS054A
7
THEORY OF OPERATION
The ADS901 is a high speed sampling analog-to-digital converter that utilizes a pipeline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The differential track/hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, 1 and 2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, 1, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track/hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track/hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. Consequently, the input signal-to-noise performance. Other parameters such as small-signal and full-power bandwidth, and wideband noise are also defined in this stage.
To accommodate a bipolar signal swing, the ADS901 operates with a common-mode voltage (VCM) which is derived from the external references. Due to the symmetric resistor ladder inside the ADS901, the VCM is situated between the top and bottom reference voltage. Equation (1) can be used for calculating the common-mode voltage level. VCM = (REFT +REFB)/2 (1)
There is a 5.0 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all "1's" at the output. The digital outputs of the ADS901 can be set to a high impedance state by driving the three-state (pin 16) with a logic "HI". Normal operation is achieved with pin 16 "LO" or Floating due to internal pull-down resistors. This function is provided for testability purposes but is not recommended to be used dynamically.
APPLICATIONS
SIGNAL SWING AND COMMON-MODE CONSIDERATIONS The ADS901 is designed to operate on a +3V single supply voltage. The nominal input signal swing is 1Vp-p, situated between +1V and +2V. This means that the signal swings 0.5V around a common-mode voltage of +1.5V, which is half the supply voltage (VCM = VS/2). In some applications it might be advantageous to increase the input signal swing. This will improve the achievable signal-to-noise performance. However, considerations should be made to keep the signal swing within the linear range of operation of the driving circuitry to avoid any excessive distortion. In extreme situations the performance of the converter will start to degrade due to variations of the input's switch onresistance over the input voltage. Therefore, the signal swing should remain approximately 0.5V away from each rail during normal operation. DRIVING THE ANALOG INPUTS AC-COUPLED DRIVER Figure 2 shows an example of an ac-coupled, single-ended interface circuit using a high-speed op amp that operates on
Op Amp Bias 1
VCM 1 CH 2
CI IN IN 1 1 2 CI CH 1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock 1 2 1 VCM 1 1
OUT OUT
2
FIGURE 1. Input Track/Hold Configuration with Timing Signals. The pipelined quantizer architecture has 9 stages with each stage containing a two-bit quantizer and a two bit digitalto-analog converter, as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the sub-clock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique provides the ADS901 with excellent differential linearity and guarantees no missing codes at the 10-bit level.
+3V +5V VIN A1 R1 1k VCM 402 C1 R1 50 0.1F IN ADS901 CM
-5V 402
0.1F
FIGURE 2. AC-Coupled, Single-Ended Interface Circuit. 8
ADS901
SBAS054A
dual supplies (OPA650, OPA658). The mid-point reference voltage, VCM, biases the bipolar, ground-referenced input signal. The capacitor C1 and resistor R1 form a high-pass filter with the -3dB frequency set at f-3dB = 1/(2 R1 C1) (2)
The values for C1 and R1 are not critical in most applications and can be set freely. The values shown correspond to a frequency of 1.6kHz. Figure 3 depicts a circuit that can be used in single-supply applications. The mid-reference voltage biases the op amp up to the appropriate common-mode voltage, for example VCM = +1.5V. With the use of capacitor CG the DC gain for the non-inverting op amp input is set to +1V/V. As a result the transfer function is modified to VOUT = VIN {(1 + RF/RG) + VCM} (3)
on a +3V supply voltage. The OPA632 provides excellent performance in this demanding application. Its wide input and output voltage ranges, an low distortion, supports the ADS901 well. The OPA632 is configured for a gain of +2. The 374 and 2.26k resistors at the input level-shift VIN so that VOUT is within the allowed output voltage range when VIN = 0. The input impedance of the driver circuit is set to match to a 50 source impedance. The input levelshifting was designed that VIN can be between 0V and 5V, while delivering an output voltage of 1V to 2V into the ADS901. Both the OPA632 and ADS901 have a powerdown function pin with the same polarity for those systems the need to conserve power. EXTERNAL REFERENCE The ADS901 requires external references on pin 22 (REFT) and 24 (REFB). Internally those pins are connected through a resistor ladder, which has a nominal resistance of 4k (15%). In order to establish a correct voltage drop across the ladder the external reference circuit must be able to typically supply 250A of current. With this current the full-scale input range of the ADS901 is set between +1V and +2V, or 1Vp-p. In general, the voltage drop across REFT and REFB determines the input full-scale range (FSR) of the ADS901. Equation (4) can be used to calculate the span. FSR = REFT - REFB (4) Depending on the application, several options are possible to supply the external reference voltages to the ADS901 without degrading the typical performance.
Again, the input coupling capacitor C1 and resistor R1 form a high-pass filter. At the same time the input impedance is defined by R1. Resistor RS isolates the op amp's output from the capacitive load to avoid gain peaking or even oscillation. It can also be used to establish a defined bandwidth to reduce the wideband noise. The recommended value is usually between 10 and 100. DC-COUPLED INTERFACE CIRCUIT Many systems are now requiring +3V single supply capability of both the A/D converter and its driver. Figure 4 shows an example for DC-coupled configuration operating solely
+5V C1 0.1F VIN OPA680 R1 1k RF 402 RG 402 CG 0.1F 22pF VCM RS 50 IN
+3V
ADS901 CM
0.1F
402
FIGURE 3. Interface Circuit. Example using the voltage feedback amplifier OPA680.
+3V 2.26k 374 VIN
OPA632
Disable
+3V Pwrdn ADS901 10-Bit 20Msps 22pF
DIS
100
57.6
562
750
FIGURE 4. DC-Coupled Interface Circuit for +3V Single-Supply Operation.
ADS901
SBAS054A
9
LOW-COST REFERENCE SOLUTION The easiest way to achieve the required reference voltages is to place the reference ladder of the ADS901 between the supply rails, as shown in Figure 5. Two additional resistors (RT, RB) are necessary to set the correct current through the ladder. However depending on the desired full-scale swing and supply voltage different resistor values might be selected. The trade-offs, when selecting this reference circuit, are variations in the reference voltages due to component tolerances and power supply variations. In any case, it is recommended to bypass the reference ladder with at least 0.1F ceramic capacitors, as shown in Figure 5. The capacitors serve a dual purpose. They will bypass most of the high frequency transient noise which results from feedthrough of the clock and switching noise from the T/H stages. Secondly, they serve as a charge reservoir to supply instantaneous current to internal nodes.
STRAIGHT OFFSET BINARY (SOB) PIN 12 FLOATING or LO 1111111111 1111111111 1111111110 1110000000 1100000000 1010000000 1000000001 1000000000 0111111111 0110000000 0100000000 0010000000 0000000001 0000000000
PRECISE REFERENCE SOLUTION For those applications requiring a higher level of dc accuracy and drift, a reference circuit with a precision reference element might be used (see Figure 6). A stable +1.2V reference voltage is established by a two terminal bandgap reference diode, the REF1004-1.2. Using a general-purpose single-supply dual operational amplifier (A1), like an OPA2237, OPA2234 or OPA2343, the two required reference voltages for the ADS901 can be generated by setting each op amp to the appropriate gain; for example: set REFT to +2V and REFB to +1V. CLOCK INPUT The clock input of the ADS901 is designed to accommodate either +5V or +3V CMOS logic levels. To drive the clock input with a minimum amount of duty cycle variation and support maximum sampling rates (20Msps), high speed or advanced CMOS logic should be used (HC/HCT, AC/ACT). When digitizing at high sampling rates, a 50% duty cycle clock with fast rise and fall times (2ns or less) are recommended to meet the rated performance specifications. However, the ADS901 performance is tolerant to duty cycle variations of as much as 10% without degradation. For applications operating with input frequencies up to Nyquist or undersampling applications, special consideration must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limitation to achieving good SNR performance. Equation (5) shows the relationship between aperture jitter, input frequency and the signal-to-noise ratio: SNR = 20log10 [1/(2 fIN tA)] (5)
SINGLE-ENDED INPUT +FS (IN = +2V) +FS -1LSB +FS -2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN +1.5V) -1LSB -1/4 Full Scale -1/2 Full Scale -3/4 Full Scale -FS +1LSB -FS (IN = +1V)
TABLE I. Coding Table for the ADS901.
For example, with a 10MHz full-scale input signal and an aperture jitter of tA = 20ps, the SNR is clock jitter limited to 58dB.
+3V 10F 0.1F RT 4k +VS 0.1F VIN 1k ADS901 0.1F CM 1k LnBy 0.1F 1k REFB +1V 0.1F RB 4k IN 1k 1k LpBy 0.1F REFT +2V 0.1F
FIGURE 5. Low Cost Solution to Supply External Reference Voltages and Recommended Reference Bypassing.
10
ADS901
SBAS054A
+VS 10 +VS 1/2 A1 RF1 10k RG1 REF1004 +1.2V 5k
+VS
Top Reference (REFT)
+LVDD
ADS901
Digital Output Stage
FIGURE 7. Independent Supply Connection for Output Stage.
3k 1/2 A1 10 Bottom Reference (REFB)
RF2
During power-down the digital outputs are set in 3-state. With the clock applied, the converter does not accurately process the sampled signal. After removing the power-down condition the output data from the following 5 clock cycles is invalid (data latency). DECOUPLING AND GROUNDING CONSIDERATIONS The ADS901 converter have several supply pins, one of which is dedicated to supply only the output driver. The remaining supply pins are not, as is often the case, divided into analog and digital supply pins since they are internally connected on the chip. For this reason it is recommended to treat the converter as an analog component and to power it from the analog supply only. Digital supply lines often carry high levels of noise which can couple back into the converter and limit the achievable performance. Because of the pipeline architecture, the converter also generates high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 8 shows the recommended decoupling scheme for the analog supplies. In most cases 0.1F ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore they should be located as close to the supply pins as possible.
RG2 A1 = OPA2237 or Equivalent.
FIGURE 6. Precise Solution to Supply External Reference Voltages. DIGITAL OUTPUTS There is a 5.0 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all "1's" at the output. The digital outputs of the ADS901 can be set to a high impedance state by driving the three-state (pin 16) with a logic "HI". Normal operation is achieved with pin 16 "LO" or Floating due to internal pull-down resistors. This function is provided for testability purposes but is not recommended to be used dynamically. The digital outputs of the ADS901 are standard CMOS stages and designed to be compatible to both high speed TTL and CMOS logic families. The logic thresholds are for low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows the ADS901 to directly interface to 3V-logic. The digital outputs of the ADS901 use a dedicated digital supply pin (pin 2, LVDD). By adjusting the voltage on LVDD, the digital output levels will vary respectively. In any case, it is recommended to limit the fan-out to one, to keep the capacitive loading on the data lines below the specified 15pF. If necessary, external buffers or latches may be used to provide the added benefit of isolating the A/D converter from any digital activities on the bus coupling back high frequency noise and degrading the performance. POWER-DOWN MODE The ADS901's low power consumption can be further reduced by initiating a power down mode. For this, the Pwrdn-Pin (Pin 17) must be tied to a logic "High" reducing the current drawn from the supply by approximately 70%. In normal operation the power-down mode is disabled by an internal pull-down resistor (50k).
ADS901 +VS 1 GND 13 14 +VS 18 GND 19 20 +VS 28
0.1F
0.1F
0.1F
FIGURE 8. Recommended Bypassing for Analog Supply Pins.
ADS901
SBAS054A
11
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Copyright (c) 2001, Texas Instruments Incorporated

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