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CY62128B MoBLTM
128K x 8 Static RAM
1CY62128B MoBLTM
Features
* 4.5V-5.5V operation * CMOS for optimum speed/power * Low active power (70 ns, LL version) -- 82.5 mW (max.) (15 mA) * Low standby power (70 ns, LL version) -- 110 W (max.) (15 A) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options
and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages.
Functional Description
The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE),
Logic Block Diagram Pin Configurations
Top View SOIC
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O 0 I/O 1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5
POWER DOWN
512x 256x 8 ARRAY
CE1 CE2 WE OE
COLUMN DECODER A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
I/O 6 I/O 7 62128-1
1 2 3 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GN GND 16 G gnc g
NC A16 A14 A12
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V CC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
A16 VCC
A15 CE2 WE A13 A8 A9 A11
A12 A14
A7
A4 A5 A6
NC
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Reverse TSOP I Top View (not to scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A11 A2 A9 A1 A8 A13 A0 I/O0 WE I/O1 CE2 A15 I/O2 GND VCC NC I/O3 A16 I/O4 A14 I/O5 A12 I/O6 A7 I/O7 A6 CE1 A5 A10 A4 OE
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 6 I/O I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 March 29, 2001
CY62128B MoBLTM
Selection Guide
CY62128B-55 CY62128B-70 Maximum Access Time Maximum Operating Current (ICC) Maximum CMOS Standby Current (ISB2) Industrial Commericial Industrial Commericial LL LL LL LL 55 20 20 15 15 70 15 15 15 15 Unit ns mA mA A A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] .................................-0.5V to VCC + 0.5V
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature.
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Industrial Commercial Ambient Temperature[2] -40C to +85C 0C to +70C V 5V 10% 5V 10%
2
CY62128B MoBLTM
Electrical Characteristics Over the Operating Range
62128B-55 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 VIH or CE2 < VIL, VIN VIH or VIN VIL, f = fMAX Max. VCC, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f = 0 VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 VIH or CE2 < VIL, VIN VIH or VIN VIL, f = fMAX Max. VCC, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f = 0 Ind'l LL 7.5 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 20 6 2.2 -0.3 -1 -1 Typ.
[3]
62128B-70 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 15 Typ.[3] Max. Unit V V V V A A mA mA
Max.
ISB1
Ind'l
LL
0.1
2
0.1
1
mA
ISB2
Automatic CE Power-Down Current --CMOS Inputs
Ind'l
LL
2.5
15
2.5
15
A
ICC
VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs
Com
LL
7.5
20
6
15
mA
ISB1
Com
LL
0.1
2
0.1
1
mA
ISB2
Automatic CE Power-Down Current --CMOS Inputs
Com
LL
2.5
15
2.5
15
A
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 9 Unit pF pF
Notes: 3. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25C, and tAA = 70 ns 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.
3
CY62128B MoBLTM
AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 990 R1 1800 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 990 GND Rise TIme: 1 V/ns VCC ALL INPUT PULSES 90% 10% 90% 10%
Fall TIme: 1 V/ns
THEVENIN EQUIVALENT 639 1.77V OUTPUT
Switching Characteristics[6] Over the Operating Range
62128B-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7, 8] Z[8] 5 20 0 55 55 45 45 0 0 45 25 0 5 20 70 60 60 0 0 50 30 0 5 25 0 70 CE1 LOW to Low Z, CE2 HIGH to Low 0 20 5 25 5 55 20 0 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 62128B-70 Min. Max. Unit
CE1 HIGH to High Z, CE2 LOW to High Z[7, 8] CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down
[9]
Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7, 8]
Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
CY62128B MoBLTM
Data Retention Characteristics (Over the Operating Range for "LL" version only)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Ind.'l LL VCC = VDR = 3.0V, CE VCC - 0.3V, VIN VCC - 0.3V or, VIN 0.3V VCC = VDR = 3.0V, CE VCC - 0.3V, VIN VCC - 0.3V or, VIN 0.3V 0 70 Conditions[10] Min. 2.0 1.5 15 Typ. Max. Unit V A
ICCDR
Data Retention Current Com.
LL
1.5
15
A
tCDR[3] tR[3]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Switching Waveforms
Read Cycle No.1[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
DATA OUT
Notes: 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
5
CY62128B MoBLTM
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[14, 15]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD
Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state 16. During this period the I/Os are in the output state and input signals should not be applied..
6
CY62128B MoBLTM
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[14, 15]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATAI/O NOTE 16 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
7
CY62128B MoBLTM
Ordering Information
Speed (ns) 55 Ordering Code CY62128BLL-55SI CY62128BLL-55SC CY62128BLL-55ZI CY62128BLL-55ZC CY62128BLL-55ZAI CY62128BLL-55ZAC CY62128BLL-70ZRI CY62128BLL-70ZRC 70 CY62128BLL-70SI CY62128BLL-70SC CY62128BLL-70ZI CY62128BLL-70ZC CY62128BLL-70ZAI CY62128BLL-70ZAC CY62128BLL-70ZRI CY62128BLL-70ZRC Document #: 38-00524-*F Package Name S34 S34 Z32 Z32 ZA32 ZA32 ZR32 ZR32 S34 S34 Z32 Z32 ZA32 ZA32 ZR32 ZR32 Package Type 32-Lead 450-Mil SOIC 32-Lead 450-Mil SOIC 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead STSOP Type I 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I 32-Lead Reverse TSOP Type I 32-Lead 450-Mil SOICI 32-Lead 450-Mil SOIC I 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead STSOP Type I 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I 32-Lead Reverse TSOP Type I Operating Range Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial
8
CY62128B MoBLTM
Package Diagrams
32-Lead (450 Mil) Molded SOIC S34
51-85081-A
32-Lead (450 Mil) Molded SOIC S34
51-85081-A
9
CY62128B MoBLTM
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-C
10
CY62128B MoBLTM
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-B
11
CY62128B MoBLTM
Package Diagrams (continued)
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-B
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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