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WF128K16, WF256K16-XCX5 5V FLASH MODULE
FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns s 40 pin Ceramic DIP (Package 303) s Organized as 128Kx16 and 256Kx16 s Sector Architecture * 8 equal size sectors of 16KBytes each per chip * Any combination of sectors can be concurrently erased. Also supports full chip erase s 100,000 Erase/Program Cycles Minimum (0C to 70C) s Data Retention, 10 Years at 125C s Commercial, Industrial and Military Temperature Ranges s 5 Volt Programming; 5V 10% Supply s Low Power CMOS s Embedded Erase and Program Algorithms s TTL Compatible Inputs and CMOS Outputs s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request.
PRELIMINARY *
FIG. 1
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PIN CONFIGURATION AND BLOCK DIAGRAM TOP VIEW
CS2*/NC CS1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE
PIN DESCRIPTION
VCC WE A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A0-16 I/O0-15 CS1-2 OE WE VCC GND
Address Inputs Data Input/Output Chip Selects Output Enable Write Enable +5.0V Power Ground
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BLOCK DIAGRAM FOR WF256K16-XCX5
I/O0-7 WE OE A0-16 I/O8-15
FLASH MODULES
* CS2 for 256Kx16 and NC for 128Kx16
BLOCK DIAGRAM FOR WF128K16-XCX5
I/O0-7 WE OE A0-16 I/O8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS1 (1) CS2
(1)
CS1
NOTE: 1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the device. CS1 and CS2 must not be enabled at the same time.
October 1998
1
White Microelectronics * Phoenix, AZ * (602) 437-1520
WF128K16, WF256K16-XCX5
ABSOLUTE MAXIMUM RATINGS (1)
Parameter Operating Temperature Supply Voltage Range (VCC) Signal voltage range (any pin except A9) (2) Storage Temperature Range Lead Temperature (soldering, 10 seconds) Data Retention Mil Temp Endurance (write/erase cycles) Mil Temp A9 Voltage for sector protect (VID) (3) -55 to +125 -2.0 to +7.0 -2.0 to +7.0 -65 to +150 +300 10 years 10,000 cycles min. -2.0 to +14.0 V Unit C V V C C Test OE capacitance WE capacitance CS capacitance I/O0-7 capacitance Address capacitance
CAPACITANCE (TA = 25C)
Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 50 50 30 30 50 Unit pF pF pF pF
pF
This parameter is guaranteed by design but not tested.
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) A9 Voltage for Sector Protect Symbol VCC VIH VIL TA TA VID Min 4.5 2.0 -0.5 -55 -40 11.5 Max 5.5 VCC + 0.3 +0.8 +125 +85 12.5 Unit V V V C C V
DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS = VIL, OE = VIH CS = VIL, OE = VIH VCC = 5.5, CS = VIH, f = 5MHz IOL = 12.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 0.85xVcc VCC -0.4 3.2 128K x 16 Min Max 10 10 70 100 6 0.45 0.85xVcc VCC -0.4 3.2 256K x 16 Min Max 10 10 80 110 8 0.45 A A mA mA mA V V V V Unit
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FLASH MODULES
VCC Active Current for Program or Erase (2) VCC Standby Current Output Low Voltage Output High Voltage Output High Voltage Low VCC Lock Out Voltage
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Microelectronics * Phoenix, AZ * (602) 437-1520
2
WF128K16, WF256K16-XCX5
PRINCIPLES OF OPERATION
The following principles of operation of the WF128K16-XCX5 and WF256K16-XCX5 are applicable to each 128K x 8 memory chip inside the MCM. Programming of the device is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell margin. Sectors can be programmed and verified in less than 0.3 seconds. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire memory is typically erased and verified in three seconds (including pre-programming).
WRITE
Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the commands, along with address and data information needed to execute the command. The command register is written by bringing Write-Enable to a logic-low level (VIL), while Chip-Select is low and OE is at VIH. Addresses are latched on the falling edge of the Write-Enable while data is latched on the rising edge of the WE pulse. Standard microprocessor write timings are used. Refer to AC Program characteristics, Figures 4 and 7.
BUS OPERATIONS READ
The device has two control functions, both of which must be logically active, to obtain data at the outputs. Chip-Select (CS) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins. Figure 3 illustrates read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic-high level (VIH), output from the device is disabled. Output pins are placed in a high impedance state.
STANDBY MODE
The device has two standby modes, a CMOS standby mode (CS input held at VCC + 0.5V), and a TTL standby mode (CS is held VIH). In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed.
Operation Read Standby Output Disable Write Enable Sector Protect Verify Sector Protect
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FLASH MODULES
TABLE 1 - BUS OPERATIONS
CS L H L L L L OE L X H H VID L WE H X H L L H A0 A0 X X A0 X L A1 A1 X X A1 X H A9 A9 X X A9 VID VID I/O DOUT HIGH Z HIGH Z DIN X Code
3
White Microelectronics * Phoenix, AZ * (602) 437-1520
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Symbol Min Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (min) Chip and Sector Erase Time Read Recovery Time Before Write VCC Setup Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (1) 1. For Toggle and Data Polling. tOES tOEH 0 10 tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tCH tWPH 50 0 25 0 25 0 40 0 20 14 2.2 0 50 12.5 0 10 60 -50 Max -60 Min 60 0 30 0 30 0 45 0 20 14 2.2 0 50 12.5 0 10 60 Max Min 70 0 35 0 30 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -70 Max -90 Min 90 0 45 0 45 0 45 0 20 14 2.2 0 50 12.5 0 10 60 Max -120 Min 120 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 0 10 60 Max -150 Min 150 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 60 Max ns ns ns ns ns ns ns ns ns s sec ns s sec ns ns Unit
AC CHARACTERISTICS - READ ONLY OPERATIONS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Read Cycle Time Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 50 50 50 25 20 20 0 -50 Max Min 60 60 60 30 20 20 0 -60 Max 70 70 70 35 20 20 0 -70 Min Max 90 90 90 40 25 25 0 -90 Min Max -120 Min 120 120 120 50 30 30 0 Max -150 Min 150 150 150 55 35 35 Max ns ns ns ns ns ns ns Unit
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FLASH MODULES
Address Access Time Chip Select Access Time OE to Output Valid Chip Select to Output High Z (1) OE High to Output High Z (1) Output Hold from Address, CS or OE Change, whichever is first 1. Guaranteed by design, not tested.
White Microelectronics * Phoenix, AZ * (602) 437-1520
4
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Write Cycle Time WE Setup Time CS Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time WE Hold from WE High CS Pulse Width High Duration of Programming Operation Duration of Erase Operation Read Recovery before Write Chip Programming Time Symbol tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tWH tCPH 50 0 25 0 25 0 40 0 20 14 2.2 0 12.5 60 -50 Min Max Min 60 0 30 0 30 0 45 0 20 14 2.2 0 12.5 60 -60 Max 70 0 35 0 30 0 45 0 20 14 2.2 0 12.5 60 -70 Min Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 12.5 60 -90 Max -120 Min 120 0 50 0 50 0 50 0 20 14 2.2 0 12.5 60 Max -150 Min 150 0 50 0 50 0 50 0 20 14 2.2 0 12.5 60 Max ns ns ns ns ns ns ns ns ns s sec ns sec Unit
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FLASH MODULES
FIG. 2
AC TEST CIRCUIT
Current Source I OL
AC TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level
D.U.T. VZ
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
1.5V
Output Timing Reference Level
C eff = 50 pf
(Bipolar Supply)
I OH Current Source
NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
5
White Microelectronics * Phoenix, AZ * (602) 437-1520
WF128K16, WF256K16-XCX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
tDF
tOH
Addresses Stable
tRC
tOE
WE
OE
Addresses
White Microelectronics * Phoenix, AZ * (602) 437-1520
6
Outputs
CS
High Z
7
FLASH MODULES
tACC
tCE
Output Valid
High Z
WF128K16, WF256K16-XCX5
FIG. 4
AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
tOH tDF tRC
tOE
PA
Data Polling
tAH
tWHWH1
PA
tDH
PD
D7
DOUT
tCE
tWPH
7
A0A0H
tAS
FLASH MODULES
5555H
tGHWL
tWC
tWP
tCS
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed. 3. D7 is the output of the complement of the data written (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
Addresses
WE
OE
CS
tDS
7
White Microelectronics * Phoenix, AZ * (602) 437-1520
5.0 V
Data
WF128K16, WF256K16-XCX5
FIG. 5
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
SA
2AAAH
5555H
5555H
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FLASH MODULES
NOTES: 1. SA is the sector address for Sector Erase.
2AAAH
5555H
tWP
AAAAH tDS
tWPH
tAS
tGHWL
tCS
tDH
5555H
tAH
8080H
AAAAH
5555H
1010H/3030H
Addresses
WE
OE
CS
Data
White Microelectronics * Phoenix, AZ * (602) 437-1520
8
VCC
tVCS
FIG. 6
CS tDF tOE
tCH
OE tOEH
AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
WE tCE
FLASH MODULES
9
I/O7 and I/O15 I/O7 and I/O15 tWHWH 1 or 2 I/O0-6 and I/O8-14 I/O0-6 and I/O8-14 Invalid tOE
tOH High Z I/O7 and I/O15 Valid Data
Data
WF128K16, WF256K16-XCX5
I/O0-15 Valid Data
White Microelectronics * Phoenix, AZ * (602) 437-1520
7
WF128K16, WF256K16-XCX5
FIG. 7
AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
PA
Data Polling
tAH
tWHWH1
PA
tAS
tGHEL
tCP
tCPH
tDH A0H
5555H
tWS
WE
OE
Addresses
CS
tDS
7
FLASH MODULES
White Microelectronics * Phoenix, AZ * (602) 437-1520
tWC
PD
D7
DOUT
NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
10
5.0 V
Data
WF128K16, WF256K16-XCX5
PACKAGE 303:
40 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
51.3 (2.020) 0.5 (0.020)
15.1 (0.595) 0.25 (0.010) 7.2 (0.285) 0.8 (0.030) PIN 1 IDENTIFIER 3.2 (0.125) MIN 0.94 (0.037) 0.25 (0.010) 2.5 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.5 (0.018) 0.05 (0.002) 0.25 (0.010) 0.05 (0.002) 15.25 (0.600) 0.25 (0.010)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION W F XXXK16 - XXX C X 5 X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: Q = Compliant M = Military Screened I = Industrial C = Commercial PACKAGE TYPE: C = 40 Pin Ceramic 0.600" DIP (Package 303) ACCESS TIME (ns) ORGANIZATION, 128K x 16 or 256K x 16 Flash PROM WHITE MICROELECTRONICS -55C to 125C -40C to +85C 0 to +70C
7
FLASH MODULES
11
White Microelectronics * Phoenix, AZ * (602) 437-1520

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