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HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix HY5W2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It is organized as 4banks of 2,097,152x16. The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.
FEATURES
* * * * * * Standard SDRAM Protocol Internal 4bank operation Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V LVTTL compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features ( HY5W26CF / HY57W281620HCT series can't support these features) - PASR(Partial Array Self Refresh) - TCSR(Temperature Compensated Self Refresh) - Deep Power Down Mode CAS latency of 1, 2, or 3 Packages : 54ball, 0.8mm pitch FBGA / 54pin, TSOP -25 ~ 85C Operation
* * *
128M SDRAM ODERING INFORMATION
Part Number
HY5W2A6C(L/S)F-H HY5W26CF-H HY57W2A1620HC(L/S)T-H HY57W281620HCT-H HY5W2A6C(L/S)F-P HY5W26CF-P HY57W2A1620HC(L/S)T-P HY57W281620HCT-P HY5W2A6C(L/S)F-S HY5W26CF-S HY57W2A1620HC(L/S)T-S HY57W281620HCT-S HHY5W2A6C(L/S)F-B HY5W26CF-B HY57W2A1620HC(L/S)T-B HY57W281620HCT-B
Clock CAS Frequency Latency
133MHz 3
Organization
4banks x 2Mb x 16
Interface
LVTTL
Package
100MHz
2
4banks x 2Mb x 16
LVTTL 54ball FBGA (HY5xxxxxxF) 54pin TSOP-II (HY5xxxxxxT)
100MHz
3
4banks x 2Mb x 16
LVTTL
66Mhz
2
4banks x 2Mb x 16
LVTTL
* HY5xxxxxx-B Series can support 40Mhz CL1 and 33Mhz CL1.
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.3 / Dec. 01
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT BALL CONFIGURATION
9 8 7 3 2 1
A B C D E F G H J < Bottom View >
1 VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 A B C D E F G H J 7 VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD
54 Ball FBGA 0.8 mm Ball Pitch
< Top View > Rev. 1.3 / Dec. 01
3
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT BALL DESCRIPTION
BALL OUT F2 F3 SYMBOL CLK CKE TYPE INPUT INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask:Controls output buffers in read mode and masks input data in write mode Data Input/Output:Multiplexed data input/output pin
G9 G7,G8
CS BA0, BA1
INPUT INPUT
H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2 F8, F7, F9 F1, E8 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A9, E7, J9, A1, E3, J1 A7, B3, C7, D3, A3, B7, C3, D7 E2, G1
A0 ~ A11
INPUT
RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15
INPUT INPUT I/O
VDD/VSS VDDQ/ VSSQ NC
SUPPLY SUPPLY -
Power supply for internal circuits Power supply for output buffers No connection
Note. Please find HY5xxxxxxT Series for standard 54TSOP-II pin configuration & description.
Rev. 1.3 / Dec. 01
4
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM
TCSR, PASR Extended Mode Register
Self refresh logic & timer
Internal Row Counter
CLK CKE State Machine CS RAS CAS WE U/LDQM
Row Active
Row Pre Decoders
2Mx16 Bank3 2Mx16 Bank2 2Mx16 Bank1 2Mx16 Bank0
Row decoders Row decoders
Row decoders
Row decoders
Sense AMP & I/O Gate
DQ0
I/O Buffer & Logic
refresh Column Active Column pre Decoders
Memory Cell Array
DQ15
Column decoders
bank select
Column Add Counter
A0 Address buffers A1
Address Registers Burst Counter Burst Length
A11 BA1 BA0
Mode Register
CAS Latency
Data Out Control
Rev. 1.3 / Dec. 01
5
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 BA0 0 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 A0
CAS Latency
Burst Length
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Type
A3 0 1 Burst Type Sequential Interleave
Burst Length
Burst Length A3 = 0 1 2 4 8
Reserved Reserved Reserved Full Page
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
A3=1 1 2 4 8
Reserved Reserved Reserved Reserved
Rev. 1.3 / Dec. 01
6
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register
BA1 BA0 1 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 A3 A2 A1 PASR A0
TCSR
TCSR (Temperature Compensated Self Refresh)
A4 0 0 1 1 A3 0 1 0 1 Temperature o C 70 45 15 85
PASR (Partial Array Self Refresh)
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 All Banks Half of Total Bank (BA1=0) Quarter of Total Bank (BA1=BA0=0) Reserved Reserved One Eighth of Total Bank (Row Address MSB=0) One Sixteenth of Total Bank (Row Address 2 MSBs=0) Reserved Self Refresh Coverage
Rev. 1.3 / Dec. 01
7
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT Power Up and Initialization
Like a Synchronous DRAM, Low Power SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 sec is required. And a precharge all command will be issued to the LP SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR & TCSR). The following these cycles, the LP SDRAM is ready for normal opeartion.
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the LP SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2, or 3), a burst type, an opearting mode to differentiate between normal mode and a special burst read and single write mode. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the LP SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the device(85, 70, 45, 15) for reducing current consumption during self refresh. The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A11 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
Rev. 1.3 / Dec. 01
8
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued, data ouputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay.
Clock Suspend
The Clock Suspend command is used to suspend the internal clock of DRAM. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations.
Power Down
The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off.
Auto Refresh
The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is "Don't care", because the specific address bits is generated by internal refresh address counter.
Self Refresh
The Self Refresh command is used to retain cell data in the Low Power SDRAM. In the Self Refresh mode, the Low Power SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Low Power SDRAM can accomplish an special Self Refresh operation by the specific modes(TCSR, PASR) programmed in extended mode registers. The Low Power SDRAM can control the refresh rate by the temperature value of TCSR (Temperature Compensated Self Refresh) and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Low Power SDRAM can reduce the self refresh current(IDD6) by using these two modes.
Deep Power Down
The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet.
Rev. 1.3 / Dec. 01
9
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT COMMAND TRUTH TABLE
Function
Mode Register Set Extended Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop Data Write/Output Enable Data Mask/Output Disable Auto Refresh Self Refresh Entry Self Refresh Exit
CKEn-1 H H H H H H H H H H H H H H H H L H L H L H L
CKEn X X X X X X X X X X X X X X H L H L H L H L H
CS L L L H L L L L L L L L
RAS L L H X L H H H H L L H X X
CAS L L H X H L L L L H H H
WE L L H X H H H L L L L L
DQM X X X X X X X X X X X X V
ADDR
A10/ AP
BA
Note 2 2
Op Code Op Code X X Row Address
Column Column Column Column
V V V V V X V
L H L H H L X X X X X X X X X X X X
X X
L L H L H L H L H L
L L X H X H X H X V X H X
L L X H X H X H X V H
H H X H X H X H X V
X X X X X X X
1
Precharge Power Down Entry Precharge Power Down Exit
Clock Suspend Entry
Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit
L
L
X X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev. 1.3 / Dec. 01
10
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT CURRENT STATE TRUTH TABLE (Sheet 1 of 3)
Current State
Command CS RAS CAS WE BA0,BA1 L L L L L L L H L L L L L L L H L L L L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X A11-A0 Description
Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA
Action
Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst
Notes 14 5
idle
Row Active
Col Add. Write/WriteAP A10 Col Add. Read/ReadAP BA A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA BA BA BA BA X X Row Add. Bank Activate Col Add. Write/WriteAP A10 Col Add. Read/ReadAP A10 No Operation X Device Deselect X
4 4 3 3 13,14 13 7 4 6 6
13,14 13 4 8,9 8
Read
L L L L H L L L
13,14 13 10 4 8 8,9
Write
L L L L H
Rev. 1.3 / Dec. 01
11
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT CURRENT STATE TRUTH TABLE (Sheet 2 of 3)
Current State
Command CS RAS CAS WE BA0,BA1 L L L L L L L H L L L L L L L H L L L L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X A11-A0 Description
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA Col Add. Write/WriteAP BA A10 Col Add. Read/ReadAP BA A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X
Action
Notes 13,14 13 4,12 4,12 12 12
Read with Auto Precharge
Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD
Write with Auto Precharge
13,14 13 4,12 4,12 12 12
13,14 13 4,12 4,12 4,12
Precharging
L L L L H L L L L L L L H
BA BA BA X X
Row Add. Bank Activate Col Add. Write/WriteAP A10 Col Add. Read/ReadAP A10 No Operation X X
Device Deselect
Row Activating
Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X
13,14 13 4,12 4,11,12 4,12 4,12
X
X
Device Deselect
Rev. 1.3 / Dec. 01
12
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT CURRENT STATE TRUTH TABLE (Sheet 3 of 3)
Current State
Command CS RAS CAS WE BA0,BA1 L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X A11-A0 Description
ILLEGAL ILLEGAL ILLEGAL ILLEGAL Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA Col Add. Write/WriteAP BA A10 Col Add. Read/ReadAP BA A10 No Operation X X
Action
Notes 13,14 13 4,13 4,12
Write Recovering
Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL No Operation: Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles
13
9
X
X
Device Deselect
Write Recovering with Auto Precharge
Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X
13,14 13 4,13 4,12 4,12 4,9,12
X
X
Device Deselect
Refreshing
Mode Register Accessing
Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X Row Add. Bank Activate BA Col Add. Write/WriteAP BA A10 BA Col Add. Read/ReadAP A10 No Operation X X Device Deselect X X Mode Register Set OP Code Auto or Self Refresh X X Precharge BA X BA Row Add. Bank Activate BA Col Add. Write/WriteAP A10 BA Col Add. Read/ReadAP A10 No Operation X X
13,14 13 13 13 13 13
13,14 13 13 13 13 13
X
X
Device Deselect
Rev. 1.3 / Dec. 01
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
Rev. 1.3 / Dec. 01
14
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT CKE Enable(CKE) Truth TABLE
CKE Current State Previous Current CS Cycle Cycle
Command RAS CAS WE X X H H H L X X X X X X X X X H L L L X H L L L X X X X X X X H H L X X X X X X X X X X X H L L X X H L L X X X X X X X H L X X X X X X X X X X X X X H L X X X H L X X X X X
BA0, A11BA1 A0
Action
INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle ILLEGAL Maintain Power Down Mode INVALID Deep Power Down mode exit Maintain Deep Power Down Mode Refer to the idle State section of the Current State Truth Table
Notes 1 2 2 2 2 2 1 2 2 1 5
H L Self Refresh L L L L L H L L L H L L H H H H H H H H H H L H H L L
X H H H H H L X H H L X H L H H H H H L L L L L X H L H L
X H L L L L X X H L X X X X H L L L L H L L L L X X X X X
X X X X X X X X X X X X X X
X X X X X X X X X X X X X X
Power Down
Deep Power Down
3 3 3 4 3 3 3 4 4
All Banks Idle
X X Auto Refresh Op Code Mode Register Set
Refer to the idle State section of the Current State Truth Table
X X Op Code X X X X X X X X X X
Entry Self Refresh Mode Register Set Power Down Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Any State other than listed above
Note : 1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200sec.
Rev. 1.3 / Dec. 01
15
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Symbol
TBD
Rating
Unit
o o
C C
-55 ~ 125 -1.0 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 50 1
260 . 10
V V V mA
W oC . Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA= -25 to 85 )
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage
Symbol
VDD VDDQ VIH VIL
Min
2.3 1.65 0.8*VDDQ -0.3
Typ
2.5
Max
2.7 2.7 VDDQ+0.3 0.2*VDDQ
Unit
V V V V 1
Note
1, 2 1, 2, 3 1, 2, 3
-
-
Note : 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD 3. Internal VREF = 0.9V
AC OPERATING TEST CONDITION (TA= -25 to 85, VDD = 2.5V, VSS = 0V) )
Parameter
AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL Vtrip tR / tF Voutref CL
Value
TBD 0.9 1 VDDQ/2 TBD
Unit
V V ns V pF
Note
Rev. 1.3 / Dec. 01
16
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT CAPACITANCE (TA=2.5 C, f=1MHz, HY5xxxxxxF Seires)
Parameter
Input capacitance CLK A0~A11, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM Data input/output capacitance DQ0 ~ DQ15
Pin
Symbol
CI1 CI2 CI/O
-H Min
2.5 1.5 4.0
-/P/S/B Max
3.0 3.0 5.5
Min
2.3 1.5 4.0
Max
3.0 3.0 6.0
Unit
pF pF pF
DC CHARACTERISTICS I (TA= -25 to 85)
Parameter
Input Leakage Current ILI
Symbol
Min
-1 -1 VDDQ - 0.2 -
Max
1 1 0.2
Unit A A
V V
Note
1 2 3 4
Output Leakage Current ILO Output High Voltage Output Low Voltage VOH VOL
Note : 1. VIN = 0 to 2.5V. All other pins are not tested under VIN=0V. 2. DOUT is disabled. VOUT= 0 to 1.95V. 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA
Rev. 1.3 / Dec. 01
17
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT DC CHARACTERISTICS II (TA= -25 to 85)
Speed Parameter Symbol Test Condition -H Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current Standby Current in Deep Power Down Mode IDD4 IDD5 IDD6 TBD Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRRC tRRC(min), All banks active CKE 0.2V
100 165 80 155 75
Unit -P
65 0.5 0.5
Note
-S
60
-B
60 mA mA mA 1
7 mA 7 5 mA 5
15 mA 15
70 125
70 125
mA mA mA
1 2 3
TBD
60
A
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II. 3. See the tables of next page for more specific IDD6 current values. - Normal Power : HY5W2A6CF / HY57W2A1620CT Series - Low Power : HY5W2A6CLF / HY57W2A1620CLT Series - Super Low Power : HY5W2A6CSF / HY57W2A1620CST Series - Standard Part : HY5W26CF / HY5W281620HCT Series
Rev. 1.3 / Dec. 01
18
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT DC CHARACTERISTICS III - Normal (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V)
Temp. ( oC)
85 70 -25~45
Memory Array 4 Banks
500 400 300
2 Banks
420 280 210
1 Bank
340 230 170
Unit
A A A
* HY5W2A6CF / HY57W2A1620CT Series
DC CHARACTERISTICS III - Low Power (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V)
Temp. ( oC)
85 70 -25~45
Memory Array 4 Banks
450 330 250
2 Banks
350 230 180
1 Bank
300 190 150
Unit A A A
* HY5W2A6CLF / HY57W2A1620CLT Series
DC CHARACTERISTICS III - Super Low Power (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V)
Temp. ( oC)
85 70 -25~45
Memory Array 4 Banks
320 250 180
2 Banks
220 180 130
1 Bank
190 150 110
Unit A A A
* HY5W2A6CSF / HY57W2A1620CST Series
DC CHARACTERISTICS III - Standard part (IDD6) (VDD=2.5V, VDDQ=1.8V & 2.5V, VSS=0V)
Temp. ( oC)
-25~85
Memory Array 4 Banks
< 450
Unit A
* HY5W26CF / HY57W281620CT Series
Rev. 1.3 / Dec. 01
19
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
H Min
7.5 10 2.5 2.5
Parameter
System Clock Cycle Time
Symbol
P Max
1000
S Max
1000
B Max
1000
Min
10 10
Min
10 12
Min
15 15
Max
1000
Unit Note
ns ns
CAS Latency=3 tCK3 CAS Latency=2 tCK2 tCHW tCLW
Clock High Pulse Width Clock Low Pulse Width
5.4 7
3 3
7 7
3 3
7 8
3.5 3.5
9 9
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 1 2
Access Time From CAS Latency=3 tAC3 Clock CAS Latency=2 tAC2 Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ
2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7
3 2 1 2 1 2 1 2 1 1 3 3
3 2 1 2 1 2 1 2 1 1 3 3
3 2 1 2 1 2 1 2 1 1 3 3
5.4 7
6 6
6 6
9 9
1 1 1 1 1 1 1 1
CLK to Data Output CAS Latency=3 tOHZ3 in High-Z Time CAS Latency=2 tOHZ2
Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 0.2v. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
Rev. 1.3 / Dec. 01
20
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
H Min
65 20 45 20 15 1 0 2 5 2 0 2 3 2 1 1
Parameter
RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z
Symbol
tRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD
P Max 100K
S Max 100K
B Max 100K
Min
70 20 50 20 20 1 0 1 3 2 0 2 3 2
Min
70 30 50 30 20 1 0 1 3 2 0 2 3 2
Min
90 30 60 30 20 1 0 1 3 2 0 2 3 2
Max 100K
Unit Note
ns ns ns ns ns
tCK tCK tCK tCK tCK tCK tCK tCK
-
-
-
-
CAS Latency=3 tPROZ3 CAS Latency=2 tPROZ2
tCK
Power Down Exit Time Self Refresh Exit Time Refresh Time
tDPE tSRE tREF
64
1 1
64
1 1
64
1 1
64
tCK tCK
1
-
-
-
-
ns
Note : 1. A new command can be given tRRC after self refresh exit.
Rev. 1.3 / Dec. 01
21
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT Special Operation for Low Power Consumption Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Current State Command CKEn-1 CKEn CS RAS CAS WE
Idle Deep Power Down
Deep Power Down Entry Deep Power Down Exit
H L
L H
L X
H X
H X
L X
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having /CS and /WE held low with /RAS and /CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
CLK CKE CS RAS CAS WE tRP Precharge if needed Deep Power Down Entry
Rev. 1.3 / Dec. 01
22
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT Deep Power Down Mode (Continued)
Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200sec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence.
CLK CKE CS RAS CAS WE
200s
tRP
tRC
Deep Power Down exit
All banks precharge
Auto refresh
Auto refresh
Mode Register Set
Extended Mode Register Set
New Command Accepted Here
Rev. 1.3 / Dec. 01
23
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT PACKAGE INFORMATION 54 Ball 0.8mm pitch 8.3mm x 10.5mm FBGA (HY5xxxxxxF Series)
0.80
10.50 6.40
0.450 0.80 6.40 8.30 0.340 1.070
Rev. 1.3 / Dec. 01
24
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T HY5W26CF / HY57W281620HCT
PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package (HY5xxxxxxT Series)
Unit : mm(inch)
Rev. 1.3 / Dec. 01
25

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