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TECHNICAL NOTE
High-performance Regulator IC Series for PCs
FET Integrated Switching Regulators for DDR-SDRAM Cores
BD95513MUV
Description BD95513MUV is a switching regulator capable of supplying high current output (up to 3A) at low output voltages (0.7V~5.0V) over a broad range of input voltages (4.5V~28V). The regulator features an internal N-MOSFET power transistor for high 3 TM efficiency and low space consumption, while incorporating ROHM's proprietary H Reg control mode technology, yielding the industry's fastest transient response time against load changes. SLLM (Simple Light Load Mode) technology is also integrated to improve efficiency when powering lighter loads, as well as soft start, variable frequency, short-circuit protection with timer latch, over-voltage protection, and REF functions. This regulator is suited for PC applications. Features 1) Internal low ON-resistance power N-MOSFET 2) Internal 5V linear voltage regulator 3 TM 3) Integrated H Reg DC/DC converter controller 4) Selectable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and forced continuous mode 5) Built-in thermal shutdown, low input, current overload, output over- and under-voltage protection circuitry 6) Soft start function to minimize rush current during startup 7) Adjustable switching frequency (f = 200 kHz ~ 1000 kHz) 8) Built-in output discharge function 9) VQFN032-V5050 package size 10) Tracking function 11) Internal bootstrap diode
Applications Mobile PCs, desktop PCs, LCD-TV, digital household electronics
Sep. 2008
Absolute Maximum Ratings (Ta = 25 C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 External VCC Voltage BOOT Voltage BOOT-SW Voltage Output Feedback Voltage SS/FS/MODE Voltage VREG Voltage EN/CTL Input Voltage PGOOD Voltage Output Current (Average) Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Junction Temperature
Symbol VCC VDD VIN EXTVCC BOOT BOOT-SW FB SS/FS/MODE VREG EN/CTL PGOOD ISW Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax
Value 7 *1 7 *1 30 *1 7 *1 35 7 *1 VCC VCC VCC 7 *1 7 *1 3 *1 0.38 *2 0.88 *3 *6 2.06 *4 *6 4.56 *5 *6 -10 ~ +100 -55 ~ +150 +150
Unit V V V V V V V V V V V A W W W W C C C
*1 Do not exceed Pd. *2 Ta 25 C (IC only), power dissipated at 3.0 mW / C. *3 Ta 25 C (single-layer board, 20.2 mm2 copper heat dissipation pad), power dissipated at 7.0 mW / C. *4 Ta 25 C (4-layer board, 10.29 mm2 copper heat dissipation pad on top layer, 5505 mm2 pad on 2nd and 3rd layer), power dissipated at 16.5 mW / C. *5 Ta 25 C (4-layer board, all layers with 5505 mm2 copper heat dissipation pads), power dissipated at 36.5 mW / C. *6 Values observed with chip backside soldered. When unsoldered, power dissipation is lower.
Operating Conditions (Ta = 25 C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 External VCC Voltage BOOT Voltage SW Voltage BOOT-SW Voltage MODE Input Voltage EN/CTL Input Voltage PGOOD Voltage Minimum On Time
Symbol VCC VDD VIN EXTVCC BOOT SW BOOT-SW MODE EN/CTL PGOOD tonmin
Min 4.5 4.5 4.5 4.5 4.5 -0.7 4.5 0 0 0 -
Max 5.5 5.5 28 5.5 33 28 5.5 5.5 5.5 5.5 100
Unit V V V V V V V V V V ns
This product is not designed for use in a radioactive environment.
2/15
Electrical Characteristics (Unless otherwise noted, Ta =25C, AVIN =12V, VCC =VDD =VREG, EN/CTL=5V, MODE=0V, RFS =180k) Parameter [Whole Device] AVIN Bias Current 1 AVIN Bias Current 2 AVIN Standby Current EN Low Voltage EN High Voltage EN Bias Voltage CTL Low Voltage CTL High Voltage CTL Bias Current [5V Regulator] VREG Input Voltage Maximum Current [5V Switch]
EXTVCC Input Threshold Voltage
Symbol IIN1 IIN2 IINstb ENlow ENhigh IEN CTLlow CTLhigh ICTL VREG IREG
Min. GND 2.3 GND 2.3 4.90 100 4.2 4.1 100 4.1 100 400 10.0 0.420 0.812 1.4 3 0.693 0.690 -100 VCC-0.5 GND 0.605 0.745
Limit Typ. 1200 150 0 12 1 5.00 4.4 1.0 4.3 160 4.3 160 500 22.0 450 120 120 0.490 1 0.840 2.2 0.700 0.700 0 0.63 0.77
Max. 1800 250 10 0.8 5.5 20 0.8 5.5 6 5.10 4.6 2.0 4.5 220 4.5 220 600 40.0 550 200 200 0.560 0.868 3.0 100 0.707 0.710 100 VCC 0.5 0.655 0.795
Unit A A A V V A V V A V mA V V mV V mV nsec sec nsec m m V ms V A mV A V V nA V V V V
Condition
EXTVCC=5V CTL=EN=0V
VIN=6.0 to 25V IREG=0 to 100mA EXTVCC:Sweep up
EVCC_UVLO Switch Resistance REVCC [Under-Voltage Lockout Protection] AVIN Threshold Voltage AVIN _ UVLO AVIN Hysteresis Voltage dAVIN _ UVLO VREG Threshold Voltage VREG_ UVLO VREG Hysteresis Voltage dVREG_ UVLO [H3REGTM Control Block] ON Time ton MAX ON Time tonmax MIN OFF Time toffmin [FET Block] High-side ON Resistance Ron_high Low-side ON Resistance Ron_low [SCP Block] SCP Startup Voltage VSCP Delay tSCP [Over-Voltage Protection Block] OVP Detect Voltage VOVP [Soft Start Block] Charge Current Iss Standby Voltage Vss_stb [Current Regulation Block] Maximum Output Current IOCP [Voltage Detection Block] Feedback Terminal Voltage 1 VFB1 Feedback Terminal Voltage 2
Feedback Terminal Bias Current
VCC:Sweep up VCC:Sweep down VREG:Sweep up VREG:Sweep down
When VFB: 30% down When VFB: 20% up
VFB2 IFB VthSLLM VthCONT VFB PL VFB PH
Ta =-10C to 100C Iout = 0A to 3A SLLM Longest low-gate off time: Continuous mode When VFB: 10% down When VFB: 10% up
[MODE Block] SLLM Condition Forced Continuous Mode [Power Good Block] VFB Power Good Low Voltage VFB Power Good High Voltage
3/15
Reference Data
100
100
100
SLLM
80
80
SLLM
80
SLLM
60
[%]
Continuous Mode
60
Continuous Mode
60 [%]
Continuous Mode
40
QLLM
[%]
40
QLLM
40
QLLM
20
20
20
0 0.01 0.1
Io [A]
1
10
0 0.01
0
0.1
Io [A]
1
10
0.01
0.1
1
10
Fig.1 Io-Efficiency (VIN=7V,VOUT=2.5V)
Fig.2 Io-Efficiency (VIN=12V,VOUT=2.5V)
Fig.3 Io-Efficiency (VIN=19V,VOUT=2.5V)
Io [A]
VOUT (50mV/div)
2sec/div
VOUT (50mV/div)
2sec/div
VOUT (50mV/div)
2sec/div
SW (10V/div) IOUT (2A/div)
SW (10V/div) IOUT (2A/div)
SW (10V/div) IOUT (2A/div)
Fig.4 Transient Response (VIN=7V, VOUT=2.5V)
Fig.5 Transient Response (VIN=12V, VOUT=2.5V)
Fig.6 Transient Response (VIN=19V, VOUT=2.5V)
2sec/div VOUT (50mV/div) VOUT (50mV/div)
2sec/div VOUT (50mV/div)
2sec/div
SW (10V/div) IOUT (2A/div)
SW (10V/div) IOUT (2A/div)
SW (10V/div) IOUT (2A/div)
Fig.7 Transient Response (VIN=7V, VOUT=2.5V)
Fig.8 Transient Response (VIN=12V, VOUT=2.5V)
Fig.9 Transient Response (VIN=19V, VOUT=2.5V)
2sec/div VOUT IL VOUT IL
2sec/div VOUT IL
2sec/div
HG LG
HG LG
HG LG
Fig.10 SLLM Mode (IOUT=0A)
Fig.11 SLLM Mode (IOUT=0.4A)
Fig.12 1 SLLM Mode (IOUT=1A)
4/15
Reference Data
10sec/div VOUT 10sec/div EN 200sec/div
VOUT 2[V/div]
SW
PGOOD
Fig.13 QLLM Mode (IOUT=0A)
Fig.14 QLLM Mode (IOUT=1A)
Fig.15 PGOOD Rising Waveform
2msec/div EN
VOUT 2[V/div]
200sec/div VIN
VOUT 2[V/div]
HG/LG SW IL 5[A/div]
PGOOD
VOUT
Fig.16 PGOOD Falling Waveform
Fig.17 SCP Timer Latch Waveform
Fig.18 VIN change (519V)
VIN EN HG/LG VREG 2[V/div] VOUT 2[V/div] VOUT SW
400sec/div
Fig.19 VIN change (195V)
Fig.20 EN wake up
5/15
Block Diagram
VREG VCC
VIN AVIN SS VDD Soft Start SS 5 1 2 3 VREFx0.85 VSSx0.85 VOUT SCP ILIM OCP 4 26 R Q MODE SW BOOT VIN VIN(4.528V)
13 EN 10 8 CTL
7 VREG AVIN UVLO
16
Reference Block
REF(0.7V) VREG 17 6 PGOOD FB 18
Delay
27 MODE EN SS REFx1.2 FB OVP H3Reg Controller Block 28 29 MODE S Driver Circuit 30 31 21 22 23 24 25 32 20 N.C. 19 VOUT VREG VDD PGND VOUT
Power Good
EXTVCC 14
UVLO ILIM AVIN SCP TSD
5V Reg
Thermal TSD Protection MODE EN/UVLO
15
VREG
11
FS
9
MODE
12
GND
Pin Configuration
PGND PGND PGND 24 PGND 25 SW 26 SW 27 SW 28 SW 29 SW 30 SW 31 PGND 32 1 VIN 2 VIN 3 VIN 4 VIN 5 6 7 8 23 22 VDD 21 N.C. VOUT 20 19 FB 18 REF 17 16 SS 15 VREG 14 EXTVcc 13 VCC 12 GND 11 FS 10 EN 9 MODE
Pin Function Table PIN No. 1-4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-25 26-31 32
Underside
PIN Name
VIN BOOT PGOOD AVIN CTL MODE EN FS GND VCC EXTVCC VREG SS REF FB VOUT N.C. VDD PGND SW PGND FIN
PIN Function Battery voltage input (4.5 ~ 28 V) HG driver power supply Power good output (high when output 10% of regulation) Battery voltage sense Linear regulator on/off (high = 5.0V, low = off) Control mode selection
GND : Continuous Mode 3.0V : QLLM VCC : SLLM
BOOT PGOOD AVIN CTL
*Connect the underside (FIN) to the ground terminal
Enable output (high when VOUT ON) Switching frequency adjustment (RFS = 30 k ~ 100 k) Sense ground Power supply input External power supply input IC reference voltage (5.0V / 200mA) Soft start condenser input Output reference voltage (0.7 V) Feedback input (0.7 V) Voltage discharge output Power supply input (5 V) Power ground Output to inductor Power ground Substrate connection
6/15
Pin Descriptions VCC This pin supplies power to the IC's internal circuitry, excluding the FET driver. The input supply voltage range is 4.5 to 5.5 V, with a maximum current draw of 900 A. This pin should be bypassed with a capacitance of approximately 0.1 F. EN Enables or disables the switching regulator. When the voltage on this pin reaches 2.3 V or higher, the internal switching regulator is turned on. At voltages less than 0.8 V, the regulator is turned off. VDD This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak current when switching on or off, this pin should be bypassed with a capacitance of approximately 1 F. VREG Output pin from the 5 V linear regulator. This pin also supplies power to the internal driver and control circuitry. VREG standby function is controlled by the CTL pin. The output supplies 5V at 100 mA and should be bypassed to ground using a 10 F capacitor with a rating of X5R or X7R. EXTVCC External power supply input for the linear regulator. When the voltage on the EXTVCC pin exceeds 4.4 V, the regulator uses it in conjunction with other power sources to supply VREG. Leave the EXTVCC pin floating when not in use. REF Reference voltage output pin. The reference voltage is set internally by the IC to 0.7 V, and the IC works to keep VREF approximately equal to VFB. Variations in voltage levels on this pin affect the output voltage, so the pin should be bypassed with a 100 pF ~ 0.1 F ceramic capacitor. SS Soft start/stop pin. When EN is set high, the capacitor between the internal current source and SS-GND controls the startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7 V), the output voltage is held at the same voltage as the SS pin. AVIN The BD95513MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this line should be bypassed with either a power capacitor or RC filter. FS Frequency-adjusting resistance input pin. Attaching a resistance of 30 k ~ 100 k adjusts the switching frequency from 200 kHz ~ 1 MHz. BOOT This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC. The maximum voltage on this pin should not exceed +30 V vs. GND or +7 V vs. SW. When operating the switching regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (VIN + VDD) ~ VDD. PGOOD Power good indicator. This open-drain output should be connected via a 100 k pull-up resistor. MODE Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode; when high, SLLM mode. CTL Linear regulator control pin. When voltage is 2.3 V or higher, a logic HIGH is recognized and the internal regulator (VREG = 5 V) is switched on. At voltages of 0.8 V or lower, a logic LOW is recognized and the regulator is switched off. However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW. FB Output voltage feedback input. VFB is held at 0.7 V by the IC. SW Output from the switching regulator to the inductor. This output swings from VIN ~ GND. The trace from the output to the inductor should be as short and wide as possible. VOUT Voltage output discharge pin. When EN is off, this output is pulled low. VIN Power supply input. The IC can accept any input from 4.5 V to 28 V. This pin should be bypassed directly to ground by a power capacitor. PGND Power ground terminal. 7/15
Operation 3 The BD95513MUV is a switching regulator incorporating ROHM's proprietary H Reg CONTROLLA control system. When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time interval. This improves the regulator's transient response. When light-load mode is activated, the IC employs the Simple Light Load Mode (SLLM) controller, further improving system efficiency.
3 TM H Reg Control (Normal Operation)
VFB VREF HG LG
When VFB falls below the reference voltage (0.7 V), the H3Reg CONTROLLA is activated; tON VREF VIN x 1 [sec](1) f
High gate output is determined by the above formula.
(Rapid Changes in Load) VFB VREF When VOUT drops due to a sudden change in load and the voltage remains below VREF after the preprogrammed tON time interval has elapsed, the system quickly restores VOUT by extending the tON time, thereby improving transient response.
Io HG
tON+
LG
Light Load Control (SLLM Mode) VFB VREF HG SLLM mode is enabled by setting the MODE pin to logic high. When the low gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), the SLLM function is activated, disabling high gate output. If VFB falls below VREF again, the high gate is switched back on, lowering the switching frequency of the regulator and yielding higher efficiency when powering light loads.
LG
0A
(QLLM Mode) VFB VREF
HG
LG
0A 8/15
QLLM mode is enabled by setting the MODE pin to HiZ or middle voltage. When the lower gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), QLLM mode is activated, disabling high gate output. If VFB falls below VREF within a programmed time interval (typ. 40 s), the high gate is switched on, but if VFB does not fall below VREF, the lower gate is forced on, dropping VFB and switching the high gate back on. The minimum switching frequency is set to 25 kHz (T = 40 S), which keeps the regulator's frequency from entering the audible spectrum but yields less efficient results than SLLM mode.
Timing Chart Soft Start Function EN tSS SS
The soft start function is enabled when the EN pin is set high. Current control circuitry takes effect at startup, yielding a moderate "ramping start" in output voltage. Soft start timing and incoming current are given by equation (2) and (3) below:
Soft start period: tSS = VREFxCss 2A(typ) [sec] (2)
VOUT Rush current: IIN(ON)= IIN CoxVOUT tss [A] (3)
(Css: soft start capacitor; Co: output capacitor)
Timer Latch-type Short Circuit Protection VREFx0.70 VOUT 1ms When output voltage falls to VREF x 0.70 or less, the output short circuit protection engages, turning the IC off after a set period of time to prevent internal damage. When EN is switched back on or when UVLO is cleared, output continues. The time period before shutting off is set internally at 1 ms.
SCP
EN/UVLO
Output Over-Voltage Protection VOUT VREFx1.2 When output reaches or exceeds VREF x 1.2, the output over-voltage protection is engaged, turning the low-side FET completely on to reduce the output (low gate on, high gate off). When the output falls, it returns to standard mode.
HG
LG Switching
9/15
External Component Selection 1. Inductor (L) Selection The inductor's value directly influences the output ripple current. As formula (4) indicates below, the greater the inductance or switching frequency, the lower the ripple current: (VIN-VOUT)xVOUT IL= [A](4) LxVINxf
The proper output ripple current setting is about 30% of maximum output
IL VOUT L Co
IL
VIN
current.
IL=0.3xIOUTmax. [A](5) L= (VIN-VOUT)xVOUT ILxVINxf [H](6)
(IL: output ripple current, f: switching frequency) Output ripple current Passing a current larger than the inductor's rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor's rated current value. To minimize possible inductor damage and maximize efficiency, choose an inductor with a low DCR and ACR resistance. 2. Output Capacitor Selection (CO)
VIN
When determining the proper output capacitor, be sure to factor in the equivalent series resistance (ESR) and equivalent series inductance (ESL) required to set the output ripple voltage at 20 mV or more.
VOUT L ESR ESL Co
When selecting the limit of the inductor, be sure to allow enough margin for the output voltage. Output ripple voltage is determined by formula (7) below: VOUT=ILxESR+ESLxIL / TON(7) (IL: Ouput ripple current, ESR: equivalent series resistance, ESL: equivalent series inductance) Also, keep in mind that the output rise time
Output Capacitor
Give special consideration to the conditions of formula (7) for output capacitance. must be established within the soft start timeframe. Co tssx(Ilimit-IOUT) VOUT (8)
tss: Soft start timeframe (see p. 10, equation (2)) Ilimit: Maximum output current
Choosing a capacitance that is too large can cause startup malfunctions, or in some cases, may engage the short circuit protection. 3. Input Capacitor Selection (CIN)
VIN CIN
In order to prevent extreme over-current conditions, the input capacitor must have a low enough ESR to fully support a large ripple in the output. The formula for RMS ripple current (IRMS) is given by equation (9) below:
VOUT
L
IRMS=IOUTx
VIN(VIN-VOUT) VIN IOUT 2
[A](9)
Co
When VIN=2xVOUT, IRMS= Input Capacitor
A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
10/15
4. Frequency Adjustment
600
From top:
500
VIN= 5V 7V 12V 19V
The resistance connected to the FS terminal adjusts the on-time (tON) during normal operation as illustrated to the left. When tON, input voltage and VREF voltage are known, the switching frequency can be determined by the following formula: F= VREF VINxtON (10)
400 Frequency [kHz]
300
200
100
However, real-life considerations (such as external MOSFET gate capacitance and switching time) must be factored in as they affect the overall switching rise and fall time. This leads to an increase in tON, lowering the total frequency slightly.
0 50 100 RFS[k] 150 200 250
0
Additionally, when output current lingers around 0A in continuous mode, this "dead time" also has an effect upon tON, further lowering the switching frequency. Confirm the switching frequency by measuring the current through the coil (at the point where current does not flow backwards) during normal operation.
The BD95513MUV operates by feeding the output voltage back through a resistive voltage divider. The output voltage is set by the following equation (see schematic below): Output Voltage = R1+R2 R2 x VREF (0.7V) + 1 2 xILxESR(11)
The switching frequency is also amplified by the same resistive voltage divider network: fsw = R1+R2 x(frequency set by RFS) [Hz](12) R2 VIN R S SLLM FB Q SLLM
TM
VIN REF(0.7V) H3RegTM CONTROLLA
Output Voltage
Driver Circuit
R1 ESR
R2
11/15
Evaluation Board Circuit (Frequency=300kHz Continuous Mode/QLLM/SLLM Example Circuit)
VIN 12V VREG
R4
VREG
EN
R1
BD95513MUV
7 AVIN 13 VCC 10 EN
VDD
21
C3
9
MODE CTL
BOOT
CTL 5V VREG(5V)
8 14 15
C12
VIN EXTVCC SW VREG PGND PGOOD 17 REF(0.7V) SS/ TRACK FS VOUT
1~4 26~31
PGND PGND
L1 1.8V/3A
C10
C11
3V
MODE
5
VOUT
REF
C4
R9 6
22~25,32
PGND
19
C13 R7
16 R6
C6 C7
PGND
11
C1
C5
12
GND
FB CE 20
18
GND
Evaluation Board Parts List Part No U1 D1 C1 C3 C4 C5 C6 C7 C11 C12 C13 Value Company ROHM ROHM KYOCERA KYOCERA KYOCERA MURATA KYOCERA KYOCERA KYOCERA KYOCERA MURATA Part name BD95513MUV RB051L-40 CM105B105K06A CM105B105K16A CM316B106K06A GRM39X7R102K50 CM105B104K06A CM105B105K16A CM316B106M16A CM05B104K25A GRM39C0G221J50 Part No R1 R4 R6 R7 R8 R9 L1 C14 C15 C16 Value 10 10 68K 31k 20k 100k 1.8uH 470uF 1uF 1uF Company ROHM ROHM ROHM ROHM ROHM ROHM SUMIDA SANYO KYOCERA KYOCERA Part name MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 CDEP104-1R8ML 2R5TPE470ML CM105B105K06A CM105B105K06A
1uF 1uF 10uF 1000pF 0.1uF 1uF 10uF 0.1uF 220pF
12/15
R8
C14
VDD
D1
Operation Notes (1) Absolute maximum ratings Exceeding the absolute maximum ratings (such as supply voltage, temperature range, etc.) may result in damage to the device. In such cases, it may be impossible to identify problems such as open circuits or short circuits. If any operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power supply polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power supply lines The PCB layout pattern should be designed to provide the IC with low-impedance GND and supply lines. To minimize noise on the supply and GND lines, ground and power supply lines of analog and digital blocks should be separated. For all power lines supplying ICs, connect a bypass capacitor between the power supply and the GND terminal. If using electrolytic capacitors, keep in mind that their capacitance is reduced at lower temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use thermal design techniques that allow for a sufficient margin for power dissipation in actual operating conditions. (6) Inter-pin shorts and mounting errors Use caution when positioning he IC for mounting on PCBs. The IC may be damaged if there are any connection errors or if pins are shorted together. (7) Operation in strong electromagnetic fields Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to malfunction. (8) ASO When using the IC, set the output transistor so that it does not exceed either absolute maximum ratings or ASO. (9) Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit), which is designed to shut down the IC only to prevent thermal overloading. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC if this circuit is activated, or in environments in which activation of this circuitry can be assumed.
BD95513MUV
TSD ON Temp. [C] (typ.) 175
Hysteresis Temp. [C] (typ.) 15
(10) Testing on application boards When testing the IC with application boards, connecting capacitors directly to low-impedance terminals can subject the IC to stress. Always discharge capacitors completely after each process or step. The IC's power supply should be turned off completely before connecting it to or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
13/15
(11) Regarding IC input pins This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistance
Pin A
Pin A N P N N P+ B N P P+ N P Sub Parasitic Element Parasitic Elements GND GND GND Other Adjacent Elements
Transistor (NPN)
Pin B
C B E B C E Parasitic Elements
B
N
P+
P+
P Substrate Parasitic Element GND
Example of IC Structure
(12) Ground wiring traces When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage.
Power Dissipation
5.5 5.0 4.56W 4.5 Power Dissipation Pd [W] 4.0
IC Only j-a = 328.9 C/W
IC mounted on 1-layer board (with 20.2 mm copper thermal pad) j-a = 142.0 C/W
2
3.5 3.0 2.5 2.06W 2.0 1.5 1.0 0.88W 0.38W 0.5 0 0 20 40 60 80 100 120 140
IC mounted on 4-layer board (with 20.2 mm pad on top layer, 2 5502 mm pad on layers 2,3) j-a = 60.7 C/W IC mounted on 4-layer board (with 5505mm pad on all layers) j-a = 27.4 C/W
2
2
Ambient Temperature Ta [C]
VQFN032-V5050 14/15
Ordering Instructions
B
D
9
5
5
1
3
M
U
V
E
2
Product name
BD955X
Package Type MUV : VQFN032-V5050
Taping type name E2= Embossed carrier tape
VQFN032-V5050

Tape Quantity Feed Direction Embossed carrier tape (with dry-pack)
2500 pcs
E2 Pin 1 is located on the upper-left corner when the reel is held on the left and fed out to the right
1234
1234
(Unit:mm)
Reel
Pin 1
Please place orders in quantities of full reels.
1234
1234
1234
Feed direction
15/15
Catalog No.08T449A '08.9 ROHM (c)
1234
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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Appendix1-Rev3.0

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