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IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
FEATURES: DESCRIPTION:
IDT23S09E
* Phase-Lock Loop Clock Distribution * 10MHz to 200MHz operating frequency * Distributes one clock input to one bank of five and one bank of four outputs * Separate output enable for each output bank * Output Skew < 250ps * Low jitter <200 ps cycle-to-cycle * IDT23S09E-1 for Standard Drive * IDT23S09E-1H for High Drive * No external RC network required * Operates at 3.3V VDD * Spread spectrum compatible * Available in SOIC and TSSOP packages
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 200MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S09E enters power down. In this mode, the device will draw less than 12A for Commercial Temperature range and less than 25A for Industrial temperature range, and the outputs are tri-stated. The IDT23S09E is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
16 CLKOUT
1 REF
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 S1
8 9 Control Logic
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2003 Integrated Device Technology, Inc.
OCTOBER 2003
DSC - 6399/8
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
SOIC/ TSSOP TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI < 0) IO (VO = 0 to VDD) VDD or GND TA = 55C (in still air) TSTG Operating Temperature Operating Temperature
(3)
Max. -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5 -50 50 100 0.7 -65 to +150 0 to +70 -40 to +85
Unit V V V mA mA mA W C C C
CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
VDD VI (2) VI
Input Clamp Current Continuous Output Current Continuous Current Maximum Power Dissipation Storage Temperature Range Commercial Temperature Range Industrial Temperature Range
APPLICATIONS:
* * * * * SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name REF(1) CLKA1(2) CLKA2(2) VDD GND CLKB1(2) CLKB2(2) S2
(3)
Pin Number 1 2 3 4, 13 5, 12 6 7 8 9
Type IN Out Out PWR GND Out Out IN IN Out Out Out Out Out
Functional Description Input reference clock, 5 Volt tolerant input Output clock for bank A Output clock for bank A 3.3V Supply Ground Output clock for bank B Output clock for bank B Select input Bit 2 Select input Bit 1 Output clock for bank B Output clock for bank B Output clock for bank A Output clock for bank A Output clock, internal feedback on this pin
S1(3) CLKB3 CLKA3
(2)
10 11 14 15
(2)
CLKB4(2)
(2)
CLKA4(2) CLKOUT
16
NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs.
2
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
S2 L L H H S1 L H L H CLKA Tri-State Driven Driven Driven CLKB Tri-State Tri-State Driven Driven CLKOUT (2) Driven Driven Driven Driven Output Source PLL PLL REF PLL PLL Shut Down N N Y N
NOTES: 1. H = HIGH Voltage Level. L = LOW Voltage Level 2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz (S2 = S1 = H) Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND IOL = 8mA IOL = 12mA (-1H) IOH = -8mA IOH = -12mA (-1H) -- -- 12 32 A mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
OPERATING CONDITIONS - COMMERCIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100MHz - 200MHz Input Capacitance Parameter Min. 3 0 -- -- -- Max. 3.6 70 30 10 7 pF Unit V
C
pF
SWITCHING CHARACTERISTICS (23S09E-1) - COMMERCIAL(1,2)
Symbol t1 Output Frequency Duty Cycle = t2 / t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge(2) Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time
(2)
Parameter 10pF Load 30pF Load
Conditions
Min. 10 10 40 -- -- -- -- 1 -- -- --
Typ. -- -- 50 -- -- -- 0 5 0 -- --
Max. 200 100 60 2.5 2.5 250 350 8.7 700 200 1
Unit MHz % ns ns ps ps ns ps ps ms
Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 in PLL bypass mode (IDT23S09E only) Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
3
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (23S09E-1H) - COMMERCIAL(1,2)
Symbol t1 Output Frequency Duty Cycle = t2 / t1 Duty Cycle = t2 / t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter PLL Lock Time Parameter 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 in PLL bypass mode (IDT23S09E only) Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin Conditions Min. 10 10 40 45 -- -- -- -- 1 -- 1 -- -- Typ. -- -- 50 50 -- -- -- 0 5 0 -- -- -- Max. 200 100 60 55 1.5 1.5 250 350 8.7 700 -- 200 1 Unit MHz % % ns ns ps ps ns ps V/ns ps ms
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz (S2 = S1 = H) Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND IOL = 8mA IOL = 12mA (-1H) IOH = -8mA IOH = -12mA (-1H) -- -- 25 35 A mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
OPERATING CONDITIONS - INDUSTRIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100MHz - 200MHz Input Capacitance Parameter Min. 3 -40 -- -- -- Max. 3.6 +85 30 10 7 pF Unit V
C
pF
4
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (23S09E-1) - INDUSTRIAL(1,2)
Symbol t1 Output Frequency Duty Cycle = t2 / t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time Parameter 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 in PLL bypass mode (IDT23S09E only) Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin Conditions Min. 10 10 40 -- -- -- -- 1 -- -- -- Typ. -- -- 50 -- -- -- 0 5 0 -- -- Max. 200 100 60 2.5 2.5 250 350 8.7 700 200 1 % ns ns ps ps ns ps ps ms Unit MHz
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (23S09E-1H) - INDUSTRIAL(1,2)
Symbol t1 Output Frequency Duty Cycle = t2 / t1 Duty Cycle = t2 / t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter PLL Lock Time Parameter 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 in PLL bypass mode (IDT23S09E only) Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin Conditions Min. 10 10 40 45 -- -- -- -- 1 -- 1 -- -- Typ. -- -- 50 50 -- -- -- 0 5 0 -- -- -- Max. 200 100 60 55 1.5 1.5 250 350 8.7 700 -- 200 1 Unit MHz % % ns ns ps ps ns ps V/ns ps ms
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
5
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
6
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS
VDD 0.1F OUTPUTS
VDD CLKOUT CLOAD 0.1F OUTPUTS
1K
CLKOUT 10pF
1K VDD 0.1F
VDD 0.1F GND GND
GND
GND
Test Circuit 1 (all Parameters Except t8)
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
SWITCHING WAVEFORMS
t1 t2 1.4V 1.4V 1.4V
Output Output
1.4V
1.4V t5
Duty Cycle Timing
Output to Output Skew
Output
0.8V t3
2V
2V
0.8V t4
3.3V 0V
REF Output t6
VDD/2
VDD/2
All Outputs Rise/Fall Time
Input to Output Propagation Delay
CLKOUT Device 1 CLKOUT Device 2 t7
VDD/2
VDD/2
Device to Device Skew 7
IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I DC PG
Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Small Outline Thin Shrink Small Outline Package
Zero Delay Clock Buffer with High Drive, 23S09E-1 23S09E-1H Spread Spectrum Compatible
Ordering Code IDT23S09E-1DC IDT23S09E-1DCI IDT23S09E-1HDC IDT23S09E-1HPG
(1)
Package Type 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin TSSOP 16-Pin TSSOP Commercial Industrial Commercial Industrial Commercial Industrial
Operating Range
IDT23S09E-1HDCI(1)
(1) (1)
IDT23S09E-1HPGI
NOTE: 1. Contact factory for availability.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8
for Tech Support: logichelp@idt.com (408) 654-6459

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