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THC63LVDM83R/THC63LVDM63R_Rev2.0
THC63LVDM83R/THC63LVDM63R
REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE
General Description
The THC63LVDM83R transmitter converts 28bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 595Mbps per LVDS channel. Also available is THC63LVDM63R that converts 21bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. Both transmitters can be programmed reduced swing LVDS through a dedicated pin for low power consumption and EMI.
Features
* 28:4 Data channel compression at up to
298 Megabytes per sec throughput
* Wide dot clock range: 20-85MHz suited for VGA, * * Support Reduced swing LVDS for Low EMI * 200mV swing LVDS/350mV swing LVDS * * * * * * * *
selectable Support Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No external components Single 3.3V supply with 125mW(TYP) Power-Down Mode Low profile 56 or 48 Lead TSSOP Package SVGA, XGA and SXGA Narrow bus (10 lines or 8 lines) reduces cable size
Clock Edge Programmable Improved Replacement for the National DS90C383 or DS90C363 .com
Block Diagram
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CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 TD0-6 7 7 7 7
THC63LVDM83R
DATA (LVDS) TA +/TB +/TC +/TD +/(140-595Mbit/On Each LVDS Channel)
CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 7 7 7
THC63LVDM63R
DATA (LVDS) TA +/TB +/TC +/-
TTL PARALLEL TO SERIAL
TTL PARALLEL TO SERIAL
TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS
(140-595Mbit/On Each LVDS Channel) TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS PLL TCLK +/CLOCK (LVDS) 20-85MHz
PLL
TCLK +/CLOCK (LVDS) 20-85MHz
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Pin Out
THC63LVDM83R THC63LVDM63R
RS TD1 TA5 TA6 GND TB0 TB1 TD2 VCC TD3 TB2 TB3 GND TB4 TB5 TD4 R/F TD5 TB6 TC0 GND TC1 TC2 TC3 TD6 VCC TC4 TC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
TA4 TA3 TA2 GND TA1 TA0 TD0 LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ LVDS GND PLL GND PLL VCC PLL GND /PDWN CLK IN TC6 GND
TA4 1 2 RS TA5 3 TA6 4 GND 5 TB0 6 TB1 7 VCC 8 9 TB2 10 TB3 GND 11 TB4 12 TB5 13 R/F 14 TB6 15 TC0 16 17 GND TC1 18 TC2 19 TC3 20 VCC 21 TC4 22 TC5 23 GND 24
48 47 46 45 44
43
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
TA3 TA2 GND TA1 TA0 N/C LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ LVDS GND PLL GND PLL VCC PLL GND /PDWN CLK IN TC6
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THC63LVDM83R /THC63LVDM63R_Rev2.0
THC63LVDM83R Pin Description
Pin Name TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 /PDWN Pin # 47, 48 45, 46 41, 42 37, 38 39, 40 51, 52, 54, 55, 56, 3, 4 6, 7, 11, 12, 14, 15, 19 20, 22, 23, 24, 27, 28, 30 50, 2, 8, 10, 16, 18, 25 32 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN IN H: Normal operation, L: Power down (all outputs are Hi-Z) Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
LVDS swing control.
RS 1 IN RS VCC : GND LVDS swing 350mV : 200mV
R/F VCC CLKIN
17 9, 26 31 5, 13, 21, 29, 53 44 36, 43, 49 34 33, 35
IN Power IN
Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in.
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GND LVDS VCC LVDS GND PLL VCC PLL GND
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Power Ground Power Ground Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
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THC63LVDM63R Pin Description
Pin Name TA+, TATB+, TBTC+, TCTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 /PDWN Pin # 40, 41 38, 39 34, 35 32, 33 44, 45, 47, 48, 1, 3, 4 6, 7, 9, 10, 12, 13, 15 16, 18, 19, 20, 22, 23, 25 27 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN H: Normal operation, L: Power down (all outputs are Hi-Z) Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
LVDS swing control.
RS 2 IN RS VCC : GND LVDS swing 350mV : 200mV
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Pin Name R/F VCC CLKIN GND LVDS VCC LVDS GND PLL VCC PLL GND
Pin # 14 8, 21 26 5, 11, 17, 24, 46 37 36, 42 29 28, 30
Type IN Power IN Ground Power Ground Power Ground
Description Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Pins for TTL inputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
Absolute Maximum Ratings 1
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Output Current Junction Temperature Storage Temperature Range -0.3V ~ +4.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) continuous +125 C -55 C ~ +150 C +260 C /10sec .com 0.5W
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Resistance to soldering heat Maximum Power Dissipation @+25 C
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Electrical Characteristics CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VIH VIL IINC IPD IRS Parameter High Level Input Voltage Low Level Input Voltage Input Current Pull Down Current RS Pull Down Current
0V VIN V CC
Conditions
Min. 2.0 GND
Typ.
Max. VCC 0.8
10
Units V V A A A
R/F pin, VIH=VCC RS pin, VIH=VCC
100 100
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. .com
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THC63LVDM83R /THC63LVDM63R_Rev2.0
LVDS Transmitter DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Conditions Normal swing VOD Differential Output Voltage RL=100 RS=VCC Reduced swing RS=GND VOD VOC VOC IOS IOZ Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current Output TRI-STATE Current VOUT=0V, RL=100 /PDWN=0V, VOUT=0V to VCC RL=100 1.125 1.25 35 1.375 35 -24
10
Min. 250
Typ. 350
Max. 450
Units mV
100
200
300
mV
mV V mV mA A
THC63LVDM83R Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Condition(*) RL=100,CL=5pF f=65MHz .com VCC=3.3V, RS=VCC f=85MHz 16 Gray Scale Pattern RL=100,CL=5pF VCC=3.3V, RS=GND 16 Gray Scale Pattern RL=100,CL=5pF VCC=3.3V, RS=VCC ITCCW Transmitter Supply Current Worst Cace Pattern RL=100,CL=5pF VCC=3.3V, RS=GND Worst Cace Pattern ITCCS Transmitter Power Down Supply Current /PDWN = L f=65MHz f=85MHz f=65MHz f=85MHz f=65MHz f=85MHz Typ. 36 39 31 34 38 41 33 36 Max. 46 49 41 44 48 51 43 46 10 Units mA mA mA mA mA mA mA mA A .
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ITCCG Transmitter Supply Current
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THC63LVDM83R /THC63LVDM63R_Rev2.0
THC63LVDM63R Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Condition(*) RL=100,CL=5pF VCC=3.3V, RS=VCC ITCCG Transmitter Supply Current 16 Gray Scale Pattern RL=100,CL=5pF VCC=3.3V, RS=GND 16 Gray Scale Pattern RL=100,CL=5pF VCC=3.3V, RS=VCC ITCCW Transmitter Supply Current Worst Cace Pattern RL=100,CL=5pF VCC=3.3V, RS=GND Worst Cace Pattern ITCCS Transmitter Power Down Supply Current /PDWN = L f=65MHz f=85MHz f=65MHz f=85MHz f=65MHz f=85MHz f=65MHz f=85MHz Typ. 33 37 29 33 35 39 31 35 Max. 41 45 36 39 43 47 38 42 10 Units mA mA mA mA mA mA mA mA A
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THC63LVDM83R /THC63LVDM63R_Rev2.0
16 Gray Scale Pattern CLKIN Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
Worst Case Pattern CLKIN
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Even TxIn Odd TxIN
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol tTCIT tTCP tTCH tTCL tTCD tTS tTH tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 CLK IN Period CLK IN High Time CLK IN Low Time CLK IN to TCLK+/- Delay TTL Data Setup to CLK IN TTL Data Hold from CKL IN LVDS Transition Time Output Data Position0 (T=11.76ns) Output Data Position1 (T=11.76ns) Output Data Position2 (T=11.76ns) Output Data Position3(T=11.76ns) Output Data Position4 (T=11.76ns) -0.2
T -- - 0.2 7 T 2 -- - 0.2 7 3 T - 0.2 -7 4 T - 0.2 -7 7
Parameter CLK IN Transition time
Min. 11.76 0.35T 0.35T 2.5 2.5
Typ. T 0.5T 0.5T 2T/7
Max. 5.0 50.0 0.65T 0.65T
Units ns ns ns ns ns ns ns
0.6 0.0
T -7 T 2 -7 3T -7 4T -7 T 5 -7 T 6 -7
1.5 +0.2
T -- + 0.2 7 T 2 -- + 0.2 7 3 T + 0.2 -7 4 T + 0.2 -7 T 5 -- + 0.2 7 T 6 -- + 0.2 7
ns ns ns ns ns ns ns ns ms
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tTOP3 tTOP2 tTPLL
T .com 0.2 Output Data Position5 (T=11.76ns) 5 -- - -
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Output Data Position6 (T=11.76ns) Phase Lock Loop Set
T 6 -- - 0.2 7
10.0
AC Timing Diagrams TTL Input
90%
90% 10% tTCIT tTCIT 80% 20%
CLK IN
10%
LVDS Output
Vdiff=(TA+)-(TA-) TA+ 5pF TALVDS Output Load 100
80%
Vdiff
20%
tLVT
tLVT
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THC63LVDM83R /THC63LVDM63R_Rev2.0
AC Timing Diagrams TTL Inputs
tTCH tTCP tTCL
VCC/2 VCC/2
CLK IN
VCC/2
tTS
tTH
Tx0-Tx6
VCC/2
DATA VALID
VCC/2
DATA VALID
tTCD
Tx+/-
Tx6
Tx5
Tx4
Tx3
Tx2
Tx1
Tx0
TCLK+
Vdiff = 0V tTOP1 tTOP0
Vdiff = 0V
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tTOP6 tTOP5 tTOP4 tTOP3 tTOP2
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DataShee
Note: 1)CLK IN: for THC63LVDM83R/THC63LVDM63R(R/F=GND), denote as solid line, for THC63LVDM83R/THC63LVDM63R(R/F=VCC), denote as dashed line 2)Vdiff = (Tyx+) - (Tyx-) , ---- (TCLKx+) - (TCLKx-)
Phase Lock Loop Set Time
/PDWN
2.0V 3.6V tTPLL
VCC
3.0V
CLKIN
Vdiff = 0V
TCLKx+/-
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Reduced Swing Characteristic (TA=25C , VCC=3.3V, RL=100)
RS - VOD characteristic
400 300 200 100 0
VOD [mV]
0
1.0
2.0
3.0
4.0
RS [V]
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Package
56 Lead Molded Thin Shrink Small Outline Package, JEDEC
14.0 0.1 56 29
Unit : millimeters
8.1 0.1 4.05
6.1 0.1
1
28 (1.0) 1.2 MAX 0.10 0.05
0.50 TYP
0.20 TYP
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.com 48 Lead Molded Thin Shrink Small Outline Package, JEDEC
Unit : millimeters 25
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12.5 0.1 48
8.1 0.1 4.05
6.1 0.1
1
24 (1.0) 1.2 MAX 0.10 0.05
0.50 TYP
0.20 TYP
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without our permission. 4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVDM83R/ THC63LVDM63R use, except for those directly related to THC63LVDM83R/THC63LVDM63R's structure, manufacture or functions. THC63LVDM83R/THC63LVDM63R is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVDM83R/THC63LVDM63R for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVDM83R/THC63LVDM63R. 7. Judgment on whether THC63LVDM83R/THC63LVDM63R comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVDM83R/THC63LVDM63R, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVDM83R/THC63LVDM63R, be sure to refer to the final technical documents.
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