View PT7A5020_382468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PT Pericom Technology Inc.
Features
* Sixteen full-duplex, serial time-division multiplexed (TDM) highway streams * Switching up to 2,048 incoming PCM channels to up to 2,048 outgoing PCM channels * Accept data rates of 2.048Mb/s, 4.096Mb/s,
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch Introduction
The PT7A5020 is a Multi-rate Large Digital Switch (MLDS). It provides 2,048 x 2,048 channel nonblocking switching among 16 input streams and 16 output streams at most. This device can operate in two modes: Single-Rate mode and Multi-Rate mode. In Single-Rate mode, the all 16 input streams and 16 output streams serial bit rate must be single rate of 8.192Mb/s, 4.096Mb/s or 2.048Mb/s. In Multi-Rate mode, the 16 input streams and the 16 output streams are both divided into two parts, the serial bit rate of each one of the four parts can be 8.192Mb/s, 4.096Mb/s or 2.048Mb/s independently. The device has many features that are programmable on stream or channel basis, including message mode, input offset delay and high impedance output control. Per steam input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input stream can be individually calibrated for input frame offset using a dedicated pin.
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8.192Mb/s (Single-Rate mode) or any combination of data rates of 2.048Mb/s, 4.096Mb/s and 8.192Mb/s (Multi-Rate mode) * 64 kbits/s granularity with optional 32 kbits/s (4bit) and 16 kbits/s (2-bit) subrate switching * Tristate function per-channel for further expansion * Low-latency/frame integrity selection per-channel * Automatic frame offset delay measurement. * Per input stream offset programming * Intel/Motorola microprocessor interface * Connection memory block programming for fast device initialization * Automatically identifies ST-BUS/GCI formats * Internal loopback per-channel for diagnostic purposes * IEEE-1149.1 (JTAG) boundary scan
Applications
* Medium and large switching platforms * CTI application * Voice/data multiplexer * Digital cross-connect * ST-BUS/GCI interface functions * DM highway data rate adaptation * LAN/WAN gateways
Pa r t Nu mb er PT7A5020J PT7A5020M
Pa ck a ge 84 - Pin PLCC 100 - Pin MQFP
PT0088(03/02)
1
Ver:0
PT Pericom Technology Inc.
Block Diagram
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CLK F0i FE/ W FPS HCLK
Shift Out Processor
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15
CTSo STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15
Single & M ultirate Tim ing Serial To Parallel Converter
Connection M em ory Parallel To Serial Converter
Data M em ory
Output Select
Control Register & CPU Interface
JTAG Test
A7-A0
D15-D8/ AD7-AD0 AS/ ALE
IM DS/ RD
CS
DTA TDI TCK IC R/W / TM S TDO TRST RESET WR
PT0088(03/02)
2
Ver:0
PT Pericom Technology Inc.
Pin Information
Pin Configuration
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
84 Pin PLCC
PT0088(03/02)
WFPS
WFPS
100 Pin MQFP
3
Ver:0
PT Pericom Technology Inc.
Pin Description
P in No. 84-PLCC 1, 11, 30, 54 64, 75 2, 32, 63 3 - 10 77 - 84 12 -27 100-MQFP 31, 41, 56, 66, 76, 99 5, 40, 67 68-75 58 - 65 81-96 Typ e Na m e
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Descr ip t ion
GND
GND
Ground.
Power
VCC STo8 - 15 STo0 - 7 STi0 - 15
+5V Power Supply. ST-BUS Output (Three-state Outputs): Serial data Output streame, data rates of 2.048, 4.096 or 8.192 Mb/s, programmable by bits DR0 - 1 in the IMS register. ST-BUS Input: Serial data input stream, data rates of 2.048, 4.096 or 8.192 Mb/s, programmable by bits DR0 - 1 in the IMS register. Frame Pulse: accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications when WFPS=0, and accepts a negative frame pulse which conforms to WFPS formats when WFPS=1. Frame Evaluation/HCLK Clock: frame measurement input when WFPS=0, when WFPS=1, the HCLK (4.096MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. Clock: Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15). In Single-Rate mode, this input accepts a 4.096, 8.192 or 16.384 MHz clock; in Multi-Rate mode, this pin only accepts 16.384 MHz clock.. Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP controller. Pulled high by an internal pull-up when not driven. Test Serial Data In: input for JTAG serial test instructions and data, pulled high by an internal pull-up when not driven. Test Serial Data Out: output for JTAG serial data on the falling edge of TCK. It is held in high impedance state when JTAG scan is not enable. Test Clock: clock to the JTAG test logic. Pulled high by an internal pull-up when not driven. Test Reset: Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the device is in the normal functional mode. Internal Connection: Connect to GND for normal operation. This pin must be low for normal operation and to comply with IEEE 1149 (JTAG) boundary scan requirements. It is pulled low internally when not driven. Device Reset (Schmitt Trigger Input): active LOW, reset the device by clearing the device internal counters, registers and setting STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100nsec to reset the device.
Ver:0
O
I
28
97
I
F0i
29
98
I
FE/HCLK
31
100
I
CLK
33 34
6 7
I I
TMS TDI
35
8
O
TDO
36
9
I
TCK
37
10
I
TRST
38
11
I
IC
39
12
I
RESET
PT0088(03/02)
4
PT Pericom Technology Inc.
P in No. 84-PLCC 40 41-48 100-MQFP 13 14-21 Typ e Na m e WFPS A0-A7 I I
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Descr ip t ion
Wide Frame Pulse Select: When 1, enables the WFP Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. Address 0 - 7: in non-multiplexed CPU bus operation, these lines provide the A0 - A7 address lines to the internal memories. Data Strobe / Read: For Motorola multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. Read/Write / Write: In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For Intel multiplexed bus operation, this input is WR. This active low input is used with CS to control the data bus (AD0 - 7, D8 - D15) lines as inputs. Chip Select: Active low input used by a processor to activate the microprocessor port of MLDS. Address Strobe or Latch Enable: This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. C P U I n t e r f a c e Mo d e : Wh e n I M i s h i g h , t h e m i c r o p r o c e s s o r p o r t i s i n t h e multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. Address/Data Bus 0 to 7: These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. D a t a B u s 8 - 1 5 : T h e s e p i n s a r e t h e e i g h t m o s t s i g n i fi c a n t d a t a b i t s o f t h e microprocessor port. Data Transfer Acknowledgement: Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. Control Output: This is a 4.096, 8.192 or 16.384Mb/s output containing 512, 1024 or 2048 bits per frame respectively in Single-Rate mode. In Multi-Rate mode, this output rate is 16.384 Mb/s. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. Output Drive Enable: This is the output enable control for the STo0 to STo15 serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo0-15 are in a high impedance state. If this input is high, the STo0-15 output drivers are enabled. However, each channel may still be put into a high impedance state by using the per channel control bit in the connection memory.
49
22
DS/RD
I
50
23
R/W / WR
I
51
24
CS
I
52
25
AS/ALE
I
53
26
IM
I
55-62
32-39
AD0-7
I/O
65-72
42-49
D8-15
I/O
73
50
DTA
O
74
55
CSTo
O
76
57
ODE
I
-
1-4 27-30 51-54 77-80
NC
No connection
PT0088(03/02)
5
Ver:0
PT Pericom Technology Inc.
Absolute Maximum Ratings
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Storage Temperature ........................................................-65oC to +125oC Ambient Temperature with Power Applied ........................ -40oC to +85oC Supply Voltage to Ground Potential (Inputs & Vcc) ........... -0.3V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) -0.3V to +7.0V DC Input Voltage ............................................................... -0.3V to +7.0V DC Input and Output Current .......................................................... 20mA Power Dissipation ................................................................................ 2W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Sym Vcc VIH VIL TA C h a r a ct er ist ics Supply Votage Input HIGH Voltage Input LOW Voltage Operating Temperature Test C on d it ion s Min 4.75 2.4 0 -40 25 Typ 5.0 Ma x 5.25 Vcc 0.4 85 Un it s V V V
O
C
Note: Typical figures are at 25oC and are for design aid only; not production tested.
PT0088(03/02)
6
Ver:0
PT Pericom Technology Inc.
Sym Descr ip t ion
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical, Power Supply and Capacitance Characteristics
Test C on d it ion s Output unloaded, 2Mb/s ICC Supply Current Output unloaded, 4Mb/s Output unloaded, 8Mb/s VIH VIL Input HIGH Voltage Input LOW Voltage Input Leakage Current (Input Pins) IIL Input Leakage Current(with an internal pull-up or -down) Output LOW Voltage Output HIGH Voltage Output High Impedance Leakage Input Pin Capacitance Output Pin Capacitance VO between GND and VCC 100 IOL = 10mA IOH = 10mA VO between GND and VCC 2.4 1.0 3.5 5 10 10 V V pF pF 2.0 0.8 15 Min Typ Ma x 50 90 170 Un it s mA mA mA V V
VOL VOH IOZ CIN COUT
AC Electrical Characteristics
Sym VTT VHM VLM Descr ip t ion TTL Threshold TTL Rise/Fall Threshold Voltage High TTL Rise/Fall Threshold Voltage Low Test C on d it ion s Min Typ 1.5 Ma x Un it s V V V
2.0 0.8
PT0088(03/02)
7
Ver:0
PT Pericom Technology Inc.
Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes
Pericom Technology Inc.
Email: support@pti.com.cn China: Asia Pacific: U.S.A.: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0088(03/02)
8
Ver:0

▲Up To Search▲

Price & Availability of PT7A5020

	To Download PT7A5020 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .