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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER BiCMOS LVPECL OC-48 TRANSMITTER AND RECEIVER CLOCK GENERATOR SONET/SDH/ATM OC-12 DIFFERENTIAL 1:16 RECEIVER GENERAL DESCRIPTION
S3064 S3064 S3064
FEATURES
* Micro-power Bipolar technology * Complies with Bellcore and ITU-T specifications * Supports 2.488 Gbps (OC-48) * Interface to both LVPECL and TTL logic * 16-bit Differential LVPECL data path * Compact 100 TQFP/TEP package * Diagnostic loopback mode * Line loopback * Signal detect input * Low jitter LVPECL interface * Single 3.3V supply * Typical Power 990 mW
The S3064 SONET/SDH DeMUX chip is a fully integrated deserialization SONET OC-48 (2.488 Gbps) interface device. The chip performs all necessary serial-to-parallel and framing functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications. Figure 1 shows a typical network application. The low jitter LVPECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3064 is packaged in a 100 TQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
Network Interface Processor
16
S3063 Tx S3064 Rx
OTX
ORX
S3056
S3064 16 Rx S3063 Tx
16
16
S3056
ORX
OTX
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Network Interface Processor
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S3064 SONET OVERVIEW
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48 consists of 144 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates.
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Photonic layer
Photonic layer
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STM-1 STM-4 STM-8 STM-16 CCITT Optical OC-1 OC-3 OC-12 OC-24 OC-48 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N). The S3064 chip supports the OC-48 data rate (2.488 Gbps).
Figure 3. STS-48/OC-48 Frame Format
A1 A1 A1 A1 48 A1 Bytes A2 A2 A2 A2 48 A2 Bytes
9 Rows
Transport Overhead 144 Columns 144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes
2
v
125 sec
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v
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER S3064 OVERVIEW
The S3064 receiver implements SONET/SDH deserialization and frame detection functions. The block diagram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes serial-to-parallel conversion and system timing. The system timing circuitry consists of management of the datastream, framing, and clock distribution throughout the front end.
S3064
The sequence of operations of the S3064 is as follows:
Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 16-bit parallel output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7 through 9. Internal clocking and control functions are transparent to the user.
Suggested Interface Devices
AMCC AMCC S3056 S3063 Clock Recovery Device OC-48 Transmitter
Figure 4. S3064 Functional Block Diagram
SDPECL
1:16 SERIAL TO PARALLEL
16
POUTP/N[15:0]
KILLRXCLK OOF FRAMEN DLEB RSDP/N
D M U X D M U X TIMING FRAME GEN BYTE DETECT
RX155MCKP/N POCLKP/N FPP/N SEARCH LLDP/N
LSDP/N RSCLKP/N LSCLKP/N
LLCLKP/N LLEB RSTB
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S3064 RECEIVER OPERATION
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
pattern would occur within one frame of data. Therefore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 s, even for extremely high bit error rates.
The S3064 receiver chip provides the first stage of digital processing of a receive SONET STS-48 bitserial stream. It converts the bit-serial 2.488 Gbps data stream into a 155.52 Mbyte/sec parallel data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). A Line Loopback (receiver to transmitter) is also provided.
Serial to Parallel Converter
The serial to parallel converter consists of three 16-bit registers. The first is a serial-in, parallel-out shift register, which performs serial to parallel conversion. The second is an 16-bit internal holding register, which transfers data from the serial to parallel register on byte boundaries as determined by the frame and byte boundary detection block. On the falling edge of the free running POCLK, the data in the holding register is transferred to an output holding register which drives POUTP/N[15:0].
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by one A2 byte. Framing pattern detection is enabled and disabled by the FRAMEN input. Detection is enabled by a rising edge on OOF when FRAMEN is active. It is disabled when a framing pattern is detected. When framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (RSD or looped transmitter data). During this time, the parallel data bus (POUTP/N[15:0]) will not contain valid data. The timing generator block takes the located byte boundary and uses it to block the incoming data stream into bytes for output on the parallel output data bus (POUTP/N[15:0]). The frame boundary is reported on the frame pulse (FP) output when any 32-bit pattern matching the framing pattern is detected on the incoming data stream. When framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. Only framing patterns aligned to the fixed byte boundary are indicated on the FP output. The probability that random data in an STS-48 stream will generate the 32-bit framing pattern is extremely small. It is highly improbable that a mimic
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output clock and data from the transmitter (LSCLK and LSD) is routed to the serial-to-parallel block in place of the normal data stream (RSCLK and RSD). When DLEB is asserted, SDPECL shall be ignored.
Line Loopback
The Line Loopback circuitry consists of alternate clock and data output drivers. When LLEB is active, it enables the Line Loopback output data and clock (LLD and LLCLK) and a receive-to-transmit loopback can be established at the serial data rate.
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Table 2. Input Pin Assignment and Description
Pin Name RSDP RSDN Level Internally Biased Diff. LVPECL Internally Biased Diff. LVPECL Diff. LVPECL Diff. LVPECL I/O I Pin # 4 5 Description
S3064
Receive Serial Data. Serial data stream signals normally connected to an optical receiver module. These inputs are clocked by the RSCLK inputs. Internally biased and terminated. Receive Serial Clock. Recovered clock signal that is synchronous with the RSD inputs. This clock is used by the receive section as the master clock to perform framing and deserialization functions. Internally biased and terminated. Loopback Serial Data. Serial data stream signals normally connected to the transmitter for loopback testing. These inputs are clocked by the LSCLK inputs. Internally terminated. Loopback Serial Clock. Clock input from the transmitter that is synchronous with the LSD inputs. This clock is used during local loopback testing to perform the framing and deserialization functions. Internally terminated. Out of Frame. Indicator used to enable framing pattern detection logic in the S3064. The framing pattern detection logic is enabled by a rising edge on OOF, and remains enabled until frame boundary is detected. OOF is an asynchronous signal with a minimum pulse width of one POCLK period. (See Figures 10 and 11.) LVPECL Signal Detect. Active High. A single-ended LVPECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDPECL is inactive, the data on the Serial Data In (RSDP/N) pins will be internally forced to a constant zero. When SDPECL is active, data on the RSDP/N pins will be processed normally. SDPECL will not affect the serial data path when DLEB is active. Diagnostic Loopback Enable. Selects diagnostic loopback. Active Low. When DLEB is inactive, the S3064 device uses the primary data (RSD) and clock (RSCLK) inputs. When active, the S3064 device uses the diagnostic loopback clock and data from the transmitter. Master Reset. Reset input for the device. Active Low. During reset, POCLK does not toggle. Line Loopback Enable. Selects Line Loopback. Active Low. When LLEB is active, the S3064 will enable the data from the LLD/LLCLK outputs. Kill Receive Clock Input. For normal operation set KILLRXCLK "High." When this input is low, it will force RX155 MCK and POCLK outputs to a logic "0" state. Frame Enable Input. For normal operation set FRAMEN High. This enables the frame detector circuit to detect A1 A2 alignment and lock to word boundary. When this input is Low, it will disable the frame detector circuit and it will lock on the last byte alignment state.
RSCLKP RSCLKN
I
8 9
LSDP LSDN LSCLKP LSCLKN
I
92 91 100 99
I
OOF
LVTTL
I
17
SDPECL SingleEnded LVPECL
I
20
DLEB
LVTTL
I
22
RSTB
LVTTL
I
25
LLEB
LVTTL
I
21
KILLRXCLK
LVTTL
I
19
FRAMEN
LVTTL
I
18
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S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Table 3. Output Pin Assignment and Description
Pin Name POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POUTP4 POUTN4 POUTP5 POUTN5 POUTP6 POUTN6 POUTP7 POUTN7 POUTP8 POUTN8 POUTP9 POUTN9 POUTP10 POUTN10 POUTP11 POUTN11 POUTP12 POUTN12 POUTP13 POUTN13 POUTP14 POUTN14 POUTP15 POUTN15 LLDP LLDN LLCLKP LLCLKN Level Diff. LVPECL I/O O Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 54 55 56 57 58 59 60 61 62 63 64 65 66 67 77 76 86 85 Description Parallel Output. Parallel data bus, a 155.52 Mbyte/sec 16-bit word, aligned to the parallel output clock (POCLK). POUT[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUT[0] is the least significant bit (corresponding to bit 16 of each PCM word, the last bit received). POUT[15:0] is updated on the falling edge of POCLK.
Low Swing Diff. CML Diff. CML
O
Line Loopback Data. A retimed version of the incoming data stream [RSD]. Enabled by LLEB. Line Loopback Clock. A buffered version of the RSCLK or LSCLK input. Enabled by LLEB.
O
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Table 3. Output Pin Assignment and Description (Continued)
Pin Name FPP FPN Level Diff. LVPECL I/O O Pin # 31 32 Description
S3064
Frame Pulse. Indicates frame boundaries in the incoming data stream. If framing pattern detection is enabled, as controlled by the OOF input, FP pulses high for one POCLK cycle when a 32-bit sequence matching the framing pattern is detected on the serial data inputs. When framing pattern detection is disabled, FP pulses high when the incoming data stream, after byte alignment, matches the framing pattern. FP is updated on the falling edge of POCLK. Parallel Output Clock. A 155.52 MHz nominally 50% duty cycle, byte rate output clock, that is aligned to POUTP/N[15:0] byte serial output data. POUTP/N[15:0] and FP are updated on the falling edge of POCLK. A1 A2 Frame Search Output. A High on this output pin indicates the frame detection circuit is activated and it is searching for a new A1 A2 byte alignment. This output will be High during the entire period of A1 A2 frame search. Once a new alignment is found, this signal will remain High for a minimum of one 155.52 MHz clock period beyond the third A2 byte before it will be set to Low. Receive Free Running 155.52 MHz Clock Output. This clock is generated by dividing the RSCLK signal by sixteen.
POCLKP POCLKN
Diff. LVPECL
O
68 69
SEARCH
LVTTL
O
26
RX155MCKP RX155MCKN
Diff. LVPECL
O
29 30
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S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Table 4. Common Pin Assignment and Description
Pin Name CORE_GND Level GND I/O Pin # 11, 13, 15, 72, 87, 88 10, 12, 14, 73, 89, 90 1, 6, 27, 53, 71, 79, 83, 84, 94, 97, 98 2, 3, 7, 28, 51, 52, 70, 78, 81, 82, 93, 95, 96 16 24 23 74, 75, 80 Core Ground Description
CORE_VCC
+3.3V
Core VCC
LVP_VCC
+3.3V
LVPECL VCC
LVP_GND
GND
LVPECL Ground
TTL_VCC TTL_GND THD NC
+3.3V GND
TTL VCC TTL Ground Thermal Diode Not Connected
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Figure 5. S3064 Pinout
LSCLKP LSCLKN LVP_VCC LVP_VCC LVP_GND LVP_GND LVP_VCC LVP_GND LSDP LSDN CORE_VCC CORE_VCC CORE_GND CORE_GND LLCLKP LLCLKN LVP_VCC LVP_VCC LVP_GND LVP_GND NC LVP_VCC LVP_GND LLDP LLDN
S3064
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SEARCH LVP_VCC LVP_GND RX155MCKP RX155MCKN FPP FPN POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POUTP4 POUTN4 POUTP5 POUTN5 POUTP6 POUTN6 POUTP7 POUTN7 POUTP8 POUTN8
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LVP_VCC LVP_GND LVP_GND RSDP RSDN LVP_VCC LVP_GND RSCLKP RSCLKN CORE_VCC CORE_GND CORE_VCC CORE_GND CORE_VCC CORE_GND TTL_VCC OOF FRAMEN KILLRXCLK SDPECL LLEB DLEB THD TTL_GND RSTB
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S3064 Pinout Top View
100 TQFP/TEP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC CORE_VCC CORE_GND LVP_VCC LVP_GND POCLKN POCLKP POUTN15 POUTP15 POUTN14 POUTP14 POUTN13 POUTP13 POUTN12 POUTP12 POUTN11 POUTP11 POUTN10 POUTP10 POUTN9 POUTP9 LVP_VCC LVP_GND LVP_GND
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S3064
Figure 6. 100 TQFP/TEP Package
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
TOP VIEW
SIDE VIEW
Thermal Management
Device S3064
1. Add 45 mA for loopback active. 2. Open outputs.
Max Power 1.32 W
jc 2.5C/W
Note: The S3064 package is equipped with an embedded conductive heatsink on the top (board side).
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Table 5. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on Vcc with Respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Input Pin High Speed LVPECL Output Source Current Min -65 -0.5 0 -0.5 Typ Max 150 +5.0 VCC +5.5 50 Units C V V V mA
S3064
ESD Ratings The S3064 is rated to the following voltages based on the human body model: 1. All pins are rated at or above 2000 V except THD, LSCLKP/N, LSDP/N, LLDP/N.
Table 6. Recommended Operating Conditions
Parameter Case Temperature Under Bias Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Pin Min 0 3.13 VCC -2 0 3.3 Typ Max 100 3.47 VCC 3.47 Units C V V V
Table 7. Power Consumption
Parameter I CC
1,2
Min
Typ 300
Max 380
Units mA
1. Add 45mA for loopback active. 2. Open outputs.
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SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Table 8. Low Swing Differential CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF (Data) VOUTSINGLE (Data) Description Low Swing CML Output LOW Voltage Low Swing CML Output HIGH Voltage Low Swing CML Serial Output Differential Voltage Swing Low Swing CML Serial Output Single-ended Voltage Swing Min VCC -0.55 VCC -0.25 360 180 Typ Max VCC -0.25 VCC -0.05 800 400 Units V V mV mV Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. 100 line-to-line.
Table 9. Differential CML Output DC Characteristics
Parameter VOL VOH VOUTDIFF Clock VOUTSINGLEClock Description CML Output LOW Voltage CML Output HIGH Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing Min VCC -1.05 VCC -0.45 700 350 Typ Max VCC -0.55 VCC -0.10 1300 650 Units V V mV mV Condition 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 13. 100 line-to-line. See Figure 13.
Table 10. Internally Biased Differential LVPECL Input DC Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Differential Input Single-Ended Swing Differential Input Resistance Min 300 150 80 100 Typ Max 1200 600 120 Units mV mV Conditions See Figure 13. See Figure 13.
Table 11. Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Differential Input Single-Ended Swing Differential Input Resistance Min VCC -2.000 VCC -1.20 300 150 80 100 Typ Max VCC -0.25 VCC -0.05 1200 600 120 Units V V mV mV See Figure 13. See Figure 13. Conditions
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Table 12. Single Ended LVPECL Input DC Characteristics1
Parameters Description Min VCC -2.30 VIL PECL Input Low Voltage VCC -2.30 VCC -1.02 VIH PECL Input High Voltage VCC -1.22 Input High Current Input Low Current -0.5 VCC -0.57 20 V A A Guaranteed at -40 C. VCC -1.50 VCC -0.57 V V Guaranteed at -40 C. Guaranteed at +85 C. Max VCC -1.44 Units V Conditions Guaranteed at +85 C.
S3064
IIH IIL
1. The AMCC LVPECL inputs are non-temperature compensated I/O which vary at 1.3 mV/C.
Table 13. Low Speed Differential LVPECL Output DC Characteristics
Parameters VOUTSINGLE VOUTDIFF VOH VOL RLOAD Description Single Ended Output Voltage Swing Diff. Output Voltage Swing Output High Voltage Output Low Voltage Min 320 640 VCC -1.15 VCC -1.95 220 Max 950 1900 VCC -0.60 VCC -1.45 Units mV mV V V Comments 220 to GND and100 lineto-line. See Figure 13. 220 to GND and100 lineto-line. See Figure 13. 220 to GND and100 lineto-line. 220 to GND and100 lineto-line.
Table 14. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage -500 2.2 Min 2.0 0.0 Max TTL VCC 0.8 50 Unit V V A A V Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min VIL = Max IOH = -100 A VIH = Min VIL = Max IoL = 4 mA
VOL
Output Low Voltage
0.5
V
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S3064
Symbol (note 1,3) tPPOUT1 tSPOUT1 tHPOUT1 tSRSD2 tHRSD2 tSLLD tHLLD (note 2) (note 2,3) (note 1) (note 2,3) POCLK Duty Cycle
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Description Min 45 -1 2 2 75 75 150 70 40 0 45 55 1.0 40 60 75 75 Max 55 +1 Units % ns ns ns ps ps ps ps ps % ns % ps ps
Table 16. AC Receiver Timing Characteristics
POCLK Low to POUT [15:0] Valid Prop. Delay POUT[15:0] and FP Set-up Time w.r.t. POCLK POUT[15:0] and FP Hold Time w.r.t. POCLK RSDP/N Set-up Time w.r.t. RSCLKP/N RSDP/N Hold Time w.r.t. RSCLKP/N LLDP/N Set-Up Time w.r.t. LLCLKP/N LLDP/N Hold Time w.r.t. LLCLKP/N RSCLK/LSCLK Clock Period RSCLK Clock Duty Cycle POUT [15:0] Rise and Fall Time LSCLK Duty Cycle Set-up time for LSDP/N w.r.t. LSCLK Hold Time for LSCLKP/N w.r.t. LSCLK
1. 220 to GND and 100 line-to-line. 2. 100 line-to line. 3. Zero crossing to zero crossing.
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Figure 7. Output Timing Diagram
POCLKP tP POUT POUTP/N[15:0], FP tS POUT tH POUT
S3064
Figure 8. Receiver Input Timing Diagram
RSCLKP tSRSD RSDP/N
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
tHRSD
Figure 9. LLD Output Timing
LLCLKP tSLLD LLDP/N tHLLD
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S3064 RECEIVER FRAMING
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. Both boundaries are recognized upon receipt of the first A2 byte. The third A2 byte is the first data byte to be reported with the correct byte alignment on the outgoing data bus (POUTP/N[15:0]). Concurrently, the frame pulse is set high for one POCLK cycle.
The frame and byte boundary detection block is activated by the rising edge of OOF, and stays active until the first FP pulse. Figure 11 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the first FP pulse. Figure 12 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the FRAMEN input.
Figure 10. Frame and Byte Detection
RECOVERED CLOCK/ REFCLK OOF SERDATI A1 A1 A1 A2 A2 A2 A2 A2 Note 1
POUT[15:0]
A1, A1 Invalid Data
A1, A1
A1, A1
A2, A2
A2, A2
Valid Data POCLK FP
1. Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
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Figure 11. OOF Timing (FRAMEN = 1)
S3064
BOUNDARY DETECTION ENABLED
OOF
FP
SEARCH
Figure 12. FRAMEN Timing
BOUNDARY DETECTION ENABLED
OOF
FRAMEN
FP
SEARCH
Figure 13. Differential Voltage Measurement
V(+) VSWING V(-)
V(+) - V(-) VD = 2 X VSWING 0.0V
Note: V(+) - V(-) is the algebraic difference of the input signals.
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S3064
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Figure 14. +5V Differential PECL Driver to S3064 Internally Biased Differential LVPECL Input AC Coupled Termination
+5V 0.01F 330 Zo=50
Vcc -0.70V (DC AVG)
+3.3V
100 Zo=50
330
0.01F
Vcc -0.70V (DC AVG) S3064 RSDP/N RSCLKP/N
Figure 15. S3056 to S3064 Internally Biased Differential LVPECL Input DC Terminations
+3.3V Zo=50
Vcc -0.70V +3.3V (DC AVG)
100
Zo=50 S3056 SERDATOP/N SERCLKOP/N
Vcc -0.70V (DC AVG) S3064 RSDP/N RSCLKP/N
Figure 16. S3064 Differential CML Output to S3063 Terminations
+3.3V 0.01 F Zo=50
VCC
+3.3V
100 k
VCC
100 k 0.01 F S3064 LLCLKP/N LLDP/N Zo=50
100
S3063 LLCLKP/N LLDP/N
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Figure 17. S3064 Differential PECL Output
S3064
+3.3V 0.1 F Zo=50 0.1 F 220 S3064 POUTP/N [15:0] 220 Zo=50
VCC 82 130 VCC 82 130
+3.3V
Figure 18. Differential PECL Output Termination
+3.3V Zo=50
VCC 82 130 Zo=50 VCC 82 130
+3.3V
S3064 POUTP/N [15:0]
Figure 19. Differential PECL Output Termination to S3064 Internally Biased Differential LVPECL Input DC Terminations
+3.3V Zo=50 100 150 Differential Driver 150 Zo=50
+3.3V
S3064 RSDP/N RSCLKP/N
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S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
Figure 20. S3063 to S3064 for Diagnostic Loopback
+3.3V Zo=50 100 Zo=50 S3063 LSDP/N LSCLKP/N S3064 LSDP/N LSCLKP/N
+3.3V
Figure 21. Single-Ended LVPECL Driver to S3064 Input AC Coupled Termination
Vcc 0.01F Zo=50 300 0.01F
Vcc -0.70V (DC AVG)
+3.3V
60 Vcc -0.70V (DC AVG)
Single-Ended Driver
S3064 RSDP/N RSCLKP/N
20
December 6, 1999 / Revision NC
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER S3064 SONET/SDH/ATM OC-48 1:16 RECEIVER S3064
Ordering Information
PREFIX DEVICE PACKAGE
S - Integrated Circuit
3064
TT - 100 TQFP/TEP
X Prefix
XXXX Device
XX Package
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
December 6, 1999 / Revision NC
E
CE
RT
21

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