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| ADD3X ATL35 CMOS Gate Array DESCRIPTION: 1 bit full adder with buffered outputs cell data sheets 1.0 Truth Table: P Q CI | SO CO ------------------000 | 0 0 001 | 1 0 010 | 1 0 011 | 0 1 100 | 1 0 101 | 0 1 110 | 0 1 111 | 1 1 P Q SO ADD3X CO ATL55Cells CI p P31 P VDD! p N33 n n N61 VDD! VSS! VDD! p P64 P88 VDD! N85 n p P82 SO p P68 p P91 p P58 p P38 n n N84 VSS! N89 N65 n n N54 VDD! VSS! N39 n VSS! VDD! p P7 Q p P70 p P94 VDD! n N11 VSS! CI n N72 VSS! N96 n p P77 CO p P98 n N79 VSS! N100 n /tech/common/scripts/dataSheetGenerator/createCellFolder.pl ($Revision: 1.35 $) Mon Oct 20 15:24:00 1997 1 ADD3X ATL35 CMOS Gate Array DESCRIPTION: 1 bit full adder with buffered outputs cell data sheets 1.0 SITES: Core = 10 Ring = 0 IO = 0 LOADS: CI=2.0 P=2.0 Q=2.0 TIMING TABLE 3V: Path ---CI -> SO CI -> CO P -> SO P -> CO Q -> SO Q -> CO Rise Slope ---------0.02771 0.02743 0.02766 0.02751 0.02750 0.02755 (NomProc,25degC,Nom trf) Rise Int -------0.36283 0.30031 0.53600 0.53227 0.63993 0.54121 Fall Slope ---------0.02524 0.02534 0.02529 0.02533 0.02527 0.02530 Fall Int -------0.34403 0.34854 0.48636 0.61277 0.47152 0.30263 ADD3X 3v 25 deg Typical Case Path Delays CI -> SO rise CI -> SO fall CI -> CO rise CI -> CO fall P -> SO rise P -> SO fall P -> CO rise P -> CO fall Q -> SO rise Q -> SO fall Q -> CO rise Q -> CO fall 10 Delay in (ns) 1 0.1 1 10 Number of unit loads 100 /tech/common/scripts/dataSheetGenerator/createCellFolder.pl ($Revision: 1.35 $) Mon Oct 20 15:24:00 1997 2 |
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