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 Preliminary User's Manual
78K0/KD1
8-Bit Single-Chip Microcontrollers
PD780121 PD780122 PD780123 PD780124 PD78F0124
PD780121(A) PD780122(A) PD780123(A) PD780124(A) PD78F0124(A)
PD780121(A1) PD780122(A1) PD780123(A1) PD780124(A1)
Document No. U16315EJ1V0UD00 (1st edition) Date Published July 2002 N CP(K)
(c)
Printed in Japan
2002
[MEMO]
2
Preliminary User's Manual U16315EJ1V0UD
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. Ethernet is a trademark of Xerox Corp. OSF/Motif is a trademark of Open Software Foundation, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
Preliminary User's Manual U16315EJ1V0UD
3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: PD78F0124, 78F0124(A) The customer must judge the need for a license: PD780121, 780122, 780123, 780124, 780121(A), 780122(A), 780123(A), 780124(A), 780121(A1), 780122(A1), 780123(A1), 780124(A1)
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M5D 98. 12
4
Preliminary User's Manual U16315EJ1V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
* Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany * United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
J02.4
Preliminary User's Manual U16315EJ1V0UD
5
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the 78K0/KD1 Series and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KD1 Series: PD780121, 780122, 780123, 780124, 78F0124, 780121(A), 780122(A), 780123(A), 780124(A), 78F0124(A), 780121(A1), 780122(A1), 780123(A1), 780124(A1)
Purpose
This manual is intended to give users an understanding of the functions described in the Organization below.
Organization
The 78K0/KD1 Series manual is separated into two parts: instructions edition (common to the 78K/0 Series).
this manual and the
78K0/KD1 User's Manual (This Manual)
78K/0 Series User's Manual Instructions
* Pin functions * Internal block functions * Interrupts * Other on-chip peripheral functions * Electrical specifications (target values)
* CPU functions * Instruction set * Explanation of each instruction
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Preliminary User's Manual U16315EJ1V0UD
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) products and (A1) products: Only the quality grade differs between standard products and (A) and (A1) products. Read the part number as follows.
* * * * *
PD780121 PD780121(A), 780121(A1) PD780122 PD780122(A), 780122(A1) PD780123 PD780123(A), 780123(A1) PD780124 PD780124(A), 780124(A1) PD78F0124 PD78F0124(A)
* To gain a general understanding of functions: Read this manual in the order of the CONTENTS. * How to interpret the register format: For a bit number enclosed in square, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the C compiler. * To check the details of a register when you know the register name: Refer to APPENDIX C REGISTER INDEX. * To know details of the 78K/0 Series instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Caution Examples in this manual employ the "standard" quality grade for general electronics. circuit actually used. Conventions Data significance: Note: Caution: Remark: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention When using examples in this manual for the "special" quality grade, review the quality grade of each part and/or
Active low representations: xxx (overscore over pin and signal name)
Supplementary information ... xxxx or xxxxB Numerical representations: Binary ... xxxx Decimal Hexadecimal ... xxxxH
Preliminary User's Manual U16315EJ1V0UD
7
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name 78K0/KD1 User's Manual 78K/0 Series Instructions User's Manual Document No. This manual U12326E
Documents Related to Development Tools (Software) (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows Based) External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based)
TM
Document No. U14445E U14446E U11789E U14297E U14298E U15373E U15802E U15185E U11537E U11536E U14610E
Documents Related to Development Tools (Hardware) (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780148-NS-EM1 Emulation Board Document No. U13731E U14889E To be prepared
Documents Related to Flash Memory Programming
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Product & Packages - Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
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Preliminary User's Manual U16315EJ1V0UD
CONTENTS
CHAPTER 1 OUTLINE .............................................................................................................................25 1.1 Features .......................................................................................................................................25 1.2 Applications.................................................................................................................................26 1.3 Ordering Information ..................................................................................................................27 1.4 Pin Configuration (Top View).....................................................................................................29 1.5 78K0/Kxx Series Lineup .............................................................................................................31 1.6 Block Diagram .............................................................................................................................33 1.7 Outline of Functions ...................................................................................................................34 CHAPTER 2 PIN FUNCTIONS ................................................................................................................36 2.1 Pin Function List .........................................................................................................................36 2.2 Description of Pin Functions .....................................................................................................39
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 P00 to P03 (port 0) .........................................................................................................................39 P10 to P17 (port 1) .........................................................................................................................39 P20 to P27 (port 2) .........................................................................................................................40 P30 to P33 (port 3) .........................................................................................................................40 P60 to P63 (port 6) .........................................................................................................................40 P70 to P77 (port 7) .........................................................................................................................40 P120 (port 12).................................................................................................................................41 P130 (port 13).................................................................................................................................41 P140 (port 14).................................................................................................................................41
2.2.10 AVREF .............................................................................................................................................41 2.2.11 AVSS ..............................................................................................................................................41 2.2.12 RESET ...........................................................................................................................................42 2.2.13 REGC .............................................................................................................................................42 2.2.14 X1 and X2.......................................................................................................................................42 2.2.15 XT1 and XT2 ..................................................................................................................................42 2.2.16 VDD and EVDD ................................................................................................................................42 2.2.17 VSS and EVSS .................................................................................................................................42 2.2.18 VPP (flash memory versions only) ...................................................................................................42 2.2.19 IC (mask ROM versions only).........................................................................................................42
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins..........................................43
CHAPTER 3 CPU ARCHITECTURE .......................................................................................................46 3.1 Memory Space.............................................................................................................................46
3.1.1 3.1.2 3.1.3 3.1.4 Internal program memory space.....................................................................................................52 Internal data memory space ...........................................................................................................53 Special function register (SFR) area...............................................................................................53 Data memory addressing ...............................................................................................................54 Control registers .............................................................................................................................59 General-purpose registers..............................................................................................................62 Special Function Registers (SFRs).................................................................................................63 Relative addressing ........................................................................................................................67
Preliminary User's Manual U16315EJ1V0UD
3.2
Processor Registers ...................................................................................................................59
3.2.1 3.2.2 3.2.3
3.3
Instruction Address Addressing ...............................................................................................67
3.3.1
9
3.3.2 3.3.3 3.3.4
Immediate addressing ................................................................................................................... 68 Table indirect addressing............................................................................................................... 69 Register addressing....................................................................................................................... 69 Implied addressing......................................................................................................................... 70 Register addressing....................................................................................................................... 71 Direct addressing........................................................................................................................... 72 Short direct addressing.................................................................................................................. 73 Special function register (SFR) addressing ................................................................................... 74 Register indirect addressing .......................................................................................................... 75 Based addressing .......................................................................................................................... 76 Based indexed addressing ............................................................................................................ 77 Stack addressing ........................................................................................................................... 77
3.4
Operand Address Addressing .................................................................................................. 70
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 78 4.1 Port Functions ............................................................................................................................ 78 4.2 Port Configuration...................................................................................................................... 80
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Port 0 ............................................................................................................................................. 81 Port 1 ............................................................................................................................................. 84 Port 2 ............................................................................................................................................. 90 Port 3 ............................................................................................................................................. 91 Port 6 ............................................................................................................................................. 93 Port 7 ............................................................................................................................................. 94 Port 12 ........................................................................................................................................... 95 Port 13 ........................................................................................................................................... 96 Port 14 ........................................................................................................................................... 97
4.3 4.4
Registers Controlling Port Function ........................................................................................ 98 Port Function Operations ........................................................................................................ 102
4.4.1 4.4.2 4.4.3 Writing to I/O port......................................................................................................................... 102 Reading from I/O port .................................................................................................................. 102 Operations on I/O port ................................................................................................................. 102
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 103 5.1 Functions of Clock Generator................................................................................................. 103 5.2 Configuration of Clock Generator .......................................................................................... 104 5.3 Registers Controlling Clock Generator.................................................................................. 105 5.4 System Clock Oscillator .......................................................................................................... 112
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 X1 oscillator ................................................................................................................................. 112 Subsystem clock oscillator........................................................................................................... 112 When subsystem clock is not used.............................................................................................. 115 Ring-OSC oscillator ..................................................................................................................... 115 Prescaler ..................................................................................................................................... 115
5.5 5.6 5.7 5.8
Clock Generator Operation ..................................................................................................... 115 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock........................... 122 Changing System Clock and CPU Clock Settings................................................................ 123
5.7.1 5.8.1 Time required for switching between system clock and CPU clock ............................................. 123 Switching from Ring-OSC clock to X1 input clock........................................................................ 124
Preliminary User's Manual U16315EJ1V0UD
Clock Switching Flowchart and Register Setting ................................................................. 124
10
5.8.2 5.8.3 5.8.4 5.8.5
Switching from X1 input clock to Ring-OSC clock ........................................................................125 Switching from X1 input clock to subsystem clock........................................................................126 Switching from subsystem clock to X1 input clock........................................................................127 Register settings...........................................................................................................................128
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00............................................................................129 6.1 Functions of 16-Bit Timer/Event Counter 00..........................................................................129 6.2 Configuration of 16-Bit Timer/Event Counter 00 ...................................................................130 6.3 Registers Controlling 16-Bit Timer/Event Counter 00...........................................................133 6.4 Operation of 16-Bit Timer/Event Counter 00 ..........................................................................139
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 Interval timer operation.................................................................................................................139 PPG output operations .................................................................................................................141 Pulse width measurement operations...........................................................................................143 External event counter operation..................................................................................................150 Square-wave output operation .....................................................................................................152 One-shot pulse output operation ..................................................................................................153
6.5
Cautions for 16-Bit Timer/Event Counter 00 ..........................................................................158
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 ...........................................................162 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 .............................................................162 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 .......................................................164 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ..............................................165 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51............................................................171
7.4.1 7.4.2 7.4.3 7.4.4 Operation as interval timer ...........................................................................................................171 Operation as external event counter.............................................................................................173 Square-wave output operation .....................................................................................................174 PWM output operation..................................................................................................................176
7.5
Cautions for 8-Bit Timer/Event Counters 50 and 51..............................................................178
CHAPTER 8 8-BIT TIMERS H0 AND H1 ...........................................................................................179 8.1 Functions of 8-Bit Timers H0 and H1 ......................................................................................179 8.2 Configuration of 8-Bit Timers H0 and H1 ...............................................................................179 8.3 Registers Controlling 8-Bit Timers H0 and H1.......................................................................182 8.4 Operation of 8-Bit Timers H0 and H1 ......................................................................................186
8.4.1 8.4.2 8.4.3 Operation as interval timer ...........................................................................................................186 Operation as PWM pulse generator .............................................................................................189 Carrier generator mode operation (8-bit timer H1 only) ................................................................195
CHAPTER 9 WATCH TIMER ................................................................................................................202 9.1 Functions of Watch Timer........................................................................................................202 9.2 Configuration of Watch Timer .................................................................................................204 9.3 Register Controlling Watch Timer...........................................................................................204 9.4 Watch Timer Operations ..........................................................................................................206
9.4.1 9.4.2 Watch timer operation ..................................................................................................................206 Interval timer operation.................................................................................................................207
CHAPTER 10 WATCHDOG TIMER ......................................................................................................209 10.1 Functions of Watchdog Timer .................................................................................................209
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10.2 Configuration of Watchdog Timer .......................................................................................... 211 10.3 Registers Controlling Watchdog Timer ................................................................................. 212 10.4 Operation of Watchdog Timer................................................................................................. 214
10.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option ..... 214 10.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option .............................................................................................................. 215 10.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) ............................................................................................................. 216 10.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) ............................................................................................................. 218
CHAPTER 11 CLOCK OUTPUT CONTROLLER ............................................................................... 219 11.1 Functions of Clock Output Controller.................................................................................... 219 11.2 Configuration of Clock Output Controller ............................................................................. 220 11.3 Registers Controlling Clock Output Controller..................................................................... 220 11.4 Clock Output Controller Operations ...................................................................................... 223 CHAPTER 12 A/D CONVERTER ......................................................................................................... 224 12.1 Functions of A/D Converter..................................................................................................... 224 12.2 Configuration of A/D Converter .............................................................................................. 226 12.3 Registers Controlling A/D Converter ..................................................................................... 228 12.4 A/D Converter Operations ....................................................................................................... 232
12.4.1 Basic operations of A/D converter ............................................................................................... 232 12.4.2 Input voltage and conversion results ........................................................................................... 234 12.4.3 A/D converter operation mode ..................................................................................................... 235
12.5 How to Read A/D Converter Characteristics Table............................................................... 238 12.6 Cautions for A/D Converter ..................................................................................................... 240 CHAPTER 13 SERIAL INTERFACE UART0 ...................................................................................... 245 13.1 Functions of Serial Interface UART0...................................................................................... 245 13.2 Configuration of Serial Interface UART0 ............................................................................... 246 13.3 Registers Controlling Serial Interface UART0....................................................................... 249 13.4 Operation of Serial Interface UART0 ...................................................................................... 253
13.4.1 Operation stop mode ................................................................................................................... 253 13.4.2 Asynchronous serial interface (UART) mode............................................................................... 254 13.4.3 Dedicated baud rate generator .................................................................................................... 262
CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 268 14.1 Functions of Serial Interface UART6...................................................................................... 268 14.2 Configuration of Serial Interface UART6 ............................................................................... 272 14.3 Registers Controlling Serial Interface UART6....................................................................... 275 14.4 Operation of Serial Interface UART6 ...................................................................................... 283
14.4.1 Operation stop mode ................................................................................................................... 283 14.4.2 Asynchronous serial interface (UART) mode............................................................................... 284 14.4.3 Dedicated baud rate generator .................................................................................................... 302
CHAPTER 15 SERIAL INTERFACE CSI10 ........................................................................................ 311 15.1 Functions of Serial Interface CSI10........................................................................................ 311 12
Preliminary User's Manual U16315EJ1V0UD
15.2 Configuration of Serial Interface CSI10 ..................................................................................311 15.3 Registers Controlling Serial Interface CSI10 .........................................................................313 15.4 Operation of Serial Interface CSI10.........................................................................................315
15.4.1 Operation stop mode ....................................................................................................................315 15.4.2 3-wire serial I/O mode ..................................................................................................................316
CHAPTER 16 INTERRUPT FUNCTIONS .............................................................................................324 16.1 Interrupt Function Types..........................................................................................................324 16.2 Interrupt Sources and Configuration ......................................................................................324 16.3 Registers Controlling Interrupt Functions .............................................................................327 16.4 Interrupt Servicing Operations ................................................................................................334
16.4.1 Maskable interrupt request acknowledgement .............................................................................334 16.4.2 Software interrupt request acknowledgement ..............................................................................336 16.4.3 Multiple interrupt servicing............................................................................................................337 16.4.4 Interrupt request hold ...................................................................................................................340
CHAPTER 17 KEY INTERRUPT FUNCTION ......................................................................................341 17.1 Functions of Key Interrupt .......................................................................................................341 17.2 Configuration of Key Interrupt.................................................................................................341 17.3 Register Controlling Key Interrupt ..........................................................................................342 CHAPTER 18 STANDBY FUNCTION ...................................................................................................343 18.1 Standby Function and Configuration......................................................................................343
18.1.1 Standby function...........................................................................................................................343 18.1.2 Registers controlling standby function ..........................................................................................345
18.2 Standby Function Operation....................................................................................................347
18.2.1 HALT mode ..................................................................................................................................347 18.2.2 STOP mode..................................................................................................................................351
CHAPTER 19 RESET FUNCTION ........................................................................................................354 19.1 Register for Confirming Reset Source....................................................................................359 CHAPTER 20 CLOCK MONITOR .........................................................................................................360 20.1 Functions of Clock Monitor .....................................................................................................360 20.2 Configuration of Clock Monitor ...............................................................................................360 20.3 Register Controlling Clock Monitor ........................................................................................361 20.4 Operation of Clock Monitor......................................................................................................362 CHAPTER 21 POWER-ON-CLEAR CIRCUIT ......................................................................................366 21.1 Functions of Power-on-Clear Circuit ......................................................................................366 21.2 Configuration of Power-on-Clear Circuit ................................................................................367 21.3 Operation of Power-on-Clear Circuit.......................................................................................367 21.4 Cautions for Power-on-Clear Circuit.......................................................................................368 CHAPTER 22 LOW-VOLTAGE DETECTOR ........................................................................................370 22.1 Functions of Low-Voltage Detector ........................................................................................370 22.2 Configuration of Low-Voltage Detector ..................................................................................370 22.3 Registers Controlling Low-Voltage Detector .........................................................................371
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13
22.4 Operation of Low-Voltage Detector........................................................................................ 374 22.5 Cautions for Low-Voltage Detector ........................................................................................ 378 CHAPTER 23 REGULATOR ................................................................................................................. 382 23.1 Outline ....................................................................................................................................... 382 CHAPTER 24 MASK OPTIONS ........................................................................................................... 383 CHAPTER 25 PD78F0124 ................................................................................................................... 384 25.1 Internal Memory Size Switching Register.............................................................................. 385 25.2 Flash Memory Programming................................................................................................... 386
25.2.1 Selection of communication mode ............................................................................................... 386 25.2.2 Flash memory programming function .......................................................................................... 387 25.2.3 Connecting Flashpro III/Flashpro IV ............................................................................................ 388 25.2.4 Connection on adapter for flash memory writing.......................................................................... 390
CHAPTER 26 INSTRUCTION SET....................................................................................................... 395 26.1 Conventions Used in Operation List ...................................................................................... 395
26.1.1 Operand identifiers and specification methods ............................................................................ 395 26.1.2 Description of operation column .................................................................................................. 396 26.1.3 Description of flag operation column............................................................................................ 396
26.2 Operation List ........................................................................................................................... 397 26.3 Instructions Listed by Addressing Type................................................................................ 405 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ............................................. 408 CHAPTER 28 PACKAGE DRAWING................................................................................................... 426 CHAPTER 29 CAUTIONS FOR WAIT................................................................................................. 427 29.1 Cautions for Wait...................................................................................................................... 427 29.2 Peripheral Hardware That Generates Wait ............................................................................ 428 29.3 Example of Wait Occurrence .................................................................................................. 429 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 430 A.1 Software Package..................................................................................................................... 432 A.2 Language Processing Software.............................................................................................. 433 A.3 Flash Memory Writing Tools ................................................................................................... 434 A.4 Debugging Tools ...................................................................................................................... 435
A.4.1 A.4.2 Hardware ..................................................................................................................................... 435 Software ...................................................................................................................................... 436
APPENDIX B EMBEDDED SOFTWARE ............................................................................................. 437 APPENDIX C REGISTER INDEX ......................................................................................................... 438 C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 438 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 441
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Preliminary User's Manual U16315EJ1V0UD
LIST OF FIGURES (1/7)
Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 5-1 5-2 5-3 Title Page
Pin I/O Circuit List ....................................................................................................................................... 44 Memory Map (PD780121) ......................................................................................................................... 47 Memory Map (PD780122) ......................................................................................................................... 48 Memory Map (PD780123) ......................................................................................................................... 49 Memory Map (PD780124) ......................................................................................................................... 50 Memory Map (PD78F0124)....................................................................................................................... 51 Data Memory Addressing (PD780121) ..................................................................................................... 54 Data Memory Addressing (PD780122) ..................................................................................................... 55 Data Memory Addressing (PD780123) ..................................................................................................... 56 Data Memory Addressing (PD780124) ..................................................................................................... 57 Data Memory Addressing (PD78F0124) ................................................................................................... 58 Format of Program Counter ........................................................................................................................ 59 Format of Program Status Word ................................................................................................................. 59 Format of Stack Pointer............................................................................................................................... 61 Data to Be Saved to Stack Memory ............................................................................................................ 61 Data to Be Restored from Stack Memory.................................................................................................... 61 Configuration of General-Purpose Registers............................................................................................... 62 Port Types................................................................................................................................................... 78 Block Diagram of P00 and P03 ................................................................................................................... 81 Block Diagram of P01.................................................................................................................................. 82 Block Diagram of P02.................................................................................................................................. 83 Block Diagram of P10.................................................................................................................................. 84 Block Diagram of P11 and P14 ................................................................................................................... 85 Block Diagram of P12.................................................................................................................................. 86 Block Diagram of P13.................................................................................................................................. 87 Block Diagram of P15.................................................................................................................................. 88 Block Diagram of P16 and P17 ................................................................................................................... 89 Block Diagram of P20 to P27 ...................................................................................................................... 90 Block Diagram of P30 to P32 ...................................................................................................................... 91 Block Diagram of P33.................................................................................................................................. 92 Block Diagram of P60 to P63 ...................................................................................................................... 93 Block Diagram of P70 to P77 ...................................................................................................................... 94 Block Diagram of P120................................................................................................................................ 95 Block Diagram of P130................................................................................................................................ 96 Block Diagram of P140................................................................................................................................ 97 Format of Port Mode Register ..................................................................................................................... 98 Format of Pull-up Resistor Option Register............................................................................................... 100 Format of Input Switch Control Register (ISC) .......................................................................................... 101 Block Diagram of Clock Generator............................................................................................................ 104 Subsystem Clock Feedback Resistor........................................................................................................ 105 Format of Processor Clock Control Register (PCC) .................................................................................. 106
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Figure No. 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 Title Page
Format of Ring-OSC Mode Register (RCM) ..............................................................................................107 Format of Main Clock Mode Register (MCM) ............................................................................................108 Format of Main OSC Control Register (MOC) ...........................................................................................109 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ................................................110 Format of Oscillation Stabilization Time Select Register (OSTS) ..............................................................111 External Circuit of X1 Oscillator.................................................................................................................112 External Circuit of Subsystem Clock Oscillator..........................................................................................112 Examples of Incorrect Resonator Connection ...........................................................................................113 Timing Diagram of CPU Default Start Using Ring-OSC ............................................................................116 Status Transition Diagram .........................................................................................................................117 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart).................................................................124 Switching from X1 Input Clock to Ring-OSC Clock (Flowchart).................................................................125 Switching from X1 Input Clock to Subsystem Clock (Flowchart) ...............................................................126 Switching from Subsystem Clock to X1 Input Clock (Flowchart) ...............................................................127 Block Diagram of 16-Bit Timer/Event Counter 00......................................................................................130 Format of 16-Bit Timer Mode Control Register 00 (TMC00)......................................................................134 Format of Capture/Compare Control Register 00 (CRC00).......................................................................135 Format of 16-Bit Timer Output Control Register 00 (TOC00) ....................................................................136 Format of Prescaler Mode Register 00 (PRM00) ......................................................................................137 Format of Port Mode Register 0 (PM0)......................................................................................................138 Control Register Settings for Interval Timer Operation ..............................................................................139 Interval Timer Configuration Diagram........................................................................................................140 Timing of Interval Timer Operation ............................................................................................................140 Control Register Settings for PPG Output Operation ................................................................................141 Configuration of PPG Output.....................................................................................................................142 PPG Output Operation Timing...................................................................................................................142 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register.........................................................................................................................143 Configuration Diagram for Pulse Width Measurement with Free-Running Counter...................................144 Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified)............................................................................144 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter .................145 CR010 Capture Operation with Rising Edge Specified..............................................................................146 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) ......................................................................................................................146 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers..............................................................................................................................147 Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) .........................................................................148 Control Register Settings for Pulse Width Measurement by Means of Restart..........................................149 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) .........149 Control Register Settings in External Event Counter Mode .......................................................................150 Configuration Diagram of External Event Counter.....................................................................................151
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LIST OF FIGURES (3/7)
Figure No. 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 9-1 9-2 9-3 Title Page
External Event Counter Operation Timing (with Rising Edge Specified) ................................................... 151 Control Register Settings in Square-Wave Output Mode .......................................................................... 152 Square-Wave Output Operation Timing .................................................................................................... 152 Control Register Settings for One-Shot Pulse Output with Software Trigger............................................. 154 Timing of One-Shot Pulse Output Operation with Software Trigger .......................................................... 155 Control Register Settings for One-Shot Pulse Output with External Trigger.............................................. 156 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) ............. 157 Start Timing of 16-Bit Timer Counter 00 (TM00) ....................................................................................... 158 Timings After Change of Compare Register During Timer Count Operation............................................. 158 Capture Register Data Retention Timing................................................................................................... 159 Operation Timing of OVF00 Flag .............................................................................................................. 160 Block Diagram of 8-Bit Timer/Event Counter 50........................................................................................ 162 Block Diagram of 8-Bit Timer/Event Counter 51........................................................................................ 163 Format of Timer Clock Selection Register 50 (TCL50).............................................................................. 165 Format of Timer Clock Selection Register 51 (TCL51).............................................................................. 166 Format of 8-Bit Timer Mode Control Register 50 (TMC50)........................................................................ 167 Format of 8-Bit Timer Mode Control Register 51 (TMC51)........................................................................ 168 Format of Port Mode Register 1 (PM1) ..................................................................................................... 170 Format of Port Mode Register 3 (PM3) ..................................................................................................... 170 Interval Timer Operation Timing................................................................................................................ 171 External Event Counter Operation Timing (with Rising Edge Specified) ................................................... 173 Square-Wave Output Operation Timing .................................................................................................... 175 PWM Output Operation Timing ................................................................................................................. 177 Timing of Operation with CR5n Changed.................................................................................................. 178 8-Bit Timer Counter 5n Start Timing.......................................................................................................... 178 Block Diagram of 8-Bit Timer H0............................................................................................................... 180 Block Diagram of 8-Bit Timer H1............................................................................................................... 180 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) ............................................................................... 183 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) ............................................................................... 184 Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) ................................................................. 185 Register Setting in Interval Timer Mode .................................................................................................... 186 Timing of Interval Timer Operation............................................................................................................ 187 Register Setting in PWM Pulse Generator Mode ...................................................................................... 189 Operation Timing in PWM Pulse Generator Mode .................................................................................... 191 Example of Connection Between 8-Bit Timer H1 and 8-Bit Timer/Event Counter 51 ................................ 195 Transfer Timing ......................................................................................................................................... 196 Register Setting in Carrier Generator Mode .............................................................................................. 197 Carrier Generator Mode Operation Timing................................................................................................ 199 Watch Timer Block Diagram...................................................................................................................... 202 Format of Watch Timer Operation Mode Register (WTM)......................................................................... 205 Operation Timing of Watch Timer/Interval Timer....................................................................................... 208
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Figure No. 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 13-1 13-2 13-3 13-4 13-5 13-6 Title Page
Block Diagram of Watchdog Timer ............................................................................................................211 Format of Watchdog Timer Mode Register (WDTM) .................................................................................212 Format of Watchdog Timer Enable Register (WDTE)................................................................................213 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) .................................216 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) ...........216 Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) ...........217 Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) ..............................218 Operation in HALT Mode...........................................................................................................................218 Block Diagram of Clock Output Controller .................................................................................................219 Format of Clock Output Selection Register (CKS).....................................................................................221 Format of Port Mode Register 14 (PM14)..................................................................................................222 Remote Control Output Application Example ............................................................................................223 Block Diagram of A/D Converter ...............................................................................................................224 Block Diagram of Power-Fail Detection Function ......................................................................................225 Format of A/D Conversion Register (ADCR) .............................................................................................226 Format of A/D Converter Mode Register (ADM) ........................................................................................228 Timing Chart When Boost Reference Voltage Generator Is Used.............................................................229 Format of Analog Input Channel Specification Register (ADS) .................................................................230 Format of Power-Fail Comparison Mode Register (PFM)..........................................................................231 Format of Power-Fail Comparison Threshold Register (PFT) ...................................................................231 Basic Operation of A/D Converter .............................................................................................................233 Relationship Between Analog Input Voltage and A/D Conversion Result..................................................234 A/D Conversion Operation.........................................................................................................................235 Power-Fail Detection (When PFEN = 1 and PFCM = 0)............................................................................236 Overall Error ..............................................................................................................................................238 Quantization Error .....................................................................................................................................238 Zero-Scale Error ........................................................................................................................................239 Full-Scale Error .........................................................................................................................................239 Integral Linearity Error ...............................................................................................................................239 Differential Linearity Error..........................................................................................................................239 Circuit Configuration of Series Resistor String ..........................................................................................240 Storing Conversion Result in ADCR and Timing of Data Read from ADCR ..............................................241 Analog Input Pin Connection .....................................................................................................................242 Timing of A/D Conversion End Interrupt Request Generation ...................................................................243 Timing of A/D Converter Sampling and A/D Conversion Start Delay ........................................................244 Block Diagram of Serial Interface UART0 .................................................................................................247 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) ........................................249 Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) ..............................251 Format of Baud Rate Generator Control Register 0 (BRGC0)...................................................................252 Format of Normal UART Transmit/Receive Data ......................................................................................257 Example of Normal UART Transmit/Receive Data Format........................................................................257
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Figure No. 13-7 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 15-1 15-2 15-3 15-4 15-5 15-6 15-7 16-1 16-2 16-3 16-4 Title Page
Normal Transmission Completion Interrupt Request Timing ..................................................................... 259 Reception Completion Interrupt Request Timing....................................................................................... 260 Noise Filter Circuit..................................................................................................................................... 261 Configuration of Baud Rate Generator ...................................................................................................... 262 Permissible Baud Rate Range During Reception...................................................................................... 266 LIN Transmission Operation...................................................................................................................... 269 LIN Reception Operation........................................................................................................................... 270 Port Configuration for LIN Reception Operation........................................................................................ 271 Block Diagram of Serial Interface UART6 ................................................................................................. 273 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) ........................................ 275 Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) .............................. 277 Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) .................................. 278 Format of Clock Selection Register 6 (CKSR6)......................................................................................... 279 Format of Baud Rate Generator Control Register 6 (BRGC6) .................................................................. 280 Format of Asynchronous Serial Interface Control Register 6 (ASICL6)..................................................... 281 Format of Normal UART Transmit/Receive Data ...................................................................................... 290 Example of Normal UART Transmit/Receive Data Format ....................................................................... 291 Normal Transmission Completion Interrupt Request Timing ..................................................................... 293 Processing Flow of Continuous Transmission........................................................................................... 295 Timing of Starting Continuous Transmission............................................................................................. 296 Timing of Ending Continuous Transmission .............................................................................................. 297 Reception Completion Interrupt Request Timing....................................................................................... 298 Reception Error Interrupt........................................................................................................................... 299 Noise Filter Circuit..................................................................................................................................... 300 SBF Transmission..................................................................................................................................... 300 SBF Reception .......................................................................................................................................... 301 Configuration of Baud Rate Generator ...................................................................................................... 303 Permissible Baud Rate Range During Reception...................................................................................... 308 Transfer Rate During Continuous Transmission ....................................................................................... 310 Block Diagram of Serial Interface CSI10 ................................................................................................... 312 Format of Serial Operation Mode Register 10 (CSIM10)........................................................................... 313 Format of Serial Clock Selection Register 10 (CSIC10) ............................................................................ 314 Timing in 3-Wire Serial I/O Mode .............................................................................................................. 319 Timing of Clock/Data Phase...................................................................................................................... 321 Output Operation of First Bit...................................................................................................................... 322 Output Value of SO10 Pin (Last Bit).......................................................................................................... 323 Basic Configuration of Interrupt Function .................................................................................................. 326 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)................................................................. 329 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) ............................................................... 330 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L)....................................................... 331
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LIST OF FIGURES (6/7)
Figure No. 16-5 16-6 16-7 16-8 16-9 16-10 16-11 17-1 17-2 18-1 18-2 18-3 18-4 18-5 18-6 18-7 19-1 19-2 19-3 19-4 19-5 20-1 20-2 20-3 21-1 21-2 21-3 22-1 22-2 22-3 22-4 22-5 22-6 22-7 23-1 Title Page
Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN)......................................................................332 Format of Program Status Word................................................................................................................333 Interrupt Request Acknowledgement Processing Algorithm......................................................................335 Interrupt Request Acknowledgement Timing (Minimum Time) ..................................................................336 Interrupt Request Acknowledgement Timing (Maximum Time) .................................................................336 Examples of Multiple Interrupt Servicing ...................................................................................................338 Interrupt Request Hold ..............................................................................................................................340 Block Diagram of Key Interrupt..................................................................................................................341 Format of Key Return Mode Register (KRM).............................................................................................342 Operation Timing When STOP Mode Is Released ....................................................................................344 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ................................................345 Format of Oscillation Stabilization Time Select Register (OSTS) ..............................................................346 HALT Mode Release by Interrupt Request Generation .............................................................................349 HALT Mode Release by RESET Input.......................................................................................................350 STOP Mode Release by Interrupt Request Generation.............................................................................352 STOP Mode Release by RESET Input ......................................................................................................353 Block Diagram of Reset Function ..............................................................................................................355 Timing of Reset by RESET Input...............................................................................................................356 Timing of Reset Due to Watchdog Timer Overflow ...................................................................................356 Timing of Reset in STOP Mode by RESET Input ......................................................................................356 Format of Reset Control Flag Register (RESF) .........................................................................................359 Block Diagram of Clock Monitor ................................................................................................................360 Format of Clock Monitor Mode Register (CLM) .........................................................................................361 Timing of Clock Monitor.............................................................................................................................363 Block Diagram of Power-on-Clear Circuit ..................................................................................................367 Timing of Internal Reset Signal Generation in Power-on-Clear Circuit ......................................................367 Example of Software Processing After Release of Reset..........................................................................368 Block Diagram of Low-Voltage Detector....................................................................................................370 Format of Low-Voltage Detection Register (LVIM) ....................................................................................372 Format of Low-Voltage Detection Level Selection Register (LVIS) ...........................................................373 Timing of Low-Voltage Detector Internal Reset Signal Generation ...........................................................375 Timing of Low-Voltage Detector Interrupt Signal Generation ....................................................................377 Example of Software Processing After Release of Reset..........................................................................379 Example of Software Processing of LVI Interrupt ......................................................................................381 Block Diagram of Regulator Periphery ......................................................................................................382
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Figure No. 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 25-10 25-11 25-12 A-1 Title Page
Format of Internal Memory Size Switching Register (IMS)........................................................................ 385 Communication Mode Selection Format ................................................................................................... 387 Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode............................................................. 388 Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode (Using Handshake) ............................. 388 Connection of Flashpro III/Flashpro IV in UART (UART0) Mode .............................................................. 389 Connection of Flashpro III/Flashpro IV in UART (UART0) Mode (Using Handshake)............................... 389 Connection of Flashpro III/Flashpro IV in UART (UART6) Mode .............................................................. 389 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode...................................... 390 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (Using Handshake) ...... 391 Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode ....................................... 392 Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode (Using Handshake)........ 393 Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode ....................................... 394 Development Tool Configuration............................................................................................................... 431
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LIST OF TABLES (1/3)
Table No. 1-1 2-1 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 7-1 8-1 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 11-1 12-1 12-2 Title Page
Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions......................................28 Pin I/O Circuit Types....................................................................................................................................43 Set Values of Internal Memory Size Switching Register (IMS) ....................................................................46 Internal Memory Capacity............................................................................................................................52 Vector Table ................................................................................................................................................52 Internal High-Speed RAM Capacity.............................................................................................................53 Special Function Register List .....................................................................................................................64 Port Functions .............................................................................................................................................79 Port Configuration........................................................................................................................................80 Pull-up Resistor of Port 6.............................................................................................................................93 Settings of Port Mode Register and Output Latch When Using Alternate Function.....................................99 Configuration of Clock Generator ..............................................................................................................104 Relationship Between CPU Clock and Minimum Instruction Execution Time............................................107 Relationship Between Operation Clocks in Each Operation Status...........................................................121 Oscillation Control Flags and Clock Oscillation Status ..............................................................................121 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock ..................................................122 Maximum Time Required for CPU Clock Switchover ................................................................................123 Clock and Register Setting ........................................................................................................................128 Configuration of 16-Bit Timer/Event Counter 00........................................................................................130 TI000 Pin Valid Edge and CR000, CR010 Capture Trigger.......................................................................131 TI010 Pin Valid Edge and CR000 Capture Trigger....................................................................................131 Configuration of 8-Bit Timer/Event Counters 50 and 51 ............................................................................164 Configuration of 8-Bit Timers H0 and H1...................................................................................................179 Watch Timer Interrupt Time.......................................................................................................................203 Interval Timer Interval Time.......................................................................................................................203 Watch Timer Configuration........................................................................................................................204 Watch Timer Interrupt Time.......................................................................................................................206 Interval Timer Interval Time.......................................................................................................................207 Loop Detection Time of Watchdog Timer ..................................................................................................209 Mask Option Setting and Watchdog Timer Operation Mode .....................................................................210 Configuration of Watchdog Timer ..............................................................................................................211 Clock Output Controller Configuration .......................................................................................................220 Configuration of A/D Converter .................................................................................................................226 Settings of ADCS and ADCE.....................................................................................................................229
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Table No. 12-3 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 15-1 16-1 16-2 16-3 16-4 16-5 17-1 17-2 18-1 18-2 18-3 18-4 18-5 19-1 19-2 20-1 20-2 24-1 25-1 25-2 25-3 25-4 26-1 Title Page
A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) .......................... 244 Configuration of Serial Interface UART0 ................................................................................................... 246 Cause of Reception Error.......................................................................................................................... 261 Set Data of Baud Rate Generator ............................................................................................................. 265 Maximum/Minimum Permissible Baud Rate Error..................................................................................... 267 Configuration of Serial Interface UART6 ................................................................................................... 272 Write Processing and Writing to TXB6 During Execution of Continuous Transmission............................. 294 Cause of Reception Error.......................................................................................................................... 299 Set Data of Baud Rate Generator ............................................................................................................. 307 Maximum/Minimum Permissible Baud Rate Error..................................................................................... 309 Configuration of Serial Interface CSI10 ..................................................................................................... 311 Interrupt Source List .................................................................................................................................. 325 Flags Corresponding to Interrupt Request Sources .................................................................................. 328 Ports Corresponding to EGPn and EGNn ................................................................................................. 332 Time from Generation of Maskable Interrupt Request Until Servicing....................................................... 334 Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing .............................. 337 Assignment of Key Interrupt Detection Pins .............................................................................................. 341 Configuration of Key Interrupt ................................................................................................................... 341 Relationship Between HALT Mode, STOP Mode, and Clock .................................................................... 343 Operating Statuses in HALT Mode............................................................................................................ 347 Operation After HALT Mode Release........................................................................................................ 350 Operating Statuses in STOP Mode ........................................................................................................... 351 Operation After STOP Mode Release ....................................................................................................... 353 Hardware Statuses After Reset................................................................................................................. 357 RESF Status When Reset Request Is Generated..................................................................................... 359 Configuration of Clock Monitor .................................................................................................................. 360 Operation Status of Clock Monitor (When CLME = 1)............................................................................... 362 Flash Memory Versions Supporting Mask Options of Mask ROM Versions.............................................. 383 Differences Between PD78F0124 and Mask ROM Versions .................................................................. 384 Internal Memory Size Switching Register Settings.................................................................................... 385 Communication Mode List......................................................................................................................... 386 Main Functions of Flash Memory Programming........................................................................................ 387 Operand Identifiers and Specification Methods......................................................................................... 395
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Table No. 29-1 29-2 Title Page
Registers That Generate Wait and Number of CPU Wait Clocks ..............................................................428 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter) ..........429
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1.1 Features
ROM, RAM capacities
Item Part Number Program Memory (ROM) Mask ROM 8 KB 16 KB 24 KB 32 KB Flash memory 32 KBNote 1024 bytesNote 1024 bytes Data Memory Internal High-Speed RAM 512 bytes
PD780121 PD780122 PD780123 PD780124 PD78F0124
Note
The internal flash memory and internal high-speed RAM capacities can be changed using the internal memory size switching register (IMS).
On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the on-chip Ring-OSC On-chip clock monitor function using on-chip Ring-OSC On-chip watchdog timer (operable with Ring-OSC clock) On-chip UART supporting LIN (Local Interconnect Network) bus On-chip key interrupt function On-chip clock output controller On-chip regulator Minimum instruction execution time can be changed from high speed (0.2 s: @ 10 MHz operation with X1 input clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) I/O ports: 39 (N-ch open drain: 4) Timer: 7 channels Serial interface: 2 channels (UART: 1 channel, CSI/UART
Note
: 1 channel)
10-bit resolution A/D converter: 8 channels Supply voltage: VDD = 2.7 to 5.5 V Note Select either of the functions of these alternate-function pins.
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1.2 Applications
Automotive equipment * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances * Outdoor air conditioner units * Microwave ovens, electric rice cookers Industrial equipment * Pumps * Vending machines * FA
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1.3 Ordering Information
Part Number Package 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) 52-pin plastic LQFP (10 x 10) Quality Grade Standard Standard Standard Standard Special Special Special Special Special Special Special Special Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special
PD780121GB-xxx-8ET PD780122GB-xxx-8ET PD780123GB-xxx-8ET PD780124GB-xxx-8ET PD780121GB(A)-xxx-8ET PD780122GB(A)-xxx-8ET PD780123GB(A)-xxx-8ET PD780124GB(A)-xxx-8ET PD780121GB(A1)-xxx-8ET PD780122GB(A1)-xxx-8ET PD780123GB(A1)-xxx-8ET PD780124GB(A1)-xxx-8ET PD78F0124M1GB-8ET PD78F0124M2GB-8ET PD78F0124M3GB-8ET PD78F0124M4GB-8ET PD78F0124M5GB-8ET PD78F0124M6GB-8ET PD78F0124M1GB(A)-8ET PD78F0124M2GB(A)-8ET PD78F0124M3GB(A)-8ET PD78F0124M4GB(A)-8ET PD78F0124M5GB(A)-8ET PD78F0124M6GB(A)-8ET
Remark xxx indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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Mask ROM versions (PD780121, 780122, 780123, and 780124) include mask options. When ordering, it is possible to select "Power-on-clear (POC) circuit can be used/cannot be used", "Ring-OSC clock can be stopped/cannot be stopped by software" and "Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63 pins)". Flash memory versions corresponding to the mask options of the mask ROM versions are as follows. Table 1-1. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions
Mask Option POC Circuit POC cannot be used Ring-OSC Cannot be stopped Can be stopped by software POC used (VPOC = 2.85 V 0.15 V) Cannot be stopped Can be stopped by software POC used (VPOC = 3.5 V 0.2 V)
Flash Memory Versions (Part Number)
PD78F0124M1GB-8ET PD78F0124M1GB(A)-8ET PD78F0124M2GB-8ET PD78F0124M2GB(A)-8ET PD78F0124M3GB-8ET PD78F0124M3GB(A)-8ET PD78F0124M4GB-8ET PD78F0124M4GB(A)-8ET PD78F0124M5GB-8ET PD78F0124M5GB(A)-8ET PD78F0124M6GB-8ET PD78F0124M6GB(A)-8ET
Cannot be stopped Can be stopped by software
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1.4 Pin Configuration (Top View)
* 52-pin plastic LQFP (10 x 10)
PD780121GB-xxx-8ET, 780122GB-xxx-8ET, 780123GB-xxx-8ET, 780124GB-xxx-8ET, PD780121GB(A)-xxx-8ET, 780122GB(A)-xxx-8ET, 780123GB(A)-xxx-8ET, PD780124GB(A)-xxx-8ET, 780121GB(A1)-xxx-8ET, 780122GB(A1)-xxx-8ET, PD780123GB(A1)-xxx-8ET, 780124GB(A1)-xxx-8ET, 78F0124M1GB-8ET, PD78F0124M2GB-8ET, 78F0124M3GB-8ET, 78F0124M4GB-8ET, 78F0124M5GB-8ET, PD78F0124M6GB-8ET, 78F0124M1GB(A)-8ET, 78F0124M2GB(A)-8ET, 78F0124M3GB(A)-8ET, PD78F0124M4GB(A)-8ET, 78F0124M5GB(A)-8ET, 78F0124M6GB(A)-8ET
P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P70/KR0 P71/KR1 P72/KR2 P73/KR3 P74/KR4
52 51 50 49 48 47 46 45 44 43 42 41 40 AVREF AVSS VPP/IC VDD REGC VSS X1 X2 RESET XT1 XT2 P130 P120/INTP0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 P75/KR5 P76/KR6 P77/KR7 P00/TI000 P01/TI010/TO00 P02 P03 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 EVDD
P33/TI51/TO51/INTP4
P16/TOH1/INTP5
P140/PCL/INTP6
P17/TI50/TO50
P32/INTP3
P31/INTP2
P30/INTP1
P15/TOH0
P60
P61
P62
P63
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVREF pin to VDD. 3. Connect the AVSS pin to VSS. 4. When using the regulator, connect the REGC pin to VSS via 0.1 F capacitor. When the regulator is not used, connect the REGC pin directly to VDD. Remark Figures in parentheses apply to the PD78F0124.
EVSS
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Pin Identification ANI0 to ANI7: AVREF: AVSS: EVDD: EVSS: IC: KR0 to KR7: P00 to P03: P10 to P17: P20 to P27: P30 to P33: P60 to P63: P70 to P77: P120: P130: P140: Analog input Analog reference voltage Analog ground Power supply for port Ground for port Internally connected Key return Port 0 Port 1 Port 2 Port 3 Port 6 Port 7 Port 12 Port 13 Port 14 PCL: REGC: RESET: RxD0, RxD6: SCK10: SI10: SO10: TO00, TO50, TO51, TOH0, TOH1: TxD0, TxD6: VDD: VPP: VSS: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Crystal (X1 input clock) Crystal (Subsystem clock) Programmable clock output Regulator capacitance Reset Receive data Serial clock input/output Serial data input Serial data output
INTP0 to INTP6: External interrupt input
TI000, TI010,TI50, TI51: Timer input
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1.5 78K0/Kxx Series Lineup
The lineup of products in the 78K0/Kxx Series (under development or in planning) is shown below.
78K0/KB1 Series: 30-pin (7.62 mm 0.65 mm pitch)
PD78F0103 PD780103 PD780102 PD780101
Flash memory: 24 KB, RAM: 768 bytes Mask ROM: 24 KB, RAM: 768 bytes Mask ROM: 16 KB, RAM: 768 bytes Mask ROM: 8 KB, RAM: 512 bytes
78K0/KC1 Series: 44-pin (10 x 10 mm 0.8 mm pitch)
PD78F0114 PD780114 PD780113 PD780112 PD780111
Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes
78K0/KD1 Series: 52-pin (10 x 10 mm 0.65 mm pitch)
PD78F0124 PD780124 PD780123 PD780122 PD780121
Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes
78K0/KE1 Series: 64-pin (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch, 14 x 14 mm 0.8 mm pitch)
PD78F0134 PD780134 PD780133 PD780132 PD780131
Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes
PD78F0138 PD780138
Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB
PD780136
78K0/KF1 Series: 80-pin (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch)
PD78F0148 PD780148 PD780146 PD780144 PD780143
Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB
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The function list in the 78K0/Kxx Series (under development or in planning) is shown below.
Part Number Item Package Internal memory (bytes) Flash memory RAM Power supply voltage Minimum instruction execution time 0.2 s (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 s (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.7 to 5.5 V) 512 - Mask ROM 8K 30 pins 16 K 24 K 24 K 768 512 - 8K 16 K - 44 pins 24 K 32 K 32 K 1K 512 - 8K 52 pins 24 K - 8K 24 K 64 pins - 48 K 60 K 32 K 1K - 60 K 2K 1K - 24 K 32 K - 80 pins 48 K 60 K 60 K 2K - 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1
16 K 32 K - 32 K 1K
16 K 32 K - 512
VDD = 2.7 to 5.5 V 0.2 s (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 s (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.7 to 5.5 V)
Clock
X1 input Sub Ring-OSC -
2 to 10 MHz 32.768 kHz 240 kHz (TYP.) 17 4 1 - 4 19 26 8 38 54
Port
CMOS I/O CMOS input CMOS output N-ch open-drain I/O
Timer
16 bits (TM0) 8 bits (TM5) 8 bits (TMH) For watch WDT - 1 ch
1 ch 2 ch 2 ch 1 ch 1 ch 1 ch -
2 ch
1 ch
2 ch
Serial interface
3-wire CSINote Automatic transmit/receive 3-wire CSI UARTNote UART supporting LINbus -
2 ch
1 ch
2 ch 1 ch
1 ch 1 ch
10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Multiplier/divider ROM correction Standby function Operating ambient temperature 11
4 ch 6 12 - 4 ch Provided 7 15 8
8 ch 9 16 19 8 ch 17 9 20
2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option) 3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided - - HALT/STOP mode Standard products, special (A) products: -40 to +85C Special (A1) products: -40 to +110C (mask ROM version only) 16 bits x 16 bits, 32 bits / 16 bits Provided -
Note Select either of the functions of these alternate-function pins.
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1.6 Block Diagram
TO00/TI010/P01 TI000/P00
16-bit timer/ event counter 00
Port 0
4
P00 to P03
Port 1 TOH0/P15 8-bit timer H0 Port 2
8
P10 to P17
8
P20 to P27
TOH1/P16
8-bit timer H1
Port 3
4
P30 to P33
TI50/TO50/P17
8-bit timer/ event counter 50
Port 6
4
P60 to P63
Port 7 TI51/TO51/P33 8-bit timer/ event counter 51 78K/0 CPU core
8
P70 to P77
Port 12 ROM (Flash memory)
P120
Watch timer
Port 13
P130
Watchdog timer
Port 14
P140
RxD0/P11 TxD0/P10
Serial interface UART0
Clock output control
PCL/P140
Clock monitor RxD6/P14 TxD6/P13 SI10/P11 SO10/P12 SCK10/P10 ANI0/P20 to ANI7/P27 AVREF AVSS INTP0/P120 INTP1/P30 to INTP4/P33 INTP5/P16 INTP6/P140 System control 4 Interrupt control RESET X1 X2 XT1 XT2 8 A/D converter Reset control Serial interface UART6 Internal high-speed RAM Power on clear/ low voltage indicator Key return 8 KR0/P70 to KR7/P77
Serial interface CSI10
Ring-OSC
IC VDD, VSS, EVDD EVSS (VPP) Voltage regulator REGC
Remark Items in parentheses are available in the PD78F0124.
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1.7 Outline of Functions
(1/2)
Item Internal memory (bytes) Mask ROM Flash memory High-speed RAM Expansion RAM Memory space X1 input clock (oscillation frequency) 64 KB Ceramic/crystal/external clock oscillation 512
PD780121
8K
PD780122
16 K -
PD780123
24 K
PD780124
32 K
PD78F0124
- 32 K
Note 1
1K -
1 KNote 1
REGC pin is directly connected 10 MHz: VDD = 4.0 to 5.5 V, 8.38 MHz: VDD = 3.3 to 5.5 V, 5 MHz: VDD = 2.7 to 5.5 V to VDD 0.1 F capacitor is connected to REGC pin Ring-OSC clock (oscillation frequency) Subsystem clock (oscillation frequency) General-purpose registers Minimum instruction execution time 8.38 MHz: VDD = 3.3 to 5.5 V, 5 MHz: VDD = 2.7 to 5.5 V On-chip Ring oscillation (240 kHz (TYP.))
Crystal/external clock oscillation (32.768 kHz) 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (X1 input clock: @ fXP = 10 MHz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.) operation) 122 s (subsystem clock: @ fXT = 32.768 kHz operation)
Instruction set
* 16-bit operation * Multiply/divide (8 bits x 8 bits x 4 banks) * Bit manipulate (set, reset, test, and Boolean operation) * BCD adjust, etc. Total: CMOS I/O CMOS input CMOS output N-ch open-drain I/O 39 26 8 1 4 1 channel 2 channels 2 channels 1 channel 1 channel
I/O ports
Timers
* * * * *
16-bit timer/event counter: 8-bit timer/event counter: 8-bit timer: Watch timer Watchdog timer:
Timer outputs Clock output
5 (PWM output: 3) * 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (X1 input clock: 10 MHz) * 32.768 kHz (subsystem clock: 32.768 kHz) 10-bit resolution x 8 channels * UART mode supporting LIN-bus: 1 channel * 3-wire serial I/O mode/UART modeNote 2: 1 channel
A/D converter Serial interface
Notes 1. 2.
The internal flash memory capacity and internal high-speed RAM capacity can be changed using the internal memory size switching register (IMS). Select either of the functions of these alternate-function pins.
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(2/2)
Item Vectored interrupt sources Key interrupt Reset Internal External 15 8 Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). * * * * * Reset using RESET pin Internal reset by watchdog timer Internal reset by clock monitor Internal reset by power-on-clear Internal reset by low-voltage detector
PD780121
PD780122
PD780123
PD780124
PD78F0124
Supply voltage Operating ambient temperature
VDD = 2.7 to 5.5 V Standard products, (A) products: TA = -40 to +85C (A1) products: TA = -40 to +110C (PD780121, 780122, 780123, and 780124 only) * 52-pin plastic LQFP (10 x 10)
Package
An outline of the timer is shown below.
16-Bit Timer/ 8-Bit Timer/ Event Counter 00 Event Counters 50 and 51 Operation mode Function Interval timer External event counter Timer output PPG output PWM output Pulse width measurement Square-wave output Interrupt source 1 channel 1 channel 1 output 1 output - 2 inputs 1 output 2 2 channels 2 channels 2 outputs - 2 outputs - 2 outputs 2 8-Bit Timers H0 and H1 Watch Timer Watchdog Timer
2 channels - 2 outputs - 2 outputs - - 2
1 channelNote - - - - - - 1
1 channel - - - - - - -
Note In the watch timer, the watch timer function and interval timer function can be used simultaneously.
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2.1 Pin Function List
(1) Port pins
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 P30 to P32 Input I/O Port 2. 8-bit input-only port. Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 6. 4-bit I/O port (N-ch open drain). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. Port 13. 1-bit output-only port. Port 14. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input Input I/O I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. After Reset Input Alternate Function TI000 TI010/TO00 - - Input SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 ANI0 to ANI7 INTP1 to INTP3
P33
INTP4/TI51/TO51
P60 to P63
I/O
Input
-
P70 to P77
I/O
Input
KR0 to KR7
P120
I/O
Input
INTP0
P130 P140
Output I/O
Output Input
- PCL/INTP6
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(2) Non-port pins (1/2)
Pin Name INTP0 INTP1 to INTP3 INTP4 INTP5 INTP6 SI10 SO10 SCK10 RxD0 RxD6 TxD0 TxD6 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 Output Input 16-bit timer/event counter 00 output External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 Output 8-bit timer/event counter 50 output 8-bit timer/event counter 51 output 8-bit timer H0 output 8-bit timer H1 output Output Input Input - Input - Clock output (for trimming of X1 input clock, subsystem clock) A/D converter analog input A/D converter reference voltage input A/D converter ground potential. Make the same potential as EVSS or VSS. Key interrupt input Connecting regulator output stabilization capacitor. Connect to VSS via a 0.1 F capacitor. To use the CPU at high speed (fXP = 10 MHz, VDD = 4.0 to 5.5 V), connect this pin directly to VDD. System reset input Connecting crystal resonator for X1 input clock oscillation Input - Input Input - - Input Input Input Input Output Serial data output from asynchronous serial interface Input Input Output I/O Input Serial data input to serial interface Serial data output from serial interface Clock input/output for serial interface Serial data input to asynchronous serial interface Input Input Input Input I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P120 P30 to P32 P33/TI51/TO51 P16/TOH1 P140/PCL P11/RxD0 P12 P10/TxD0 P11/SI10 P14 P10/SCK10 P13 P00
TI010 TO00 TI50 TI51 TO50 TO51 TOH0 TOH1 PCL ANI0 to ANI7 AVREF AVSS KR0 to KR7 REGC
P01/TO00 P01/TI010 P17/TO50 P33/TO51/INTP4 P17/TI50 P33/TI51/INTP4 P15 P16/INTP5 P140/INTP6 P20 to P27 - - P70 to P77 -
RESET X1 X2 XT1 XT2
Input Input - Input -
- - -
- - - - -
Connecting crystal resonator for subsystem clock oscillation
- -
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(2) Non-port pins (2/2)
Pin Name VDD EVDD VSS EVSS IC VPP I/O - - - - - - Function Positive power supply (except for ports) Positive power supply for ports Ground potential (except for ports) Ground potential for ports Internally connected. Connect directly to EVSS or VSS. Flash memory programming mode setting. High-voltage application for program write/verify. Connect directly to EVSS or VSS in normal operation mode. After Reset - - - - - - Alternate Function - - - - - -
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2.2 Description of Pin Functions
2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P03 function as timer I/O. (a) TI000 This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00. (b) TI010 This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00. (c) TO00 This is a timer output pin. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10, SO10 These are serial interface serial data I/O pins. (b) SCK10 This is the serial interface serial clock I/O pin. (c) RxD0, RxD6, TxD0, and TxD6 These are the serial data I/O pins of the asynchronous serial interface. (d) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
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(e) TO50, TOH0, and TOH1 These are timer output pins. (f) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit input-only port. (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins and timer I/O pins. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin. 2.2.5 P60 to P63 (port 6) P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. 2.2.6 P70 to P77 (port 7) P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units.
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(1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. 2.2.7 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.8 P130 (port 13) P130 functions as a 1-bit output-only port. 2.2.9 P140 (port 14) P140 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input and clock output. The following operation modes can be specified in 1-bit units. (1) Port mode P140 functions as a 1-bit I/O port. P140 can be set to input or output in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 functions as external interrupt request input and clock output. (a) INTP6 This is the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. 2.2.10 AVREF This is the A/D converter reference voltage input pin. When A/D converter is not used, connect this pin to VDD. 2.2.11 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the EVSS pin or VSS pin.
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2.2.12 RESET This is the active-low system reset input pin. 2.2.13 REGC This is the pin for connecting the capacitor for the regulator. Connect this pin to VSS via a 0.1 F capacitor. To use the CPU at high speed (fXP = 10 MHz, VDD = 4.0 to 5.5 V), connect this pin directly to VDD and apply the same potential to it as the VDD pin. 2.2.14 X1 and X2 These are the pins for connecting a crystal resonator for X1 input clock oscillation. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. 2.2.15 XT1 and XT2 These are the pins for connecting a crystal resonator for subsystem clock oscillation. When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin. 2.2.16 VDD and EVDD VDD is the positive power supply pin for other than ports. EVDD is the positive power supply pin for ports. 2.2.17 VSS and EVSS VSS is the ground potential pin for other than ports. EVSS is the ground potential pin for ports. 2.2.18 VPP (flash memory versions only) This is a pin for flash memory programming mode setting and high-voltage application for program write/verify. Connect directly to EVSS or VSS in the normal operation mode. 2.2.19 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KD1 Series at shipment. Connect it directly to EVSS or VSS pin with the shortest possible wire in the normal operation mode. When a potential difference is produced between the IC pin and the EVSS or VSS pin because the wiring between these two pins is too long or external noise is input to the IC pin, the user's program may not operate normally. * Connect the IC pin directly to EVSS or VSS pin.
EVSS or VSS
IC
As short as possible
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1. Pin I/O Circuit Types
Pin Name P00/TI000 P01/TI010/TO00 P02 P03 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P20/ANI0 to P27/ANI7 P30/INTP1 to P32/INTP3 P33/TI51/TO51/INTP4 P60, P61 (Mask ROM version) P60, P61 (Flash memory version) P62, P63 (Mask ROM version) P62, P63 (Flash memory version) P70/KR0 to P77/KR7 P120/INTP0 P130 P140/PCL/INTP6 RESET XT1 XT2 AVREF AVSS IC VPP - - - 3-C 8-A 2 16 - - - - Output I/O Input 13-S 13-R 13-W 13-V 8-A Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Leave open. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. - Connect directly to EVDD or VDD. Leave open. Connect directly to EVDD or VDD. Connect directly to EVSS or VSS. Connect directly to EVSS or VSS. 9-C 8-A Input I/O Connect to EVDD or EVSS. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Input: Connect to EVSS. Output: Leave open and keep this pin to low. 8-A 5-A 8-A 5-A I/O Circuit Type 8-A I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
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Figure 2-1. Pin I/O Circuit List (1/2)
Type 2 Type 8-A EVDD Pullup enable
P-ch VDD
IN
Data Schmitt-triggered input with hysteresis characteristics Output disable
P-ch IN/OUT N-ch
Type 3-C
Type 9-C
EVDD P-ch Data N-ch OUT IN P-ch N-ch AVSS VREF (threshold voltage) + - Comparator
Input enable
Type 5-A
EVDD
Type 13-R
Pullup enable VDD Data P-ch
P-ch IN/OUT Data Output disable IN/OUT N-ch
Output disable
N-ch
Input enable
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Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-S Type 13-W
Mask option
EVDD IN/OUT Data Output disable N-ch
IN/OUT
Data Output disable
N-ch
Input enable
Middle-voltage input buffer
Type 13-V EVDD
Mask option
Type 16 Feedback cut-off IN/OUT P-ch
Data Output disable
N-ch
Input enable Middle-voltage input buffer
XT1
XT2
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3.1 Memory Space
Products in the 78K0/KD1 Series can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial value of the internal memory size switching register (IMS) of all products in the 78K0/KD1 Series is fixed (IMS = CFH). Therefore, set the value corresponding to each product as indicated below. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
Internal Memory Size Switching Register (IMS)
PD780121 PD780122 PD780123 PD780124 PD78F0124
42H 44H C6H C8H Value corresponding to mask ROM version
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Figure 3-1. Memory Map (PD780121)
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits
Internal high-speed RAM 512 x 8 bits F D 0 0H F C F FH Data memory space 1 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 2 0 0 0H 1 F F FH Program memory space 0 0 0 0H Internal ROM 8192 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area
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Figure 3-2. Memory Map (PD780122)
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits
Internal high-speed RAM 512 x 8 bits F D 0 0H F C F FH Data memory space 3 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 4 0 0 0H 3 F F FH Program memory space 0 0 0 0H Internal ROM 16384 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area
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Figure 3-3. Memory Map (PD780123)
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits F B 0 0H F A F FH Data memory space 5 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 6 0 0 0H 5 F F FH Program memory space 0 0 0 0H Internal ROM 24576 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area
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Figure 3-4. Memory Map (PD780124)
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits F B 0 0H F A F FH Data memory space 7 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 8 0 0 0H 7 F F FH Program memory space 0 0 0 0H Internal ROM 32768 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area
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Figure 3-5. Memory Map (PD78F0124)
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits F B 0 0H F A F FH Data memory space 7 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 8 0 0 0H 7 F F FH Program memory space 0 0 0 0H Flash memory 32768 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area
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3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KD1 Series products incorporate internal ROM (or flash memory), as shown below. Table 3-2. Internal Memory Capacity
Part Number Structure Internal ROM Capacity 8192 x 8 bits (0000H to 1FFFH) 16384 x 8 bits (0000H to 3FFFH) 24576 x 8 bits (0000H to 5FFFH) 32768 x 8 bits (0000H to 7FFFH) Flash memory
PD780121 PD780122 PD780123 PD780124 PD78F0124
Mask ROM
The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon RESET input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-3. Vector Table
Vector Table Address 0000H Interrupt Source RESET input, POC, LVI, clock monitor, WDT INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/INTST0 Vector Table Address 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H Interrupt Source INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6
0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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3.1.2 Internal data memory space 78K0/KD1 Series products incorporate the following internal high-speed RAMs. Table 3-4. Internal High-Speed RAM Capacity
Part Number Internal High-Speed RAM 512 x 8 bits (FD00H to FEFFH)
PD780121 PD780122 PD780123 PD780124 PD78F0124
1024 x 8 bits (FB00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned.
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3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of the instruction to be executed next is addressed by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing). Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KD1 Series, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Data memory addressing is illustrated in Figures 3-6 to 3-10. For details of each addressing mode, refer to 3.4 Operand Address Addressing. Figure 3-6. Data Memory Addressing (PD780121)
F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing
Internal high-speed RAM 512 x 8 bits F E 2 0H F E 1 FH F D 0 0H F C F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved
2 0 0 0H 1 F F FH
Internal ROM 8192 x 8 bits 0 0 0 0H
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Figure 3-7. Data Memory Addressing (PD780122)
F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing
Internal high-speed RAM 512 x 8 bits F E 2 0H F E 1 FH F D 0 0H F C F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved
4 0 0 0H 3 F F FH
Internal ROM 16384 x 8 bits 0 0 0 0H
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Figure 3-8. Data Memory Addressing (PD780123)
F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing
Internal high-speed RAM 1024 x 8 bits F E 2 0H F E 1 FH F B 0 0H F A F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved
6 0 0 0H 5 F F FH
Internal ROM 24576 x 8 bits 0 0 0 0H
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Figure 3-9. Data Memory Addressing (PD780124)
F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing
Internal high-speed RAM 1024 x 8 bits F E 2 0H F E 1 FH F B 0 0H F A F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved
8 0 0 0H 7 F F FH
Internal ROM 32768 x 8 bits 0 0 0 0H
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Figure 3-10. Data Memory Addressing (PD78F0124)
F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing
Internal high-speed RAM 1024 x 8 bits F E 2 0H F E 1 FH F B 0 0H F A F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved
8 0 0 0H 7 F F FH
Flash memory 32768 x 8 bits 0 0 0 0H
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3.2 Processor Registers
The 78K0/KD1 Series products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Format of Program Counter
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-12. Format of Program Status Word
7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY
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(a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and only non-maskable interrupt requests become acknowledgeable. Other interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area.
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Figure 3-13. Format of Stack Pointer
15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-14. Data to Be Saved to Stack Memory
Interrupt and BRK instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Register pair lower Register pair upper SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP
PUSH rp instruction
CALL, CALLF, and CALLT instructions
PC7 to PC0 PC15 to PC8 PSW
Figure 3-15. Data to Be Restored from Stack Memory
RETI and RETB instructions
POP rp instruction
RET instruction
SP SP + 1 SP SP + 2
Register pair lower Register pair upper SP
SP SP + 1 SP + 2
PC7 to PC0 PC15 to PC8
SP SP + 1 SP + 2 SP SP + 3
PC7 to PC0 PC15 to PC8 PSW
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3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-16. Configuration of General-Purpose Registers (a) Absolute name
16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-bit processing
(b) Function name
16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing
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3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined by the header file "sfrbit.h" in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: W: Read only Write only
* Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input.
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Table 3-5. Special Function Register List (1/3)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF23H FF26H FF27H FF28H FF29H FF2AH FF2BH FF2CH FF2EH FF30H FF31H 8-bit timer counter 50 8-bit timer compare register 50 8-bit timer H compare register 00 8-bit timer H compare register 10 8-bit timer H compare register 01 8-bit timer H compare register 11 8-bit timer counter 51 Port mode register 0 Port mode register 1 Port mode register 3 Port mode register 6 Port mode register 7 A/D converter mode register Analog input channel specification register Power-fail comparison mode register Power-fail comparison threshold register Port mode register 12 Port mode register 14 Pull-up resistor option register 0 Pull-up resistor option register 1 TM50 CR50 CMP00 CMP10 CMP01 CMP11 TM51 PM0 PM1 PM3 PM6 PM7 ADM ADS PFM PFT PM12 PM14 PU0 PU1 R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH 00H 00H 00H 00H FFH FFH 00H 00H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H Receive buffer register 6 Transmit buffer register 6 Port 12 Port 13 Port 14 Serial I/O shift register 10 16-bit timer counter 00 RXB6 TXB6 P12 P13 P14 SIO10 TM00 R R/W R/W R/W R/W R R - - - - - - - - - - - FFH FFH 00H 00H 00H 00H 0000H Port 0 Port 1 Port 2 Port 3 Port 6 Port 7 A/D conversion result register P0 P1 P2 P3 P6 P7 ADCR R/W R/W R R/W R/W R/W R - 8 Bits - 16 Bits - - - - - - After Reset 00H 00H 00H 00H 00H 00H Undefined
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Table 3-5. Special Function Register List (2/3)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF33H FF37H FF3CH FF3EH FF40H FF41H FF43H FF48H FF49H FF4FH FF50H FF53H FF55H FF56H FF57H FF58H FF69H FF6AH FF6BH FF6CH FF6DH FF6EH FF6FH FF70H FF71H FF72H FF73H FF74H FF80H FF81H FF84H FF8CH FF98H FF99H FFA0H FFA1H Pull-up resistor option register 3 Pull-up resistor option register 7 Pull-up resistor option register 12 Pull-up resistor option register 14 Clock output selection register 8-bit timer compare register 51 8-bit timer mode control register 51 External interrupt rising edge enable register External interrupt falling edge enable register Input switch control register Asynchronous serial interface operation mode register 6 Asynchronous serial interface reception error status register 6 Asynchronous serial interface transmission status register 6 Clock selection register 6 Baud rate generator control register 6 Asynchronous serial interface control register 6 8-bit timer H mode register 0 Timer clock selection register 50 8-bit timer mode control register 50 8-bit timer H mode register 1 8-bit timer H carrier control register 1 Key return mode register Watch timer operation mode register Asynchronous serial interface operation mode register 0 Baud rate generator control register 0 Receive buffer register 0 Asynchronous serial interface reception error status register 0 Transmit shift register 0 Serial operation mode register 10 Serial clock selection register 10 Transmit buffer register 10 Timer clock selection register 51 Watchdog timer mode register Watchdog timer enable register Ring-OSC mode register Main clock mode register PU3 PU7 PU12 PU14 CKS CR51 TMC51 EGP EGN ISC ASIM6 ASIS6 ASIF6 CKSR6 BRGC6 ASICL6 TMHMD0 TCL50 TMC50 TMHMD1 TMCYC1 KRM WTM ASIM0 BRGC0 RXB0 ASIS0 TXS0 CSIM10 CSIC10 SOTB10 TCL51 WDTM WDTE RCM MCM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - After Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 00H 00H FFH 16H 00H 00H 00H 00H 00H 00H 00H 01H 1FH FFH 00H FFH 00H 00H Undefined 00H 67H 9AH 00H 00H
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Table 3-5. Special Function Register List (3/3)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FFA2H FFA3H FFA4H FFA9H FFACH FFBAH FFBBH FFBCH FFBDH FFBEH FFBFH FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFF0H FFFBH Main OSC control register MOC R/W R R/W R/W R R/W R/W R/W R/W R/W R/W IF0L IF0H IF1L MK0 R/W R/W R/W MK0L R/W MK0H R/W MK1L PR0 R/W PR0L R/W PR0H R/W PR1L
Note 2
8 Bits
16 Bits - - - - - - - - - - -
After Reset 00H 00H 05H 00H 00HNote 1 00H 00H 00H 00H 00H 00H 00H 00H
- - - -
Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register Clock monitor mode register Reset control flag register 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 Low-voltage detection register Low-voltage detection level selection register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Internal memory size switching register Processor clock control register OSTS CLM RESF TMC00 PRM00 CRC00 TOC00 LVIM LVIS IF0
-
00H FFH FFH
-
FFH FFH FFH
R/W R/W R/W
- - -
FFH CFH 00H
IMS PCC
Notes 1. 2.
This value varies depending on the reset source. The initial value of IMS is fixed (IMS = CFH) in all products in the 78K0/KD1 Series regardless of the internal memory capacity. Therefore, set the following value to each product.
Internal Memory Size Switching Register (IMS)
PD780121 PD780122 PD780123 PD780124 PD78F0124
42H 44H C6H C8H Value corresponding to mask ROM version
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction.
The
When S = 0, all bits of are 0. When S = 1, all bits of are 1.
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3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions
7 CALL or BR Low Addr. High Addr. 0
15 PC
87
0
In the case of CALLF !addr11 instruction
76 fa10-8 fa7-0 4 3 CALLF 0
15 PC 0 0 0 0
11 10 1
87
0
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3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration]
7 Operation code 1 6 1 5 ta4-0 1 0 1
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (Table) Low Addr.
0
Effective address+1
High Addr.
15 PC
8
7
0
3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A 0 7 X 0
15 PC
8
7
0
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KD1 Series instruction words, the following instructions employ implied addressing.
Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values that become decimal correction targets A register for storage of digit data that undergoes digit rotation
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.
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3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format]
Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL
`r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r
Operation code 0 1 1 0 0 0 1 0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 1 0 0 0 0 1 0 0
Register specify code
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3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format]
Identifier addr16 Description Label or 16-bit immediate data
[Description example] MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 1 0 0 0 1 1 1 0 OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7 OP code addr16 (lower) addr16 (upper) 0
Memory
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3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration] shown below. [Operand format]
Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only)
[Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code 0 0 0 1 0 0 0 1 OP code
0
0
1
1
0
0
0
0
30H (saddr-offset)
0
1
0
1
0
0
0
0
50H (immediate data)
[Illustration]
7 OP code saddr-offset 0
Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0
When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1
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3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Description Special function register name 16-bit manipulatable special function register name (even address only)
[Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 1 1 1 1 0 1 1 0 OP code
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7 OP code sfr-offset 0
SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0
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3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier - [DE], [HL] Description
[Description example] MOV A, [DE]; when selecting [DE] as register pair
Operation code 1 0 0 0 0 1 0 1
[Illustration]
16 DE D 87 E The memory address specified with the register pair DE 0
7 The contents of the memory addressed are transferred. 7 A 0
Memory
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3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier - [HL + byte] Description
[Description example] MOV A, [HL + 10H]; when setting byte to 10H
Operation code 1 0 1 0 1 1 1 0
0
0
0
1
0
0
0
0
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3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier - [HL + B], [HL + C] Description
[Description example] In the case of MOV A, [HL + B]
Operation code 1 0 1 0 1 0 1 1
3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] In the case of PUSH DE
Operation code 1 0 1 1 0 1 0 1
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4.1 Port Functions
78K0/KD1 Series products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-1. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types
P30 Port 3 P33 P60 Port 6 P63 P70
P00 Port 0 P03 P10
Port 1
P17 Port 7 P20
P77 Port 12 Port 13 Port 14 P120 P130 P140 P27
Port 2
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Table 4-1. Port Functions
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 P30 to P32 Input I/O Port 2. 8-bit input-only port. Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 6. 4-bit I/O port (N-ch open drain). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. Port 13. 1-bit output-only port. Port 14. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input Input I/O I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. After Reset Input Alternate Function TI000 TI010/TO00 - - Input SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 ANI0 to ANI7 INTP1 to INTP3
P33
INTP4/TI51/TO51 -
P60 to P63
I/O
Input
P70 to P77
I/O
Input
KR0 to KR7
P120
I/O
Input
INTP0
P130 P140
Output I/O
Output Input
- PCL/INTP6
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4.2 Port Configuration
Ports consist of the following hardware. Table 4-2. Port Configuration
Item Control registers Configuration Port mode register (PM0, PM1, PM3, PM6, PM7, PM12, PM14) Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12, PU14) Input switch control register (ISC) Total: 39 (CMOS I/O: 26, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4) * Mask ROM version Total: 30 (software control: 26, mask option specification: 4) * Flash memory version: Total: 26
Port Pull-up resistor
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4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O. RESET input sets port 0 to input mode. Figures 4-2 to 4-4 show block diagrams of port 0. Figure 4-2. Block Diagram of P00 and P03
EVDD WRPU
PU00, PU03
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P00, P03) WRPM
P00/TI000, P03
PM00, PM03
PU0: PM: RD: WR:
Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal
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Figure 4-3. Block Diagram of P01
EVDD WRPU
PU01
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P01) WRPM
P01/TI010/TO00
PM01
Alternate function
PU0: PM: RD: WR:
Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal
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Figure 4-4. Block Diagram of P02
EVDD WRPU
PU02 RD
P-ch
Internal bus
WRPORT Output latch (P02) WRPM
Selector
P02
PM02
Alternate function
PU0: PM: RD: WR:
Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal
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4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. RESET input sets port 1 to input mode. Figures 4-5 to 4-10 show block diagrams of port 1. Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not write to serial clock selection register 10 (CSIC10). Figure 4-5. Block Diagram of P10
EVDD WRPU
PU10
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P10) WRPM
P10/SCK10/TxD0
PM10
Alternate function
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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Figure 4-6. Block Diagram of P11 and P14
EVDD WRPU
PU11, PU14
P-ch
Alternate function RD
Internal bus Selector
WRPORT Output latch (P11, P14) WRPM
P11/SI10/RxD0, P14/RxD6
PM11, PM14
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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Figure 4-7. Block Diagram of P12
EVDD WRPU
PU12 RD
P-ch
Internal bus
WRPORT Output latch (P12) WRPM
Selector
P12/SO10
PM12
Alternate function
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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Figure 4-8. Block Diagram of P13
EVDD WRPU
PU13 RD
P-ch
Internal bus
WRPORT Output latch (P13) WRPM
Selector
P13/TxD6
PM13
Alternate function
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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Figure 4-9. Block Diagram of P15
EVDD WRPU
PU15 RD
P-ch
Internal bus
WRPORT Output latch (P15) WRPM
Selector
P15/TOH0
PM15
Alternate function
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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Figure 4-10. Block Diagram of P16 and P17
EVDD WRPU
PU16, PU17
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P16, P17) WRPM
Selector
P16/TOH1/INTP5, P17/TI50/TO50
PM16, PM17
Alternate function
PU1: PM: RD: WR:
Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal
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4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27
RD
Internal bus
+
P20/ANI0 to P27/ANI7
A/D converter
-
VREF
RD:
Port 2 read signal
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4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input. RESET input sets port 3 to input mode. Figures 4-12 and 4-13 show block diagrams of port 3. Figure 4-12. Block Diagram of P30 to P32
EVDD WRPU
PU30 to PU32
P-ch
Alternate function RD
Internal bus Selector
WRPORT Output latch (P30 to P32) WRPM
P30/INTP1 to P32/INTP3
PM30 to PM32
PU3: PM: RD: WR:
Pull-up resistor option register 3 Port mode register Port 3 read signal Port 3 write signal
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Figure 4-13. Block Diagram of P33
EVDD WRPU
PU33
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P33) WRPM
P33/INTP4/TI51/TO51
PM33
Alternate function
PU0: PM: RD: WR:
Pull-up resistor option register 3 Port mode register Port 3 read signal Port 3 write signal
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4.2.5 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on whether the product is a mask ROM version or a flash memory version. Table 4-3. Pull-up Resistor of Port 6
Pins P60 to P63 Mask ROM version Flash memory version An on-chip pull-up resistor can be specified in 1-bit units by mask option On-chip pull-up resistors are not provided
RESET input sets port 6 to input mode. Figure 4-14 shows a block diagram of port 6. Figure 4-14. Block Diagram of P60 to P63
EVDD RD Mask option resistor
Mask ROM versions only No pull-up resistor for flash memory versions
Selector
Internal bus
WRPORT Output latch (P60 to P63) P60 to P63
WRPM PM60 to PM63
PM: RD: WR:
Port mode register Port 6 read signal Port 6 write signal
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4.2.6 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). This port can also be used for key return input. RESET input sets port 7 to input mode. Figure 4-15 shows a block diagram of port 7. Figure 4-15. Block Diagram of P70 to P77
EVDD WRPU
PU70 to PU77
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P70 to P77) WRPM
P70/KR0 to P77/KR7
PM70 to PM77
PU7: PM: RD: WR:
Pull-up resistor option register 7 Port mode register Port 7 read signal Port 7 write signal
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4.2.7 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used for external interrupt input. RESET input sets port 12 to input mode. Figure 4-16 shows a block diagram of port 12. Figure 4-16. Block Diagram of P120
EVDD WRPU
PU120
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P120) WRPM
Selector
P120/INTP0
PM120
PU12: Pull-up resistor option register 12 PM: RD: WR: Port mode register Port 12 read signal Port 12 write signal
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4.2.8 Port 13 Port 13 is a 1-bit output-only port. Figure 4-17 shows a block diagram of port 13. Figure 4-17. Block Diagram of P130
RD
Internal bus
WRPORT Output latch (P130) P130
RD: WD:
Port 13 read signal Port 13 write signal
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4.2.9 Port 14 Port 14 is a 1-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input and clock output. RESET input sets port 14 to input mode. Figure 4-18 shows a block diagram of port 14. Figure 4-18. Block Diagram of P140
EVDD WRPU
PU140
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P140) WRPM
P140/PCL/INTP6
PM140
Alternate function
PU14: Pull-up resistor option register 14 PM: RD: WR: Port mode register Port 14 read signal Port 14 write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers. * Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, PM14) * Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, PU14) * Input switch control register (ISC) (1) Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 4-4. Figure 4-19. Format of Port Mode Register
Symbol PM0 7 1 7 PM1 PM17 7 PM3 1 7 PM6 1 7 PM7 PM77 7 PM12 1 7 PM14 1 6 1 6 PM16 6 1 6 1 6 PM76 6 1 6 1 5 1 5 PM15 5 1 5 1 5 PM75 5 1 5 1 4 1 4 PM14 4 1 4 1 4 PM74 4 1 4 1 3 PM03 3 PM13 3 PM33 3 PM63 3 PM73 3 1 3 1 2 PM02 2 PM12 2 PM32 2 PM62 2 PM72 2 1 2 1 1 PM01 1 PM11 1 PM31 1 PM61 1 PM71 1 1 1 1 0 PM00 0 PM10 0 PM30 0 PM60 0 PM70 0 PM120 0 PM140 FF2EH FFH R/W FF2CH FFH R/W FF27H FFH R/W FF26H FFH R/W FF23H FFH R/W FF21H FFH R/W Address FF20H After reset FFH R/W R/W
PMmn
Pmn pin I/O mode selection (m = 0, 1, 3, 6, 7, 12, 14; n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
0 1
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Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function
Pin Name Alternate Function Function Name P00 P01 TI000 TI010 TO00 P10 SCK10 I/O Input Input Output Input Output TxD0 P11 SI10 RxD0 P12 P13 P14 P15 P16 SO10 TxD6 RxD6 TOH0 TOH1 INTP5 P17 TI50 TO50 P30 to P32 P33 INTP1 to INTP3 INTP4 TI51 TO51 P70 to P77 P120 P140 KR0 to KR7 INTP0 PCL INTP6 Output Input Input Output Output Input Output Output Input Input Output Input Input Input Output Input Input Output Input 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 1 x x 0 x 1 1 x x 0 1 x 0 0 x x 0 x x x 0 x x 0 x PMxx Pxx
Remark x: Pxx:
Don't care Port output latch
PMxx: Port mode register
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(2) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, P70 to P77, P120, or P140 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, PU12, and PU14. On-chip pull-up resistors cannot be used for bits set to output mode and bits used as alternatefunction output pins, regardless of the settings of PU0, PU1, PU3, PU7, PU12, and PU14. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Caution Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask ROM versions. Figure 4-20. Format of Pull-up Resistor Option Register
Symbol PU0 7 0 7 PU1 PU17 7 PU3 0 7 PU7 PU77 7 PU12 0 7 PU14 0 6 0 6 PU16 6 0 6 PU76 6 0 6 0 5 0 5 PU15 5 0 5 PU75 5 0 5 0 4 0 4 PU14 4 0 4 PU74 4 0 4 0 3 PU03 3 PU13 3 PU33 3 PU73 3 0 3 0 2 PU02 2 PU12 2 PU32 2 PU72 2 0 2 0 1 PU01 1 PU11 1 PU31 1 PU71 1 0 1 0 0 PU00 0 PU10 0 PU30 0 PU70 0 PU120 0 PU140 FF3EH 00H R/W FF3CH 00H R/W FF37H 00H R/W FF33H 00H R/W FF31H 00H R/W Address FF30H After reset 00H R/W R/W
PUmn
Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 7, 12, 14; n = 0 to 7) On-chip pull-up resistor not connected On-chip pull-up resistor connected
0 1
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(3) Input switch control register (ISC) This register is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. For the port configuration during LIN reception, refer to Figure 14-3 Port Configuration for LIN Reception Operation in CHAPTER 14 SERIAL INTERFACE UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 4-21. Format of Input Switch Control Register (ISC)
Address: FF4FH Symbol ISC After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 0 1 ISC1 0 ISC0
ISC1 0 1 TI000 input RxD6 input
Input signal selection
ISC0 0 1 INTP0 input RxD6 input
Input signal selection
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is off, the pin status does not change. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
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5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. * X1 oscillator The X1 oscillator oscillates a clock of 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the main OSC control register (MOC) and processor clock control register (PCC). * Ring-OSC oscillator The Ring-OSC oscillator oscillates a clock of 240 kHz (TYP.). Oscillation can be stopped by setting the RingOSC mode register (RCM) when "Can be stopped by software" is set by a mask option and the X1 input clock is used as the CPU clock. * Subsystem clock oscillator The subsystem clock oscillator oscillates a clock of 32.768 kHz. Oscillation cannot be stopped. When subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the processor clock control register (PCC), and the power consumption can be reduced in the STOP mode.
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5.2 Configuration of Clock Generator
The clock generator consists of the following hardware. Table 5-1. Configuration of Clock Generator
Item Control registers Configuration Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) X1 oscillator Ring-OSC oscillator Subsystem clock oscillator
Oscillator
Figure 5-1. Block Diagram of Clock Generator
Internal bus Main OSC control register (MOC) MCC CLS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 3 4 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) Controller C P U CPU clock (fCPU) Processor clock control register (PCC) CLS CSS PCC2 PCC1 PCC0
MCS MCM0
X1 X1 oscillator X2 fXP fX Operation clock switch fX 2 Ring-OSC oscillator Prescaler fX 22 fX 23 fX 24
Selector
fR
Watch clock, clock output function Prescaler Clock to peripheral hardware Mask option 1: Cannot be stopped 0. Can be stopped RSTOP Ring-OSC mode register (RCM) Internal bus Prescaler 8-bit timer H1, watchdog timer 1/2 fXT Subsystem clock oscillator XT1 XT2
FRC
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5.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator. * Processor clock control register (PCC) * Ring-OSC mode register (RCM) * Main clock mode register (MCM) * Main OSC control register (MOC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop and whether to use the on-chip feedback resistor of the subsystem clock oscillator. The PCC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PCC to 00H. Figure 5-2. Subsystem Clock Feedback Resistor
FRC P-ch Feedback resistor
XT1
XT2
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Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH Symbol PCC 7 MCC MCC 0 1 FRC 0 1 CLS 0 1 CSSNote 4 X1 input clock or Ring-OSC clock Subsystem clock PCC2 PCC1 PCC0 CPU Clock (fCPU) Selection MCM0 = 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 Setting prohibited fX fX/2 fX/2 fX/2
2 3
After reset: 00H 6 FRC
R/WNote 1 5 CLS 4 CSS 3 0 2 PCC2 1 PCC1 0 PCC0
Control of X1 oscillator operationNote 2 Oscillation possible Oscillation stopped Subsystem clock feedback resistor selectionNote 3 On-chip feedback resistor used On-chip feedback resistor not used CPU clock status
MCM0 = 1 fXP fXP/2 fXP/22 fXP/23 fXP/24
fR fR/2 fR/2 fR/2
2 3
fX/24 fXT/2
fR/24
Other than above
Notes 1. 2.
Bit 5 is read-only. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP instruction should not be used.
3.
The feedback resistor is required to adjust the bias point of the oscillation waveform to close to the middle of the power supply voltage. Setting FRC to 1 can further reduce the current consumption in the STOP mode, but only when the subsystem clock is not used.
4.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register (MCM) are 1.
Caution Be sure to set bit 3 to 0. Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM) 2. fX: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock oscillation frequency) 3. fR: Ring-OSC clock oscillation frequency 4. fXP: X1 input clock oscillation frequency 5. fXT: Subsystem clock oscillation frequency
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The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KD1 Series. Therefore, the relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Note
Minimum Instruction Execution Time: 2/fCPU X1 Input Clock (at 10 MHz Operation) Ring-OSC ClockNote (at 240 kHz (TYP.) Operation) 8.3 s (TYP.) 16.6 s (TYP.) 33.2 s (TYP.) 66.4 s (TYP.) 132.8 s (TYP.) - - 122.1 s Subsystem Clock (at 32.768 kHz Operation) - - - - -
fX fX/2 fX/2 fX/2 fX/2
2
0.2 s 0.4 s 0.8 s 1.6 s 3.2 s
3
4
fXT/2
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see Figure 5-5). (2) Ring-OSC mode register (RCM) This register sets the operation mode of Ring-OSC. This register is valid when "Can be stopped by software" is set for Ring-OSC by a mask option, and the X1 input clock or subsystem clock is selected as the CPU clock. If "Cannot be stopped" is selected for Ring-OSC by a mask option, settings for this register are invalid. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of Ring-OSC Mode Register (RCM)
Address: FFA0H Symbol RCM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 RSTOP
RSTOP 0 1 Ring-OSC oscillating Ring-OSC stopped
Ring-OSC oscillating/stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting RSTOP.
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(3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-5. Format of Main Clock Mode Register (MCM)
Address: FFA1H Symbol MCM 7 0 After reset: 00H 6 0 R/WNote 5 0 4 0 3 0 2 0 1 MCS 0 MCM0
MCS 0 1 Operates with Ring-OSC clock Operates with X1 input clock
CPU clock status
MCM0 0 1 Ring-OSC clock X1 input clock
Selection of clock supplied to CPU
Note Bit 1 is read-only. Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral hardware (fX = 240 kHz (TYP.)). Operation of the peripheral hardware with Ring-OSC clock cannot be guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the Ring-OSC clock. Note, however, that the following peripheral hardware can be used when the CPU operates on the Ring-OSC clock. * Watchdog timer * Clock monitor * 8-bit timer H1 when fR/2 is selected as count clock
7
* Peripheral hardware selecting external clock as the clock source (Except when external count clock of TM00 is selected (TI000 valid edge)) 2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1 input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is changed from 1 to 0).
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(4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-6. Format of Main OSC Control Register (MOC)
Address: FFA2H Symbol MOC 7 MSTOP MSTOP 0 1 X1 oscillator operating X1 oscillator stopped After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0
Control of X1 oscillator operation
Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting MSTOP. 2. To stop X1 oscillation during operation with the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not possible).
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(5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H. Figure 5-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H Symbol OSTC 7 0 MOST11 1 1 1 1 1 After reset: 00H 6 0 MOST13 0 1 1 1 1 R 5 0 MOST14 0 0 1 1 1 4 MOST11 MOST15 0 0 0 1 1 3 MOST13 MOST16 0 0 0 0 1 2 MOST14 1 MOST15 0 MOST16
Oscillation stabilization time status 2 /fXP min. (204.8 s min.)
11
213/fXP min. (819.2 s min.) 214/fXP min. (1.64 ms min.) 215/fXP min. (3.27 ms min.) 216/fXP min. (6.55 ms min.)
Caution After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. Remarks 1. Values in parentheses are for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency
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(6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock. After STOP mode is released with Ring-OSC selected as CPU clock, the oscillation stabilization time must be confirmed by OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2 0 0 0 1 1
OSTS1 0 1 1 0 0 Other than above
OSTS0 1 0 1 0 1
11
Oscillation stabilization time selection 2 /fXP (204.8 s) 213/fXP (819.2 s) 214/fXP (1.64 ms) 215/fXP (3.27 ms) 216/fXP (6.55 ms) Setting prohibited
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation.
STOP mode release X1 pin voltage waveform a VSS
Remarks 1. Values in parentheses are for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency
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5.4 System Clock Oscillator
5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 8.38 MHz, 10 MHz when REGC pin is directly connected to VDD) connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is directly connected to VDD. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin. Figure 5-9 shows the external circuit of the X1 oscillator. Figure 5-9. External Circuit of X1 Oscillator (a) Crystal, ceramic oscillation
IC X1 VSS Crystal resonator or ceramic resonator
(b) External clock
External clock
X1
X2
X2
5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator when the REGC pin is directly connected to VDD. In this case, input the clock signal to the XT1 pin and the inverse signal to the XT2 pin. Figure 5-10 shows an external circuit of the subsystem clock oscillator. Figure 5-10. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock
External clock
IC XT1 32.768 kHz VSS XT2
XT1
XT2
Cautions are listed on the next page.
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Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figure 5-11 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 5-11 shows examples of incorrect resonator connection. Figure 5-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line
PORT
IC
X2
X1
IC
X2
X1
VSS
VSS
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
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Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
VDD0
Pmn IC X2 X1
High current
IC
X2
X1
A VSS
B High current
C
VSS
(e) Signals are fetched
IC
X2
X1
VSS
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. To prevent that from occurring, it is recommended to wire X2 and XT1 so that they are not in parallel, and to connect the IC pin between X2 and XT1 directly to VSS.
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5.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect to EVDD or VDD XT2: Leave open In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the X1 input clock and Ring-OSC clock stop. To minimize leakage current, the above on-chip feedback resistor can be set not to be used via bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as described above. 5.4.4 Ring-OSC oscillator Ring-OSC oscillator is incorporated in this product. "Can be stopped by software" or "Cannot be stopped" can be selected by a mask option. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)). 5.4.5 Prescaler The prescaler generates various clocks by dividing the X1 oscillator output (fX) when the X1 input clock is selected as the clock to be supplied to the CPU. Caution When the Ring-OSC clock is selected as the clock supplied to the CPU, the prescaler generates various clocks by dividing the Ring-OSC oscillator output (fX) (fX = 240 kHz (TYP.)).
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * X1 input clock fXP * Ring-OSC clock fR * Subsystem clock fXT * CPU clock fCPU * Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KD1 Series, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction.
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(2) Improvement of performance Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-12. Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC
X1 input clock (fXP)
Ring-OSC clock (fR)
Subsystem clock (fXT)
RESET
Switched by software
CPU clock Operation stopped: 17/fR
Ring-OSC clock
X1 input clock
X1 oscillation stabilization time: 211/fXP to 216/fXPNote
Note Check using the oscillation stabilization time counter status register (OSTC). (a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the RingOSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped. (b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit 0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1 (MCS) of MCM. (c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when "Can be stopped by software" is selected for the Ring-OSC by a mask option, if the X1 input or subsystem clock is used as the CPU clock. Make sure that MCS is 1 at this time. (d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time. When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the STOP instruction).
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(e) Select the X1 input clock oscillation stabilization time (2 /fXP, 2 /fXP, 2 /fXP, 2 /fXP, 2 /fXP) using the oscillation stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC). A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively. Figure 5-13. Status Transition Diagram (1/4) (1) When "Ring-OSC can be stopped by software" is selected by mask option (when subsystem clock is not used)
HALTNote 4 Interrupt Interrupt HALT instruction Status 4 RSTOP = 0 CPU clock: fXP fXP: Oscillating fR: Oscillation stopped RSTOP = 1Note 1 Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating Interrupt HALT instruction MCM0 = 0 MCM0 = 1Note 2 HALT instruction HALT instruction
11
13
14
15
16
Interrupt
Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating
MSTOP = 1Note 3
Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating MSTOP = 0
Interrupt STOP instruction
STOP instruction
Interrupt STOP instruction
STOP instruction Interrupt Interrupt
STOPNote 4 Reset release
ResetNote 5
Notes 1. 2.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC).
3. 4.
When shifting from status 2 to status 1, make sure that MCS is 0. When "Ring-OSC can be stopped by software" is selected by a mask option, the watchdog timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer. However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (2/4) (2) When "Ring-OSC can be stopped by software" is selected by mask option (when subsystem clock is used)
Status 6 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating/ oscillation stopped MCC = 1 MCC = 0 HALT instruction Interrupt HALTNote 4 HALT instruction Interrupt HALT instruction Interrupt HALT instruction HALT instruction
Interrupt
Status 5 CPU clock: fXT fXP: Oscillating fR: Oscillating/ oscillation stopped
CSS = 0Note 6 CSS = 1Note 5
Status 4 Status 3 CPU clock: fXP RSTOP = 0 CPU clock: fXP fXP: Oscillating fXP: Oscillating fR: Oscillation RSTOP = 1Note 1 fR: Oscillating stopped
Interrupt Status 1 Status 2 MCM0 = 0 MSTOP = 1Note 3 CPU clock: fR CPU clock: fR fXP: Oscillation fXP: Oscillating stopped MCM0 = 1Note 2 fR: Oscillating MSTOP = 0 fR: Oscillating STOP STOP instruction instruction Interrupt Interrupt Interrupt STOPNote 4 Reset release
STOP instruction
ResetNote 7
Notes 1. 2.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC).
3. 4.
When shifting from status 2 to status 1, make sure that MCS is 0. When "Ring-OSC can be stopped by software" is selected by a mask option, the Ring-OSC oscillator is stopped after the HALT or STOP instruction has been executed, regardless of the setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) and bit 0 (MCM0) of the main clock mode register (MCM).
5. 6. 7.
Shifting to status 5 (subsystem clock operation) can be performed only from status 3 or 4 (X1 input clock operation). Shifting to status 1 or status 2 from status 5 is not possible. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (3/4) (3) When "Ring-OSC cannot be stopped" is selected by mask option (when subsystem clock is not used)
HALT
Interrupt
Interrupt HALT instruction
HALT instruction Interrupt
HALT instruction
Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating
MCM0 = 0 MCM0 = 1Note 1
Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating
MSTOP = 1Note 2
MSTOP = 0 STOP instruction
Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating
Interrupt STOP instruction STOP instruction
Interrupt
Interrupt
STOPNote 3
Reset release ResetNote 4
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC).
2. 3.
When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped" is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution.
4.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (4/4) (4) When "Ring-OSC cannot be stopped" is selected by mask option (when subsystem clock is used)
Status 5 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1 HALT instruction Status 4 CPU clock: fXT fXP: Oscillating fR: Oscillating/ oscillation stopped Interrupt HALT HALT instruction Interrupt HALT instruction Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating MCM0 = 0 MCM0 = 1Note 1 Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating Interrupt HALT instruction Interrupt HALT instruction
CSS = 0Note 5 CSS = 1Note 4
MSTOP = 1Note 2
MSTOP = 0 STOP instruction
Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating
Interrupt STOP instruction STOP instruction Interrupt
Interrupt
STOPNote 3
Reset release ResetNote 6
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC).
2. 3.
When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped" is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution.
4. 5. 6.
Shifting to status 4 (subsystem clock operation) can be performed only from status 3 (X1 input clock operation). Shifting to status 1 or status 2 from status 4 is not possible. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Table 5-3. Relationship Between Operation Clocks in Each Operation Status
Status X1 Oscillator Note 1 Ring-OSC Oscillator Note 2 RSTOP = 0 Stopped Stopped Oscillating Oscillating Oscillating Stopped RSTOP = 1 Stopped Oscillating Ring-OSC Note 3 Note 4 Stopped Stopped Ring-OSC X1 Subsystem Clock Oscillator CPU Clock After Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1
Operation Mode Reset STOP HALT
Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Notes 1. 2. 3. 4. When "Cannot be stopped" is selected for Ring-OSC by a mask option. When "Can be stopped by software" is selected for Ring-OSC by a mask option. Operates using the CPU clock at STOP instruction execution. Operates using the CPU clock at HALT instruction execution.
Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) Table 5-4. Oscillation Control Flags and Clock Oscillation Status
X1 Oscillator MSTOP = 1
Note
Ring-OSC Oscillator Oscillating
RSTOP = 0 RSTOP = 1
Stopped Setting prohibited Oscillating
MSTOP = 0
Note
RSTOP = 0 RSTOP = 1
Oscillating Stopped
MCC = 1Note
RSTOP = 0 RSTOP = 1
Stopped
Oscillating Stopped
MCC = 0
Note
RSTOP = 0 RSTOP = 1
Oscillating
Oscillating Stopped
Note Setting X1 oscillator oscillating/stopped differs depending on the CPU clock used. * When the Ring-OSC clock is used as the CPU clock: Set using the MSTOP bit * When the subsystem clock is used as the CPU clock: Set using the MCC bit Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: Bit 7 of the processor clock control register (PCC) RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
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5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 5-5). Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock. To stop the clock, wait for the number of clocks shown in Table 5-5 before stopping. Table 5-5. Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
PCC PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 PCC0 0 1 0 1 0 fXP/fR + 1 clock fXP/2fR + 1 clock fXP/4fR + 1 clock fXP/8fR + 1 clock fXP/16fR + 1 clock Time Required for Switching X1Ring-OSC Ring-OSCX1 2 clocks
Caution To calculate the maximum time, set fR = 120 kHz. Remarks 1. PCC: Processor clock control register 2. fXP: X1 input clock oscillation frequency 3. fR: Ring-OSC clock oscillation frequency 4. The maximum time is the number of clocks of the CPU clock before switching.
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5.7 Changing System Clock and CPU Clock Settings
5.7.1 Time required for switching between system clock and CPU clock The system clock and CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 5-6). Whether the system is operating on the X1 input clock (or Ring-OSC clock) or the subsystem clock can be ascertained using bit 5 (CLS) of the PCC register. Table 5-6. Maximum Time Required for CPU Clock Switchover
Set Value Before Switchover Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0 0 0 0 0 0 0 1 0 1 0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
x
x
x
16 clocks 8 clocks 4 clocks 4 clocks
16 clocks 8 clocks
16 clocks 8 clocks 4 clocks
16 clocks 8 clocks 4 clocks
fXP/fXT clocks (306 clocks) fXP/2fXT clocks (153 clocks) fXP/4fXT clocks (77 clocks) fXP/8fXT clocks (39 clocks) fXP/16fXT clocks (20 clocks)
0 1 1 x
1 0 x
1 0 x
2 clocks 1 clock 1 clock
2 clocks 1 clock 1 clock
2 clocks 1 clock 1 clock 1 clock 1 clock
2 clocks
1 clock
Remarks 1. The maximum time is the number of clocks of the CPU clock before switching. 2. Figures in parentheses apply to operation with fXP = 10 MHz and fXT = 32.768 kHz. Caution Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1 input clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS from 1 to 0).
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5.8 Clock Switching Flowchart and Register Setting
5.8.1 Switching from Ring-OSC clock to X1 input clock Figure 5-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
After reset release
Register initial value after reset
PCC = 00H RCM = 00H MCM = 00H MOC = 00H OSTC = 00H OSTS = 05HNote
; fCPU = fR ; Ring-OSC oscillation ; Ring-OSC clock operation ; X1 oscillation ; Oscillation stabilization time status register ; Oscillation stabilization time fXP/216
Each processing
OSTC checkNote X1 oscillation stabilization time has not elapsed
; X1 oscillation stabilization time status check
Ring-OSC clock operation
X1 oscillation stabilization time has elapsed
PCC setting Ring-OSC clock operation (dividing set PCC) MCM.0 1
MCM.1 (MCS) is changed from 0 to 1 X1 input clock operation X1 input clock operation
Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released during X1 input clock operation.
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5.8.2 Switching from X1 input clock to Ring-OSC clock Figure 5-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
Register setting in X1 input clock operation
PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H
; X1 oscillation ; X1 input clock or Ring-OSC clock ; X1 input clock operation
Yes: RSTOP = 1 X1 input clock operation RCM.0Note (RSTOP) = 1? ; Ring-OSC oscillating?
No: RSTOP = 0 RSTOP = 0
MCM0 0
; Ring-OSC clock operation
MCM.1 (MCS) is changed from 1 to 0 Ring-OSC clock operation Ring-OSC clock operation
Note Required only when "clock can be stopped by software" is selected for Ring-OSC by a mask option.
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5.8.3 Switching from X1 input clock to subsystem clock Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart)
Register setting in X1 input clock operation
PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H
; X1 oscillation ; X1 input clock or Ring-OSC clock ; X1 input clock operation
X1 input clock operation
CSS 1
; Subsystem clock operation
MCS = 1 not changed. CLS is changed from 0 to 1. Subsystem clock
Subsystem clock operation
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5.8.4 Switching from subsystem clock to X1 input clock Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart)
PCC.4 (CSS) = 1 MCM = 03H
; Subsystem clock operation
No: X1 oscillating MCC = 1? ; X1 oscillating?
Yes: X1 oscillation stopped
MCC 0 Subsystem clock operation
; X1 oscillation enabled
OSTC check X1 oscillation stabilization time not elapsed
; Wait for X1 oscillation stabilization time
X1 oscillation stabilization time elapsed
CSS 0
; X1 input clock operation
CLS is changed from 1 to 0. MCS = 1 not changed. X1 input clock operation X1 input clock operation
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5.8.5 Register settings Table 5-7. Clock and Register Setting
fCPU Mode PCC Register MCC X1 input clock
Note 2
Setting Flag
Status Flag
MCM MOC RCM PCC MCM Register Register Register Register Register MCM0 1 1 0 0 1 1 1
Note 5
CSS 0 0 0 0 1 1 1 1
MSTOP RSTOPNote 1 0 0 0 1 0 0 0 0
Note 6
CLS 0 0 0 0 1 1 1 1
MCS 1 1 0 0 1 1 1 1
Ring-OSC oscillating Ring-OSC stopped
0 0 0 0
Note 3
0 1 0 0 0 0 1 1
Ring-OSC clock
X1 oscillating X1 stopped
Subsystem clock
Note 4
X1 oscillating, Ring-OSC oscillating X1 stopped, Ring-OSC oscillating X1 oscillating, Ring-OSC stopped X1 stopped, Ring-OSC stopped
0 1 0 1
Note 5
Note 6
Note 5
Note 6
1
Note 5
Note 6
Notes 1. 2. 3. 4. 5. 6.
Valid only when "clock can be stopped by software" is selected for Ring-OSC by a mask option. Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set, the X1 oscillation does not stop). Do not set MCC = 1 during Ring-OSC operation (even if MCC = 1 is set, the X1 oscillation does not stop). To stop X1 oscillation during Ring-OSC operation, use MSTOP. Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode. From subsystem clock operation mode, only X1 input clock operation mode can be shifted to. Do not set MCM0 = 0 (shifting to Ring-OSC operation) during subsystem clock operation. Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does not stop). To stop X1 oscillation during subsystem clock operation, use MCC.
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6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval. (2) PPG output 16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) Pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. (4) External event counter 16-bit timer/event counter 00 can measure the number of pulses of an externally input signal. (5) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. (6) One-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely.
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6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item Timer counter Register Timer output Control registers 16 bits x 1 (TM00) 16-bit timer capture/compare register: 16 bits x 2 (CR000, CR010) 1 (TO00) 16-bit timer mode control register 00 (TMC00) 16-bit timer capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 0 (PM0)Note Configuration
Note See Figure 4-2 Block Diagram of P00 and P03 and Figure 4-3 Block Diagram of P01. Figure 6-1 shows the block diagram. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000
Selector
INTTM000
Selector
TI010/TO00/P01
Noise eliminator
16-bit timer capture/compare register 000 (CR000) Match
Selector
fX fX/22 fX/28
16-bit timer counter 00 (TM00) Match
Clear Output controller TO00/TI010/ P01
fX
Noise eliminator
2 Noise eliminator 16-bit timer capture/compare register 010 (CR010)
Selector
TI000/P00
INTTM010
CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus
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(1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the mode in which clear & start occurs when inputting the valid edge of TI000 <4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000 <5> OSPT00 is set in one-shot pulse output mode (2) 16-bit timer capture/compare register 000 (CR000) CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register 00 (CRC00). * When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the interval time when TM00 is set to interval timer operation. * When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or TI010 valid edge is set using prescaler mode register 00 (PRM00). If the capture trigger is specified to be the valid edge of the TI000 pin, the situation is as shown in Table 6-2. On the other hand, when the capture trigger is specified to be the valid edge of the TI010 pin, the situation is as shown in Table 6-3. Table 6-2. TI000 Pin Valid Edge and CR000, CR010 Capture Trigger
ES001 0 0 1 1 ES000 0 1 0 1 TI000 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges CR000 Capture Trigger Rising edge Falling edge Setting prohibited No capture operation CR010 Capture Trigger Falling edge Rising edge Setting prohibited Both rising and falling edges
Table 6-3. TI010 Pin Valid Edge and CR000 Capture Trigger
ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges TI010 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges CR000 Capture Trigger
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CR000 can be set by a 16-bit memory manipulation instruction. RESET input clears CR000 to 0000H. Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match of TM00 and CR000. However, in the free-running mode and in the clear mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated following overflow (FFFFH). 2. If the changed value of CR000 is smaller than the value of 16-bit timer counter 00 (TM00), TM00 continues counting and starts counting again from 0 after overflow. Therefore, if the value of CR000 after the change is smaller than before the change, the timer should be restarted after CR000 is changed. 3. When P01 is used as the valid edge of TI010, it cannot be used as the timer output (TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge of TI010. 4. When CR000 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 5. Do not rewrite CR000 during TM00 operation. (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). * When CR010 is used as a compare register The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM010) is generated if they match. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by prescaler mode register 00 (PRM00). CR010 can be set by a 16-bit memory manipulation instruction. RESET input clears CR010 to 0000H. Cautions 1. Set CR010 to other than 0000H. This means a 1-pulse count operation cannot be performed when CR010 is used as the event counter. However, in the free-running mode and in the clear mode using the valid edge of TI000, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated following overflow (FFFFH). 2. When CR010 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 3. CR010 can be rewritten during TM00 operation. For details, refer to Remark 2 in Figure 6-12.
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6.3 Registers Controlling 16-Bit Timer/Event Counter 00
The following five registers are used to control 16-bit timer/event counter 00. * 16-bit timer mode control register 00 (TMC00) * Capture/compare control register 00 (CRC00) * 16-bit timer output control register 00 (TOC00) * Prescaler mode register 00 (PRM00) * Port mode register 0 (PM0) (1) 16-bit timer mode control register 00 (TMC00) This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to values other than 0, 0 (operation stop mode), respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation.
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Figure 6-2. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH Symbol TMC00 7 0 6 0 After reset: 00H 5 0 4 0 R/W 3 2 1 0
TMC003 TMC002 TMC001 OVF00
TMC003 TMC002 TMC001
Operating mode and clear mode selection Operation stop (TM00 cleared to 0) Free-running mode
TO00 output timing selection
Interrupt request generation
0 0 0
0 0 1
0 1 0
No change
Not generated
Match between TM00 and CR000 or match between TM00 and CR010 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge
Generated on match between TM00 and CR000, or match between TM00 and CR010
0
1
1
1 1 1
0 0 1
0 1 0
Clear & start occurs on TI000 valid edge Clear & start occurs on match between TM00 and CR000
-
Match between TM00 and CR000 or match between TM00 and CR010 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge
1
1
1
OVF00 0 1 Overflow not detected Overflow detected
16-bit timer counter 00 (TM00) overflow detection
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag. 2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00). 3. If any of the following modes: the mode in which clear & start occurs on match between TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or freerunning mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Remarks 1. TO00: 2. TI000: 3. TM00: 16-bit timer/event counter 00 output pin 16-bit timer/event counter 00 input pin 16-bit timer counter 00
4. CR000: 16-bit timer capture/compare register 000 5. CR010: 16-bit timer capture/compare register 010
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(2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-3. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH Symbol CRC00 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC002 1 CRC001 0 CRC000
CRC002 0 1
CR010 operating mode selection Operates as compare register Operates as capture register
CRC001 0 1
CR000 capture trigger selection Captures on valid edge of TI010 Captures on valid edge of TI000 by reverse phase
CRC000 0 1
CR000 operating mode selection Operates as compare register Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC00. 2. When the mode in which clear & start occurs on a match between TM00 and CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. To ensure that the capture operation is performed properly, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (PRM00). (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the R-S type flip-flop (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC00 to 00H.
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Figure 6-4. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH Symbol TOC00 7 0 After reset: 00H 6 OSPT00 R/W 5 OSPE00 4 TOC004 3 LVS00 2 LVR00 1 TOC001 0 TOE00
OSPT00 0 1
One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger
OSPE00 0 1
One-shot pulse output operation control Successive pulse output mode One-shot pulse output modeNote
TOC004 0 1
Timer output F/F control using match of CR010 and TM00 Disables inversion operation Enables inversion operation
LVS00 0 0 1 1
LVR00 0 1 0 1
16-bit timer/event counter 00 timer output F/F status setting No change Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TOC001 0 1
Timer output F/F control using match of CR000 and TM00 Disables inversion operation Enables inversion operation
TOE00 0 1
16-bit timer/event counter 00 output control Disables output (output fixed to level 0) Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC004. 2. If LVS00 and LVR00 are read after data is set, 0 is read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the operating clock is required to write to OSPT00 successively.
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(4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H. Figure 6-5. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH Symbol PRM00 7 ES101 After reset: 00H 6 ES100 R/W 5 ES001 4 ES000 3 0 2 0 1 PRM001 0 PRM000
ES101 0 0 1 1
ES100 0 1 0 1 Falling edge Rising edge Setting prohibited
TI010 valid edge selection
Both falling and rising edges
ES001 0 0 1 1
ES000 0 1 0 1 Falling edge Rising edge Setting prohibited
TI000 valid edge selection
Both falling and rising edges
PRM001 0 0 1 1
PRM000 0 1 0 1 fX (10 MHz) fX/22 (2.5 MHz) fX/28 (39.06 kHz) TI000 valid edgeNote
Count clock selection
Note The external clock requires a pulse two times longer than internal clock (fX). Cautions 1. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI000 and the capture trigger. 2. Always set data to PRM00 after stopping the timer operation. 3. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when reenabling operation after the operation has been stopped once, the rising edge is not detected. 4. When P01 is used as the TI010 valid edge, it cannot be used as the timer output (TO00), and when used as TO00, it cannot be used as the TI010 valid edge. Remarks 1. fX: X1 input clock oscillation frequency 2. TI000, TI010: 16-bit timer/event counter 00 input pin 3. Figures in parentheses are for operation with fX = 10 MHz.
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(5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to FFH. Figure 6-6. Format of Port Mode Register 0 (PM0)
Address: FF20H Symbol PM0 7 1 6 1 After reset: FFH 5 1 4 1 R/W 3 2 1 0
PM03 PM02 PM01 PM00
PM0n 0 1
P0n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off)
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6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-7 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 000 (CR000) as the interval. When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated. The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). See 6.5 Cautions for 16-Bit Timer/Event Counter 00 (2) 16-bit timer capture/compare register setting for details of the operation when the compare register value is changed during timer count operation. Figure 6-7. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 1 1 0/1 0 Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 0/1 0/1 0 CR000 used as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. For details, see Figures 6-2 and 6-3.
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Figure 6-8. Interval Timer Configuration Diagram
16-bit timer capture/compare register 000 (CR000)
INTTM000 fX fX/22 fX/28 TI000/P00 Noise eliminator
Selector
16-bit timer counter 00 (TM00)
OVF00
Clear circuit
fX
Figure 6-9. Timing of Interval Timer Operation
t
Count clock TM00 count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N
Count start CR000 INTTM000 N
Interrupt acknowledged TO00 Interval time Interval time
Interrupt acknowledged
Interval time
Remark Interval time = (N + 1) x t N = 0001H to FFFFH
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6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively. Figure 6-10. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 1 1 0 0 Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 0 x 0 CR000 used as compare register CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 0 0 0 1 0/1 0/1 1 1 Enables TO00 output Inverts output on match between TM00 and CR000 Specifies initial value of TO00 output F/F Inverts output on match between TM00 and CR010 Disables one-shot pulse output
Cautions 1. Values in the following range should be set in CR000 and CR010: 0000H < CR010 < CR000 FFFFH 2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). Remark x: Don't care
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Figure 6-11. Configuration of PPG Output
16-bit timer capture/compare register 000 (CR000)
fX fX/22 fX/28 TI000/P00 Noise eliminator fX
Selector
16-bit timer counter 00 (TM00)
Clear circuit
Output controller
TO00/TI010/P01
16-bit timer capture/compare register 010 (CR010)
Figure 6-12. PPG Output Operation Timing
t
Count clock TM00 count value 0000H 0001H Count start CR000 capture value CR010 capture value TO00 Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H
Clear
Caution CR000 cannot be rewritten during TM00 operation. Remarks 1. 0000H < M < N FFFFH 2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation using the following procedure. <1> Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0) <2> Disable the INTTM010 interrupt (TMMK010 = 1) <3> Rewrite CR010 <4> Wait for 1 cycle of the TM00 count clock <5> Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1) <6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0) <7> Enable the INTTM010 interrupt (TMMK010 = 0)
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6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode (see register settings in Figure 6-13), and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of PRM00. For valid edge detection, sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-13. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 1 0/1 0 CR000 used as compare register CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. For details, see Figures 6-2 and 6-3.
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Figure 6-14. Configuration Diagram for Pulse Width Measurement with Free-Running Counter
fX
Selector
fX/22 fX/28
16-bit timer counter 00 (TM00)
OVF00
TI000
16-bit timer capture/compare register 010 (CR010) INTTM010 Internal bus
Figure 6-15. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified)
t
Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3
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(2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-16), it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Any of three edgesrising, falling, or both edgescan be selected as the valid edge of the TI000 pin and the TI010 pin, specified using bits 4 and 5 (ES000 and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00, respectively. For valid edge detection of the TI000 and TI010 pins, sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-16. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000 CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. For details, see Figure 6-2.
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* Capture operation (free-running mode) The capture register operation when capture trigger is input is shown below. Figure 6-17. CR010 Capture Operation with Rising Edge Specified
Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N N-3 N-2 N-1 N N+1
Figure 6-18. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified)
t
Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 capture value INTTM000 OVF00 D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
(10000H - D1 + (D2 + 1)) x t
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(3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-19), it is possible to measure the pulse width of the signal input to the TI000 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Either of two edgesrising or fallingcan be selected as the valid edge of the TI000 pin specified using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). For TI000 pin valid edge detection, sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 6-20. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
t
Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3
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(4) Pulse width measurement by means of restart When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count operation (see Figure 6-21). Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). In valid edge detection, sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-21. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 1 0 0/1 0 Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000.
CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. For details, see Figure 6-2. Figure 6-22. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
t
Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 D1 x t D2 x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H
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6.4.4 External event counter operation The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out). Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). Because operation is carried out only after the valid edge is detected twice by sampling using the internal clock (fX), noise with short pulse widths can be eliminated. Figure 6-23. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 1 1 0/1 0 Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 0/1 0/1 0 CR000 used as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. For details, see Figures 6-2 and 6-3.
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Figure 6-24. Configuration Diagram of External Event Counter
16-bit timer capture/compare register 000 (CR000) Match INTTM000 fX fX/28 fX Valid edge of TI000 Noise eliminator Noise eliminator 16-bit timer capture/compare register 010 (CR010)
Selector
Clear 16-bit timer counter 00 (TM00) OVF00
fX/22
Internal bus
Figure 6-25. External Event Counter Operation Timing (with Rising Edge Specified)
TI000 pin input TM00 count value CR000 INTTM000 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H
Caution When reading the external event counter count value, TM00 should be read.
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6.4.5 Square-wave output operation A square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals of the count value preset to CR000 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected frequency to be output. Figure 6-26. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00 TMC00 0 0 0 0 1 1 0 0 Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000 CRC00 0 0 0 0 0 0/1 0/1 0 CR000 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 0 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F. Does not invert output on match between TM00 and CR010. Disables one-shot pulse output.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. For details, see Figures 6-3 and 6-4. Figure 6-27. Square-Wave Output Operation Timing
Count clock TM00 count value CR000 INTTM000 TO00 pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H
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6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-27, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software. By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000 (CR000)
Note
.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00 register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Cautions 1. Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing.
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Figure 6-28. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC00 0 0 0 0 0 TMC002 TMC001 1 0 OVF00 0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC00 0 0 0 0 0 0 0/1 CRC000 0
CR000 as compare register CR010 as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 TOC00 0 0 1 1 LVS00 0/1 LVR00 0/1 TOC001 1 TOE00 1
Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F/F Inverts output upon match between TM00 and CR010 Sets one-shot pulse output mode
Set to 1 for output
Caution Do not set 0000H to the CR000 and CR010 registers. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. For details, see Figures 6-3 and 6-4.
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Figure 6-29. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value CR000 set value OSPT00 INTTM010 INTTM000 TO00 pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. Remark N < M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-30, and by using the valid edge of the TI000 pin as an external trigger. The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES001) of prescaler mode register 00 (PRM00). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (CR000)
Note
.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored.
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Figure 6-30. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 TMC00 0 0 0 0 1 0 0 OVF00 0
Clears and starts at valid edge of TI000 pin
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC00 0 0 0 0 0 0 0/1 CRC000 0
CR000 used as compare register CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 TOC00 0 0 1 1 LVS00 0/1 LVR00 0/1 TOC001 1 TOE00 1
Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F/F Inverts output upon match between TM00 and CR010 Sets one-shot pulse output mode
Caution Do not set 0000H to the CR000 and CR010 registers. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. For details, see Figures 6-3 and 6-4.
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Figure 6-31. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
Set TMC00 to 08H (TM00 count starts) Count clock TM00 count value 0000H 0001H CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark N < M
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6.5 Cautions for 16-Bit Timer/Event Counter 00
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-32. Start Timing of 16-Bit Timer Counter 00 (TM00)
Count clock
TM00 count value
0000H
0001H
0002H
0003H
0004H
Timer start
(2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match between TM00 and CR000) Set 16-bit timer capture/compare registers 000, 010 (CR000, CR010) to other than 0000H. This means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 00 is used as an event counter. (3) Operation after compare register change during timer count operation If the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR000 changes is smaller than that (N) before the change, it is necessary to restart the timer after changing CR000. Figure 6-33. Timings After Change of Compare Register During Timer Count Operation
Count clock
CR000 X-1
N
M
TM00 count value
X
FFFFH
0000H
0001H
0002H
Remark N > X > M
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(4) Capture register data retention timing If the valid edge of the TI000 pin is input during 16-bit timer capture/compare register 010 (CR010) read, CR010 performs a capture operation. However, the value read at this time is not guaranteed. The interrupt request flag (TMIF010) is set upon detection of the valid edge. Figure 6-34. Capture Register Data Retention Timing
Count clock TM00 count value Edge input Interrupt request flag Capture read signal CR010 interrupt value X N+2 M+1 N N+1 N+2 M M+1 M+2
Capture
Capture, but read value is not guaranteed
(5) Valid edge setting Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). (6) Re-triggering one-shot pulse (a) One-shot pulse output by software When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a match with the CR010 register, occurs. (b) One-shot pulse output with external trigger If the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) One-shot pulse output function When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.
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(7) Operation of OVF00 flag <1> The OVF00 flag is set to 1 in the following case. When of the following modes: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear & start occurs on a TI00 valid edge, or the free-running mode, is selected CR000 is set to FFFFH TM00 is counted up from FFFFH to 0000H. Figure 6-35. Operation Timing of OVF00 Flag
Count clock CR000 TM00 OVF00 INTTM000 FFFFH FFFEH FFFFH 0000H 0001H
<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. (8) Conflicting operations Conflict between the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture trigger input (CR000/CR010 used as capture register) Capture trigger input has priority. The data read from CR000/CR010 is undefined. (9) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI000/TI010 pins are not acknowledged. <3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur.
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(10) Capture operation <1> If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI000 is not possible. <2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (PRM00). <3> The capture operation is performed at the falling edge of the count clock. An interrupt request input (INTTM000/INTTM010), however, is generated at the rise of the next count clock. (11) Compare operation <1> When the 16-bit timer capture/compare register (CR000/CR010) is overwritten during timer operation, a match interrupt may be generated or a clear operation may not be performed normally if that value is close to or larger than the timer value. <2> A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has been input. (12) Edge detection <1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter 00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful therefore when pulling up the TI000 or TI010 pin. However, the rising edge is not detected at restart after the operation has been stopped once. <2> The sampling clock used to eliminate noise differs when the TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only after a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Mask circuit
8-bit timer compare register 50 (CR50) TI50/TO50/P17 fX fX/2 fX/22 fX/26 fX/28 fX/213 Match
Selector
Selector
INTTM50
8-bit timer OVF counter 50 (TM50) Clear
Selector
S Q INV R
TO50/TI50/P17
3 Selector
S R
Invert level
TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50)
TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus
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Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
Mask circuit
8-bit timer compare register 51 (CR51) TI51/TO51/P33/INTP4 fX fX/2 fX/24 fX/26 fX/28 fX/212 Match
Selector
Selector
INTTM51
8-bit timer OVF counter 51 (TM51) Clear
Selector
S Q INV R
TO51/TI51/P33/INTP4
3 Selector
S R
Invert level
TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51)
TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus
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7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item Timer register Register Timer output Control registers 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) 1 (TO5n) Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1)Note or port mode register 3 (PM3)Note Configuration
Note See Figure 4-10 Block Diagram of P16 and P17 and Figure 4-13 Block Diagram of P33. (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. When the count value is read during operation, count clock input is temporary stopped, and then the count value is read. In the following situations, the count value is cleared to 00H. <1> RESET input <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In PWM mode, when the TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n match, the TO5n pin becomes inactive. The value of CR5n can be set within 00H to FFH. Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1
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7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following three registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI5n input. TCL5n can be set by an 8-bit memory manipulation instruction. RESET input clears TCL5n to 00H. Remark n = 0, 1 Figure 7-3. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500
TCL502 0 0 0 0 1 1 1 1
TCL501 0 0 1 1 0 0 1 1
TCL500 0 1 0 1 0 1 0 1 TI50 falling edge TI50 rising edge fX (10 MHz) fX/2 (5 MHz) fX/22 (2.5 MHz) fX/26 (156.25 kHz) fX/28 (39.06 kHz) fX/213 (1.22 kHz)
Count clock selection
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz.
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Figure 7-4. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH Symbol TCL51 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL512 1 TCL511 0 TCL510
TCL512 0 0 0 0 1 1 1 1
TCL511 0 0 1 1 0 0 1 1
TCL510 0 1 0 1 0 1 0 1 TI51 falling edge TI51 rising edge fX (10 MHz) fX/2 (5 MHz) fX/24 (625 kHz) fX/26 (156.25 kHz) fX/28 (39.06 kHz) fX/212 (2.44 kHz)
Count clock selection
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz.
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(2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip-flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH Symbol TMC50 7 TCE50 After reset: 00H 6 TMC506 R/WNote 5 0 4 0 3 LVS50 2 LVR50 1 TMC501 0 TOE50
TCE50 0 1
TM50 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start
TMC506 0 1
TM50 operating mode selection Mode in which clear & start occurs on a match between TM50 and CR50 PWM (free-running) mode
LVS50 0 0 1 1
LVR50 0 1 0 1 No change
Timer output F/F status setting
Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TMC501
In other modes (TMC506 = 0) Timer F/F control
In PWM mode (TMC506 = 1) Active level selection Active-high Active-low
0 1
Inversion operation disabled Inversion operation enabled
TOE50 0 1
Timer output control Output disabled (TO50 pin outputs the low level) Output enabled
Note Bits 2 and 3 are write-only. (Refer to Caution and Remark on the page after the next.)
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Figure 7-6. Format of 8-Bit Timer Mode Control Register 51 (TMC51)
Address: FF43H Symbol TMC51 7 TCE51 After reset: 00H 6 TMC516 R/WNote 5 0 4 0 3 LVS51 2 LVR51 1 TMC511 0 TOE51
TCE51 0 1
TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start
TMC516 0 1
TM51 operating mode selection Mode in which clear & start occurs on a match between TM51 and CR51 PWM (free-running) mode
LVS51 0 0 1 1
LVR51 0 1 0 1 No change
Timer output F/F status setting
Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TMC511
In other modes (TMC516 = 0) Timer F/F control
In PWM mode (TMC516 = 1) Active level selection Active-high Active-low
0 1
Inversion operation disabled Inversion operation enabled
TOE51 0 1
Timer output control Output disabled (TO51 pin outputs the low level) Output enabled
Note Bits 2 and 3 are write-only. (Refer to Caution and Remark on the next page.)
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Cautions 1. To clear TCE5n to 0, set the interrupt mask flag (TMMK5n) to 1 beforehand. Otherwise, an interrupt may occur when TCE5n is cleared. TCE5n is cleared to 0 as follows. TMMK5n = 1; TCE5n = 0; TMIF5n = 0; TMMK5n = 0;
* * *
Mask set Timer clear Interrupt request flag clear Mask clear Timer start
TCE5n = 1;
* * *
2. The settings of LVS5n and LVR5n are valid in other than PWM mode. 3. Do not rewrite TMC5n1 and TOE5n simultaneously. 4. When switching to the PWM mode, do not rewrite TM5n6 and LVS5n or LVR5n simultaneously. 5. To rewrite TMC5n6, stop operation beforehand. Remarks 1. In PWM mode, PWM output is made inactive by setting TCE5n to 0. 2. If LVS5n and LVR5n are read after data is set, 0 is read. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1
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(3) Port mode register 1 (PM1) and port mode register 3 (PM3) These registers set ports 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, set PM17 and PM33 and the output latches of P17 and P33 to 0. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 7-7. Format of Port Mode Register 1 (PM1)
Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10
PM1n 0 1
P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
Figure 7-8. Format of Port Mode Register 3 (PM3)
Address: FF23H Symbol PM3 7 0 After reset: FFH 6 0 R/W 5 0 4 0 3 PM33 2 PM32 1 PM31 0 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off)
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7.4 Operations of 8-Bit Timer/Event Counters 50 and 51
7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). [Setting] <1> Set the registers. * TCL5n: * CR5n: * TMC5n: Select the count clock. Compare value Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Set TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Figure 7-9. Interval Timer Operation Timing (1/2) (a) Basic operation
t Count clock TM5n count value 00H 01H N 00H 01H N 00H 01H N
Count start CR5n TCE5n INTTM5n N
Clear N
Clear N N
Interrupt acknowledged TO5n Interval time Interval time
Interrupt acknowledged
Interval time
Remark Interval time = (N + 1) x t N = 00H to FFH n = 0, 1
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Figure 7-9. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H
t Count clock TM5n 00H CR5n TCE5n INTTM5n TO5n 00H 00H 00H 00H
Interval time
(c) When CR5n = FFH
t Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged TO5n Interval time Interrupt acknowledged FF 01 FE FF FF 00 FE FF FF 00
Remark n = 0, 1
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7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. [Setting] <1> Set each register. * TCL5n: Select TI5n input edge. TI5n falling edge TCL5n = 00H TI5n rising edge TCL5n = 01H * CR5n: Compare value CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 0000xx00B x = Don't care) <2> When TCE5n = 1 is set, the number of pulses input from TI5n is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Figure 7-10. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n Count start TM5n count value CR5n INTTM5n 00 01 02 03 04 05 N-1 N N 00 01 02 03
* TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
Remark N = 00H to FFH n = 0, 1
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7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). [Setting] <1> Set each register. * Set the port latches (P17 and P33) * TCL5n: Select the count clock. * CR5n: Compare value CR5n.
LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting High-level output Low-level output
Note
and port mode registers (PM17 and PM33)
Note
to 0.
* TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and
Timer output F/F inversion enabled Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. Frequency = fCNT/2 (N + 1) (N: 00H to FFH, fCNT: Count clock) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remark n = 0, 1
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Figure 7-11. Square-Wave Output Operation Timing
Count clock
TMn count value
00H
01H
02H
N-1
N
00H
01H
02H
N-1
N
00H
Count start CR5n N
TO5nNote
Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
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7.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty ratio pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. (1) PWM output basic operation [Setting] <1> Set each register. * Set the port latches (P17, P33) * CR5n: Compare value The timer output F/F is not changed.
TMC5n1 0 1 Active-high Active-low Active Level Selection
Note
and port mode registers (PM17, PM33)
Note
to 0.
* TCL5n: Select the count clock. * TMC5n: Stop the count operation, select PWM mode.
Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Set TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 [PWM output operation] <1> PWM output (output from TO5n) outputs an inactive level after the count operation starts until an overflow occurs. <2> When an overflow occurs, the active level set in <1> above is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. Remark n = 0, 1
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Figure 7-12. PWM Output Operation Timing (a) Basic operation (active level = H)
Count clock TM5n CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H
(b) CR5n = 00H
Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N+1N+2 FFH 00H 01H 02H M 00H
(c) CR5n = FFH
TM5n CR5n TCE5n INTTM5n TO5n
00H 01H FFH
FFH 00H 01H 02H
N N+1 N+2
FFH 00H 01H 02H
M 00H
Inactive level
Active level
Active level Inactive level
Inactive level
Remark n = 0, 1
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(2) Operation with CR5n changed Figure 7-13. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is reloaded to CR5n at overflow immediately after change.
Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> CR5n change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2
(b) CR5n value is changed from N to M after clock rising edge of FFH Value is reloaded to CR5n at second overflow.
Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> CR5n change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
Caution When reading from CR5n between <1> and <2> in Figure 7-13, the value read differs from the actual value (read value: M, actual value of CR5n: N).
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51
(1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 7-14. 8-Bit Timer Counter 5n Start Timing
Count clock TM5n count value 00H Timer start 01H 02H 03H 04H
Remark n = 0, 1
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8.1 Functions of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 have the following functions. * 8-bit-accuracy interval timer * 8-bit-accuracy PWM pulse generator mode * 8-bit-accuracy carrier generator mode (8-bit timer H1 only)
8.2 Configuration of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 consist of the following hardware. Table 8-1. Configuration of 8-Bit Timers H0 and H1
Item Timer register Registers Timer output Control registers 8-bit timer counter Hn (TMHn) 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Two outputs (TOHn) 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register 1 (TMCYC1)Note Configuration
Note 8-bit timer H1 only Remark n = 0, 1 Figures 8-1 and 8-2 show the block diagrams.
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Figure 8-1. Block Diagram of 8-Bit Timer H0
Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01TMMD00 TOLEV0 TOEN0
8-bit timer H compare register 10 (CMP10)
8-bit timer H compare register 00 (CMP00)
3
2
Decoder Selector Match Interrupt generator
F/F R
TOH0/P15
fX fX/2 fX/22 fX/26 fX/210 TO50/TI50/P17
Output controller
Level inversion
Selector
8-bit timer counter H0 (TMH0) Clear PWM mode signal
1 0
Timer H enable signal
INTTMH0
Figure 8-2. Block Diagram of 8-Bit Timer H1
Internal bus 8-bit timer H mode control register 1 (TMHMD1)
TMHE1 CKS12 CKS11 CKS10 TMMD11TMMD10 TOLEV1 TOEN1 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1)
8-bit timer H compare register 11 (CMP11)
8-bit timer H compare register 01 (CMP01)
3
2
Decoder Selector Match Interrupt generator
F/F R
Reload/ interrupt control
INTTM51 TOH1/ INTP5/ P16
fX fX/22 fX/24 fX/26 fX/212 fR/27
Output controller
Level inversion
Selector
8-bit timer counter H1 (TMH1) Carrier generator mode signal PWM mode signal
1 0
Clear
Timer H enable signal
INTTMH1
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(1) 8-bit timer H compare register 0n (CMP0n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H.
After reset: 00H 7 CMP0n R/W 6 Address: FF18H, FF1AH 5 4 3 2 1 0
Caution This register cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H.
After reset: 00H 7 CMP1n R/W 6 Address: FF19H, FF1BH 5 4 3 2 1 0
The CMP1n register can be rewritten during timer count operation. In the carrier generator mode, an interrupt request signal (INTTMHn) is generated if the values of the timer counter and CMP1n register match after setting the CMP1n register. The timer counter value is cleared at the same time. If the CMP1n register value is rewritten during timer operation, reloading is performed at the timing at which the counter value and CMP1n register value match. If the transfer timing and writing from CPU to CMP1n register conflict, transfer is not performed. Caution In the PWM pulse generator mode and carrier generator mode, be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). Remark n = 0, 1
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8.3 Registers Controlling 8-Bit Timers H0 and H1
8-bit timers H0 and H1 are controlled by 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) and 8-bit timer H carrier control register 1 (TMCYC1) Note 8-bit timer H1 only (1) 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) These registers control the mode of timer H. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Note
.
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Figure 8-3. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
Address: FF69H 7 TMHMD0 TMHE0 After reset: 00H 6 CKS02 R/W 5 CKS01 4 CKS00 3 2 1 0 TOEN0
TMMD01 TMMD00 TOLEV0
TMHE0 0 1
Timer operation enable Stops timer count operation Enables timer count operation (count operation started by inputting clock)
CKS02 0 0 0 0 1 1
CKS01 0 0 1 1 0 0
CKS00 0 1 0 1 0 1 fX fX/2 fX/2 fX/2 fX/2
2 6 10
Count clock (fCNT) selection (10 MHz) (5 MHz) (2.5 MHz) (156.25 kHz) (9.77 kHz)
TO50 Setting prohibited
Other than above
TMMD01 TMMD00 0 1 0 0 Interval timer mode
Timer operation mode
PWM pulse generator mode Setting prohibited
Other than above
TOLEV0 0 1 Low level High level
Timer output level control (in default mode)
TOEN0 0 1 Disables output Enables output
Timer output control
Cautions 1. When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited. 2. In the PWM pulse generator mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to the CMP10 register). Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz
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Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
Address: FF6CH 7 TMHMD1 TMHE1 After reset: 00H 6 CKS12 R/W 5 CKS11 4 CKS10 3 2 1 0 TOEN1
TMMD11 TMMD10 TOLEV1
TMHE1 0 1
Timer operation enable Stops timer count operation Enables timer count operation (count operation started by inputting clock)
CKS12 0 0 0 0 1 1
CKS11 0 0 1 1 0 0
CKS10 0 1 0 1 0 1 fX fX/2 fX/2
2 4
Count clock (fCNT) selection (10 MHz) (2.5 MHz) (625 kHz) (156.25 kHz) (2.44 kHz) (1.88 kHz (TYP.))
fX/26 fX/2
12 7
fR/2
Other than above
Setting prohibited
TMMD11 TMMD10 0 0 1 0 1 0 Interval timer mode
Timer operation mode
Carrier generator mode PWM pulse generator mode Setting prohibited
Other than above
TOLEV1 0 1 Low level High level
Timer output level control (in default mode)
TOEN1 0 1 Disables output Enables output
Timer output control
Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 2. In the PWM pulse generator mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 3. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. Remarks 1. fX: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at fX = 10 MHz, fR = 240 kHz (TYP.).
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(2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-5. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
Address: FF6DH 7 TMCYC1 0 After reset: 00H 6 0 R/WNote 5 0 4 0 3 0 2 RMC1 1 NRZB1 0 NRZ1
RMC1 0 0 1 1
NRZB1 0 1 0 1 Low-level output
Remote control output
High-level output Low-level output Carrier pulse output
NRZ1 0 1
Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status)
Note Bit 0 is read-only.
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8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. (1) Usage Generates the INTTMHn signal repeatedly at the same interval. <1> Set each register. Figure 8-6. Register Setting in Interval Timer Mode (i) Setting timer H mode register n (TMHMDn)
TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1
Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped
(ii) CMP0n register setting * Compare value (N) <2> Count operation starts when TMHEn = 1. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N +1)/fCNT
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set TMHEn to 0. Remark n = 0, 1
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(2) Timing chart The timing in interval timer mode is shown below. Figure 8-7. Timing of Interval Timer Operation (1/2) (a) Basic operation
Count clock Count start
8-bit timer counter Hn
00H
01H
N
00H Clear
01H
N
00H Clear
01H 00H
CMP0n
N
TMHEn
INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn operation. If these are inactive from the first, the level is retained. Remark n = 0, 1 N = 00H to FFH
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Figure 8-7. Timing of Interval Timer Operation (2/2) (b) Operation when CMP0n = FFH
Count clock Count start
8-bit timer counter Hn
00H
01H
FEH
FFH
00H Clear
FEH
FFH
00H Clear
CMP0n
FFH
TMHEn
INTTMHn
TOHn Interval time
(c) Operation when CMP0n = 00H
Count clock Count start
8-bit timer counter Hn
00H
CMP0n
00H
TMHEn
INTTMHn
TOHn Interval time
Remark n = 0, 1
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8.4.2 Operation as PWM pulse generator In PWM mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM mode is as follows. TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn and the CMP1n register match. (1) Usage In PWM mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 8-8. Register Setting in PWM Pulse Generator Mode (i) Setting timer H mode register n (TMHMDn)
TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1
Timer output enabled Timer output level inversion setting PWM mode selection Count clock (fCNT) selection Count operation stopped
(ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) < FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time, the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register.
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<4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty ratio can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty ratio are as follows. PWM pulse output cycle = (N+1)/fCNT Duty ratio = Inactive width : Active width = (M + 1) : (N - M) At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not
Cautions 1. In PWM mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register).
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(2) Timing chart The operation timing in PWM mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) < FFH Remark n = 0, 1 Figure 8-9. Operation Timing in PWM Pulse Generator Mode (1/4) (a) Basic operation
Count clock
8-bit timer counter Hn
00H 01H
A5H 00H 01H 02H
A5H 00H 01H 02H
A5H 00H
CMP0n
A5H
CMP1n
01H
TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4>
<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0). <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1
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Figure 8-9. Operation Timing in PWM Pulse Generator Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H
Count clock
8-bit timer counter Hn
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
FFH 00H
CMP0n
FFH
CMP1n
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
(c) Operation when CMP0n = FFH, CMP1n = FEH
Count clock
8-bit timer counter Hn
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
FEH FFH 00H
CMP0n
FFH
CMP1n
FEH
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark n = 0, 1
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Figure 8-9. Operation Timing in PWM Pulse Generator Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H
Count clock
8-bit timer counter Hn
00H
01H 00H 01H 00H
00H 01H 00H 01H
CMP0n
01H
CMP1n
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark n = 0, 1
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Figure 8-9. Operation Timing in PWM Pulse Generator Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H 03H, CMP0n = A5H)
Count clock
8-bit timer counter Hn 00H 01H 02H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
CMP0n
A5H
CMP1n
01H <2>
01H (03H) <2>'
03H
TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> <3> <4> <5> <6>
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0). <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1
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8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. In carrier generator mode, the connection between 8-bit timer H1 and 8-bit timer/event counter 51 is as shown below. Figure 8-10. Example of Connection Between 8-Bit Timer H1 and 8-Bit Timer/Event Counter 51
INTTM51
8-bit timer/event counter 51
TO51 TMMD10, TMMD11 INTTM51 Selector INTC INTTM5H1
8-bit timer H1
INTTMH1 TOH1
Prescaler
CPU
(1) Carrier generation In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of 8-bit timer/event counter 51 and the NRZ1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below.
RMC1 Bit 0 0 1 1 NRZ1 Bit 0 1 0 1 Output Low-level output High-level output Low-level output Carrier pulse output
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To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 8-11. Transfer Timing
TMHE1 8-bit timer H1 count clock
INTTM51
INTTM5H1 <1>Note NRZ1 0 <2> NRZB1 1 0 1 1 0
RMC1
<1> The INTTM51 signal is synchronized with the count clock of 8-bit timer H1 and is output as the INTTM5H1 signal. <2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. Note When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. Caution Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
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(3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-12. Register Setting in Carrier Generator Mode (i) Setting 8-bit timer H mode register 1 (TMHMD1)
CKS12 0/1 CKS11 0/1 CKS10 0/1 TMMD11 TMMD10 TOLEV1 0 1 0/1 TOEN1 0/1
TMHE1 TMHMD1 0
Timer output enabled Timer output level inversion setting Carrier generator mode selection Count clock (fCNT) selection Count operation stopped
(ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... Carrier output enable bit (v) TCL51 and TMC51 register setting * Refer to 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, 8-bit timer H1 starts counting. <3> When TCE51 of 8-bit timer mode control register 51 (TMC51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with 8-bit timer H1 and output as the INTTM5H1 signal. transferred to the NRZ1 bit. <8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. <9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, set TMHE1 to 0.
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INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
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If the setting value of the CMP01 register is 1, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty ratio are as follows. Carrier clock output cycle = (1 + M + 2)/fCNT Duty ratio = High-level width : Low-level width = ( M + 1) : (1 + 1) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. (4) Timing chart The carrier output control timing is shown below. Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10 bits of TMHMD1 register) or more are required from when the CMP11 register value is changed to when the value is transferred to the register. 3. Be sure to set the RMC1 bit before the count operation is started.
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Figure 8-13. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = 1, CMP11 = 1
8-bit timer H1 count clock 8-bit timer counter H1 count value CMP01 CMP11 TMHE1 INTTMH1 <1> <2> Carrier clock 8-bit timer 51 count clock TM51 count value CR51 TCE51 <5> INTTM51 NRZB1 NRZ1 Carrier clock TOH1 <7> 0 0 1 1 0 <6> 0 1 0 1 0
00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H N 00H N 00H N N 00H N 00H N
N
<3>
<4>
<1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level.
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Figure 8-13. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = 1, CMP11 = M (operation when carrier clock phase is asynchronous to NRZ1 phase)
8-bit timer H1 count clock 8-bit timer counter H1 count value CMP01 CMP11 TMHE1 INTTMH1 <1> <2> Carrier clock 8-bit timer 51 count clock TM51 count value CR51 TCE51 <5> INTTM51 NRZB1 NRZ1 Carrier clock TOH1 <7> 0 0 1 1 0 <6> 0 1 0 1 0
00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H
M
<3>
<4>
<1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> When the carrier clock phase becomes asynchronous to the NRZ1 bit phase, a carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
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Figure 8-13. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed
8-bit timer H1 count clock
8-bit timer counter H1 count value
00H 01H
N
00H 01H
M
00H
N
00H 01H
L
00H
CMP01 <3> CMP11 M M (L)
N <3>' L
TMHE1
INTTMH1 <2> Carrier clock <1> <4> <5>
<1> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is cleared and the INTTMH1 signal is output. <3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match (<3>'). <4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match, the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L).
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CHAPTER 9 WATCH TIMER
9.1 Functions of Watch Timer
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1. Watch Timer Block Diagram
Clear
Selector
Selector
5-bit counter Clear
Selector
INTWT
fX/27 fXT
fW
11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29
Selector
INTWTI
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Watch timer operation mode register (WTM) Internal bus
Remark
fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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(1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time
Interrupt Time 2 /fW 2 /fW 213/fW 214/fW
5 4
When Operated at fXT = 32.768 kHz 488 s 977 s 0.25 s 0.5 s
When Operated at fX = 10 MHz 205 s 410 s 0.105 s 0.210 s
Remark
fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
(2) Interval timer Interrupt requests (INTWTI) are generated at preset time intervals. Table 9-2. Interval Timer Interval Time
Interval Time 2 /fW 25/fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW
11 10 9 8 7 6 4
When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms
When Operated at fX = 10 MHz 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms
Remark
fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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9.2 Configuration of Watch Timer
The watch timer consists of the following hardware. Table 9-3. Watch Timer Configuration
Item Counter Prescaler Control register 5 bits x 1 11 bits x 1 Watch timer operation mode register (WTM) Configuration
9.3 Register Controlling Watch Timer
The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears WTM to 00H.
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Figure 9-2. Format of Watch Timer Operation Mode Register (WTM)
Address: FF6FH Symbol WTM 7 WTM7 After reset: 00H 6 WTM6 R/W 5 WTM5 4 WTM4 3 WTM3 2 WTM2 1 WTM1 0 WTM0
WTM7 0 1 fX/2 (78.125 kHz) fXT (32.768 kHz)
7
Watch timer count clock selection
WTM6 0 0 0 0 1 1 1 1
WTM5 0 0 1 1 0 0 1 1
WTM4 0 1 0 1 0 1 0 1 2 /fW 25/fW 26/fW 27/fW 28/fW 29/fW 210/fW 211/fW
4
Prescaler interval time selection
WTM3 0 0 1 1
WTM2 0 1 0 1 2 /fW 213/fW 25/fW 24/fW
14
Interrupt time selection
WTM1 0 1 Clear after operation stop Start
5-bit counter operation control
WTM0 0 1
Watch timer operation enable Operation stop (clear both prescaler and timer) Operation enable
Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT) 2. fX: X1 input clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. Figures in parentheses apply to operation with fX = 10 MHz, fXT = 32.768 kHz.
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9.4 Watch Timer Operations
9.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are set to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by setting WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 2 x 1/fW
11
seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 9-4. Watch Timer Interrupt Time
WTM3 WTM2 Interrupt Time Selection 214/fW 2 /fW 2 /fW 2 /fW
4 5 13
When Operated at fXT = 32.768 kHz (WTM7 = 1) 0.5 s 0.25 s 977 s 488 s
When Operated at fX = 10 MHz (WTM7 = 0) 0.210 s 0.105 s 410 s 205 s
0 0 1 1
0 1 0 1
Remark
fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation stops. Table 9-5. Interval Timer Interval Time
WTM6 WTM5 WTM4 24/fW 2 /fW 26/fW 27/fW 2 /fW 2 /fW 2 /fW 2 /fW
11 10 9 8 5
Interval Time
When Operated at fXT = 32.768 kHz (WTM7 = 1) 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms
When Operated at fX = 10 MHz (WTM7 = 0) 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Remark
fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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Figure 9-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter 0H Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nxT T nxT Overflow Overflow
Caution
When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM. This is because there is a delay of one 11-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the specified intervals.
Remark
fW: Watch timer clock frequency n: The number of times of interval timer operations Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0)
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10.1 Functions of Watchdog Timer
The watchdog timer detects an inadvertent program loop. If a program loop is detected, an internal reset signal (WDTRES) is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 19 RESET FUNCTION. Table 10-1. Loop Detection Time of Watchdog Timer
Loop Detection Time During Ring-OSC Clock Operation fR/2 (8.53 ms) fR/212 (17.07 ms) fR/213 (34.13 ms) fR/214 (68.27 ms) fR/215 (136.53 ms) fR/216 (273.07 ms) fR/217 (546.13 ms) fR/218 (1.09 s)
11
During X1 Input Clock Operation fXP/2 (819.2 s)
13
fXP/214 (1.64 ms) fXP/215 (3.28 ms) fXP/216 (6.55 ms) fXP/217 (13.11 ms) fXP/218 (26.21 ms) fXP/219 (52.43 ms) fXP/220 (104.86 ms)
Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the on-chip Ring-OSC as shown in Table 10-2.
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Table 10-2. Mask Option Setting and Watchdog Timer Operation Mode
Mask Option Ring-OSC Cannot Be Stopped Watchdog timer clock source Operation after reset Operation mode selection Features Fixed to fR
Note 1
Ring-OSC Can Be Stopped by Software * Selectable by software (fXP, fR or stopped) * When reset is released: fR Operation starts with maximum interval (fR/218). The clock selection/interval can be changed only once. The watchdog timer can be stopped in standby modeNote 2.
.
Operation starts with the maximum interval (fR/218). The interval can be changed only once. * The watchdog timer cannot be stopped. * Current in STOP mode 10 A
Notes 1. 2.
As long as power is being supplied, Ring-OSC oscillation cannot be stopped (except in the reset period). Clock supply to the watchdog timer is stopped in accordance with the watchdog timer clock source as follows: <1> When the clock source is fXP Clock supply to the watchdog timer is stopped while fXP is stopped, during HALT/STOP instruction execution, and during the oscillation stabilization time. <2> When the clock source is fR Clock supply to the watchdog timer is stopped if fR is stopped by software before STOP instruction execution when the CPU clock is fXP and during HALT/STOP instruction execution.
Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency
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10.2 Configuration of Watchdog Timer
The watchdog timer consists of following hardware. Table 10-3. Configuration of Watchdog Timer
Item Control registers Configuration Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE)
Figure 10-1. Block Diagram of Watchdog Timer
fR/22 fXP/2
4
Clock input controller 2
16-bit counter or fR/211 to fR/218 Clear
fXP/213 to fXP/220 Selector
Output controller
WDTRES (internal reset signal)
3
3
Watchdog timer enable register (WDTE)
0
1
1
WDCS4 WDCS3 WDCS2 WDCS1 WDCS0
Watchdog timer mode register (WDTM) Internal bus
Mask option (to set "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software")
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10.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. RESET input sets this register to 67H. Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF98H Symbol WDTM 7 0 After reset: 67H 6 1 R/W 5 1 4 WDCS4 3 WDCS3 2 WDCS2 1 WDCS1 0 WDCS0
WDCS4Note 1 WDCS3Note 1 0 0 1 0 1 x Ring-OSC clock (fR) X1 input clock (fXP)
Operation clock selection
Watchdog timer operation stopped
WDCS2Note 2 WDCS1Note 2 WDCS0Note 2
Overflow time setting During Ring-OSC clock operation During X1 input clock operation fXP/213 (819.2 s) fXP/214 (1.64 ms) fXP/215 (3.28 ms) fXP/216 (6.55 ms) fXP/217 (13.11 ms) fXP/218 (26.21 ms) fXP/219 (52.43 ms) fXP/220 (104.86 ms)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fR/211 (8.53 ms) fR/212 (17.07 ms) fR/213 (34.13 ms) fR/2 (68.27 ms) fR/215 (136.53 ms) fR/216 (273.07 ms) fR/217 (546.13 ms) fR/218 (1.09 s)
14
Notes 1. 2.
If "Ring-OSC cannot be stopped" is specified by a mask option, this cannot be set. The RingOSC clock will be selected no matter what value is written. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT. 2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Ring-OSC cannot be stopped" is selected by a mask option, other values are ignored).
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Cautions 3. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing attempted a second time, an internal reset signal is generated. 4. WDTM cannot be set by a 1-bit memory manipulation instruction. Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 9AH. Figure 10-3. Format of Watchdog Timer Enable Register (WDTE)
Address: FF99H Symbol WDTE 7 After reset: 9AH 6 R/W 5 4 3 2 1 0
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated (an error occurs in the assembler). 3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
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10.4 Operation of Watchdog Timer
10.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock * Cycle: fR/2 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
18
* Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instruction 3.
Notes 1, 2
.
* Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution.
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10.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock oscillation frequency (fR) * Cycle: fR/2 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
18
* Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instruction
Notes 1, 2, 3
.
* Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Ring-OSC clock (fR) X1 input clock (fXP) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. If other values are set, the watchdog timer cannot be operated (an error occurs in the assembler). 3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0. For the watchdog timer operation during STOP mode and HALT mode in each status, refer to 10.4.3 Watchdog timer operation in STOP mode and 10.4.4 Watchdog timer operation in HALT mode.
Notes 1. 2.
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10.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0. Figure 10-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
Normal operation
CPU operation fXP
STOP
Oscillation stabilization time
Normal operation
Oscillation stopped fR Watchdog timer
Oscillation stabilization time (set by OSTS register)
Operating
Operation stopped
Operating
(2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the Ring-OSC clock (fR) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. counter is not cleared to 0. Figure 10-5. Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
Normal operation
After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
CPU operation fXP
STOP
Oscillation stabilization time
Normal operation
Oscillation stopped fR Watchdog timer
Oscillation stabilization time (set by OSTS register)
Operating Operation stopped
Operating
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(3) When the CPU clock is the Ring-OSC clock (fR) and the watchdog timer operation clock is the X1 input clock (fXP) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0. <1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses. <2> The CPU clock is switched to the X1 input clock (fXP). Figure 10-6. Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) <1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) has elapsed
Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register)
STOP
Clock supply stopped
Normal operation (Ring-OSC clock)
<2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP)
Normal operation (Ring-OSC clock) Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) Clock supply stopped CPU clock fR fXPNote STOP Normal operation (X1 input clock)
Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register (OSTC).
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(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (fR) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. counter is not cleared to 0. Figure 10-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register)
After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
STOP
Clock supply stopped
Normal operation (Ring-OSC clock)
10.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the X1 input clock (fXP), Ring-OSC clock (fR), or subsystem clock (fXT), or whether the operation clock of the watchdog timer is the X1 input clock (fXP) or Ring-OSC clock (fR). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0. Figure 10-8. Operation in HALT Mode
CPU operation Normal operation fXP HALT Normal operation
fR fXT Watchdog timer Operating Operation stopped Operating
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11.1 Functions of Clock Output Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. Figure 11-1 shows the block diagram of clock output controller. Figure 11-1. Block Diagram of Clock Output Controller
fX Prescaler 8
fX to fX/27
Selector
Clock controller
PCL/INTP6/P140
fXT
CLOE
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS) Internal bus
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11.2 Configuration of Clock Output Controller
The clock output controller consists of the following hardware. Table 11-1. Clock Output Controller Configuration
Item Control registers Configuration Clock output selection register (CKS) Port mode register 14 (PM14)Note
Note See Figure 4-18 Block Diagram of P140.
11.3 Registers Controlling Clock Output Controller
The following two registers are used to control the clock output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CKS to 00H.
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Figure 11-2. Format of Clock Output Selection Register (CKS)
Address: FF40H Symbol CKS 7 0 After reset: 00H 6 0 R/W 5 0 4 CLOE 3 CCS3 2 CCS2 1 CCS1 0 CCS0
CLOE 0 1
PCL output enable/disable specification Clock division circuit operation stopped. PCL fixed to low level. Clock division circuit operation enabled. PCL output enabled.
CCS3 0 0 0 0 0 0 0 0 1
CCS2 0 0 0 0 1 1 1 1 0
CCS1 0 0 1 1 0 0 1 1 0
CCS0 0 1 0 1 0 1 0 1 0 fX (10 MHz) fX/2 (5 MHz)
PCL output clock selection
fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.125 kHz) fXT (32.768 kHz) Setting prohibited
Other than above
Remarks 1. fX: X1 input clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. Figures in parentheses are for operation with fX = 10 MHz or fXT = 32.768 kHz.
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(2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output, set PM140 and the output latch of P140 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM14 to FFH. Figure 11-3. Format of Port Mode Register 14 (PM14)
Address: FF2EH Symbol PM14 7 1 After reset: FFH 6 1 5 1 R/W 4 1 3 1 2 1 1 1 0 PM140
PM140 0 1
P140 pin I/O mode selection Output mode (output buffer on) Input mode (output buffer off)
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11.4 Clock Output Controller Operations
The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 11-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after securing high level of the clock. Figure 11-4. Remote Control Output Application Example
CLOE * Clock output *
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CHAPTER 12 A/D CONVERTER
12.1 Functions of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. (2) Power-fail detection function This function is used to detect a voltage drop in a battery. The A/D conversion result (ADCR register value) and power-fail comparison threshold register (PFT) value are compared. comparative condition has been matched. Figure 12-1. Block Diagram of A/D Converter
Series resistor string ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Sample & hold circuit
Selector
INTAD is generated only when a
Voltage comparator
Tap selector
AVREF (Can be used as analog power supply)
Successive approximation register (SAR)
AVSS
Controller
INTAD
3
A/D conversion result register (ADCR)
ADS2 ADS1 ADS0 Analog input channel specification register (ADS)
ADCS
FR2
FR1
FR0
ADCE
A/D converter mode register (ADM) Internal bus
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Figure 12-2. Block Diagram of Power-Fail Detection Function
PFCM ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 PFEN
Selector
Selector
INTAD
A/D converter
Comparator
ADS2 ADS1 ADS0 Analog input channel specification register (ADS)
PFEN PFCM
Power-fail comparison threshold register (PFT) Power-fail comparison mode register (PFM) Internal bus
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12.2 Configuration of A/D Converter
The A/D converter consists of the following hardware. Table 12-1. Configuration of A/D Converter
Item Analog input Registers Configuration 8 channels (ANI0 to ANI7) Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT)
Control registers
(1) Successive approximation register (SAR) This register compares the analog input voltage value with the voltage tap (compare voltage) value applied from the series resistor string, and holds the result starting from the most significant bit (MSB). When the result up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR) The ADCR is 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB). ADCR can be read by a 16-bit memory manipulation instruction. RESET input makes ADCR undefined. Figure 12-3. Format of A/D Conversion Register (ADCR)
Address: FF08H, FF09H Symbol ADCR After reset: Undefined FF09H R FF08H
0
0
0
0
0
0
Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT. Read the conversion result following conversion completion before writing to ADM and ADS. Using
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(3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input with the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the analog input. (6) ANI0 to ANI7 pins These eight-channel analog input pins input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 are alternate-function pins that can also be used for digital input. Cautions 1. Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher or a voltage of AVSS or lower (even if within the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. addition, the converted values of the other channels may also be affected. 2. The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (7) AVREF pin The AVREF pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals based on a voltage between AVREF and AVSS. In a standby mode, the current flowing into series resistor strings can be reduced by changing the input voltage of the AVREF pin to AVSS level. It can also be used as the analog power supply. When the A/D converter is used, be sure to use the AVREF pin for the power supply. Caution A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. (8) AVSS pin The AVSS pin is the GND potential pin for the A/D converter. Always use the AVSS pin at the same potential as the VSS0 pin, even when the A/D converter is not used. In
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12.3 Registers Controlling A/D Converter
The following four registers are used to control the A/D converter. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * Power-fail comparison mode register (PFM) * Power-fail comparison threshold register (PFT) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-4. Format of A/D Converter Mode Register (ADM)
Address: FF28H Symbol ADM 7 ADCS After reset: 00H 6 0 5 FR2 R/W 4 FR1 3 FR0 2 0 1 0 0 ADCE
ADCS 0 1
A/D conversion operation control Stops conversion operation Enables conversion operation
FR2
FR1
FR0
Conversion time selectionNote 1 fX = 2 MHz fX = 8.38 MHz fX = 10 MHz
0 0 0 1 1 1
0 0 1 0 0 1
0 1 0 0 1 0
288/fX 240/fX 192/fX 144/fX 120/fX 96/fX
144 sNote 1 34.3 s 120 s 96 s 72 s 60 s 48 s
Note 1
28.8 s 24.0 s 19.2 s 14.4 s 12.0 sNote 1
28.6 s 22.9 s 17.2 s 14.3 s
11.5 sNote 1 9.6 sNote 1
Other than above
Setting prohibited
ADCE 0 1
Boost reference voltage generator operation controlNote 2 Stops operation of reference voltage generator Enables operation of reference voltage generator
Notes 1. 2.
Set so that the A/D conversion time is 14 s or longer but less than 100 s. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that generates the reference voltage for boosting is controlled by ADCE, and it takes 14 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 14 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result.
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Table 12-2. Settings of ADCS and ADCE
ADCS 0 0 1 1 ADCE 0 1 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Conversion mode (reference voltage generator operation stoppedNote) Conversion mode (reference voltage generator operates)
Note Data of first conversion cannot be used. Figure 12-5. Timing Chart When Boost Reference Voltage Generator Is Used
Boost reference voltage generator: operating ADCE Boost reference voltage Conversion operation ADCS Note Conversion waiting Conversion operation Conversion stopped
Note 14 s or more is required for reference voltage stabilization. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data. 2. For the sampling time of the A/D converter and the A/D conversion start delay time, refer to (11) in 12.6 Cautions for A/D Converter. 3. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT. Remark fX: X1 input clock oscillation frequency
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(2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-6. Format of Analog Input Channel Specification Register (ADS)
Address: FF29H Symbol ADS 7 0 After reset: 00H 6 0 5 0 R/W 4 0 3 0 2 ADS2 1 ADS1 0 ADS0
ADS2 0 0 0 0 1 1 1 1
ADS1 0 0 1 1 0 0 1 1
ADS0 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Analog input channel specification
Cautions 1. Be sure to set bits 3 to 7 of ADS to 0. 2. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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(3) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is a register that controls the comparison operation. PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-7. Format of Power-Fail Comparison Mode Register (PFM)
Address: FF2AH Symbol PFM 7 PFEN After reset: 00H 6 PFCM 5 0 R/W 4 0 3 0 2 0 1 0 0 0
PFEN 0 1
Power-fail comparison enable Stops power-fail comparison (used as a normal A/D converter) Enables power-fail comparison (used for power-fail detection)
PFCM 0 ADCR3 PFT3 ADCR3 < PFT3 1 ADCR3 PFT3 ADCR3 < PFT3
Power-fail comparison mode selection Interrupt request signal (INTAD) generation No INTAD generation No INTAD generation INTAD generation
Caution If data is written to PFM, a wait cycle is generated. Do not write data to PFM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT. (4) Power-fail comparison threshold register (PFT) The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the values with the A/D conversion result. 8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result. PFT can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-8. Format of Power-Fail Comparison Threshold Register (PFT)
Address: FF2BH Symbol PFT 7 PFT7 After reset: 00H 6 PFT6 5 PFT5 R/W 4 PFT4 3 PFT3 2 PFT2 1 PFT1 0 PFT0
Caution If data is written to PFT, a wait cycle is generated. Do not write data to PFT when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with analog input channel specification register (ADS). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation is ended. <4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <5> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <6> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) VDD * Bit 9 = 0: (1/4) VDD The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <7> Comparison is continued in this way up to bit 0 of SAR. <8> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. Caution The first A/D conversion value immediately after A/D conversion operations start may not fall within the rating.
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Figure 12-9. Basic Operation of A/D Converter
Conversion time Sampling time
A/D converter operation
Sampling
A/D conversion
SAR Undefined
Conversion result
ADCR
Conversion result
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to one of the ADM, analog input channel specification register (ADS), power-fail comparison mode register (PFM), or power-fail comparison threshold register (PFT) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. RESET input makes the A/D conversion result register (ADCR) undefined.
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12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression.
ADCR = INT ( or
VIN AVREF
x 1024 + 0.5)
(ADCR - 0.5) x
AVREF 1024
- VIN < (ADCR + 0.5) x
AVREF 1024
where, INT( ): VIN: AVREF:
Function which returns integer part of value in parentheses Analog input voltage AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value Figure 12-10 shows the relationship between the analog input voltage and the A/D conversion result. Figure 12-10. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021 A/D conversion result (ADCR) 3
2
1
0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1
Input voltage/AVREF
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12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM). * Normal 10-bit A/D converter (PFEN = 0) * Power-fail detection function (PFEN = 1) (1) A/D conversion operation (when PFEN = 0) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 0, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADS is rewritten during A/D conversion, the A/D conversion under execution is suspended, and the A/D conversion of the newly selected analog input channel is started. If 0 is written to ADCS of ADM during A/D conversion, the conversion operation is immediately stopped. Figure 12-11. A/D Conversion Operation
Rewriting ADM ADCS = 1
Rewriting ADS
ADCS = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is stopped Conversion result is not retained
Stopped
ADCR
ANIn
ANIn
ANIm
INTAD (PFEN = 0)
Remarks 1. n = 0 to 7 2. m = 0 to 7
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(2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started. When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM. <1> When PFEN = 0 INTAD is generated at the end of each A/D conversion. <2> When PFEN = 1 and PFCM = 0 The ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when ADCR PFT. <3> When PFEN = 1 and PFCM = 1 The ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when ADCR < PFT. Figure 12-12. Power-Fail Detection (When PFEN = 1 and PFCM = 0)
A/D conversion
ANIn
ANIn
ANIn
ANIn
ADCR
80H
7FH
80H
PFT
80H
INTAD (PFEN = 1) Note First conversion Condition match
Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is replaced by the next conversion result. Remark n = 0 to 7
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The setting methods are described below. * When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Set bit 7 (ADCS) of ADM to 1. <4> An interrupt request signal (INTAD) is generated. <5> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <6> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS. <7> An interrupt request signal (INTAD) is generated. <8> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <9> Clear ADCS to 0. <10> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <3> is 14 s or more. 2. It is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. However, do not use the first conversion result after <3> in this case. 4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0. * When used as power-fail function <1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1. <2> Set power-fail comparison condition using bit 6 (PFCM) of PFM. <3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <4> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <5> Set a threshold value to the power-fail comparison threshold register (PFT). <6> Set bit 7 (ADCS) of ADM to 1. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <8> ADCR and PFT are compared and an interrupt request signal (INTAD) is generated if the conditions match. <9> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS. <10> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <11> ADCR and the power-fail comparison threshold register (PFT) are compared and an interrupt request signal (INTAD) is generated if the conditions match. <12> Clear ADCS to 0. <13> Clear ADCE to 0. Cautions 1. Make sure the period of <3> to <6> is 14 s or more. 2. It is no problem if order of <3>, <4>, and <5> is changed. 3. <3> can be omitted. However, do not use the first conversion result after <6> in this case. 4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.
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12.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/2 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 12-13. Overall Error
1......1
10
Figure 12-14. Quantization Error
1......1
Ideal line
Digital output
Digital output
Overall error
1/2LSB
Quantization error 1/2LSB
0......0 0 Analog input AVREF
0......0 0 Analog input AVREF
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(4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 12-15. Zero-Scale Error
111
Digital output (Lower 3 bits)
It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
Figure 12-16. Full-Scale Error
Digital output (Lower 3 bits)
Ideal line 011
Full-scale error 111 110 101 000
010 001 000 0 1 2 3 AVREF Analog input (LSB)
Zero-scale error
Ideal line
0
AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB)
Figure 12-17. Integral Linearity Error
Figure 12-18. Differential Linearity Error
1......1
1......1 Ideal line
Digital output
Ideal 1LSB width
Digital output
0......0 0
Integral linearity error Analog input AVREF
Differential linearity error 0......0 0 Analog input AVREF
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(8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling time
Conversion time
12.6 Cautions for A/D Converter
(1) Power consumption in standby mode The A/D converter stops operating in the standby mode. At this time, the power consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 0). Figure 12-19 shows the circuit configuration of series resistor string. Figure 12-19. Circuit Configuration of Series Resistor String
AVREF
P-ch
ADCS
Series resistor string AVSS
(2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected.
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(3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end of conversion ADCR read has priority. After the read operation, the new conversion result is written to ADCR. Old data can be read from ADCR at the timing of (1) and new data can be read from ADCR at the timing of (2) as shown in Figure 12-20. A master-slave configuration is employed for transferring the A/D conversion result to ADCR. Figure 12-20. Storing Conversion Result in ADCR and Timing of Data Read from ADCR (1) Timing to read old data
Internal clock INTAD Master write signal A/D conversion (master) Slave write signal ADCR (slave) Read data Conversion result N Conversion result N
Conversion result N
Conversion end
Conversion result N + 1
(2) Timing to read new data
Internal clock INTAD Master write signal A/D conversion (master) Slave write signal ADCR (slave) Read data Conversion result N + 1 Conversion result N + 1
Conversion result N
Conversion end
Conversion result N + 1
<2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal (INTAD) generated.
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(4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 12-21, to reduce noise. Figure 12-21. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF
ANI0 to ANI7 C = 100 to 1,000 pF
AVSS VSS
(5) ANI0/P20 to ANI7/P27 The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 12-21). (7) AVREF pin input impedance A series resistor string of several tens of 10 k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
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(8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 12-22. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite (start of ANIn conversion) ADS rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remarks 1. n = 0 to 7 2. m = 0 to 7 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. incorrect conversion result to be read. Do not read ADCR when the CPU is operating on the subsystem clock and oscillation of the X1 input clock is stopped. Using timing other than the above may cause an
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(11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 12-23 and Table 12-3. Figure 12-23. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS 1 or ADS rewrite
ADCS
Sampling timing
INTAD
Wait period
A/D Sampling conversion time start delay time
Conversion time
Table 12-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay TimeNote MIN. 0 0 0 1 1 1 0 0 1 0 0 1 Other than above 0 1 0 0 1 0 288/fX 240/fX 192/fX 144/fX 120/fX 96/fX Setting prohibited 40/fX 32/fX 24/fX 20/fX 16/fX 12/fX - 32/fX 28/fX 24/fX 16/fX 14/fX 12/fX - 36/fX 32/fX 28/fX 18/fX 16/fX 14/fX - MAX.
Note The A/D conversion start delay time is the time after wait period. For the wait function, refer to CHAPTER 29 CAUTIONS FOR WAIT. Remark fX: X1 clock oscillation frequency
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13.1 Functions of Serial Interface UART0
Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not executed and can enable a reduction in the power consumption. For details, refer to 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. * Two-pin configuration TXD0: Transmit data output pin RXB0: Receive data input pin * Length of transfer data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Four operating clock inputs selectable * Fixed to LSB-first transfer Cautions 1. The initial value of the TXD0 pin is high level. Exercise care when using the TXD0 pin as a port pin. 2. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 3. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 4. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks after RXE0 = 0 is set.
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13.2 Configuration of Serial Interface UART0
Serial interface UART0 consists of the following hardware. Table 13-1. Configuration of Serial Interface UART0
Item Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Configuration
Control registers
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Figure 13-1. Block Diagram of Serial Interface UART0
Filter
RxD0/SI10/P11
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Receive shift register 0 (RXS0)
fX/2 fX/23 fX/25 TO50/TI50/P17 (TM50 output)
Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator Reception unit Internal bus
INTSR0
Reception control
Receive buffer register 0 (RXB0)
Selector
Baud rate generator control register 0 (BRGC0) Registers
Baud rate generator
INTST0
Transmission control
Transmit shift register 0 (TXS0)
TxD0/SCK10/P10
Transmission unit
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(1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RESET input or POWER0 = 0 sets this register to FFH. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated.
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13.3 Registers Controlling Serial Interface UART0
Serial interface UART0 is controlled by the following three registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial transfer operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
Address: FF70H After reset: 01H R/W Symbol ASIM0 7 POWER0 6 TXE0 5 RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1
POWER0 0
Note
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock.
1
TXE0 0 1
Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission.
RXE0 0 1
Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception.
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear POWER0 to 0. 3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks after RXE0 = 0 is set. 4. Be sure to set bit 0 to 1.
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Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01 0 0 1 1 PS00 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parityNote Judges as odd parity. Judges as even parity.
CL0 0 1
Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits
SL0 0 1 Number of stop bits = 1 Number of stop bits = 2
Specifies number of stop bits of transmit data
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 2. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit.
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(2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this register is read. Figure 13-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R Symbol ASIS0 7 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0
PE0 0 1
Status flag indicating parity error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the parity of transmit data does not match the parity bit on completion of reception.
FE0 0 1
Status flag indicating framing error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the stop bit is not detected on completion of reception.
OVE0 0 1
Status flag indicating overrun error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If receive data is set to the RXB register and the next reception operation is completed before the data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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(3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and controls the baud rate. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH. Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W Symbol BRGC0 7 TPS01 6 TPS00 5 0 4 MDL04 3 MDL03 2 MDL02 1 MDL01 0 MDL00
TPS01 0 0 1 1
TPS00 0 1 0 1 TM50 output (TO50) fX/2 (5 MHz) fX/23 (1.25 MHz) fX/25 (312.5 kHz)
Base clock (fXCLK) selection
MDL04
MDL03
MDL02 x 0 0 0 * * * * * 0 0 1 1 1
MDL01 x 0 0 1 * * * * * 1 1 0 1 1
MDL00 x 0 1 0 * * * * * 0 1 0 0 1
k x 8 9 10 * * * * * 26 27 28 30 31
Selection of 5-bit counter output clock Setting prohibited fXCLK/8 fXCLK/9 fXCLK/10 * * * * * fXCLK/26 fXCLK/27 fXCLK/28 fXCLK/30 fXCLK/31
0 0 0 0 * * * * * 1 1 1 1 1
0 1 1 1 * * * * * 1 1 1 1 1
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits 2. fX: 3. k: 4. x: X1 input clock oscillation frequency Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care
5. Figures in parentheses apply to operation at fX = 10 MHz
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13.4 Operation of Serial Interface UART0
This section explains the two modes of serial interface UART0. 13.4.1 Operation stop mode In this mode, serial transfer cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. (1) Register setting The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W Symbol ASIM0 7 POWER0 6 TXE0 5 RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1
POWER0 0
Note
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock.
1
TXE0 0 1
Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission.
RXE0 0 1
Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception.
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear POWER0 to 0. 3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks after RXE0 = 0 is set.
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13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Register setting The UART mode is set by asynchronous serial interface operation mode register 0 (ASIM0) and asynchronous serial interface reception error status register 0 (ASIS0). (a) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial transfer operations of serial interface UART0. ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W Symbol ASIM0 7 POWER0 6 TXE0 5 RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1
POWER0 0
Note
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock.
1
TXE0 0 1
Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission.
RXE0 0 1
Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear POWER0 to 0. 3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks after RXE0 = 0 is set. 4. Be sure to set bit 0 to 1.
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PS01 0 0 1 1
PS00 0 1 0 1
Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity.
Reception operation Reception without parity Reception as 0 parityNote Judges as odd parity. Judges as even parity.
CL0 0 1
Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits
SL0 0 1 Number of stop bits = 1 Number of stop bits = 2
Specifies number of stop bits of transmit data
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 2. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit.
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(b) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this register is read.
Address: FF73H After reset: 00H R Symbol ASIS0 7 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0
PE0 0 1
Status flag indicating parity error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the parity of transmit data does not match the parity bit on completion of reception.
FE0 0 1
Status flag indicating framing error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the stop bit is not detected on completion of reception.
OVE0 0 1
Status flag indicating overrun error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If receive data is set to the RXB register and the next reception operation is completed before the data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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(2) Communication operation (a) Normal transmit/receive data format Figure 13-5 shows the format of the transmit/receive data. Figure 13-5. Format of Normal UART Transmit/Receive Data
1 data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bit
Character bits
One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 0 (ASIM0). Figure 13-6. Example of Normal UART Transmit/Receive Data Format 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Transfer data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Transfer data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
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(b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur.
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(c) Transmission The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 13-7 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 13-7. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1
TXD0 (output)
START
D0
D1
D2
D6
D7
Parity STOP
INTST0
2. Stop bit length: 2
TXD0 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST0
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(d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) or a framing error (FE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception. Figure 13-8. Reception Completion Interrupt Request Timing in Figure 13-8). If the RXD0 pin is low level at this time, it is recognized
RXD0 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR0
RXB0
Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0) before reading RXB0.
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(e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt servicing (INTSR0) (refer to Table 13-2). The contents of ASIS0 are reset to 0 when ASIS0 is read. Table 13-2. Cause of Reception Error
Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). Value of ASIS0 04H 02H 01H
(f)
Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 13-9, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 13-9. Noise Filter Circuit
Base clock
RXD0/SI10/P11
In
Q
Internal signal A
In
Q
Internal signal B
Match detector
LD_EN
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13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock (Clock) The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock "Clock" and its frequency is called fXCLK. "Clock" is fixed to low level when POWER0 = 0. * Transmission counter This counter stops, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 13-10. Configuration of Baud Rate Generator
POWER0
fX/2
POWER0, TXE0 (or RXE0)
fX/23 Selector fX/25 TO50/TI50/P17 (TM50 output) Match detector 1/2 Baud rate Clock (fXCLK) 5-bit counter
BRGC0: TPS01, TPS00
BRGC0: MDL04 to MDL00
Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: RXE0: BRGC0: Bit 6 of ASIM0 Bit 5 of ASIM0 Baud rate generator control register 0
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(2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter. (a) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and controls the baud rate. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH.
Address: FF71H After reset: 1FH R/W Symbol BRGC0 7 TPS01 6 TPS00 5 0 4 MDL04 3 MDL03 2 MDL02 1 MDL01 0 MDL00
TPS01 0 0 1 1 MDL04 0 0 0 0 * * * * * 1 1 1 1 1
TPS00 0 1 0 1 MDL03 0 1 1 1 * * * * * 1 1 1 1 1 TM50 output (TO50) fX/2 (5 MHz) fX/23 (1.25 MHz) fX/25 (312.5 kHz) MDL02 x 0 0 0 * * * * * 0 0 1 1 1 MDL01 x 0 0 1 * * * * * 1 1 0 1 1
Base clock (fXCLK) selection
MDL00 x 0 1 0 * * * * * 0 1 0 0 1
k x 8 9 10 * * * * * 26 27 28 30 31
Selection of 5-bit counter output clock Setting prohibited fXCLK/8 fXCLK/9 fXCLK/10 * * * * * fXCLK/26 fXCLK/27 fXCLK/28 fXCLK/30 fXCLK/31
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits 2. fX: 3. k: 4. x: X1 input clock oscillation frequency Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care
5. Figures in parentheses apply to operation with fX = 10 MHz
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(b) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK 2xk [bps]
fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
(c) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock (Clock) = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%]
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(3) Example of setting baud rate Table 13-3. Set Data of Baud Rate Generator
Baud Rate [bps] TPS01, TPS00 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 - - 3 3 3 2 2 2 1 1 1 fX = 10.0 MHz k - - 16 15 8 20 16 8 22 16 11 Calculated ERR[%] Value - - 9766 10417 19531 31250 39063 78125 113636 156250 227273 - - 1.73 0.16 1.73 0 1.73 1.73 -1.36 1.73 -1.36 TPS01, TPS00 - 3 3 3 2 2 2 1 1 1 1 fX = 8.38 MHz k - 27 14 13 27 17 14 27 18 14 9 Calculated ERR[%] Value - 4850 9353 10072 19398 30809 38796 77593 116389 149643 232778 - 1.03 -2.58 -3.15 1.03 -1.41 -2.58 1.03 1.03 -2.58 1.03 TPS01, TPS00 3 3 2 2 2 - 2 1 1 - - fX = 4.19 MHz k Calculated ERR[%] Value 2425 4676 9699 10475 18705 - 38796 74821 116389 - - 1.03 -2.58 1.03 0.72 -2.58 - 1.03 -2.58 1.03 - -
27 14 27 25 14 - 27 14 9 - -
Remark TPS01, TPS00: k: fX: ERR:
Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK)) Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) X1 input clock oscillation frequency Baud rate error
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(4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 13-11. Permissible Baud Rate Range During Reception
Latch timing Transfer rate of UART0
Start bit
Bit 0 FL
Bit 1
Bit 7
Parity bit
Stop bit
1 data frame (11 x FL)
Minimum permissible transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 13-11, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-
1
Brate: Baud rate of UART0 k: FL: Set value of BRGC0 1-bit data length
Margin of latch timing: 2 clocks
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Minimum permissible transfer rate: FLmin = 11 x FL -
k-2 2k
x FL =
21k + 2 2k
FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)- =
1
22k 21k + 2
Brate
Similarly, the maximum permissible transfer rate can be calculated as follows. 10 11 k+2 2xk 21k - 2 2xk
x FLmax = 11 x FL - 21k - 2 20k
x FL =
FL
FLmax =
FL x 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)- =
1
20k 21k - 2
Brate
The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 13-4. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) 8 16 24 31 Maximum Permissible Baud Rate Error +3.53% +4.14% +4.34% +4.44% Minimum Permissible Baud Rate Error -3.61% -4.19% -4.38% -4.47%
Remarks 1. The accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: Set value of BRGC0
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14.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not executed and can enable a reduction in the power consumption. For details, refer to 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network) bus. The functions of this mode are outlined below. * Two-pin configuration TXD6: Transmit data output pin RXB6: Receive data input pin * Data length of transfer data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Twelve operating clock inputs selectable * MSB- or LSB-first transfer selectable * Inverted transmission operation * Tuning break field transmission from 13 to 20 bits * More than 11 bits can be identified for tuning break field reception (SBF reception flag provided). Cautions 1. The initial value of the TXD6 pin is the high level. Exercise care when using the TXD6 pin as a port pin. 2. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data (it must be able to recognize a low-level start bit). 3. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 4. If data is continuously transmitted, the transfer rate from the stop bit to the next start bit is extended two clocks. However, this does not affect the result of transfer because the Do not use the reception side initializes the timing when it has detected a start bit. continuous transmission function if the interface is incorporated in LIN.
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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 14-1 and 14-2 outline the transmission and reception operations of LIN. Figure 14-1. LIN Transmission Operation
Wakeup signal frame Sleep bus 13-bitNote 2 SBF 8 bitsNote 3 Note 1 transmission 55H transmission Data Data Data Data transmission transmission transmission transmission Tuning break field Checksum field
Tuning field
Match field
Data field
Data field
TX6 Note 4
INTST6
Notes 1. 2.
The interval between each field is controlled by software. The tuning break field is output by hardware. The output width is equal to the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6). If the output width needs to be adjusted more accurately, use baud rate generator control register 6 (BRGC6).
3. 4.
The wakeup signal frame is substituted by 80H transfer in the 8-bit mode. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
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Figure 14-2. LIN Reception Operation
Wakeup signal frame Sleep bus 13 bitsNote 2 SBF reception Disable Enable Note 3 Reception interrupt (INTSR6) Note 1 Edge detection (INTP0) Note 4 Capture timer Disable Enable SF reception ID reception Data reception Data Data reception receptionNote 5 Tuning break field Checksum field
Tuning field
Match field
Data field
Data field
RX6
Notes 1. 2.
The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. Reception continues until the STOP bit is detected. When 11 bits or more of SBF have been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If less than 11 bits of SBF have been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored.
3.
If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH.
4. 5.
Calculate the baud rate error from the value obtained from the capture timer, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again.
To perform a LIN receive operation, use a configuration like the one shown in Figure 14-3. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the tuning break field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated using the time and number of bits of the tuning break field. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.
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Figure 14-3. Port Configuration for LIN Reception Operation
MPX A Q B
P14/RXD6
RXD6 input
Port mode (PM14) Port latch (P14)
P120/INTP0
MPX A Q B
MPX A Q B
INTP0 input
Port mode (PM120) Port latch (P120)
Port input switch control (ISC0) 0: A output 1: B output
P00/TI000
MPX A Q B
MPX A Q B
TI000 input
Port mode (PM00) Port latch (P00)
Port input switch control (ISC1) 0: A output 1: B output
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 4-21) The resources used in the LIN communication operation are shown below. * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the tuning break field (SBF) length and divides it by the number of bits. * Serial interface UART6
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14.2 Configuration of Serial Interface UART6
Serial interface UART6 consists of the following hardware. Table 14-1. Configuration of Serial Interface UART6
Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Configuration
Control registers
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Figure 14-4. Block Diagram of Serial Interface UART6
Filter INTSR6 Reception control Receive shift register 6 (RXS6)
RXD6/P14
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INTSRE6
Asynchronous serial interface operation mode register 6 (ASIM6) fX-fX/210
Asynchronous serial interface reception error status register 6 (ASIS6)
Baud rate generator Reception unit Internal bus
Asynchronous serial interface control register 6 (ASICL6)
Receive buffer register 6 (RXB6)
Selector
TO50/TI50/P17 (TM50 output) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface transmission status register 6 (ASIF6) Asynchronous serial interface control register 6 (ASICL6)
Clock selection register 6 (CKSR6)
Baud rate generator
Transmit buffer register 6 (TXB6)
INTST6 Registers
Transmission control
Transmit shift register 6 (TXS6)
TXD6/P13
Transmission unit
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(1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by the receive shift register. Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). However, if the same value is continuously transmitted in the transmission mode (POWER6 = 1 and TXE6 = 1), the same value can be written. (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the internal clock. TXS6 cannot be directly manipulated by a program.
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14.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following six registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial transfer operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W Symbol ASIM6 7 POWER6 6 TXE6 5 RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6
POWER6 0
Note 1
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock
1Note 2
TXE6 0 1
Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission
Notes 1. 2.
The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the POWER6 bit.
Caution At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear POWER6 to 0.
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Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
RXE6 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception
PS61 0 0 1 1
PS60 0 1 0 1
Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity.
Reception operation Reception without parity Reception as 0 parityNote Judges as odd parity. Judges as even parity.
CL6 0 1
Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits
SL6 0 1 Number of stop bits = 1 Number of stop bits = 2
Specifies number of stop bits of transmit data
ISRM6 0 1
Enables/disables occurrence of reception completion interrupt in case of error "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur).
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear POWER6 to 0. 2. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 3. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 4. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 5. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. Figure 14-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF53H After reset: 00H R Symbol ASIS6 7 0 6 0 5 0 4 0 3 0 2 PE6 1 FE6 0 OVE6
PE6 0 1
Status flag indicating parity error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception
FE6 0 1
Status flag indicating framing error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the stop bit is not detected on completion of reception
OVE6 0 1
Status flag indicating overrun error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If receive data is set to the RXB register and the next reception operation is completed before the data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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(3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register can be set by an 8-bit memory manipulation instruction, and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 14-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF55H After reset: 00H R Symbol ASIF6 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF6 0 TXSF6
TXBF6 0 1
Transmit buffer data flag If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6 0
Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
1
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the value of the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The operation is not guaranteed if data is written to TXB6 while the TXBF6 flag is 1. 2. While continuous transmission is being executed, check the value of the TXSF6 flag after the transmission completion interrupt to determine the subsequent write processing to TXB6. * If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written. * If TXSF6 is 0: Continuous transmission is complete. Data of 2 bytes can be written. When doing so, observe Caution 1 above. 3. While continuous transmission is in progress, check that TXSF6 is 0 after the transmission completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 = 0). If clearing is executed while the TXSF6 flag is 1, the transmit data cannot be guaranteed.
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(4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W Symbol CKSR6 7 0 6 0 5 0 4 0 3 TPS63 2 TPS62 1 TPS61 0 TPS60
TPS63 0 0 0 0 0 0 0 0 1 1 1 1
TPS62 0 0 0 0 1 1 1 1 0 0 0 0 Other
TPS61 0 0 1 1 0 0 1 1 0 0 1 1
TPS60 0 1 0 1 0 1 0 1 0 1 0 1 fX (10 MHz) fX/2 (5 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.13 kHz) fX/28 (39.06 kHz) fX/29 (19.53 kHz) fX/210 (9.77 kHz)
Base clock (fXCLK)
TM50 output (TO50) Setting prohibited
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency
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(5) Baud rate generator control register 6 (BRGC6) This register selects the base clock of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 14-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W Symbol BRGC6 7 MDL67 6 MDL66 5 MDL65 4 MDL64 3 MDL63 2 MDL62 1 MDL61 0 MDL60
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62 x 0 0 0 * * * * * 1 1 1 1
MDL61 x 0 0 1 * * * * * 0 0 1 1
MDL60 x 0 1 0 * * * * * 0 1 0 1
k x 8 9 10 * * * * * 252 253 254 255
Output clock selection of 8-bit counter Setting prohibited fXCLK/8 fXCLK/9 fXCLK/10 * * * * * fXCLK/252 fXCLK/253 fXCLK/254 fXCLK/255
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 1 1 1 * * * * * 1 1 1 1
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate value is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: 3. x: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) Don't care
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(6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial transfer operations of serial interface UART6. ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to 16H. Remark ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). However, transfer is started by refresh because bit 6 (SBRT6) and bit 5 (SBTT6) of ASICL6 are cleared to 0 when communication is complete (when an interrupt signal is generated). Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
Address: FF58H After reset: 16H R/WNote Symbol ASICL6 7 SBRF6 6 SBRT6 5 SBTT6 4 SBL62 3 SBL61 2 SBL60 1 DIR6 0 TXDLV6
SBRF6 0 1
SBF reception status flag If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly SBF reception in progress
SBRT6 0 1 SBF reception trigger
SBF reception trigger -
SBTT6 0 1 SBF transmission trigger
SBF transmission trigger -
Note Bit 7 is read-only. Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold the status of the SBRF6 flag. 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission.
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Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62 1 1 1 0 0 0 0 1 SBL61 0 1 1 0 0 1 1 0 SBL60 1 0 1 0 1 0 1 0 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length. SBF is output with 19-bit length. SBF is output with 20-bit length.
DIR6 0 1 MSB-first transfer LSB-first transfer
MSB/LSB-first transfer
TXDLV6 0 1 Normal output of TXD6 Inverted output of TXD6
Enables/disables inverting TXD6 output
Caution Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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14.4 Operation of Serial Interface UART6
This section explains the two modes of serial interface UART6. 14.4.1 Operation stop mode In this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. (1) Register setting The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Address: FF50H After reset: 01H R/W Symbol ASIM6 7 POWER6 6 TXE6 5 RXE6 4 PS61 3 PS60 2 CL 1 SL6 0 ISRM6
POWER6 0
Note 1
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock.
1Note 2
TXE6 0 1
Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). Enables transmission
RXE6 0 1
Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception
Notes 1. 2.
The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the POWER6 bit.
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear POWER6 to 0. 2. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear POWER6 to 0.
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14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Register setting The UART mode is set by asynchronous serial interface operation mode register 6 (ASIM6), asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), and asynchronous serial interface control register 6 (ASICL6). (a) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial transfer operations of serial interface UART6. ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Address: FF50H After reset: 01H R/W Symbol ASIM6 7 POWER6 6 TXE6 5 RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6
POWER6 0
Note 1
Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. Enables operation of the internal operation clock.
1Note 2
TXE6 0 1
Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission
Notes 1. 2.
The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the POWER6 bit.
Caution At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear POWER6 to 0.
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RXE6 0 1
Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception
PS61 0 0 1 1
PS60 0 1 0 1
Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity.
Reception operation Reception without parity Reception as 0 parityNote Judges as odd parity. Judges as even parity.
CL6 0 1
Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits
SL6 0 1 Number of stop bits = 1 Number of stop bits = 2
Specifies number of stop bits of transmit data
ISRM6 0 1
Enables/disables occurrence of reception completion interrupt in case of error "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur).
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear POWER6 to 0. 2. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 3. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 4. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 5. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(b) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read.
Address: FF53H After reset: 00H R Symbol ASIS6 7 0 6 0 5 0 4 0 3 0 2 PE6 1 FE6 0 OVE6
PE6 0 1
Status flag indicating parity error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception
FE6 0 1
Status flag indicating framing error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the stop bit is not detected on completion of reception
OVE6 0 1
Status flag indicating overrun error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If receive data is set to the RXB register and the next reception operation is completed before the data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
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(c) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register can be set by an 8-bit memory manipulation instruction, and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Address: FF55H After reset: 00H R Symbol ASIF6 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF6 0 TXSF6
TXBF6 0 1
Transmit buffer data flag If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6 0 1
Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the value of the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The operation is not guaranteed if data is written to TXB6 while the TXBF6 flag is 1. 2. While continuous transmission is being executed, check the value of the TXSF6 flag after the transmission completion interrupt to determine the subsequent write processing to TXB6. * If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written. * If TXSF6 is 0: Continuous transmission is complete. Data of 2 bytes can be written. When doing so, observe Caution 1 above. 3. While continuous transmission is in progress, check that TXSF6 is 0 after the transmission completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 = 0). If clearing is executed while the TXSF6 flag is 1, the transmit data cannot be guaranteed.
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(d) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial transfer operations of serial interface UART6. ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to 16H. Remark ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). However, transfer is started by refresh because bit 6 (SBRT6) and bit 5 (SBTT6) of ASICL6 are cleared to 0 when communication is complete (when an interrupt signal is generated).
Address: FF58H After reset: 16H R/WNote Symbol ASICL6 7 SBRF6 6 SBRT6 5 SBTT6 4 SBL62 3 SBL61 2 SBL60 1 DIR6 0 TXDLV6
SBRF6 0 1
SBF reception status flag If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly SBF reception in progress
SBRT6 0 1 SBF reception trigger
SBF reception trigger -
SBTT6 0 1 SBF transmission trigger
SBF transmission trigger -
Note Bit 7 is read-only. Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold the status of the SBRF6 flag. 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission.
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SBL62 1 1 1 0 0 0 0 1
SBL61 0 1 1 0 0 1 1 0
SBL60 1 0 1 0 1 0 1 0
SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length. SBF is output with 19-bit length. SBF is output with 20-bit length.
DIR6 0 1 MSB-first transfer LSB-first transfer
MSB/LSB-first transfer
TXDLV6 0 1 Normal output of TXD6 Inverted output of TXD6
Enables/disables inverting TXD6 output
Caution Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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(2) Communication operation (a) Normal transmit/receive data format Figure 14-11 shows the format of the transmit/receive data. Figure 14-11. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception
1 data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bit
Character bits
2. MSB-first transmission/reception
1 data frame
Start bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity bit
Stop bit
Character bits
One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 6 (ASIM6). Whether data is transferred with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
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Figure 14-12. Example of Normal UART Transmit/Receive Data Format 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H, TXD6 pin inverted output
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Transfer data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Transfer data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
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(b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur.
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(c) Normal transmission The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin, starting from the LSB. When transmission is completed, a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 14-13 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 14-13. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1
TXD6 (output)
START
D0
D1
D2
D6
D7
Parity STOP
INTST6
2. Stop bit length: 2
TXD6 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST6
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(d) Continuous transmission When transmit shift register 6 (TXS6) has started the shift operation, the next transmit data can be written to transmit buffer register 6 (TXB6). As a result, data can be transmitted without intermission even while an interrupt that has occurred after transmission of one data frame is being serviced, thus realizing an efficient communication rate. To transmit data continuously, however, transmission processing must be executed while referencing bits 1 (TXBF6) and 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6). Caution When the device is incorporated in LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). Table 14-2. Write Processing and Writing to TXB6 During Execution of Continuous Transmission
TXBF6 TXSF6 Write Processing During Execution of Continuous Transmission Enables writing 2 bytes or transmission completion processing Enables writing 1 byte Enables writing 2 bytes or transmission completion processing Enables writing 1 byte Writing to TXB6 During Execution of Continuous Transmission Enables writing
0
0
0 1 1
1 0 1
Enables writing Disables writing Disables writing
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the value of the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The operation is not guaranteed if data is written to TXB6 while the TXBF6 flag is 1. 2. While continuous transmission is being executed, check the value of the TXSF6 flag after the transmission completion interrupt to determine the subsequent write processing to TXB6. * If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written. * If TXSF6 is 0: Continuous transmission is completed. Data of 2 bytes can be written. To do so, observe Caution 1 above. 3. While continuous transmission is in progress, check that TXSF6 is 0 after the transmission completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 = 0). If clearing is executed while the TXSF6 flag is 1, the transmit data cannot be guaranteed.
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Figure 14-14 shows the processing flow of continuous transmission. Figure 14-14. Processing Flow of Continuous Transmission
Set registers.
Write transmit data to TXB6 register.
No
Read ASIF6 register. TXBF6 = 0? Yes Interrupt occurs.
Transfer executed necessary number of times? No
Yes
No
Read ASIF6 register. TXSF6 = 1? Yes
Read ASIF6 register. TXSF6 = 0? Yes
No
Write transmit data to TXB6 register.
Wait for interrupt.
Completion of transmission processing
Remark TXB6:
Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
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Figure 14-15 shows the timing of starting continuous transmission, and Figure 14-16 shows the timing of ending continuous transmission. Figure 14-15. Timing of Starting Continuous Transmission
TXD6 INTST6 Start Data (1) Parity Stop Start Data (2) Parity Stop Start
TXB6
FF
Data (1)
Data (2)
Data (3)
TXS6 TXBF6 TXSF6
FF
Data (1)
Data (2)
Data (3)
Note
Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXB6: TXS6: ASIF6: TXD6 pin (output) Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6
INTST6: Interrupt request signal
TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6
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Figure 14-16. Timing of Ending Continuous Transmission
TXD6 INTST6 Stop Start Data (n-1) Parity Stop Start Data (n) Parity Stop
TXB6
Data (n-1)
Data (n)
TXS6
Data (n-1)
Data (n)
FF
TXBF6 TXSF6 POWER6 or TXE6
Remark TXD6: INTST6: TXB6: TXS6: ASIF6: TXBF6: TXSF6: TXE6:
TXD6 pin (output) Interrupt request signal Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 Bit 1 of ASIF6 Bit 0 of ASIF6 Bit 6 of asynchronous serial interface operation mode register (ASIM6)
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
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(e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) or a framing error (FE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 14-17. Reception Completion Interrupt Request Timing in Figure 14-17). If the RXD6 pin is low level at this time, it is recognized
RXD6 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR6
RXB6
Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6.
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(f)
Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (refer to Table 14-3). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 14-3. Cause of Reception Error
Reception Error Parity error
Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 6 (RXB6).
Value of ASIS6 04H
Framing error Overrun error
02H 01H
The error interrupt can be separated into INTSR6 and INTSRE6 by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 14-18. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (INTSR6 and INTSRE6 are separated) (a) No error during reception
INTSR6
(b) Error during reception
INTSR6
INTSRE6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception
INTSR6 INTSRE6
INTSR6 INTSRE6
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(g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-19, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-19. Noise Filter Circuit
Base clock
RXD6/P14
In
Q
Internal signal A
In
Q
Internal signal B
Match detector
LD_EN
(h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, refer to Figure 14-1 LIN Transmission Operation. The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. Transmission is enabled when bit 6 (TXE6) of ASIM6 is set to 1 next time, and SBF transmission operation is started when bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. After transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) are output. When SBF transmission has been completed, a transmission completion interrupt request (INTST6) is generated, and SBTT6 is automatically cleared. After SBF transmission has been completed, the normal transmission mode is restored. Transmission is stopped until the data to be transmitted next is written to transmit buffer register 6 (TXB6) or SBTT6 is set to 1. Figure 14-20. SBF Transmission
TXD6
1
2
3
4
5
6
7
8
9
10
11
12
13
Stop
INTST6
SBTT6
Remark TXD6:
TXD6 pin (output)
INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
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(i)
SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 14-21. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
RXD6 1 2 3 4 5 6 7 8 9 10 11
SBRT6 /SBRF6
INTSR6
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
RXD6 1 2 3 4 5 6 7 8 9 10
SBRT6 /SBRF6
INTSR6
"0"
Remark RXD6:
RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request
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14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock (Clock) The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock (Clock) and its frequency is called fXCLK. Clock is fixed to the low level when POWER6 = 0. * Transmission counter This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected.
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Figure 14-22. Configuration of Baud Rate Generator
POWER6
fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 TO50/TI50/P17 (TM50 output)
POWER6, TXE6 (or RXE6)
Selector
Clock (fXCLK)
8-bit counter
Match detector
1/2
Baud rate
CKSR6: TPS63 to TPS60
BRGC6: MDL67 to MDL60
Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: RXE6: CKSR6: BRGC6: Bit 6 of ASIM6 Bit 5 of ASIM6 Clock selection register 6 Baud rate generator control register 6
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(2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Address: FF56H After reset: 00H R/W Symbol CKSR6 7 0 6 0 5 0 4 0 3 TPS63 2 TPS62 1 TPS61 0 TPS60
TPS63 0 0 0 0 0 0 0 0 1 1 1 1
TPS62 0 0 0 0 1 1 1 1 0 0 0 0 Other
TPS61 0 0 1 1 0 0 1 1 0 0 1 1
TPS60 0 1 0 1 0 1 0 1 0 1 0 1 fX (10 MHz) fX/2 (5 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.13 kHz) fX/28 (39.06 kHz) fX/29 (19.53 kHz) fX/210 (9.77 kHz) TM50 output Setting prohibited
Base clock (fXCLK)
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency
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(b) Baud rate generator control register 6 (BRGC6) This register selects the base clock of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Address: FF57H After reset: FFH R/W Symbol BRGC6 7 MDL67 6 MDL66 5 MDL65 4 MDL64 3 MDL63 2 MDL62 1 MDL61 0 MDL60
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62 x 0 0 0 * * * * * 1 1 1 1
MDL61 x 0 0 1 * * * * * 0 0 1 1
MDL60 x 0 1 0 * * * * * 0 1 0 1
k x 8 9 10 * * * * * 252 253 254 255
Output clock selection of 8-bit counter Setting prohibited fXCLK/8 fXCLK/9 fXCLK/10 * * * * * fXCLK/252 fXCLK/253 fXCLK/254 fXCLK/255
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 0 0 0 * * * * * 1 1 1 1
0 1 1 1 * * * * * 1 1 1 1
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate value is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care
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(c) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK 2xk [bps]
fXCLK: Frequency of base clock (Clock) selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)
(d) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock (Clock) = 20 MHz = 20,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 01000001B (k = 65) Target baud rate = 153600 bps Baud rate = 20 M/(2 x 65) = 20000000/(2 x 65) = 153846 [bps] Error = (153846/153600 - 1) x 100 = 0.160 [%]
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(3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator
Baud Rate [bps] TPS63 to TPS60 600 1200 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 6H 5H 4H 3H 2H 2H 1H 1H 0H 0H 0H 0H 0H fX = 10.0 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1202 2404 4808 9615 10417 19231 31250 38462 76923 116279 151515 227272 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 0.94 -1.36 -1.36 6H 5H 4H 3H 2H 2H 1H 0H 0H 0H 0H 0H 0H fX = 8.38 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1201 2403 4805 9610 10371 19200 31268 38440 76182 116388 155185 232777 0.11 0.11 0.11 0.11 0.11 0.28 0.11 0.06 0.11 -0.80 1.03 1.03 1.03 5H 4H 3H 2H 1H 1H 0H 0H 0H 0H 0H 0H 0H fX = 4.19 MHz k Calculated ERR[%] Value 601 1201 2403 4805 9610 10475 19220 31268 38090 77593 116389 149643 232778 0.11 0.11 0.11 0.11 0.11 -0.28 0.11 0.06 -0.80 1.03 1.03 -2.58 1.03
130 130 130 130 130 120 130 80 130 65 43 33 22
109 109 109 109 109 101 109 134 109 55 36 27 18
109 109 109 109 109 101 109 67 55 27 18 14 9
Caution The maximum permissible frequency of the base clock (fXCLK) is 25 MHz. Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK)) k: fX: ERR: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) X1 input clock oscillation frequency Baud rate error
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(4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-23. Permissible Baud Rate Range During Reception
Latch timing Transfer rate of UART6
Start bit
Bit 0 FL
Bit 1
Bit 7
Parity bit
Stop bit
1 data frame (11 x FL)
Minimum permissible transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 14-23, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-
1
Brate: Baud rate of UART6 k: FL: Set value of BRGC6 1-bit data length
Margin of latch timing: 2 clocks Minimum permissible transfer rate: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL
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Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)- =
1
22k 21k + 2
Brate
Similarly, the maximum permissible transfer rate can be calculated as follows. 10 11 k+2 2xk 21k - 2 2xk
x FLmax = 11 x FL - 21k - 2 20k
x FL =
FL
FLmax =
FL x 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)- =
1
20k 21k - 2
Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 14-5. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) 8 20 50 100 255 Maximum Permissible Baud Rate Error +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Permissible Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73%
Remarks 1. The accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: Set value of BRGC6
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(5) Transfer rate during continuous transmission When data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two clocks from the normal value. However, the result of transfer is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 14-24. Transfer Rate During Continuous Transmission
1 data frame Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL
Start bit FL
Bit 0 FL
Bit 1 FL
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK, the following expression is satisfied. FLstp = FL + 2/fXCLK Therefore, the transfer rate during continuous transmission is: Transfer rate = 11 x FL + 2/fXCLK
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15.1 Functions of Serial Interface CSI10
Serial interface CSI10 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to transfer 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). The processing time of data transfer can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is transferred with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface.
15.2 Configuration of Serial Interface CSI10
Serial interface CSI10 consists of the following hardware. Table 15-1. Configuration of Serial Interface CSI10
Item Registers Control registers Configuration Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Serial operation mode register 10 (CSIM10) Serial clock selection register 10 (CSIC10)
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Figure 15-1. Block Diagram of Serial Interface CSI10
Internal bus 8 SI10/P11/RXD0 Serial I/O shift register 10 (SIO10) 8 Transmit buffer register 10 (SOTB10) Output selector SO10/P12
Transmit data controller
Output latch
Transmit controller
fX/2 to fX/27 SCK10/P10/TXD0
Selector
Clock start/stop controller & clock phase controller
INTCSI10
(1) Transmit buffer register 10 (SOTB10) This register sets the transmit data. Transmission/reception is started by writing data to SOTB10 when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and output to the serial output pin (SO10). SOTB10 can be written or read by an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication). (2) Serial I/O shift register 10 (SIO10) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. During reception, the data is read from the serial input pin (SI10) to SIO10. RESET input clears this register to 00H. Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).
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15.3 Registers Controlling Serial Interface CSI10
Serial interface CSI10 is controlled by the following two registers. * Serial operation mode register 10 (CSIM10) * Serial clock selection register 10 (CSIC10) (1) Serial operation mode register 10 (CSIM10) CSIM10 is used to select the operation mode and enable or disable operation. CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 15-2. Format of Serial Operation Mode Register 10 (CSIM10)
Address: FF80H After reset: 00H R/WNote 1 Symbol CSIM10 7 CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10
CSIE10 0 1
Operation control in 3-wire serial I/O mode Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as generalpurpose port pins). Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
TRMD10Note 2 0
Note 3
Transmit/receive mode control Receive mode (transmission disabled) Transmit/receive mode
1
DIR10Note 4 0 1 MSB LSB
First bit specification
CSOT10Note 5 0 1 Communication is stopped. Communication is in progress.
Operation mode flag
Notes 1. 2. 3. 4. 5.
Bit 0 is read-only. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 pin is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). CSOT10 is cleared if CSIE10 is set to 0 (operation stopped).
Caution Be sure to set bit 5 to 0.
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(2) Serial clock selection register 10 (CSIC10) CSIC10 is used to select the phase of the data clock and set the count clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 15-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100
CKP10 0
DAP10 0
SCK10 SO10 SI10 input timing
Data clock phase selection
Type 1
D7 D6 D5 D4 D3 D2 D1 D0
0
1
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
2
1
0
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
3
1
1
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
4
CKS102 0 0 0 0 1 1 1 1
CKS101 0 0 1 1 0 0 1 1
CKS100 0 1 0 1 0 1 0 1 fX/2 (5 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.13 kHz)
CSI10 count clock selection
External clock input to SCK10
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/TXD0, P11/SI10/RXD0, and P12/SO10 as general-purpose port pins. 2. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency
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15.4 Operation of Serial Interface CSI10
Serial interface CSI10 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 15.4.1 Operation stop mode Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, and P12/SO10 pins can be used as ordinary I/O port pins in this mode. (1) Register setting The operation stop mode is set by serial operation mode register 10 (CSIM10). (a) Serial operation mode register 10 (CSIM10) CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H.
Address: FF80H After reset: 00H R/W Symbol CSIM10 7 CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10
CSIE10 0 1
Operation control in 3-wire serial I/O mode Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as generalpurpose port pins). Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
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15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines. (1) Register setting The 3-wire serial I/O mode is set by serial operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10). (a) Serial operation mode register 10 (CSIM10) This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Address: FF80H After reset: 00H R/WNote 1 Symbol CSIM10 7 CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10
CSIE10 0 1
Operation control in 3-wire serial I/O mode Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as generalpurpose port pins). Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
TRMD10Note 2 0
Note 3
Transmit/receive mode control Receive mode (transmission disabled) Transmit/receive mode
1
DIR10Note 4 0 1 MSB LSB
First bit specification
CSOT10Note 5 0 1 Communication is stopped. Communication is in progress.
Operation mode flag
Notes 1. 2. 3. 4. 5.
Bit 0 is read-only. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 pin is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). CSOT10 is cleared if CSIE10 is set to 0 (operation stopped).
Caution Be sure to set bit 5 to 0.
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(b) Serial clock selection register 10 (CSIC10) CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100
CKP10 0
DAP10 0
SCK10 SO10 SI10 input timing
Data clock phase selection
Type 1
D7 D6 D5 D4 D3 D2 D1 D0
0
1
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
2
1
0
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
3
1
1
SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0
4
CKS102 0 0 0 0 1 1 1 1
CKS101 0 0 1 1 0 0 1 1
CKS100 0 1 0 1 0 1 0 1 fX/2 (5 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.13 kHz)
CSI10 count clock selection
External clock input to SCK10
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/TXD0, P11/SI10/RXD0, and P12/SO10 as general-purpose port pins. 2. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency
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(2) Setting of ports <1> Transmit/receive mode (a) To use externally input clock as system clock (SCK10) Bit 1 (PM11) of port mode register 1: Set to 1 Bit 2 (PM12) of port mode register 1: Cleared to 0 Bit 0 (PM10) of port mode register 1: Set to 1 Bit 2 (P12) of port 1: Cleared to 0 (b) To use internal clock as system clock (SCK10) Bit 1 (PM11) of port mode register 1: Set to 1 Bit 2 (PM12) of port mode register 1: Cleared to 0 Bit 0 (PM10) of port mode register 1: Cleared to 0 Bit 2 (P12) of port 1: Cleared to 0 Bit 0 (P10) of port 1: Set to 1 <2> Receive mode (with transmission disabled) (a) To use externally input clock as system clock (SCK10) Bit 1 (PM11) of port mode register 1: Set to 1 Bit 0 (PM10) of port mode register 1: Set to 1 (b) To use internal clock as system clock (SCK10) Bit 1 (PM11) of port mode register 1: Set to 1 Bit 0 (PM10) of port mode register 1: Cleared to 0 Bit 0 (P10) of port 1: Set to 1 Remark The transmit/receive mode or receive mode is selected by using bit 6 (TRMD10) of serial operation mode register 10 (CSIM10).
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(3) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition, data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. Reception is started when data is read from serial I/O shift register 10 (SIO10). After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared to 0. Then the next communication is enabled. Caution Do not access the control register and data register when CSOT10 = 1 (during serial communication). Figure 15-4. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)
SCK10 Read/write trigger
SOTB10
55H (communication data)
SIO10
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT10
INTCSI10 CSIIF10
SI10 (receive AAH)
SO10
55H is written to SOTB10.
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Figure 15-4. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)
SCK10
Read/write trigger
SOTB10
55H (communication data)
SIO10
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT10
INTCSI10 CSIIF10
SI10 (input AAH)
SO10
55H is written to SOTB10.
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Figure 15-5. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0
SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0
(b) Type 2; CKP10 = 0, DAP10 = 1
SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0
(c) Type 3; CKP10 = 1, DAP10 = 0
SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0
(d) Type 4; CKP10 = 1, DAP10 = 1
SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0
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(4) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 15-6. Output Operation of First Bit (1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit
The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising) edge of SCK10, and the data is output from the SO10 pin. (2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit 3rd bit
The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10 register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling) edge of SCK10, and the data is output from the SO10 pin.
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(5) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 15-7. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.)
(2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.)
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16.1 Interrupt Function Types
The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see Table 16-1). A standby release signal is generated. Eight external interrupt requests and 15 internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control.
16.2 Interrupt Sources and Configuration
A total of 24 interrupt sources exist for maskable and software interrupts (see Table 16-1).
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Table 16-1. Interrupt Source List
Interrupt Type Maskable Default PriorityNote 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Interrupt Source Name INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/ INTST0 INTTMH1 INTTMH0 INTTM50 INTTM000 UART6 reception error generation End of UART6 reception End of UART6 transmission End of CSI10 transfer/end of UART0 transmission Match between TMH1 and CRH1 (when compare register is specified) Match between TMH0 and CRH0 (when compare register is specified) Match between TM50 and CR50 (when compare register is specified) Match between TM00 and CR000 (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) Match between TM00 and CR010 (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) End of A/D conversion End of UART0 reception or reception error generation Watch timer reference time interval signal Match between TM51 and CR51 (when compare register is specified) Key interrupt detection Watch timer overflow Pin input edge detection BRK instruction execution Reset input Power-on reset Low-voltage detection External Internal External - - Internal Trigger Low-voltage detection Pin input edge detection Internal/ External Internal External Vector Table Address 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H (A) Basic Configuration TypeNote 2 (A) (B)
15
INTTM010
0022H
16 17 18 19 20 21 22 Software Reset - -
INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 BRK RESET POC LVI
0024H 0026H 0028H 002AH 002CH 002EH 0030H 003EH 0000H (C) (A) (B) (D) -
Clock monitor X1 oscillation stop detection WDT WDT overflow
Notes 1. 2.
The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 22 is the lowest. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1.
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Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator
Standby release signal
(B) External maskable interrupt (INTP0 to INTP6)
Internal bus
External interrupt edge enable register (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
IF: IE: ISP: MK: PR:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
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Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Interrupt request
Key interrupt detector
IF
Priority controller
Vector table address generator
1 when KRMn = 1 (n = 0 to 7) Standby release signal
(D) Software interrupt
Internal bus
Interrupt request
Vector table address generator
IF: IE: ISP: MK: PR:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
KRM: Key return mode register
16.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specification flag register (PR0L, PR0H, PR1L) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 16-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources.
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Table 16-2. Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Register INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10 INTST0 INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 TMIFH1 TMIFH0 TMIF50 TMIF000 TMIF010 ADIF SRIF0 WTIIF TMIF51 KRIF WTIF PIF6 IF1L TMMKH1 TMMKH0 TMMK50 TMMK000 TMMK010 ADMK SRMK0 WTIMK TMMK51 KRMK WTMK PMK6 MK1L TMPRH1 TMPRH0 TMPR50 TMPR000 TMPR010 ADPR SRPR0 WTIPR TMPR51 KRPR WTPR PPR6 PR1L LVIIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 SREIF6 SRIF6 STIF6 DUALIF0Note IF0H IF0L LVIMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 SREMK6 SRMK6 STMK6 DUALMK0 MK0H Interrupt Mask Flag Register MK0L LVIPR PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 SREPR6 SRPR6 STPR6 DUALPR0 PR0H Priority Specification Flag Register PR0L
Note If either of the two types of interrupt sources is generated, these flags are set (1).
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input. IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W Symbol IF0L 7 SREIF6 6 PIF5 5 PIF4 4 PIF3 3 PIF2 2 PIF1 1 PIF0 0 LVIIF
Address: FFE1H Symbol IF0H
After reset: 00H 7 6 TMIF000
R/W 5 TMIF50 4 TMIFH0 3 TMIFH1 2 DUALIF0 1 STIF6 0 SRIF6
TMIF010
Address: FFE2H Symbol IF1L
After reset: 00H 7 0
Note
R/W 5 WTIF 4 KRIF 3 TMIF51 2 WTIIF 1 SRIF0 0 ADIF
6 PIF6
XXIFX 0 1
Interrupt request flag No interrupt request signal is generated Interrupt request is generated, interrupt request status
Note Be sure to set bit 7 of IF1L to 0. Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. 2. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form 16-bit register MK0, they are set by a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)
Address: FFE4H Symbol MK0L After reset: FFH 7 SREMK6 6 PMK5 R/W 5 PMK4 4 PMK3 3 PMK2 2 PMK1 1 PMK0 0 LVIMK
Address: FFE5H Symbol MK0H
After reset: FFH 7 6 TMMK000
R/W 5 TMMK50 4 TMMKH0 3 TMMKH1 2 DUALMK0 1 STMK6 0 SRMK6
TMMK010
Address: FFE6H Symbol MK1L
After reset: FFH 7 1
Note
R/W 5 WTMK 4 KRMK 3 TMMK51 2 WTIMK 1 SRMK0 0 ADMK
6 PMK6
XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled
Interrupt servicing control
Note Be sure to set bit 7 of MK1L to 1.
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(3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 16-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L)
Address: FFE8H Symbol PR0L After reset: FFH 7 SREPR6 6 PPR5 R/W 5 PPR4 4 PPR3 3 PPR2 2 PPR1 1 PPR0 0 LVIPR
Address: FFE9H Symbol PR0H
After reset: FFH 7 6 TMPR000
R/W 5 TMPR50 4 TMPRH0 3 TMPRH1 2 DUALPRO 1 STPR6 0 SRPR6
TMPR010
Address: FFEAH Symbol PR1L
After reset: FFH 7 1
Note
R/W 5 WTPR 4 KRPR 3 TMPR51 2 WTIPR 1 SRPR0 0 ADPR
6 PPR6
XXPRX 0 1 High priority level Low priority level
Priority level selection
Note Be sure to set bit 7 of PR1L to 1.
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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP6. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 16-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H Symbol EGP After reset: 00H 7 0 6 EGP6 R/W 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0
Address: FF49H Symbol EGN
After reset: 00H 7 0 6 EGN6
R/W 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0
EGPn 0 0 1 1
EGNn 0 1 0 1 Interrupt disabled Falling edge Rising edge
INTPn pin valid edge selection (n = 0 to 6)
Both rising and falling edges
Table 16-3 shows the ports corresponding to EGPn and EGNn. Table 16-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register EGP0 EGP1 EGP2 EGP3 EGP4 EGP5 EGP6 EGN0 EGN1 EGN2 EGN3 EGN4 EGN5 EGN6 P120 P30 P31 P32 P33 P16 P140 Edge Detection Port Interrupt Request Signal INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6
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(5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 16-6. Format of Program Status Word
7 PSW IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (low-priority interrupt disabled) Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled)
1
IE 0 1
Interrupt request acknowledgement enable/disable Disabled Enabled
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16.4 Interrupt Servicing Operations
16.4.1 Maskable interrupt request acknowledgement A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 16-4 below. For the interrupt request acknowledgement timing, see Figures 16-8 and 16-9. Table 16-4. Time from Generation of Maskable Interrupt Request Until Servicing
Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum TimeNote 32 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 16-7 shows the interrupt request acknowledgement algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction.
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Figure 16-7. Interrupt Request Acknowledgement Processing Algorithm
Start
No
xxIF = 1? Yes (interrupt request generation)
No
xxMK = 0? Yes
Interrupt request held pending Yes (High priority)
xxPR = 0? No (Low priority)
Yes
Any high-priority interrupt request among those simultaneously generated with xxPR = 0?
Interrupt request held pending No No IE = 1? Yes
Any high-priority interrupt request among those simultaneously generated with xxPR = 0?
Yes
No
Any high-priority interrupt request among those simultaneously generated?
Interrupt request held pending
Yes
Interrupt request held pending
No Vectored interrupt servicing IE = 1? Yes ISP = 1? Yes
Interrupt request held pending No
Interrupt request held pending No
Interrupt request held pending
Vectored interrupt servicing
xxIF:
Interrupt request flag
xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls acknowledgement of maskable interrupt request (1 = Enable, 0 = Disable) Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
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Figure 16-8. Interrupt Request Acknowledgement Timing (Minimum Time)
6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Instruction Instruction
PSW and PC saved, jump to interrupt servicing
Interrupt servicing program
Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 16-9. Interrupt Request Acknowledgement Timing (Maximum Time)
25 clocks CPU processing xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Instruction Divide instruction 6 clocks
PSW and PC saved, jump to interrupt servicing
Interrupt servicing program
Remark 1 clock: 1/fCPU (fCPU: CPU clock) 16.4.2 Software interrupt request acknowledgement A software interrupt request is acknowledged by BRK instruction execution. disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. Software interrupts cannot be
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16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 16-5 shows interrupt requests enabled for multiple interrupt servicing and Figure 16-10 shows multiple interrupt servicing examples. Table 16-5. Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing
Multiple Interrupt Request Maskable Interrupt Request PR = 0 Interrupt Being Serviced Maskable interrupt ISP = 0 ISP = 1 Software interrupt IE = 1 IE = 0 x x x IE = 1 x PR = 1 IE = 0 x x x
Remarks 1.
: Multiple interrupt servicing enabled
2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: IE = 1: Interrupt request acknowledgement is disabled. Interrupt request acknowledgement is enabled.
4. PR is a flag contained in PR0L, PR0H, and PR1L. PR = 0: Higher priority level PR = 1: Lower priority level
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Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI
IE = 0 EI INTyy (PR = 0)
IE = 0 EI INTzz (PR = 0)
IE = 0
INTxx (PR = 1)
RETI IE = 1 IE = 1 RETI IE = 1 RETI
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgement. Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
EI
IE = 0 EI
INTxx (PR = 0)
INTyy (PR = 1) IE = 1
RETI
1 instruction execution
IE = 0
RETI IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgement disabled
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Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing IE = 0 EI INTyy (PR = 0) RETI IE = 1 INTxx servicing INTyy servicing
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgement disabled
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16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW. bit, CY * MOV1 CY, PSW. bit * AND1 CY, PSW. bit * OR1 CY, PSW. bit * XOR1 CY, PSW. bit * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW. bit, $addr16 * BF PSW. bit, $addr16 * BTCLR PSW. bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 16-11 shows the timing at which interrupt requests are held pending. Figure 16-11. Interrupt Request Hold
PSW and PC saved, jump to interrupt servicing Interrupt servicing program
These
CPU processing
Instruction N
Instruction M
xxIF
Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
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CHAPTER 17 KEY INTERRUPT FUNCTION
17.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 17-1. Assignment of Key Interrupt Detection Pins
Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Description Controls KR0 signal in 1-bit units. Controls KR1 signal in 1-bit units. Controls KR2 signal in 1-bit units. Controls KR3 signal in 1-bit units. Controls KR4 signal in 1-bit units. Controls KR5 signal in 1-bit units. Controls KR6 signal in 1-bit units. Controls KR7 signal in 1-bit units.
17.2 Configuration of Key Interrupt
The key interrupt consists of the following hardware. Table 17-2. Configuration of Key Interrupt
Item Control register Configuration Key return mode register (KRM)
Figure 17-1. Block Diagram of Key Interrupt
KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM)
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17.3 Register Controlling Key Interrupt
(1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 17-2. Format of Key Return Mode Register (KRM)
Address: FF6EH Symbol KRM 7 KRM7 After reset: 00H 6 KRM6 5 KRM5 R/W 4 KRM4 3 KRM3 2 KRM2 KRM1 0 KRM0
KRMn 0 1
Key interrupt mode control Does not detect key interrupt signal Detects key interrupt signal
Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports.
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CHAPTER 18 STANDBY FUNCTION
18.1 Standby Function and Configuration
18.1.1 Standby function Table 18-1. Relationship Between HALT Mode, STOP Mode, and Clock
X1 Input Clock HALT mode STOP mode Oscillation continues Oscillation stopped Ring-OSC Clock Oscillation continues Oscillation continues Subsystem Clock Oscillation continues Oscillation continues CPU Clock Operation stopped Operation stopped
The standby function is designed to reduce the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped, but the system clock oscillator continues oscillating. In this mode, power consumption is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 input clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU power consumption. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. STOP mode can be used only when operating on the X1 input clock or Ring-OSC clock. HALT mode can be used when operating on the X1 input clock, Ring-OSC clock, or subsystem clock. However, when the STOP instruction is executed during Ring-OSC clock operation, the X1 oscillator stops, but Ring-OSC oscillator does not stop. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction. 3. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 4. Ring-OSC clock oscillation cannot be stopped in the STOP mode. However, when the RingOSC clock is used as the CPU clock, the CPU operation is stopped for 17/fR (s) after STOP mode is released.
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Figure 18-1. Operation Timing When STOP Mode Is Released
STOP mode release STOP mode
X1 input clock
Ring-OSC clock X1 input clock is selected as CPU clock when STOP instruction is executed Ring-OSC clock is selected as CPU clock when STOP instruction is executed Operation stopped (17/fR)
HALT status (oscillation stabilization time set by OSTS)
X1 input clock
Ring-OSC clock
X1 input clock
Clock switched by software
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18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H. Figure 18-2. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H Symbol OSTC After reset: 00H 7 0 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16
MOST11 1 1 1 1 1
MOST13 0 1 1 1 1
MOST14 0 0 1 1 1
MOST15 0 0 0 1 1
MOST16 0 0 0 0 1
Oscillation stabilization time status 2 /fX min. (204.8 s min.)
11
213/fX min. (819.2 s min.) 214/fX min. (1.64 ms min.) 215/fX min. (3.27 ms min.) 216/fX min. (6.55 ms min.)
Caution After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. Remarks 1. Values in parentheses are for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock. After STOP mode is released when the Ring-OSC clock is selected, check the oscillation stabilization time using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 18-3. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H Symbol OSTS After reset: 05H 7 0 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2 0 0 0 1 1
OSTS1 0 1 1 0 0 Other than above
OSTS0 1 0 1 0 1
11
Oscillation stabilization time selection 2 /fX (204.8 s) 213/fX (819.2 s) 214/fX (1.64 ms) 215/fX (3.27 ms) 216/fX (6.55 ms) Setting prohibited
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation.
STOP mode release X1 pin voltage waveform a VSS
Remarks 1. Values in parentheses are for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency
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18.2 Standby Function Operation
18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below. Table 18-2. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on X1 Input Clock When Ring-OSC Oscillation Continues When Subsystem Clock Used Item System clock CPU Port (latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 8-bit timer H1 Watch timer Watchdog timer Ring-OSC cannot be stoppedNote 4 Ring-OSC can be stoppedNote 4 A/D converter Serial interface UART0 UART6 CSI10 Clock monitor Power-on-clear functionNote 5 Low-voltage detection function External interrupt When Subsystem Clock Not Used When Ring-OSC Oscillation StoppedNote 1 When Subsystem Clock Used When Subsystem Clock Not Used When HALT Instruction Is Executed While CPU Is Operating on Ring-OSC Clock When X1 Input Clock Oscillation Continues When Subsystem Clock Used When Subsystem Clock Not Used When X1 Input Clock Oscillation Stopped When Subsystem Clock Used When Subsystem Clock Not Used
The X1 oscillator, Ring-OSC oscillator, and subsystem clock oscillator are able to oscillate. Clock supply to the CPU is stopped. Operation stopped Status before HALT mode was set is retained Operable Operable Operable Operable Operable Operable Operable Operation stopped Operable Operable Operable Operable Operable Operable Operable Operable Operation stopped Not operable Operable only when TO50 is selected as the serial clock during TM50 operation Operable only when external SCK10 is selected as the serial clock Operable Operation stopped Operable
Note 2
Operation stopped Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TO50 is selected as the count clock during 8-bit timer/event counter 50 operation Operable only when fR/2 is selected as the count clock Operable - Operable
Note 2 7
Operable
Note 3
Not operable OperableNote 3 Not operable
Operable
Notes 1. 2. 3. 4. 5.
When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 24 MASK OPTIONS). Operable when the X1 input clock is selected. Operable when the subsystem clock is selected. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option.
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Table 18-2. Operating Statuses in HALT Mode (2/2)
HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues Item System clock CPU Port (latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 8-bit timer H1 When Ring-OSC Oscillation Continues When Ring-OSC Oscillation StoppedNote 1 When X1 Input Clock Oscillation Stopped When Ring-OSC Oscillation Continues When Ring-OSC Oscillation StoppedNote 1
The X1 oscillator, Ring-OSC oscillator, and subsystem clock oscillator are able to oscillate. Clock supply to the CPU is stopped. Operation stopped Status before HALT mode was set is retained Operable Operable Operable Operable Operable Operable only when the X1 input clock is selected as the count clock Operation stopped Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TO50 is selected as the count clock during 8-bit timer/event counter 50 operation Operable only when fR/27 is selected as the count clock Operation stopped
Watch timer Watchdog timer Ring-OSC cannot be stoppedNote 2 Ring-OSC can be stoppedNote 2 A/D converter Serial interface UART0 UART6 CSI10 Clock monitor Power-on-clear functionNote 3 Low-voltage detection function External interrupt
Operable Operable Operation stopped Operable Operable Operable Operable Operable Operable Operable Operable Operation stopped -
Operable only when subsystem clock is selected Operable -
Not operable Operable only when TO50 is selected as the serial clock during TM50 operation Operable only when external clock is selected as the serial clock
Notes 1. 2. 3.
When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 24 MASK OPTIONS). "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option.
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(2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 18-4. HALT Mode Release by Interrupt Request Generation
Interrupt request Wait
HALT instruction Standby release signal Operating mode
CPU clock X1 input clock, Ring-OSC clock, or subsystem clock
HALT mode Oscillation
Wait
Operating mode
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks
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(b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-5. HALT Mode Release by RESET Input (1) When X1 input clock is used as CPU clock
HALT instruction
RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Oscillation stabilization time (211/fX to 216/fX)
CPU clock
Operating mode (X1 input clock)
HALT mode Oscillates
X1 input clock
(2) When Ring-OSC clock or subsystem clock is used as CPU clock
HALT instruction
RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period
CPU clock
Operating mode
HALT mode Oscillates
Ring-OSC clock Ring-OSC clock or or subsystem clock subsystem clock
Remarks 1. fX: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency Table 18-3. Operation After HALT Mode Release
Release Source Maskable interrupt request MKxx 0 PRxx 0 IE 0 ISP x x 1 0 1 x x Operation Next address instruction execution Interrupt servicing execution Next address instruction execution Interrupt servicing execution HALT mode held Reset processing
0 0 0 0 1 RESET input -
0 1 1 1 x -
1 0 x 1 x x
x: Don't care
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18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. Table 18-4. Operating Statuses in STOP Mode
STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on X1 Input Clock When Ring-OSC Oscillation Continues Item System clock CPU Port (latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 8-bit timer H1 Watch timer Watchdog timer Ring-OSC cannot be stoppedNote 4 Ring-OSC can be stoppedNote 4 A/D converter Serial interface UART0 UART6 CSI10 Clock monitor Power-on-clear functionNote 5 Low-voltage detection function External interrupt Operable only when external SCK10 is selected as the serial clock Operation stopped Operable Operable Operable When Ring-OSC Oscillation StoppedNote 1 When STOP Instruction Is Executed While CPU Is Operating on RingOSC Clock
When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem Clock Used Clock Not Used Clock Used Clock Not Used Clock Used Clock Not Used Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped. Operation stopped Status before STOP mode was set is retained Operation stopped Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TO50 is selected as the count clock during 8-bit timer/event counter 50 operation OperableNote 2 Operable
Note 3
Operation stopped Operation stopped Operable
Note 3
OperableNote 2 Operation stopped OperableNote 3 Operation stopped
Operable Operation stopped Operation stopped
-
Operable
Operable only when TO50 is selected as the serial clock during TM50 operation
Notes 1. 2. 3. 4. 5.
When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 24 MASK OPTIONS). Operation continues only when fR/2 is selected as the count clock. Operable when the subsystem clock is selected. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option.
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(2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 18-6. STOP Mode Release by Interrupt Request Generation (1) When X1 input clock is used as CPU clock
STOP instruction Wait (set by OSTS)
After the oscillation
stabilization time has elapsed, if interrupt acknowledgement is enabled, vectored interrupt servicing is carried
Standby release signal Oscillation stabilization wait status Oscillates Oscillation stabilization time (set by OSTS)
CPU clock Operating mode (X1 input clock) Oscillates
STOP mode Oscillation stopped
Operating mode (X1 input clock)
X1 input clock
(2) When Ring-OSC clock is used as CPU clock
STOP instruction
Standby release signal Operation stopped (17/fR) Oscillates
CPU clock Ring-OSC clock
Operating mode (Ring-OSC clock)
STOP mode
Operating mode (Ring-OSC clock)
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
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(b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 18-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock
STOP instruction
RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Oscillation stabilization time (211/fX to 216/fX) Reset period
CPU clock Operating mode (X1 input clock) Oscillates
STOP mode Oscillation stopped
X1 input clock
(2) When Ring-OSC clock is used as CPU clock
STOP instruction
RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period
CPU clock Operating mode (Ring-OSC clock) Ring-OSC clock
STOP mode Oscillates
Table 18-5. Operation After STOP Mode Release
Release Source Maskable interrupt request MKxx 0 0 PRxx 0 0 IE 0 1 ISP x x 1 0 1 x x Operation Next address instruction execution Interrupt servicing execution Next address instruction execution Interrupt servicing execution STOP mode held Reset processing
0 0 0 1 RESET input -
1 1 1 x -
0 x 1 x x
x: Don't care
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The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is input. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 19-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a high level is input to the RESET pin, the reset is released and program execution starts using the RingOSC clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 19-2 to 19-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see CHAPTER 21 POWER-ON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output.
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Figure 19-1. Block Diagram of Reset Function
Internal bus Reset control flag register (RESF) WDTRF Set WDTRES (Watchdog timer reset signal) Clear CLMRF Set Clear LVIRF Set Clear
CLMRESB (Clock monitor reset signal)
Reset signal
RESET
POCRESB (Power-on-clear circuit reset signal) LVIRESB (Low-voltage detector reset signal)
Reset signal to LVIM/LVIS register
Reset signal
Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register
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Figure 19-2. Timing of Reset by RESET Input
X1 Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock)
CPU clock RESET
Normal operation
Internal reset signal Delay Port pin Delay Hi-ZNote
Figure 19-3. Timing of Reset Due to Watchdog Timer Overflow
X1 Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock)
CPU clock Watchdog timer overflow Internal reset signal
Normal operation
Port pin
Hi-ZNote
Caution A watchdog timer internal reset resets the watchdog timer. Figure 19-4. Timing of Reset in STOP Mode by RESET Input
X1
STOP instruction execution
CPU clock Normal operation RESET
Stop status (Oscillation stop)
Reset period (Oscillation stop)
Operation stop (17/fR)
Normal operation (Reset processing, Ring-OSC clock)
Internal reset signal Delay Port pin Delay Hi-ZNote
Note The port pins become high impedance, except for P130, which is set to low-level output. Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 21 POWERON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.
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Table 19-1. Hardware Statuses After Reset (1/2)
Hardware Program counter (PC)Note 1 Status After Reset The contents of the reset vector table (0000H, 0001H) are set. Undefined 02H UndefinedNote 2 UndefinedNote 2 00H FFH 00H 00H CFH 00H 00H 00H 00H 05H 00H 0000H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P0 to P3, P6, P7, P12 to P14) (output latches) Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, PM14) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, PU14) Input switch control register (ISC) Internal memory size switching register (IMS) Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time select register (OSTS) Oscillation stabilization time counter status register (OSTC) 16-bit timer/event counter 00 Timer counter 00 (TM00) Capture/compare registers 000, 010 (CR000, CR010) Mode control register 00 (TMC00) Prescaler mode register 00 (PRM00) Capture/compare control register 00 (CRC00) Timer output control register 00 (TOC00) 8-bit timer/event counters 50, 51 Timer counters 50, 51 (TM50, TM51) Compare registers 50, 51 (CR50, CR51) Timer clock selection registers 50, 51 (TCL50, TCL51) Mode control registers 50, 51 (TMC50, TMC51) 8-bit timers H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) Mode registers (TMHMD0, TMHMD1) Carrier control register 1 (TMCYC1)Note 3 Watch timer Clock output controller Operation mode register (WTM) Clock output selection register (CKS)
Notes 1. 2. 3.
During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. When a reset is executed in the standby mode, the pre-reset status is held even after reset. 8-bit timer H1 only.
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Table 19-1. Hardware Statuses After Reset (2/2)
Hardware Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Baud rate generator control register 0 (BRGC0) Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Serial interface CSI10 Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Serial operation mode register 10 (CSIM10) Serial clock selection register 10 (CSIC10) Key interrupt Clock monitor Reset function Low-voltage detector Key return mode register (KRM) Mode register (CLM) Reset control flag register (RESF) Low-voltage detection register (LVIM) Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) Status After Reset 67H 9AH Undefined 00H 00H 00H 00H FFH FFH 01H 1FH FFH FFH 01H 00H 00H 00H FFH 16H Undefined 00H 00H 00H 00H 00H 00HNote 00HNote 00HNote 00H FFH FFH 00H 00H
Note These values vary depending on the reset source.
Reset Source Register RESF LVIM LVIS See Table 19-2. Cleared (00H) Cleared (00H) Cleared (00H) Cleared (00H) Held RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI
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19.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/KD1 Series. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 19-5. Format of Reset Control Flag Register (RESF)
Address: FFACH Symbol RESF 7 0 After reset: 00HNote 6 0 R 5 0 4 WDTRF 3 0 2 0 1 CLMRF 0 LVIRF
WDTRF 0 1
Internal reset request by watchdog timer (WDT) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated.
CLMRF 0 1
Internal reset request by clock monitor (CLM) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated.
LVIRF 0 1
Internal reset request by low-voltage detector (LVI) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated.
Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 19-2. Table 19-2. RESF Status When Reset Request Is Generated
Reset Source Flag WDTRF CLMRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Held Set (1) Held Held Held Set (1) RESET input Reset by POC Reset by WDT Reset by CLM Reset by LVI
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20.1 Functions of Clock Monitor
The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 19 RESET FUNCTION. The clock monitor automatically stops under the following conditions. * In STOP mode and during the oscillation stabilization time * When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1) * During the oscillation stabilization time after reset is released * When the Ring-OSC clock is stopped Remark MSTOP: Bit 7 of the main OSC control register (MOC)
20.2 Configuration of Clock Monitor
Clock monitor consists of the following hardware. Table 20-1. Configuration of Clock Monitor
Item Control register Clock monitor mode register (CLM) Configuration
Figure 20-1. Block Diagram of Clock Monitor
X1 input clock
Internal reset signal
Ring-OSC clock Enable/disable
CLME Clock monitor mode register (CLM)
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20.3 Register Controlling Clock Monitor
Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 20-2. Format of Clock Monitor Mode Register (CLM)
Address: FFA9H Symbol CLM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 CLME
CLME 0 1
Enables/disables clock monitor operation Disables clock monitor operation Enables clock monitor operation
Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal reset signal. 2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. CLMRF is read by software and then automatically cleared to 0. CLMRF is cleared under the following conditions. * * * RESET input Internal reset signal generation by POC After read by software
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CHAPTER 20 CLOCK MONITOR
20.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The start and stop conditions are as follows. When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). * In STOP mode and during the oscillation stabilization time * During the oscillation stabilization time after reset is released * When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1) * When the Ring-OSC clock is stopped Remark MSTOP: Bit 7 of the main OSC control register (MOC) Table 20-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock X1 input clock Operation Mode STOP mode X1 Input Clock Status Stopped Ring-OSC Clock Status Oscillating Stopped RESET input
Note
Clock Monitor Status Stopped
Oscillating StoppedNote
HALT mode
Oscillating
Oscillating Stopped
Note
Operating Stopped Stopped
Ring-OSC clock
STOP mode RESET input HALT mode
Stopped
Oscillating
Oscillating Stopped
Operating Stopped
Note The Ring-OSC clock is stopped only when the "Ring-OSC can be stopped by software" is selected by a mask option. If "Ring-OSC cannot be stopped" is selected, the Ring-OSC clock cannot be stopped. The clock monitor timing is as shown in Figure 20-3.
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Figure 20-3. Timing of Clock Monitor (1/3) (1) When internal reset is executed by oscillation stop of X1 input clock
4 clocks of Ring-OSC clock
X1 input clock
Ring-OSC clock Internal reset signal
CLME
CLMRFNote
Note CLMRF is read by software and then automatically cleared to 0. CLMRF is cleared under the following conditions. * RESET input * Internal reset signal generation by POC * After read by software (2) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
Normal operation
CPU operation X1 input clock
STOP
Oscillation stabilization time
Normal operation
Oscillation stopped Ring-OSC clock
Oscillation stabilization time (set by OSTS register)
CLME Clock monitor status Monitoring Monitoring stopped Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time.
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Figure 20-3. Timing of Clock Monitor (2/3) (3) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
Normal operation Clock supply stopped
CPU operation X1 input clock
STOP
Normal operation (Ring-OSC clock)
Oscillation stopped Ring-OSC clock
Oscillation stabilization time (set by OSTS register)
17 clocks CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. (4) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time)
Normal operation Clock supply stopped
CPU operation X1 input clock
Reset
Normal operation (Ring-OSC clock)
Oscillation stopped Ring-OSC clock Oscillation stopped RESET 17 clocks
Oscillation stabilization time
Set to 1 by software
CLME Clock monitor status Monitoring Monitoring stopped Monitoring
Waiting for end of oscillation stabilization time
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. Even if CLME is set to 1 by software during the oscillation stabilization time of the X1 input clock, Monitoring is monitoring is not performed until the oscillation stabilization time of the X1 input clock ends. automatically started at the end of the oscillation stabilization time.
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Figure 20-3. Timing of Clock Monitor (3/3) (5) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
Normal operation Clock supply stopped
CPU operation X1 input clock
Reset
Normal operation (Ring-OSC clock)
Oscillation stabilization time Ring-OSC clock 17 clocks RESET Set to 1 by software
CLME Clock monitor status Monitoring Monitoring stopped Monitoring
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. When CLME is set to 1 by software at the end of the oscillation stabilization time of the X1 input clock, monitoring is started.
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD < VPOC. * The following can be selected by a mask option.
* * *
POC disabled POC used (detection voltage: VPOC = 2.85 V 0.15 V) POC used (detection voltage: VPOC = 3.5 V 0.2 V)
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT, LVI, or the clock monitor. For details of the RESF, refer to CHAPTER 19 RESET FUNCTION.
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21.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit
VDD VDD
+ Internal reset signal -
Detection voltage source (VPOC)
21.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC) are compared, and when VDD < VPOC, an internal reset signal is generated. Figure 21-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (VDD) POC detection voltage (VPOC)
2.7 V Time Internal reset signal
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21.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 21-3. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
Reset
Checking cause of resetNote 2 Power-on-clear
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register.
Start timer (set to 50 ms)
; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (240 kHz)/27 x compare 100 = 53 ms (fR: Ring-OSC clock oscillation frequency)
Note 1
Check stabilization of oscillation
; Check the stabilization of oscillation of the X1 input clock by using the OSTC register.
Change CPU clock
; Change the CPU clock from the Ring-OSC clock to the X1 input clock.
No
50 ms has passed? (TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes Initialization processing
; Initialization of ports
Notes 1. 2.
If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page.
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Figure 21-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause
Check reset cause
WDTRF of RESF register = 1?
Yes
No Reset processing by watchdog timer
CLMRF of RESF register = 1?
Yes
No Reset processing by clock monitor
LVIRF of RESF register = 1?
Yes
No Reset processing by low-voltage detector
Power-on-clear/external reset generated
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CHAPTER 22 LOW-VOLTAGE DETECTOR
22.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. * Detection levels (seven levels) of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, refer to CHAPTER 19 RESET FUNCTION.
22.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown below. Figure 22-1. Block Diagram of Low-Voltage Detector
VDD
Low-voltage detection level selector
VDD
N-ch Internal reset signal
Selector
+ -
INTLVI Detection voltage source (VLVI)
3 LVIS2 LVIS1 LVIS0
Low-voltage detection level selection register (LVIS) Internal bus
LVION
LVIE
LVIMD
LVIF
Low-voltage detection register (LVIM)
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22.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS)
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(1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears LVIM to 00H. Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
Address: FFBEH Symbol LVIM 7 LVION After reset: 00H 6 0 R/WNote 1 5 0 4 LVIE 3 0 2 0 1 LVIMD 0 LVIF
LVIONNotes 2, 3 0 1 Disables operation Enables operation
Enables low-voltage detection operation
LVIENotes 2, 4, 5 0 1 Disables operation Enables operation
Specifies reference voltage generator
LVIMDNote 2 0 1
Low-voltage detection operation mode selection Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI) Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIFNote 6 0 1
Low-voltage detection flag Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled Supply voltage (VDD) < detection voltage (VLVI)
Notes 1. 2. 3.
Bit 0 is read-only. LVION, LVIE, and LVIMD are cleared to 0 at a reset other than an LVI reset. These are not cleared to 0 at an LVI reset. When LVION is set to 1, operation of the comparator in the LVI circuit is started. confirmed at LVIF. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
4.
When LVIE is set to 1, a reference voltage generator operation in the LVI circuit is started. Use software to instigate a wait of at least 2 ms from when LVIE is set to 1 until LVION is set to 1.
5. 6.
If "use POC" is selected by a mask option, leave LVIE as 0. A wait time (2 ms) until LVION is set to 1 is not necessary. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0.
Caution To stop LVI, follow either of the procedures below. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then clear LVIE to 0.
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(2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 22-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
Address: FFBFH Symbol LVIS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 LVIS2 1 LVIS1 0 LVIS0
LVIS2 0 0 0 0 1 1 1 1
LVIS1 0 0 1 1 0 0 1 1
LVIS0 0 1 0 1 0 1 0 1 VLVI0 (4.3 V 0.2 V) VLVI1 (4.1 V 0.2 V) VLVI2 (3.9 V 0.2 V) VLVI3 (3.7 V 0.2 V) VLVI4 (3.5 V 0.2 V)Note VLVI5 (3.3 V 0.15 V)Note VLVI6 (3.1 V 0.15 V)Note Setting prohibited
Detection level
Note When the detection voltage of the POC circuit is specified as VPOC = 3.5 V 0.2 V by a mask option, do not select VLVI4 to VLVI6 as the LVI detection voltage. Even if VLVI4 to VLVI6 are selected, POC circuit has priority.
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22.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Confirm that "supply voltage (VDD) > detection voltage (VLVI)" at bit 0 (LVIF) of LVIM. <8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <5>. 2. If "use POC" is selected by a mask option, procedures <3> and <4> are not required. 3. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed.
*
When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order.
*
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Figure 22-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1> Time
LVIE flag (set by software)
Not cleared <3> <4> 2 ms or longer
Not cleared Clear Not cleared Clear
LVION flag (set by software) <5>
Not cleared
<6> 0.2 ms or longer LVIF flag <7> LVIMD flag (set by software) <8> Clear LVIRF flagNote Not cleared Not cleared Clear
LVI reset signal Cleared by software POC reset signal Cleared by software
Internal reset signal
Note LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 19 RESET FUNCTION. Remark <1> to <8> in Figure 22-4 above correspond to <1> to <8> in the description of "when starting operation" in 22.4 (1) When used as reset.
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CHAPTER 22 LOW-VOLTAGE DETECTOR
(2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Confirm that "supply voltage (VDD) > detection voltage (VLVI)" at bit 0 (LVIF) of LVIM. <8> Clear the interrupt request flag of LVI (LVIIF) to 0. <9> Release the interrupt mask flag of LVI (LVIMK). <10> Execute the EI instruction (when vector interrupts are used). Caution If "use POC" is selected by a mask option, procedures <3> and <4> are not required. * When stopping operation Either of the following procedures must be executed.
*
When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVION to 0 first, and then clear LVIE to 0.
*
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Figure 22-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1> <9> Cleared by software LVIE flag (set by software) Time
<3> <4> 2 ms or longer
LVION flag (set by software) <5> <6> 0.2 ms or longer LVIF flag <7> INTLVI
LVIIF flag <8> Cleared by software Internal reset signal
Remark <1> to <9> in Figure 22-5 above correspond to <1> to <9> in the description of "when starting operation" in 22.4 (2) When used as interrupt.
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22.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take action (2) below. In this system, take the following actions. (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports.
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Figure 22-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
Reset
Checking cause of resetNote 2 LVI
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register.
Start timer (set to 50 ms)
; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (240 kHz)/27 x compare 100 = 53 ms (fR: Ring-OSC clock oscillation frequency)
Note 1
Check stabilization of oscillation
; Check the stabilization of oscillation of the X1 input clock by using the OSTC register.
Change CPU clock
; Change the CPU clock from the Ring-OSC clock to the X1 input clock.
No
50 ms has passed? (TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes Initialization processing
; Initialization of ports
Notes 1. 2.
If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page.
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Figure 22-6. Example of Software Processing After Release of Reset (2/2) * Checking reset cause
Check reset cause
WDTRF of RESF register = 1?
Yes
No Reset processing by watchdog timer
CLMRF of RESF register = 1?
Yes
No Reset processing by clock monitor
LVIRF of RESF register = 1?
No
Yes Power-on-clear/external reset generated
Reset processing by low-voltage detector
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(2) When used as interrupt Disable interrupts (DI) in the servicing routine of the LVI interrupt, and check to see if "supply voltage (VDD) > detection voltage (VLVI)", by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Then enable interrupts (EI). In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, disable interrupts (DI), wait for the supply voltage fluctuation period, check that "supply voltage (VDD) > detection voltage (VLVI)" with the LVIF flag, and then enable interrupts (EI). Figure 22-7. Example of Software Processing of LVI Interrupt * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
LVI LVI interrupt
DI
; Disable interrupts.
Start timer (set to 50 ms)
LVI interrupt servicing
No
50 ms has passed? (TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated
Yes
No
LVIF1 of LVIM register = 0?
; Check that supply voltage (VDD) > detection voltage (VLVI).
Yes
EI
; Enable interrupts.
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CHAPTER 23 REGULATOR
23.1 Outline
The 78K0/KD1 Series includes a circuit to realize low-voltage operation inside the device. regulator output voltage, connect the REGC pin to VSS via a 0.1 F capacitor. The regulator of the 78K0/KD1 Series stops operating in the following cases. * During the reset period * In STOP mode * In HALT mode when the CPU is operating on the subsystem clock Figure 23-1 shows the block diagram of the periphery of the regulator. Figure 23-1. Block Diagram of Regulator Periphery To stabilize the
EVDD system I/O buffer
Internal digital circuits EVDD
A/D converter X1, Ring, sub oscillator AVREF Bidirectional level shifter REGC
Flash memory ( PD78F0124 only)
Regulator VDD VPP 0.1 F
Remark To use the CPU at high speed (fXP = 10 MHz, VDD = 4.0 to 5.5 V), connect the REGC pin directly to VDD and use at the same potential as the VDD pin.
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Mask ROM versions are provided with the following mask options. 1. Power-on-clear (POC) circuit * POC cannot be used * POC used (detection voltage: VPOC = 2.85 V 0.15 V) * POC used (detection voltage: VPOC = 3.5 V 0.2 V) 2. Ring-OSC * Cannot be stopped * Can be stopped by software 3. Pull-up resistor of P60 to P63 pins * Pull-up resistor can be incorporated in 1-bit units (Pull-up resistors are not available for the flash memory versions.) Flash memory versions that support the mask options of the mask ROM versions are as follows. Table 24-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions
Mask Option POC Circuit POC cannot be used Ring-OSC Cannot be stopped Can be stopped by software POC used (VPOC = 2.85 V 0.15 V) Cannot be stopped Can be stopped by software POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped Can be stopped by software Flash Memory Version
PD78F0124M1 PD78F0124M2 PD78F0124M3 PD78F0124M4 PD78F0124M5 PD78F0124M6
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CHAPTER 25 PD78F0124
The PD78F0124 is provided as the flash memory version of the 78K0/KD1 Series. The PD78F0124 replaces the internal mask ROM of the PD780124 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 25-1 lists the differences between the
PD78F0124 and the mask ROM versions.
Table 25-1. Differences Between PD78F0124 and Mask ROM Versions
Item Internal ROM configuration Internal ROM capacity
PD78F0124
Flash memory 32 KB
Note
Mask ROM Versions Mask ROM
PD780121: 8 KB PD780122: 16 KB PD780123: 24 KB PD780124: 32 KB PD780121: 512 bytes PD780122: 512 bytes PD780123: 1024 bytes PD780124: 1024 bytes
Available None
Internal high-speed RAM capacity
1024 bytesNote
IC pin VPP pin Electrical specifications
None Available
Refer to CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES).
Note The same capacity as the mask ROM versions can be specified by means of the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions.
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25.1 Internal Memory Size Switching Register
The PD78F0124 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved. IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution Be sure to set the value of the relevant mask ROM version at initialization. Figure 25-1. Format of Internal Memory Size Switching Register (IMS)
Address: FFF0H Symbol IMS After reset: CFH 7 RAM2 6 RAM1 R/W 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0
RAM2 0 1
RAM1 1 1 Other than above
RAM0 0 0 512 bytes
Internal high-speed RAM capacity selection
1024 bytes Setting prohibited
ROM3 0 0 0 1
ROM2 0 1 1 0
ROM1 1 0 1 0
ROM0 0 0 0 0 8 KB 16 KB 24 KB 32 KB
Internal ROM capacity selection
Other than above
Setting prohibited
The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 25-2. Table 25-2. Internal Memory Size Switching Register Settings
Target Mask ROM Versions IMS Setting 42H 44H C6H C8H
PD780121 PD780122 PD780123 PD780124
Caution When using a mask ROM version, be sure to set the value indicated in Table 25-2 to IMS.
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CHAPTER 25 PD78F0124
25.2 Flash Memory Programming
On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is performed after connecting a dedicated flash programmer (Flashpro III (FL-PR3, PGFP3)/Flashpro IV (FL-PR4, PG-FP4)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III/Flashpro IV. Remarks 1. FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd. 2. USB is supported only by Flashpro IV. 25.2.1 Selection of communication mode Writing to flash memory is performed using Flashpro III/Flashpro IV and serial communication. Select the communication mode for writing from Table 25-3. For the selection of the communication mode, a format like the one shown in Figure 25-2 is used. The communication mode is selected according to the number of VPP pulses shown in Table 25-3. Table 25-3. Communication Mode List
Communication Mode 3-wire serial I/O Number of Channels 1 Pin UsedNote SCK10/TxD0/P10 SI10/RxD0/P11 SO10/P12 SCK10/TxD0/P10 SI10/RxD0/P11 SO10/P12 HS/P15/TOH0 UART (UART0) 1 TxD0/SCK10/P10 RxD0/SI10/P11 TxD0/SCK10/P10 RxD0/SI10/P11 HS/P15/TOH0 UART (UART6) 1 TxD6/P13 RxD6/P14 Number of VPP Pulses 0
3
8 11
9
Note After shifting to flash memory programming mode, all pins not used for flash memory programming are set to the same state as after reset. Therefore, since all ports become output high-impedance, pin processing, such as connecting to VDD or VSS via a resistor is required if the output high-impedance state is not acknowledged by external devices. Caution Be sure to select the number of VPP pulses shown in Table 25-3 for the communication mode.
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Figure 25-2. Communication Mode Selection Format
VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash memory write mode
25.2.2 Flash memory programming function Flash memory writing is performed via command and data transmit/receive operations using the selected communication mode. The main functions are listed in Table 25-4. Table 25-4. Main Functions of Flash Memory Programming
Function Reset Batch verify Batch erase Batch blank check High-speed write Continuous write Status Oscillation frequency setting Erase time setting Baud rate setting Silicon signature read Description Used to detect write stop and transmission synchronization. Compares entire memory contents and input data. Erases the entire memory contents. Checks the erase status of the entire memory. Performs writing to flash memory according to write start address and number of write data (bytes). Performs successive write operations using the data input with high-speed write operation. Checks the current operation mode and operation end. Inputs the resonator oscillation frequency information. Inputs the memory erase time. Sets the communication rate when the UART mode is used. Outputs the device name, memory capacity, and device block information.
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25.2.3 Connecting Flashpro III/Flashpro IV The connection between Flashpro III/Flashpro IV and the PD78F0124 differs depending on the communication mode (3-wire serial I/O or UART). Figures 25-3 to 25-7 show the connection diagrams of each case. Figure 25-3. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode
Flashpro III/Flashpro IV VPP VDD RESET SCK SO SI GND VPP VDD/EVDD/AVREF RESET SCK10 SI10 SO10 VSS/EVSS/AVSS
PD78F0124
Figure 25-4. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode (Using Handshake)
Flashpro III/Flashpro IV VPP VDD RESET SCK SO SI HS GND VPP VDD/EVDD/AVREF RESET SCK10 SI10 SO10 HS (P15) VSS/EVSS/AVSS
PD78F0124
Caution Be sure to connect the REGC pin of the PD78F0124 in either of the following two ways. * Connect to GND of Flashpro III/Flashpro IV via 0.1 F capacitor * Connect directly to VDD of Flashpro III/Flashpro IV
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Figure 25-5. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode
Flashpro III/Flashpro IV VPP VDD RESET SO SI GND
PD78F0124
VPP VDD/EVDD/AVREF RESET RxD0 TxD0 VSS/EVSS/AVSS
Figure 25-6. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode (Using Handshake)
Flashpro III/Flashpro IV VPP VDD RESET SO SI HS GND
PD78F0124
VPP VDD/EVDD/AVREF RESET RxD0 TxD0 HS (P15) VSS/EVSS/AVSS
Figure 25-7. Connection of Flashpro III/Flashpro IV in UART (UART6) Mode
Flashpro III/Flashpro IV VPP VDD RESET SO SI GND VPP VDD/EVDD/AVREF RESET RxD6 TxD6 VSS/EVSS/AVSS
PD78F0124
Caution Be sure to connect the REGC pin of the PD78F0124 in either of the following two ways. * Connect to GND of Flashpro III/Flashpro IV via 0.1 F capacitor * Connect directly to VDD of Flashpro III/Flashpro IV
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25.2.4 Connection on adapter for flash memory writing Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 25-8. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode
VDD (2.7 to 5.5 V) GND
LVDD (VDD2) VDD GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 3 4 5Note 6 7 8 9 10 11 12 38 37 36 35 34
PD78F0124
33 32 31 30 29 28
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
Note Be sure to connect the REGC pin in either of the following two ways. * Connect to GND via 0.1 F capacitor * Connect directly to VDD
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Figure 25-9. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (Using Handshake)
VDD (2.7 to 5.5 V) GND
LVDD (VDD2) VDD GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 3 4 5Note 6 7 8 9 10 11 12 38 37 36 35 34
PD78F0124
33 32 31 30 29 28
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
Note Be sure to connect the REGC pin in either of the following two ways. * Connect to GND via 0.1 F capacitor * Connect directly to VDD
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Figure 25-10. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode
VDD (2.7 to 5.5 V) GND
LVDD (VDD2) VDD GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 3 4 5Note 6 7 8 9 10 11 12 38 37 36 35 34
PD78F0124
33 32 31 30 29 28
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
Note Be sure to connect the REGC pin in either of the following two ways. * Connect to GND via 0.1 F capacitor * Connect directly to VDD
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Figure 25-11. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode (Using Handshake)
VDD (2.7 to 5.5 V) GND
LVDD (VDD2) VDD GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 3 4 5Note 6 7 8 9 10 11 12 38 37 36 35 34
PD78F0124
33 32 31 30 29 28
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
Note Be sure to connect the REGC pin in either of the following two ways. * Connect to GND via 0.1 F capacitor * Connect directly to VDD
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Figure 25-12. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode
VDD (2.7 to 5.5 V) GND
LVDD (VDD2) VDD GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 3 4 5Note 6 7 8 9 10 11 12 38 37 36 35 34
PD78F0124
33 32 31 30 29 28
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
Note Be sure to connect the REGC pin in either of the following two ways. * Connect to GND via 0.1 F capacitor * Connect directly to VDD
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This chapter lists each instruction set of the 78K0/KD1 Series in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E).
26.1 Conventions Used in Operation List
26.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 26-1. Operand Identifiers and Specification Methods
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Specification Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbolNote Special function register symbol (16-bit manipulatable register even addresses only)Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, refer to Table 3-5 Special Function Register List.
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26.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): : : :
A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) : Inverted data Signed 8-bit data (displacement value)
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
addr16: 16-bit immediate data or label jdisp8:
26.1.3 Description of flag operation column (Blank): Not affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
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26.2 Operation List
Instruction Group 8-bit data transfer Clocks
Note 1 Note 2
Mnemonic MOV
Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A
Note 3
Bytes 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1
Note 3
Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A (sfr)
Flag Z AC CY
4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8
- 7 7 - - 5 5 5 5 9+n 9+m 7 5 5 5+n 5+m 5+n 5+m 9+n 9+m 7+n 7+m 7+n 7+m - 6 6
Note 3
x x
x x
x x
XCH
A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
1 2 2 3 1 1 2 2 2
10 + n + m A (addr16) 6 + n + m A (DE) 6 + n + m A (HL) 10 + n + m A (HL + byte) 10 + n + m A (HL + B) 10 + n + m A (HL + C)
Notes 1. 2. 3.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruction Group 16-bit data transfer
Mnemonic MOVW
Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX
Note 3
Bytes 3 4 4 2 2 2 2 1 1 3 3
Note 3
Clocks
Note 1 Note 2
Operation rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX
Flag Z AC CY
6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 10 10 8 8 8 8 - -
Note 3
12 + 2n AX (addr16) 12 + 2m (addr16) AX - - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XCHW 8-bit operation ADD
AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
1 2 3
Note 4
2 2 2 3 1 2 2 2 2 3
ADDC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 4
2 2 2 3 1 2 2 2
Notes 1. 2. 3. 4.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Only when rp = BC, DE or HL Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruction Group 8-bit operation
Mnemonic SUB
Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
Bytes 2 3 2 2 2 3 1 2 2 2 2 3
Note 3
Clocks
Note 1 Note 2
Operation A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C)
Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
SUBC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
AND
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. 2. 3.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read.
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Instruction Group 8-bit operation
Mnemonic OR
Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
Bytes 2 3 2 2 2 3 1 2 2 2 2 3
Note 3
Clocks
Note 1 Note 2
Operation A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C)
Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
XOR
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
CMP
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. 2. 3.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read.
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Instruction Group 16-bit operation
Mnemonic ADDW SUBW CMPW
Operands AX, #word AX, #word AX, #word X C r saddr
Bytes 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2
Clocks
Note 1 Note 2
Operation AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time
Flag Z AC CY x x x x x x x x x
- - - - - - 6 - 6 - - - - - -
Multiply/ divide Increment/ decrement
MULU DIVUW INC
x x x x
x x x x
DEC
r saddr
INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjustment Bit manipulate ADJBA ADJBS MOV1
rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL]
x x x x
10 12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 10 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 4 4 6 - 4 - 6 6 - 4 - 6 - - 7 7 - 7 7+n 8 8 - 8 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY x x x x x x x x x x x x x
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY
3 3 2 3 2 3 3 2 3 2
8 + n + m (HL).bit CY
Notes 1. 2.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruction Group Bit manipulate
Mnemonic AND1
Operands CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
Bytes 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2
Clocks
Note 1 Note 2
Operation CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY
Flag Z AC CY x x x x x x x x x x x x x x x
7 7 - 7 7+n 7 7 - 7 7+n 7 7 - 7 7+n 6 8 - 6
OR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
XOR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x
x
x
8 + n + m (HL).bit 1 6 8 - 6 - - -
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x
x
x
8 + n + m (HL).bit 0 1 0 x
SET1 CLR1 NOT1
CY CY CY
Notes 1. 2.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruction Group Call/return
Mnemonic CALL CALLF
Operands !addr16 !addr11
Bytes 3 2 7 5
Clocks
Note 1 Note 2
Operation (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0
Flag Z AC CY
- -
CALLT
[addr5]
1
6
-
BRK
1
6
-
RET RETI
1 1
6 6
- -
RRR
RETB Stack manipulate PUSH PSW rp POP PSW rp MOVW SP, #word SP, AX AX, SP Unconditional BR branch !addr16 $addr16 AX Conditional BC branch BNC BZ BNZ $addr16 $addr16 $addr16 $addr16
1 1 1 1 1 4 2 2 3 2 2 2 2 2 2
6 2 4 2 4 - - - 6 6 8 6 6 6 6
- - - - - 10 8 8 - - - - - - -
RRR
RRR
Notes 1. 2.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program.
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Instruction Group
Mnemonic
Operands saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
Bytes 3 4 3 3 3 4 4 3 4 3 4 4 3 4 3 2 2 3 2 1 2 2 2 2 8 - 8 - 10 10 - 8 - 10 10 - 8 - 10 6 6 8 4 2 - - 6 6
Clocks
Note 1 Note 2
Operation PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit
Flag Z AC CY
Conditional BT branch
9 11 - 9 11 + n 11 11 - 11 11 + n 12 12 - 12
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
BTCLR
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
x
x
x
12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit - - 10 - - 6 6 - - B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode
DBNZ
B, $addr16 C, $addr16 saddr, $addr16
CPU control
SEL NOP EI DI HALT STOP
RBn
Notes 1. 2.
When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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26.3 Instructions Listed by Addressing Type
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 [HL + B] First Operand A [HL + C] 1 None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV MOV XCH XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
INC DEC
B, C sfr saddr MOV MOV
DBNZ
MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV
DBNZ
INC DEC
!addr16 PSW
PUSH POP
[DE] [HL] [HL + byte] [HL + B] [HL + C] X C
MOV MOV MOV ROR4 ROL4
MULU DIVUW
Note Except r = A
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(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX ADDW SUBW CMPW MOVW MOVWNote MOVW XCHW MOVW MOVW MOVW MOVW #word AX rpNote sfrp saddrp !addr16 SP None
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
SET1 CLR1 SET1 CLR1 SET1 CLR1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
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(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16
Compound instruction
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
These specifications are only target values, and may not be satisfied by mass-produced products. The electrical specifications (target values) of (A1) products are under evaluation. Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter Supply voltage Symbol VDD EVDD REGC VSS EVSS AVREF AVSS VPP Input voltage VI1 Conditions Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3
Note 1
Unit V V V V V V V V
Note 1
PD78F0124 Note 2
P00 to P03, P10 to P17, P20 to P27, P30 to P33, P60, P61, P70 to P77, P120, P130, P140, X1, X2, XT1, XT2, RESET P62, P63 N-ch open drain On-chip pull-up resistor
-0.3 to +10.5 -0.3 to VDD + 0.3
V
VI2
-0.3 to +13 -0.3 to VDD + 0.3Note 1 -0.3 to +10.5 -0.3 to VDD + 0.3Note 1 AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3Note 1
Note 1
V V V V V mA mA mA
VI3 Output voltage Analog input voltage Output current, high VO VAN IOH
VPP in flash programming mode (PD78F0124 only)
Per pin Total of all pins -60 mA P00 to P03, P10 to P14, P70 to P77 P15 to P17, P30 to P33, P60 to P63, P120, P130, P140
-10 -30 -30
(Refer to Note on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter Output current, low Symbol IOL Per pin Conditions P00 to P03, P10 to P17, P30 to P33, P70 to P77, P120, P130, P140 P60 to P63 Total of all pins 70 mA P00 to P03, P10 to P14, P70 to P77 P15 to P17, P30 to P33, P60 to P63, P120, P130, P140 Ratings 20 Unit mA
30 35
mA mA
35 -40 to +85 -65 to +150 -40 to +125
mA C C
Operating ambient temperature Storage temperature
TA Tstg
In normal operation mode Mask ROM version
PD78F0124
Notes 1. Must be 6.5 V or lower. 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (15 s if the supply voltage is dropped by the regulator) (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below).
2.7 V 0V a b
VDD
VPP 2.7 V 0V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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X1 Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Resonator Recommended Circuit Ceramic resonator Parameter Oscillation frequency (fXP)Note 1 Conditions When a capacitor is connected to the REGC pinNote 2 When the REGC pin is directly connected to VDD Oscillation frequency (fXP)Note 1 When a capacitor is connected to the REGC pinNote 2 When the REGC pin is directly connected to VDD X1 input frequency (fXP)Note 1 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V X1 input high/low-level width (tXPH, tXPL) 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 3.3 V VDD 5.5 V 2.7 V VDD < 3.3 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 3.3 V VDD 5.5 V 2.7 V VDD < 3.3 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V MIN. 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 46 56 96 TYP. MAX. 8.38 5.0 10 8.38 5.0 8.38 5.0 10 8.38 5.0 10 8.38 5.0 500 500 500 ns MHz MHz MHz MHz Unit MHz
IC (VPP) X1
X2
C1
C2
Crystal resonator
IC (VPP) X1
X2
C1
C2
External clockNote 3
X1
X2
Notes 1. 2. 3.
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. When the REGC pin is connected to VSS via a 0.1 F capacitor. Connect the REGC pin directly to VDD.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the Ring-OSC after reset, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Ring-OSC Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 480 Unit kHz
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz
IC (VPP) XT2 Rd C4
XT1
C3
External clock
XT2
XT1
XT1 input frequency (fXT)Note XT1 input high-/low-level width (tXTH, tXTL)
32 12
38.5 15
kHz
s
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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DC Characteristics (1/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Output current, high Symbol IOH Per pin Total of P00 to P03, P10 to P14, P70 to P77 Total of P15 to P17, P30 to P33, P60 to P63, P120, P130, P140 All pins Output current, low IOL Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V MIN. TYP. MAX. -5 -25 -25 Unit mA mA mA
2.7 V VDD < 4.0 V
-10 10
mA mA
Per pin for P00 to P03, P10 4.0 V VDD 5.5 V to P17, P30 to P33, P70 to P77, P120, P130, P140 Per pin for P60 to P63 Total of P00 to P03, P10 to P14, P70 to P77 Total of P15 to P17, P30 to P33, P60 to P63, P120, P130, P140 All pins 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V
15 30 30
mA mA mA
2.7 V VDD < 4.0 V 0.7VDD 0.8VDD
10 VDD VDD
mA V V
Input voltage, high
VIH1 VIH2
P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, RESET P20 to P27Note P60, P61 P62, P63 X1, X2, XT1, XT2 P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, RESET P20 to P27Note P60, P61 P62, P63 X1, X2, XT1, XT2
VIH3 VIH4 VIH5 VIH6 Input voltage, low VIL1 VIL2
0.7AVREF 0.7VDD 0.7VDD VDD - 0.5 0 0
AVREF VDD 12 VDD 0.3VDD 0.2VDD
V V V V V V
VIL3 VIL4 VIL5 VIL6
0 0 0 0
0.3AVREF 0.3VDD 0.3VDD 0.4
V V V V
Note When used as A/D converter analog input pins, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (2/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Output voltage, high Symbol VOH Conditions Total of P00 to P03, P10 to P14, P70 to P77 IOH = -25 mA Total of P15 to P17, P30 to P33, P60 to P63, P120, P130, P140 IOH = -25 mA IOH = -100 A Output voltage, low VOL1 Total of P00 to P03, P10 to P14, P70 to P77 IOL = 30 mA Total of P15 to P17, P30 to P33, P60 to P63, P120, P130, P140 IOL = 30 mA IOL = 400 A VOL2 Input leakage current, high ILIH1 P60 to P63 VI = VDD MIN. TYP. MAX. Unit V
4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA
V
2.7 V VDD < 4.0 V VDD - 0.5 4.0 V VDD 5.5 V, IOL = 10 mA 4.0 V VDD 5.5 V, IOL = 10 mA 1.3
V V
1.3
V
2.7 V VDD < 4.0 V IOL = 15 mA P00 to P03, P10 to P17, P30 to P33, P60, P61, P70 to P77, P120, P130, P140, RESET P20 to P27 X1, X2, XT1, XT2 P62, P63 (N-ch open drain) P00 to P03, P10 to P17, P20 to P27, P30 to P33, P60, P61, P70 to P77, P120, P130, P140, RESET X1, X2, XT1, XT2 P62, P63 (N-ch open drain)
0.4 2.0 3
V V
A
VI = AVREF ILIH2 ILIH3 Input leakage current, low ILIL1 VI = VDD VI = 12 V VI = 0 V
3 20 3 -3
A A A A
ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value VPP supply voltage (PD78F0124) ILOL RL VPP1 VO = VDD VO = 0 V VI = 0 V
-20 -3
Note
A A A A
k V
3 -3 10 0 30 100 0.2VDD
In normal operation mode
Note If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -45 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (3/4): PD78F0124 (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Supply currentNote 1 Symbol IDD1 X1 crystal oscillation operating modeNote 2 Conditions fXP = 10 MHz When A/D converter is stopped VDD = 5.0 V 10%Notes 3, 7 When A/D converter is operating Note 9 fXP = 8.38 MHz When A/D converter is stopped VDD = 5.0 V 10%Notes 3, 8 When A/D converter is operating Note 9 fXP = 5 MHz VDD = 3.0 V 10%Note 3 IDD2 X1 crystal oscillation HALT mode When A/D converter is stopped When A/D converter is operating
Note 9
MIN. TYP. MAX. Unit 11.5 24.2 12.5 26.3 8.5 9.5 5.5 6.5 1.6 17 19 11 13 3.2 6.4 0.8 1.6 3.8 0.4 0.8 1.6 0.7 0.4 115 95 2.1 1.2 230 190 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
fXP = 10 MHz When peripheral functions are stopped VDD = 5.0 V 10%Notes 3, 7 When peripheral functions are operating fXP = 8.38 MHz When peripheral functions are stopped VDD = 5.0 V 10%Notes 3, 8 When peripheral functions are operating fXP = 5 MHz VDD = 3.0 V 10%Note 3
When peripheral functions are stopped When peripheral functions are operating
IDD3
Ring-OSC operating modeNote 4
VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD4
32.768 kHz VDD = 5.0 V 10% crystal oscillation VDD = 3.0 V 10% operating modeNotes 4, 6 32.768 kHz VDD = 5.0 V 10% crystal oscillation VDD = 3.0 V 10% HALT modeNotes 4, 6 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON POC: ON VDD = 3.0 V 10%
Note 5
A A
IDD5
30 6 0.1 14 3.5
60 18 30 58 35.5
A A A A A A A A A A
IDD6
, RING: OFF , RING: ON
Note 5
17.5 63.5 0.05 7.5 3.5 11 10 25 15.5 30.5
POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON
Note 5
, RING: OFF
POC: ONNote 5, RING: ON
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When main system clock is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped. When the REGC pin is directly connected to VDD. When the REGC pin is connected to VSS via a 0.1 F capacitor. Including the current that flows through the AVREF pin.
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DC Characteristics (4/4): Mask ROM version (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Supply currentNote 1 Symbol IDD1 X1 crystal oscillation operating modeNote 2 Conditions fXP = 10 MHz When A/D converter is stopped VDD = 5.0 V 10%Notes 3, 7 When A/D converter is operatingNote 9 fXP = 8.38 MHz When A/D converter is stopped VDD = 5.0 V 10%Notes 3, 8 When A/D converter is operatingNote 9 fXP = 5 MHz VDD = 3.0 V 10%Note 3 IDD2 X1 crystal oscillation HALT mode When A/D converter is stopped When A/D converter is operating
Note 9
MIN. TYP. MAX. Unit 5.8 6.8 3.8 4.8 1.8 2.8 1.2 13.3 15.5 7.6 9.6 4.2 6.5 2.4 4.8 0.8 1.6 3.8 0.4 0.8 1.6 0.3 0.9 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
fXP = 10 MHz When peripheral functions are stopped VDD = 5.0 V 10%Notes 3, 7 When peripheral functions are operating fXP = 8.38 MHz When peripheral functions are stopped VDD = 5.0 V 10%Notes 3, 8 When peripheral functions are operating fXP = 5 MHz VDD = 3.0 V 10%Note 3
When peripheral functions are stopped When peripheral functions are operating
IDD3
Ring-OSC operating modeNote 4
VDD = 5.0 V 10% VDD = 3.0 V 10%
0.19 0.57 45 25 90 50
IDD4
32.768 kHz VDD = 5.0 V 10% crystal oscillation VDD = 3.0 V 10% operating modeNotes 4, 6 32.768 kHz VDD = 5.0 V 10% crystal oscillation VDD = 3.0 V 10% HALT modeNotes 4, 6 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON POC: ON VDD = 3.0 V 10%
Note 5
A A
IDD5
30 6 0.1 14 3.5
60 18 30 58 35.5
A A A A A A A A A A
IDD6
, RING: OFF , RING: ON
Note 5
17.5 63.5 0.05 7.5 3.5 11 10 25 15.5 30.5
POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON
Note 5
, RING: OFF
POC: ONNote 5, RING: ON
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When main system clock is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped. When the REGC pin is directly connected to VDD. When the REGC pin is connected to VSS via a 0.1 F capacitor. Including the current that flows through the AVREF pin.
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AC Characteristics
(1) Basic operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Main system clock operation X1 input clock Conditions Note 1 MIN. 3.3 V VDD 5.5 V 0.238 2.7 V VDD < 3.3 V Note 2 4.0 V VDD 5.5 V 0.4 0.2 TYP. MAX. 16 16 16 16 16 8.33 122 16.67 125 Unit
s s s s s s s s s
3.3 V VDD < 4.0 V 0.238 2.7 V VDD < 3.3 V Ring-OSC clock Subsystem clock operation TI000, TI010 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V TI50, TI51 input frequency fTI5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V TI50, TI51 input high-level width, tTIH5, low-level width tTIL5 Interrupt input high-level width, low-level width Key return input low-level width tINTH, tINTL tKR 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V RESET low-level width tRST 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 50 100 1 50 100 10 0.4 4.17 114 2/fsam + 0.1Note 3 2/fsam + 0.2Note 3
10 5
MHz
ns ns
s
ns ns
s
Notes 1. 2. 3.
When the REGC pin is connected to VSS via a 0.1 F capacitor. When the REGC pin is directly connected to VDD. Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 or TI010 valid edge as the count clock, fsam = fXP.
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TCY vs. VDD (X1 Input Clock Operation) (a) When REGC pin is connected to VSS via 0.1 F capacitor
20.0 16.0 10.0
Cycle time TCY [ s]
5.0
2.0 1.0
Guaranteed operation range
0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 2.7 3.3 4.0 5.0 5.5 6.0
Supply voltage VDD [V]
(b) When REGC pin is directly connected to VDD
20.0 16.0 10.0
Cycle time TCY [ s]
5.0
2.0 1.0
Guaranteed operation range
0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 2.7 3.3 4.0 5.0 5.5 6.0
Supply voltage VDD [V]
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(2) Serial interface (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps
(b) UART mode (UART0, dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps
(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)
Parameter SCK10 cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V SCK10 high-/low-level width SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tKH1, tKL1 tSIK1 tKSI1 tKSO1 C = 100 pF
Note
MIN. 200 240 400 tKCY1/2-10 30 30
TYP.
MAX.
Unit ns ns ns ns ns ns
30
ns
Note C is the load capacitance of the SCK10 and SO10 output lines. (d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)
Parameter SCK10 cycle time SCK10 high-/low-level width SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 C = 100 pF
Note
Conditions
MIN. 400 tKCY2/2 80 50
TYP.
MAX.
Unit ns ns ns ns
120
ns
Note C is the load capacitance of the SO10 output line.
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AC Timing Test Points (Excluding X1 Input)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test points
Clock Timing
1/fXP tXPL tXPH
X1 input
VIH6 (MIN.) VIL6 (MAX.)
1/fXT tXTL tXTH VIH6 (MIN.) VIL6 (MAX.)
XT1 input
TI Timing
tTIL0 tTIH0
TI00, TI010
1/fTI5 tTIL5 tTIH5
TI50, TI51
Interrupt Request Input Timing
tINTL tINTH
INTP0 to INTP6
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RESET Input Timing
tRSL
RESET
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK10
tSIKm
tKSIm
SI10
Input data
tKSOm
SO10
Output data
Remark m = 1, 2
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A/D Converter Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter Resolution Overall error
Notes 1, 2
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.3
MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0
Unit bit %FSR %FSR
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
Conversion time
tCONV
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
14 17
s s
%FSR %FSR %FSR %FSR LSB LSB LSB LSB V
Zero-scale error
Notes 1, 2
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
Full-scale error
Notes 1, 2
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
Integral non-linearity error
Note 1
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
Differential non-linearity error
Note 1
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V
Analog input voltage
VIAN
AVSS
AVREF
Notes 1. 2.
Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
POC Circuit Characteristics (TA = -40 to +85C)
Parameter Detection voltage Symbol VPOC0 VPOC1 Power supply rise time tPTH Conditions Mask option = 3.5 V Mask option = 2.85 V VDD: 0 V 2.7 V VDD: 0 V 3.3 V Response delay time 1
Note
MIN. 3.3 2.7 0.0015 0.002
TYP. 3.5 2.85
MAX. 3.7 3.0 1500 1800 3.0 1.0
Unit V V ms ms ms ms ms
tPTHD tPD tPW
When power supply rises, after reaching detection voltage (MAX.) When power supply falls, VDD = 1.7 V 0.2
Response delay time 2Note Minimum pulse width
Note Time required from voltage detection to reset release. POC Circuit Timing
Supply voltage (VDD)
Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD
Time
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LVI Circuit Characteristics (TA = -40 to +85C)
Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 Response time
Note 1
Conditions
MIN. 4.1 3.9 3.7 3.5 3.3 3.15 2.95
TYP. 4.3 4.1 3.9 3.7 3.5 3.3 3.1 0.2
MAX. 4.5 4.3 4.1 3.9 3.7 3.45 3.25 2.0
Unit V V V V V V V ms ms
tLD tLW 0.2
Minimum pulse width
Reference voltage stabilization wait tLWAIT0 timeNote 2 Operation stabilization wait time Note 3 tLWAIT1
0.5 0.1
2.0 0.2
ms ms
Notes 1. 2. 3.
Time required from voltage detection to interrupt output or RESET output. Time required from setting LVIE to 1 to reference voltage stabilization when POC = OFF is selected by the POC mask option. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 2. VPOCn < VLVIm (n = 0, 1, m = 0 to 6) LVI Circuit Timing
Supply voltage (VDD)
Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD
LVIE 1 LVION 1
Time
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Release signal set time Symbol VDDDR tSREL Conditions MIN. 1.6 0 TYP. MAX. 5.5 Unit V
s
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Flash Memory Programming Characteristics: PD78F0124 (TA = +10 to +60C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics
Parameter VPP supply voltage VDD supply current VPP supply current Step erase time
Note 1
Symbol VPP2 IDD IPP Ter Tera Twb Cwb Cerwb Twr
Note 6
Conditions During flash memory programming When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP = VPP2
MIN. 9.7
TYP. 10.0
MAX. 10.3 37 100
Unit V mA mA s s/chip ms Times Times
0.199 When step erase time = 0.2 s 49.4 When writeback time = 50 ms
0.2
0.201 20
Overall erase time Writeback time
Note 2
Note 3
50
50.6 60 16
Number of writebacks per 1 writeback commandNote 4 Number of erases/writebacks Step write time
Note 5
48 When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite 48
50
52 520 20
s s
Times
Overall write time per word
Twrw Cerwr
Number of rewrites per chipNote 7
Notes 1. 2. 3. 4. 5. 6. 7.
The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites
Remark The range of the operating clock during flash memory programming is the same as the range during normal operation.
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(2) Serial write operation characteristics
Parameter Set time from VDD to VPP Symbol tDP Conditions MIN. 10 10 2 TYP. MAX. Unit
s s
ms
Release time from VPP to RESET tPR VPP pulse input start time from RESET VPP pulse high-/low-level width VPP pulse input end time from RESET VPP pulse low-level input voltage VPP pulse high-level input voltage tRP
tPW tRPE VPPL VPPH
8 20 0.8VDD 9.7 10.0 1.2VDD 10.3
s
ms V V
Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPPL 0V tPR tRPE VDD RESET (input) 0V tPW tDP tRP tPW
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CHAPTER 28 PACKAGE DRAWING
52-PIN PLASTIC LQFP (10x10)
A B
detail of lead end 39 40 27 26 S P C D T
R 52 1 F J G H I
M
L U
14 13 Q
K M
ITEM A B C MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.1 1.1 0.320.06 0.13 0.65 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.05 0.10 1.4 0.10.05 3 +4 -3 1.50.1 0.25 0.60.15 S52GB-65-8ET-2
N
S
S
D F G H I J K L M N P Q R S T U
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CHAPTER 29 CAUTIONS FOR WAIT
29.1 Cautions for Wait
This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table 29-1). This must be noted when real-time processing is performed.
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CHAPTER 29 CAUTIONS FOR WAIT
29.2 Peripheral Hardware That Generates Wait
Table 29-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 29-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral Hardware Watchdog timer Serial interface UART0 Serial interface UART6 A/D converter WDTM ASIS0 ASIS6 ADM ADS PFM PFT ADCR Register Write Read Read Write Write Write Write Read 1 to 5 clocks (when ADM.5 flag = "1") 1 to 9 clocks (when ADM.5 flag = "0") Access Number of Wait Clocks 3 clocks (fixed) 1 clock (fixed) 1 clock (fixed) 2 to 5 clocksNote (when ADM.5 flag = "1") 2 to 9 clocksNote (when ADM.5 flag = "0")
{(1/fMACRO) x 2/(1/fCPU)} + 1 *The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by (1/fCPU), and is rounded up if it exceeds tCPUL. fMACRO: Macro operating frequency (When bit 5 (FR2) of ADM = "1": fX/2, when bit 5 (FR2) of ADM = "0": fX/22) fCPU: CPU clock frequency tCPUL: Low-level width of CPU clock
Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1. Remarks 1. The clock is the CPU clock (fCPU). 2. When the CPU is operating on the subsystem clock and the X1 input clock is stopped, do not access the registers listed above using an access method in which a wait request is issued.
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29.3 Example of Wait Occurrence
<1> Watchdog timer Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) Number of execution clocks: 10 (7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).) <2> Serial interface UART6 Number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).) <3> A/D converter Table 29-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter) * When fX = 10 MHz, tCPUL = 50 ns
Value of Bit 5 (FR2) of ADM Register 0 fX fX/2 fX/22 fX/23 fX/2 1 fX fX/2 fX/2 fX/2
2 4
fCPU
Number of Wait Clocks 9 clocks 5 clocks 3 clocks 2 clocks 0 clocks (1 clock 5 clocks 3 clocks 2 clocks 0 clocks (1 clock
Note Note
Number of Execution Clocks 14 clocks 10 clocks 8 clocks 7 clocks
)
5 clocks (6 clocksNote) 10 clocks 8 clocks 7 clocks
3
)
5 clocks (6 clocksNote) 5 clocks (6 clocksNote)
fX/24
0 clocks (1 clockNote)
Note On execution of MOV A, ADCR Remark The clock is the CPU clock (fCPU). fX: X1 input clock frequency tCPUL: Low-level width of CPU clock
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0/KD1 Series. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT
TM
compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95, 98, 2000 * Windows NT
TM
Ver 4.0
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration
Language Processing Software * Assembler package * C compiler package * C library source file * Device file
Debugging Tool * System simulator * Integrated debugger * Device file
Embedded Software * Real-time OS
Host Machine (PC)
Interface adapter, PC card interface, etc.
Flash Memory Write Environment In-Circuit Emulator Flash programmer Emulation board Power supply unit Flash memory write adapter Performance board
On-chip flash memory version
Emulation probe
Conversion socket or conversion adapter Target system
Remark The item in the broken-line box differs according to the development environment. Hardware.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0 78K/0 Series software package Development tools (software) common to the 78K/0 Series are combined in this package. Part number: SxxxxSP78K0
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSP78K0
xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM
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A.2 Language Processing Software
RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780124) (sold separately). This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxRA78K0 CC78K0 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an assembler package and device file (both sold separately). This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxCC78K0 DF780124 Device file
Notes 1, 2
This file contains information peculiar to the device. This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780124
CC78K0-L C library source file
Note 3
This is a source file of the functions that configure the object library included in the C compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0-L
Notes 1. 2. 3.
The DF780124 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0. Under development The CC78K0-L is not included in the software package (SP78K0).
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APPENDIX A DEVELOPMENT TOOLS
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxRA78K0 SxxxxCC78K0
xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700 SPARCstationTM
TM
Host Machine PC-9800 series, IBM PC/AT compatibles
OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UXTM (Rel. 10.10) SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.1)
Supply Medium 3.5-inch 2HD FD
CD-ROM
SxxxxDF780124 SxxxxCC78K0-L
xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD
A.3 Flash Memory Writing Tools
Flashpro III (part number: FL-PR3, PG-FP3) Flashpro IV (part number: FL-PR4, PG-FP4) Flash programmer FA-52GB-8ET Flash memory writing adapter Flash programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory writing adapter used connected to the Flashpro III/Flashpro IV. * FA-52GB-8ET: For 52-pin plastic LQFP (GB-8ET type)
Remark FL-PR3, FL-PR4, and FA-52GB-8ET are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
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A.4 Debugging Tools
A.4.1 Hardware
IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. This board is connected to the IE-78K0-NS to expand its functions. Adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. Product that combines the IE-78K0-NS and IE-78K0-NS-PA This adapter is used for supplying power from a 100 V to 240 V AC outlet.
IE-78K0-NS-PA Performance board IE-78K0-NS-A In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-780148-NS-EM1 Emulation board NP-H52GB-TQ Emulation probe
This adapter is required when using a PC-9800 series computer (except notebook type) as the IE-78K0-NS(-A) host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the IE-78K0-NS(-A) host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC/AT compatible computer as the IE-78K0NS(-A) host machine (ISA bus compatible). This adapter is required when using a computer with a PCI bus as the IE-78K0-NS(-A) host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This emulation probe is used to connect the in-circuit emulator and target system, and is designed for a 52-pin plastic LQFP (GB-8ET type). TGB-052SBP This conversion adapter is used to connect the NP-H52GB-TQ and target system board Conversion adapter to which a 52-pin plastic LQFP (GB-8ET type) can be connected.
Remarks 1. NP-H52GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGB-052SBP is a product of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672)
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APPENDIX A DEVELOPMENT TOOLS
A.4.2 Software
SM78K0 System simulator This system simulator is used to perform debugging at C source level or assembler level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an incircuit emulator, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with a device file (DF780124) (sold separately). Part number: SxxxxSM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulator IE-78K0-NS(-A)) This debugger is a control program used to debug 78K/0 Series microcontrollers. It adopts a graphical user interface, which is equivalent visually and operationally to Windows or OSF/MotifTM. It also has an enhanced debugging function for C language programs, and thus trace results can be displayed on screen at C-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. In addition, by incorporating function expansion modules such as a task debugger and system performance analyzer, the efficiency of debugging programs that run on real-time OSs can be improved. It should be used in combination with a device file (sold separately). Part number: SxxxxID78K0-NS
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSM78K0 SxxxxID78K0-NS
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD
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APPENDIX B EMBEDDED SOFTWARE
The following embedded products are available for efficient development and maintenance of the 78K0/KD1 Series.
Real-Time OS
RX78K0 Real-time OS The RX78K0 is a real-time OS conforming to the ITRON specifications. A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780124) (both sold separately). The real-time OS is a DOS-based application. It should be used in the DOS prompt when using it in Windows. Part number: SxxxxRX78013-
Caution To purchase the RX78K0, first fill in the purchase application form and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxRX78013-
001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Object source program for mass production
xxxx AA13 AB13 BB13 3P16 3K13 3K15
Host Machine PC-9800 series IBM PC/AT compatibles
OS Windows (Japanese version)
Note
Supply Medium 3.5-inch 2HD FD 3.5-inch 2HD FD
Windows (Japanese version)Note Windows (English version)
Note
HP9000 series 700 SPARCstation
HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1)
DAT 3.5-inch 2HD FD 1/4-inch CGMT
Note Can also be operated in DOS environment.
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APPENDIX C REGISTER INDEX
C.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A] A/D conversion result register (ADCR)....................................................................................................................... 226 A/D converter mode register (ADM) ........................................................................................................................... 228 Analog input channel specification register (ADS) ..................................................................................................... 230 Asynchronous serial interface control register 6 (ASICL6)..................................................................................281, 288 Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................249, 253, 254 Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................275, 283, 284 Asynchronous serial interface reception error status register 0 (ASIS0) .............................................................251, 256 Asynchronous serial interface reception error status register 6 (ASIS6) .............................................................277, 286 Asynchronous serial interface transmission status register 6 (ASIF6) ................................................................278, 287 [B] Baud rate generator control register 0 (BRGC0) .................................................................................................252, 263 Baud rate generator control register 6 (BRGC6) .................................................................................................280, 305 [C] Capture/compare control register 00 (CRC00)........................................................................................................... 135 Clock monitor mode register (CLM) ........................................................................................................................... 361 Clock output selection register (CKS) ........................................................................................................................ 220 Clock selection register 6 (CKSR6).....................................................................................................................279, 304 [E] 8-bit timer compare register 50 (CR50)...................................................................................................................... 164 8-bit timer compare register 51 (CR51)...................................................................................................................... 164 8-bit timer counter 50 (TM50)..................................................................................................................................... 164 8-bit timer counter 51 (TM51)..................................................................................................................................... 164 8-bit timer H carrier control register 1 (TMCYC1)....................................................................................................... 185 8-bit timer H compare register 00 (CMP00) ............................................................................................................... 181 8-bit timer H compare register 01 (CMP01) ............................................................................................................... 181 8-bit timer H compare register 10 (CMP10) ............................................................................................................... 181 8-bit timer H compare register 11 (CMP11) ............................................................................................................... 181 8-bit timer H mode register 0 (TMHMD0) ................................................................................................................... 182 8-bit timer H mode register 1 (TMHMD1) ................................................................................................................... 182 8-bit timer mode control register 50 (TMC50) ............................................................................................................ 167 8-bit timer mode control register 51 (TMC51) ............................................................................................................ 167 External interrupt falling edge enable register (EGN)................................................................................................. 332 External interrupt rising edge enable register (EGP).................................................................................................. 332 [I] Input switch control register (ISC) .............................................................................................................................. 101 Internal memory size switching register (IMS)............................................................................................................ 385 Interrupt mask flag register 0H (MK0H)...................................................................................................................... 330 Interrupt mask flag register 0L (MK0L)....................................................................................................................... 330
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APPENDIX C REGISTER INDEX
Interrupt mask flag register 1L (MK1L)........................................................................................................................330 Interrupt request flag register 0H (IF0H) .....................................................................................................................329 Interrupt request flag register 0L (IF0L) ......................................................................................................................329 Interrupt request flag register 1L (IF1L) ......................................................................................................................329 [K] Key return mode register (KRM) .................................................................................................................................342 [L] Low-voltage detection level selection register (LVIS)..................................................................................................373 Low-voltage detection register (LVIM) ........................................................................................................................372 [M] Main clock mode register (MCM) ................................................................................................................................108 Main OSC control register (MOC) ...............................................................................................................................109 [O] Oscillation stabilization time counter status register (OSTC) ..............................................................................110, 345 Oscillation stabilization time select register (OSTS)............................................................................................111, 346 [P] Port 0 (P0) ....................................................................................................................................................................81 Port 1 (P1) ....................................................................................................................................................................84 Port 12 (P12) ................................................................................................................................................................95 Port 13 (P13) ................................................................................................................................................................96 Port 14 (P14) ................................................................................................................................................................97 Port 2 (P2) ....................................................................................................................................................................90 Port 3 (P3) ....................................................................................................................................................................91 Port 6 (P6) ....................................................................................................................................................................93 Port 7 (P7) ....................................................................................................................................................................94 Port mode register 0 (PM0)...................................................................................................................................98, 138 Port mode register 1 (PM1)...................................................................................................................................98, 170 Port mode register 12 (PM12).......................................................................................................................................98 Port mode register 14 (PM14)...............................................................................................................................98, 222 Port mode register 3 (PM3)...................................................................................................................................98, 170 Port mode register 6 (PM6)...........................................................................................................................................98 Port mode register 7 (PM7)...........................................................................................................................................98 Power-fail comparison mode register (PFM)...............................................................................................................231 Power-fail comparison threshold register (PFT)..........................................................................................................231 Prescaler mode register 00 (PRM00)..........................................................................................................................137 Priority specification flag register 0H (PR0H)..............................................................................................................331 Priority specification flag register 0L (PR0L) ...............................................................................................................331 Priority specification flag register 1L (PR1L) ...............................................................................................................331 Processor clock control register (PCC) .......................................................................................................................105 Pull-up resistor option register 0 (PU0) .......................................................................................................................100 Pull-up resistor option register 1 (PU1) .......................................................................................................................100 Pull-up resistor option register 12 (PU12) ...................................................................................................................100 Pull-up resistor option register 14 (PU14) ...................................................................................................................100
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APPENDIX C REGISTER INDEX
Pull-up resistor option register 3 (PU3) ...................................................................................................................... 100 Pull-up resistor option register 7 (PU7) ...................................................................................................................... 100 [R] Receive buffer register 0 (RXB0) ............................................................................................................................... 248 Receive buffer register 6 (RXB6) ............................................................................................................................... 274 Reset control flag register (RESF) ............................................................................................................................. 359 Ring-OSC mode register (RCM) ................................................................................................................................ 107 [S] Serial clock selection register 10 (CSIC10).........................................................................................................314, 317 Serial I/O shift register 10 (SIO10) ............................................................................................................................. 312 Serial operation mode register 10 (CSIM10)...............................................................................................313, 315, 316 16-bit timer capture/compare register 000 (CR000) ................................................................................................... 131 16-bit timer capture/compare register 010 (CR010) ................................................................................................... 132 16-bit timer counter 00 (TM00)................................................................................................................................... 131 16-bit timer mode control register 00 (TMC00)........................................................................................................... 133 16-bit timer output control register 00 (TOC00).......................................................................................................... 135 [T] Timer clock selection register 50 (TCL50).................................................................................................................. 165 Timer clock selection register 51 (TCL51).................................................................................................................. 165 Transmit buffer register 10 (SOTB10) ........................................................................................................................ 312 Transmit buffer register 6 (TXB6)............................................................................................................................... 274 Transmit shift register 0 (TXS0) ................................................................................................................................. 248 [W] Watch timer operation mode register (WTM) ............................................................................................................. 204 Watchdog timer enable register (WDTE) ................................................................................................................... 213 Watchdog timer mode register (WDTM)..................................................................................................................... 212
440
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APPENDIX C REGISTER INDEX
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A] ADCR: ADM: ADS: ASICL6: ASIF6: ASIM0: ASIM6: ASIS0: ASIS6: [B] BRGC0: BRGC6: [C] CKS: CKSR6: CLM: CMP00: CMP01: CMP10: CMP11: CR000: CR010: CR50: CR51: CRC00: CSIC10: CSIM10: [E] EGN: EGP: [I] IF0H: IF0L: IF1L: IMS: ISC: [K] KRM: [L] LVIM: Low-voltage detection register ................................................................................................................372
Preliminary User's Manual U16315EJ1V0UD
A/D conversion result register .................................................................................................................226 A/D converter mode register ...................................................................................................................228 Analog input channel specification register .............................................................................................230 Asynchronous serial interface control register 6..............................................................................281, 288 Asynchronous serial interface transmission status register 6..........................................................278, 287 Asynchronous serial interface operation mode register 0 .......................................................249, 253, 254 Asynchronous serial interface operation mode register 6 .......................................................275, 283, 284 Asynchronous serial interface reception error status register 0.......................................................251, 256 Asynchronous serial interface reception error status register 6.......................................................277, 286
Baud rate generator control register 0.............................................................................................252, 263 Baud rate generator control register 6.............................................................................................280, 305
Clock output selection register ................................................................................................................220 Clock selection register 6 ................................................................................................................279, 304 Clock monitor mode register ...................................................................................................................361 8-bit timer H compare register 00............................................................................................................181 8-bit timer H compare register 01............................................................................................................181 8-bit timer H compare register 10............................................................................................................181 8-bit timer H compare register 11............................................................................................................181 16-bit timer capture/compare register 000 ..............................................................................................131 16-bit timer capture/compare register 010 ..............................................................................................132 8-bit timer compare register 50 ...............................................................................................................164 8-bit timer compare register 51 ...............................................................................................................164 Capture/compare control register 00.......................................................................................................135 Serial clock selection register 10.....................................................................................................314, 317 Serial operation mode register 10 ...........................................................................................313, 315, 316
External interrupt falling edge enable register .........................................................................................332 External interrupt rising edge enable register..........................................................................................332
Interrupt request flag register 0H.............................................................................................................329 Interrupt request flag register 0L .............................................................................................................329 Interrupt request flag register 1L .............................................................................................................329 Internal memory size switching register ..................................................................................................385 Input switch control register.....................................................................................................................101
Key return mode register.........................................................................................................................342
441
APPENDIX C REGISTER INDEX
LVIS: [M] MCM: MK0H: MK0L: MK1L: MOC: [O] OSTC: OSTS: [P] P0: P1: P12: P13: P14: P2: P3: P6: P7: PCC: PFM: PFT: PM0: PM1: PM12: PM14: PM3: PM6: PM7: PR0H: PR0L: PR1L: PRM00: PU0: PU1: PU12: PU14: PU3: PU7: [R] RCM: RESF: RXB0:
Low-voltage detection level selection register ........................................................................................ 373
Main clock mode register........................................................................................................................ 108 Interrupt mask flag register 0H ............................................................................................................... 330 Interrupt mask flag register 0L................................................................................................................ 330 Interrupt mask flag register 1L................................................................................................................ 330 Main OSC control register ...................................................................................................................... 109
Oscillation stabilization time counter status register ........................................................................110, 345 Oscillation stabilization time select register .....................................................................................111, 346
Port 0........................................................................................................................................................ 81 Port 1........................................................................................................................................................ 84 Port 12...................................................................................................................................................... 95 Port 13...................................................................................................................................................... 96 Port 14...................................................................................................................................................... 97 Port 2........................................................................................................................................................ 90 Port 3........................................................................................................................................................ 91 Port 6........................................................................................................................................................ 93 Port 7........................................................................................................................................................ 94 Processor clock control register ............................................................................................................. 105 Power-fail comparison mode register ..................................................................................................... 231 Power-fail comparison threshold register ............................................................................................... 231 Port mode register 0 ..........................................................................................................................98, 138 Port mode register 1 ..........................................................................................................................98, 170 Port mode register 12 ............................................................................................................................... 98 Port mode register 14 ........................................................................................................................98, 222 Port mode register 3 ..........................................................................................................................98, 170 Port mode register 6 ................................................................................................................................. 98 Port mode register 7 ................................................................................................................................. 98 Priority specification flag register 0H ...................................................................................................... 331 Priority specification flag register 0L....................................................................................................... 331 Priority specification flag register 1L....................................................................................................... 331 Prescaler mode register 00 .................................................................................................................... 137 Pull-up resistor option register 0............................................................................................................. 100 Pull-up resistor option register 1............................................................................................................. 100 Pull-up resistor option register 12........................................................................................................... 100 Pull-up resistor option register 14........................................................................................................... 100 Pull-up resistor option register 3............................................................................................................. 100 Pull-up resistor option register 7............................................................................................................. 100
Ring-OSC mode register ........................................................................................................................ 107 Reset control flag register....................................................................................................................... 359 Receive buffer register 0 ........................................................................................................................ 248
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APPENDIX C REGISTER INDEX
RXB6: [S] SIO10: SOTB10: [T] TCL50: TCL51: TM00: TM50: TM51: TMC00: TMC50: TMC51: TMCYC1:
Receive buffer register 6 .........................................................................................................................274
Serial I/O shift register 10........................................................................................................................312 Transmit buffer register 10 ......................................................................................................................312
Timer clock selection register 50.............................................................................................................165 Timer clock selection register 51.............................................................................................................165 16-bit timer counter 00 ............................................................................................................................131 8-bit timer counter 50 ..............................................................................................................................164 8-bit timer counter 51 ..............................................................................................................................164 16-bit timer mode control register 00.......................................................................................................133 8-bit timer mode control register 50.........................................................................................................167 8-bit timer mode control register 51.........................................................................................................167 8-bit timer H carrier control register 1......................................................................................................185
TMHMD0: 8-bit timer H mode register 0...................................................................................................................182 TMHMD1: 8-bit timer H mode register 1...................................................................................................................182 TOC00: TXB6: TXS0: [W] WDTE: WDTM: WTM: Watchdog timer enable register ..............................................................................................................213 Watchdog timer mode register ................................................................................................................212 Watch timer operation mode register ......................................................................................................204 16-bit timer output control register 00......................................................................................................135 Transmit buffer register 6 ........................................................................................................................274 Transmit shift register 0...........................................................................................................................248
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[MEMO]
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