View M58LT256JSB_578587.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58LT256JST M58LT256JSB
256 Mbit (16 Mb x 16, multiple bank, multilevel, burst) 1.8 V supply, secure Flash memories
Features
Supply voltage - VDD = 1.7 V to 2.0 V for program, erase and read - VDDQ = 2.7 V to 3.6 V for I/O Buffers - VPP = 9 V for fast program Synchronous / Asynchronous Read - Synchronous Burst Read mode: 52 MHz - Random access: 85 ns - Asynchronous Page Read mode Synchronous Burst Read Suspend Programming time - 5 s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank memory array: 16 Mbit banks - Parameter Blocks (top or bottom location) Dual operations - program/erase in one Bank while read in others - No delay between read and write operations Block protection - All blocks protected at Power-up - Any combination of blocks can be protected with zero latency - Absolute Write Protection with VPP = VSS Security - Software security features - 64 bit unique device number - 2112 bit user programmable OTP Cells Common Flash Interface (CFI) 100 000 program/erase cycles per block

BGA
TBGA64 (ZA) 10 x 13 mm

Electronic signature - Manufacturer Code: 20h - Top Device Codes: M58LT256JST: 885Eh - Bottom Device Codes M58LT256JSB: 885Fh TBGA64 package - ECOPACK(R) compliant

June 2007
Rev 2
1/106
www.st.com 1
Contents
M58LT256JST, M58LT256JSB
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Address inputs (A0-A23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 4.4 4.5 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
4.6 4.7 4.8 4.9 4.10
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 The Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 24
4.10.1 4.10.2 4.10.3 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11 4.12 4.13 4.14 4.15 4.16
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Protect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Unprotect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Program/Erase Controller Status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . 33 Erase Suspend Status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase/Blank Check Status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program Status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VPP Status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Block Protection Status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bank Write/Multiple Word Program Status bit (SR0) . . . . . . . . . . . . . . . . 35
6
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Contents
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6.9
Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1 7.2 7.3 Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 9
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 46 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1 9.2 9.3 9.4 Reading a block's protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Protected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Unprotected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Protection operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . 49
10 11 12 13 14
Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 50 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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M58LT256JST, M58LT256JSB
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X-Latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Program/Erase times and endurance cycles, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Asynchronous Read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Synchronous Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write ac characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reset and Power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 M58LT256JST - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 M58LT256JST - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M58LT256JST - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M58LT256JSB - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 M58LT256JSB - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 M58LT256JSB - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Bank and Erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Bank and Erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Bank and Erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Command Interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . . 99 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of tables Table 48. Table 49.
M58LT256JST, M58LT256JSB
Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 103 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TBGA64 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Asynchronous Random Access Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Asynchronous Page Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Synchronous Burst Read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Single Synchronous Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous Burst Read Suspend ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Clock input ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Reset and Power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Blank Check flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Buffer Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 90 Block Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Protect/Unprotect operation flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Protection Register Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Buffer Enhanced Factory Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 95
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Description
M58LT256JST, M58LT256JSB
1
Description
The M58LT256JST/B are 256 Mbit (16 Mbit x 16) non-volatile Secure Flash memories. They may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 2.7 V to 3.6 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The devices feature an asymmetrical block architecture. The M58LT256JST/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 16 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 15 main blocks of 64 kwords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3. The Parameter Blocks are located at the top of the memory address space for the M58LT256JST, and at the bottom for the M58LT256JSB. Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory programming command available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at Power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT256JST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at Power-up. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 64 bit segment One-
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M58LT256JST, M58LT256JSB
Description
Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register Memory map. The M58LT256JST/B also has a full set of Software security features that are not described in this datasheet, but are documented in a dedicated Application Note. For further information please contact STMicroelectronics. The M58LT256JST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package. They are supplied with all the bits erased (set to '1'). Figure 1. Logic diagram
VDD VDDQ VPP 16 A0-A23 W E G RP L K M58LT256JST M58LT256JSB WAIT DQ0-DQ15
VSS
VSSQ
AI13299
Table 1.
Signal names
Function Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable Reset Clock Latch Enable Wait Supply voltage Supply voltage for input/output buffers Optional supply voltage for Fast Program & Erase Ground Ground input/output supply Not connected internally Do not use Inputs I/O Input Input Input Input Input Input Output Direction
Signal name A0-A23 DQ0-DQ15 E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU
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Description Figure 2.
M58LT256JST, M58LT256JSB TBGA64 package connections (top view through package)
1 2 3 4 5 6 7 8
A
A0
A5
A7
VPP
A12
VDD
A17
A21
B
A1
VSS
A8
E
A13
NC
A18
WAIT
C
A2
A6
A9
A11
A14
NC
A19
A20
D
A3
A4
A10
RP
NC
NC
A15
A16
E
DQ8
DQ1
DQ9
DQ3
DQ4
NC
DQ15
NC
F
K
DQ0
DQ10
DQ11
DQ12
NC
NC
G
G
A22
NC
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
L
NC
VDD
VSSQ
DQ13
VSS
DQ7
A23
AI13414
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M58LT256JST, M58LT256JSB Table 2. Bank architecture
Bank size 16 Mbits 16 Mbits 16 Mbits 16 Mbits ---Parameter blocks 4 blocks of 16 kwords ----
Description
Number Parameter Bank Bank 1 Bank 2 Bank 3 ----
Main blocks 15 blocks of 64 kwords 16 blocks of 64 kwords 16 blocks of 64 kwords 16 blocks of 64 kwords ---16 blocks of 64 kwords 16 blocks of 64 kwords
Bank 14 Bank 15
16 Mbits 16 Mbits
-
Figure 3.
Memory map
M58LT256JST - Top Boot Block Address lines A0-A23 000000h 00FFFFh 64 Kword 16 Main Blocks 64 Kword Parameter Bank M58LT256JSB - Bottom Boot Block Address lines A0-A23 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 0F0000h 0FFFFFh 100000h 10FFFFh Bank 1 1F0000h 1FFFFFh 200000h 20FFFFh Bank 2 2F0000h 2FFFFFh 300000h 30FFFFh Bank 3 3F0000h 3FFFFFh 15 Main Blocks 64 Kword 16 Kword 4 Parameter Blocks Bank 15 16 Kword F00000h F0FFFFh FF0000h FFFFFFh 64 Kword 16 Main Blocks 64 Kword 64 Kword 64 Kword 64 Kword 16 Main Blocks 64 Kword 64 Kword 16 Main Blocks 16 Kword 4 Parameter Blocks 16 Kword 64 Kword 15 Main Blocks 64 Kword 64 Kword 16 Main Blocks
Bank 15 0F0000h 0FFFFFh
C00000h C0FFFFh Bank 3 CF0000h CFFFFFh D00000h D0FFFFh Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Bank 1 EF0000h EFFFFFh F00000h F0FFFFh FE0000h FEFFFFh FF0000h FF3FFFh FFC000h FFFFFFh
64 Kword 16 Main Blocks 64 Kword 64 Kword 16 Main Blocks 64 Kword 64 Kword 16 Main Blocks 64 Kword 64 Kword
Parameter Bank
AI13403b
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Signal descriptions
M58LT256JST, M58LT256JSB
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address inputs (A0-A23)
The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.2
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.6
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply current IDD2. Refer to Table 20: DC characteristics - currents, for the value of IDD2. After Reset all blocks are in the Protected state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
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M58LT256JST, M58LT256JSB
Signal descriptions
2.7
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.8
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.9
Wait (WAIT)
Wait is an output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
2.10
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).
2.11
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD.
2.12
VPP Program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
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Signal descriptions
M58LT256JST, M58LT256JSB
2.13
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.14
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
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M58LT256JST, M58LT256JSB
Bus operations
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 9, 10 and 11 Read ac waveforms, and Tables 22 and 23 Read ac characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 15 and 16, Write ac waveforms, and Tables 24 and 25, Write ac characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
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Bus operations
M58LT256JST, M58LT256JSB
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus operations(1)
E VIL VIL VIL VIL VIH X G VIL VIH X VIH X X W VIH VIL VIH VIH X X L VIL(3) VIL(3) VIL X X X RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z Hi-Z WAIT(2) DQ15-DQ0 Data output Data input Data output or Hi-Z(4) Hi-Z Hi-Z Hi-Z
Operation Bus Read Bus Write Address Latch Output Disable Standby Reset
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command. 3. L can be tied to VIH if the valid address has been previously latched. 4. Depends on G.
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M58LT256JST, M58LT256JSB
Command interface
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 4: Command codes, Table 5: Standard commands, Table 6: Factory commands, and Appendix D: Command interface state tables, for a summary of the Command Interface. Table 4. Command codes
Command Block Protect Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Program Setup Clear Status Register Block Protect Setup, Block Unprotect Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Blank Check Setup Protection Register Program Blank Check Confirm Program/Erase Resume, Block Erase Confirm, Block Unprotect Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm Buffer Program Read Array
Hex code 01h 03h 10h 20h 40h 50h 60h 70h 80h 90h 98h B0h BCh C0h CBh D0h E8h FFh
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Command interface
M58LT256JST, M58LT256JSB
4.1
Read Array command
The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank will return to Read Array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent read operations will output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9 for the description of the Status Register bits.
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M58LT256JST, M58LT256JSB
Command interface
4.3
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer and Device codes, the Protection Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer code, the Device code, the Protection Status of the addressed bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 15: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual operation limitations for details). See Appendix B: Common Flash Interface, Tables 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44 for details on the information contained in the Common Flash Interface memory area.
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Command interface
M58LT256JST, M58LT256JSB
4.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.
4.6
Block Erase command
The Block Erase command is used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command.

The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 16: Program/Erase times and endurance cycles,. See Appendix C, Figure 23: Block Erase flowchart and pseudocode, for a suggested flowchart for using the Block Erase command.
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M58LT256JST, M58LT256JSB
Command interface
4.7
The Blank Check command
The Blank Check command is used to check whether a Main Array Block has been completely erased. Only one Block at a time can be checked. To use the Blank Check command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command:

The first bus cycle writes the Blank Check command (BCh) to any address in the Block to be checked. The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the Block to be checked and starts the Blank Check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during Blank Check is Read Status Register. Dual Operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend. The SR7 Status Register bit indicates the status of the Blank Check operation in progress: SR7 = '0' means that the Blank Check operation is still ongoing. SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the Blank Check operation has failed. At the end of the operation the bank remains in the Read Status Register mode until another command is written to the Command Interface. See Appendix C, Figure 20: Blank Check flowchart and pseudocode, for a suggested flowchart for using the Blank Check command. Typical Blank Check times are given in Table 16: Program/Erase times and endurance cycles,.
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Command interface
M58LT256JST, M58LT256JSB
4.8
Program command
The program command is used to program a single word to the memory array. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the Program command.

The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the word being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 16: Program/Erase times and endurance cycles,. The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 19: Program flowchart and pseudocode, for the flowchart for using the Program command.
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M58LT256JST, M58LT256JSB
Command interface
4.9
Buffer Program command
The Buffer Program command makes use of the device's 32-word Write Buffer to speed up programming. Up to 32 words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard nonbuffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block.
After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. Use n+1 Bus Write cycles to load the address and data for each word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32 word boundary. The final Bus Write cycle confirms the Buffer Program command and starts the program operation.
3.
4.
All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 21: Buffer Program flowchart and pseudocode, for a suggested flowchart on using the Buffer Program command.
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Command interface
M58LT256JST, M58LT256JSB
4.10
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The use of the Buffer Enhanced Factory Program command requires certain operating conditions:

VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30 C 10 C The targeted block must be unprotected The start address must be aligned with the start of a 32 word buffer boundary The address must remain the Start Address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program command consists of three phases: the Setup phase, the Program and Verify phase, and the Exit phase. Please refer to Table 6: Factory commands for detail information.
4.10.1
Setup phase
The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command.

The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error.
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M58LT256JST, M58LT256JSB
Command interface
4.10.2
Program and Verify phase
The Program and Verify phase requires 32 cycles to program the 32 words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next word. Each subsequent word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next word. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary.
2.
3.
The Program and Verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase.
Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.
4.10.3
Exit Phase
Status Register P/E.C. bit SR7 set to `1' indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 16. See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudocode, for a suggested flowchart on using the Buffer Enhanced Factory Program command.
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Command interface
M58LT256JST, M58LT256JSB
4.11
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The following commands are accepted during Program/Erase Suspend: - - - - - Program/Erase Resume Read Array (data from erase-suspended block or program-suspended word is not valid) Read Status Register Read Electronic Signature Read CFI query
Additionally, if the suspended operation was a Block Erase then the following commands are also accepted: - - - - - Clear Status Register Program (except in erase-suspended block) Buffer Program (except in erase suspended blocks) Block Protect Block Unprotect
During an erase suspend the block being erased can be protected by issuing the Block Protect command. When the Program/Erase Resume command is issued the operation will complete. It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. Refer to Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudocode, and Figure 24: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Suspend command.
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M58LT256JST, M58LT256JSB
Command interface
4.12
Program/Erase Resume command
The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudocode, and Figure 24: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Resume command.
4.13
Protection Register Program command
The Protection Register Program command is used to program the user One-TimeProgrammable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one word at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two Bus Write cycles are required to issue the Protection Register Program command.

The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 15: Dual operation limitations for details) The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map, and Table 8: Protection Register locks, for details on the Lock bits. See Appendix C, Figure 26: Protection Register Program flowchart and pseudocode, for a flowchart for using the Protection Register Program command.
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Command interface
M58LT256JST, M58LT256JSB
4.14
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command.

The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles, that is A0 = CR0, A1 = CR1, ..., A15 = CR15. Addresses A16-A23 are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register.
4.15
Block Protect command
The Block Protect command is used to protect a block and prevent program or erase operations from changing the data in it. All blocks are protected after power-up or reset. Two Bus Write cycles are required to issue the Block Protect command.

The first bus cycle sets up the Block Protect command. The second Bus Write cycle latches the block address and protects the block.
Once the command has been issued subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection, for a detailed explanation. See Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudocode, for a flowchart for using the Block Protect command.
4.16
Block Unprotect command
The Block Unprotect command is used to unprotect a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unprotect command.

The first bus cycle sets up the Block Unprotect command. The second Bus Write cycle latches the block address and unprotects the block.
Once the command has been issued subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection, for a detailed explanation and Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudocode, for a flowchart for using the Block Unprotect command.
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M58LT256JST, M58LT256JSB Table 5. Standard commands(1)
Bus operations Cycles Commands 1st cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 Write Write Write Write Write Write Write Write Buffer Program(4) n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Protect Block Unprotect 1 1 2 2 2 2 Write Write Write Write Write Write Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BA(3) Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h Op.
Command interface
2nd cycle Add WA BKA(2) BKA
(2)
Data RD SRD ESD QD
Read Read Read Read
BKA(2)
Write Write Write Write Write
BA WA BA PA2 X
D0h PD n PD2 D0h
Write Write Write Write
PRA CRD BA BA
PRD 03h 01h D0h
1. X = Don't Care, WA = Word Address in targeted bank, RD =Read Data, SRD =Status Register Data, ESD = Electronic Signature Data, QD =Query Data, BA =Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7. 3. Any address within the bank can be used. 4. n+1 is the number of words to be programmed.
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Command interface Table 6. Factory commands
M58LT256JST, M58LT256JSB
Bus Write operations(1) Command Phase Cycles 1st Add Blank Check Setup 2 2 BA BKA or WA(2) WA1 NOT BA1(4) 2nd 3rd Final -1 Add Data Final Add Data
Data Add Data Add Data BCh 80h PD1 X BA WA1 WA1 CBh D0h PD2 WA1 PD3
Buffer Enhanced Program/ 32 Factory Verify(3) Program Exit 1
WA1 PD31 WA1 PD32
1. WA = Word Address in targeted bank, BKA = Bank Address, PD =Program Data, BA = Block Address, X = Don't Care. 2. Any address within the bank can be used. 3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
Table 7.
Electronic signature codes
Code Address (h) Bank Address + 000 Top Bank Address + 001 Bank Address + 001 Block Address + 002 Unprotected 0000 Bank Address + 005 ST Factory Default CR(1) 0002 Bank Address + 080 0000 Bank Address + 081 Bank Address + 084 Unique Device Number OTP Area PRLD(1) OTP Area Data (h) 0020 885E (M58LT256JST) 885F (M58LT256JSB) 0001
Manufacturer code Device code Bottom Protected Block Protection Configuration Register Protection Register PR0 Lock
OTP Area Permanently Protected
Protection Register PR0 Bank Address + 085 Bank Address + 088 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16 Bank Address + 089 Bank Address + 08A Bank Address + 109
1. CR = Configuration Register, PRLD = Protection Register Lock Data.
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M58LT256JST, M58LT256JSB Figure 4. Protection Register memory map
PROTECTION REGISTERS
Command interface
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah Protection Register Lock 89h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
88h 85h 84h
PR0 User Programmable OTP
Unique device number 81h 80h Protection Register Lock 10
AI07563
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Command interface Table 8. Protection Register locks
Lock
M58LT256JST, M58LT256JSB
Description Number Address Bits Bit 0 Lock 1 80h Bit 1 pre-programmed to protect Unique Device Number, address 81h to 84h in PR0 protects 64 bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 reserved Bit 0 Bit 1 Bit 2 ---Lock 2 89h protects 128 bits of OTP segment PR1 protects 128 bits of OTP segment PR2 protects 128 bits of OTP segment PR3 ---protects 128 bits of OTP segment PR14 protects 128 bits of OTP segment PR15 protects 128 bits of OTP segment PR16
Bit 13 Bit 14 Bit 15
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M58LT256JST, M58LT256JSB
Status Register
5
Status Register
The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank always read the Status Register during program and erase operations if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the following text descriptions.
5.1
Program/Erase Controller Status bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.
5.2
Erase Suspend Status bit (SR6)
The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
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Status Register
M58LT256JST, M58LT256JSB
5.3
Erase/Blank Check Status bit (SR5)
The Erase/Blank Check Status bit is used to identify if there was an error during a Block Erase operation. When the Erase/Blank Check Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase/Blank Check Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). The Erase/Blank Check Status bit is also used to indicate whether an error occurred during the Blank Check operation: if the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the Erase/Blank Check Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail.
5.4
Program Status bit (SR4)
The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail.
5.5
VPP Status bit (SR3)
The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. When the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
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M58LT256JST, M58LT256JSB
Status Register
5.6
Program Suspend Status bit (SR2)
The Program Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
5.7
Block Protection Status bit (SR1)
The Block Protection Status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is High (set to `1'), a program or erase operation has been attempted on a protected block. Once set High, the Block Protection Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
5.8
Bank Write/Multiple Word Program Status bit (SR0)
The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next word. For further details on how to use the Status Register, see the flowcharts and pseudocodes provided in Appendix C.
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Status Register Table 9.
Bit
M58LT256JST, M58LT256JSB Status Register bits
Name Type Logic level(1) '1' Ready Busy Erase Suspended Erase In progress or Completed Erase/Blank Check Error Erase/Blank Check Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Bank Write Status Status SR7 = `1' '0' SR7 = `0' Program or erase operation in addressed bank Program or erase operation in a bank other than the addressed bank No program or erase operation in the device Definition
SR7 P/E.C. Status Erase Suspend Status Erase/Blank Check Status
Status '0' '1' Status '0' '1' Error '0' '1' Error '0' '1'
SR6
SR5
SR4 Program Status
SR3 VPP Status Program Suspend Status Block Protection Status
Error '0' '1' Status '0' '1' Error '0'
SR2
SR1
SR0 SR7 = `1' Not Allowed Multiple Word Program Status (Buffer Enhanced Factory Program mode) '1' Status '0' SR7 = `0'
1. Logic level '1' is High, '0' is Low.
the device is NOT ready for the next SR7 = `0' Buffer loading or is going to exit the BEFP mode SR7 = `1' the device has exited the BEFP mode the device is ready for the next Buffer loading
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M58LT256JST, M58LT256JSB
Configuration Register
6
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 11 They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1
Read Select bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to '1' for asynchronous access.
6.2
X-Latency bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 5: X-Latency and data output configuration example. For correct operation the X-Latency bits can only assume the values in Table 11: Configuration Register. Table 10 shows how to set the X-Latency parameter, taking into account the speed class of the device and the Frequency used to read the Flash memory in Synchronous mode. Table 10. X-Latency settings
fmax 30 MHz 40 MHz 52 MHz tKmin 33 ns 25 ns 19 ns X-Latency min 3 4 5
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Configuration Register
M58LT256JST, M58LT256JSB
6.3
Wait Polarity bit (CR10)
The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High.
6.4
Data Output Configuration bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When the Data Output Configuration bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration bit is '1' the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition:
tK > tKQV + tQVK_CPU tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time.
where

If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 5: X-Latency and data output configuration example.
6.5
Wait Configuration bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid. When the Wait Configuration bit is Low (set to '0') the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to '1'), the Wait output pin is asserted one data cycle before the WAIT state.
6.6
Burst Type bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to '1'), as the memory outputs from sequential addresses only. See Table 12: Burst type definition, for the sequence of addresses output from a given starting address in sequential mode.
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M58LT256JST, M58LT256JSB
Configuration Register
6.7
Valid Clock Edge bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to '1') the rising edge of the Clock is the active edge.
6.8
Wrap Burst bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to `0') the burst read wraps. When it is High (set to `1') the burst read does not wrap.
6.9
Burst length bits (CR2-CR0)
The Burst Length bits are used to set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is aligned to an 8-word boundary no WAIT state is needed and the WAIT output is not asserted. If the starting address is not aligned to an 8-word boundary, WAIT becomes asserted when the burst sequence crosses the first 8-word boundary to indicate that the device needs an internal delay to read the successive words in the array. WAIT is asserted only once during a continuous burst access. See also Table 12: Burst type definition. CR14, CR5 and CR4 are reserved for future use.
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Configuration Register Table 11.
Bit CR15 CR14
M58LT256JST, M58LT256JSB Configuration Register
Description Read Select 1 Reserved 010 011 100 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Asynchronous Read (Default at power-on) Value 0 Description Synchronous Read
CR13-CR11
X-Latency
101 110 111
Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration 0 1 0 CR8 Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 CR3 Valid Clock Edge 1 Reserved 0 Wrap Burst 1 001 CR2-CR0 Burst Length 010 111 No Wrap (default) 4 words 8 words Continuous (default) Wrap Rising Clock edge (default) Sequential (default) Falling Clock edge WAIT is active High (default) Data held for one clock cycle Data held for two clock cycles (default)(1) WAIT is active during WAIT state WAIT is active one data cycle before WAIT state(1) (default) Reserved WAIT is active Low
1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
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M58LT256JST, M58LT256JSB Table 12.
Mode Start Add. 0 1 2 3 ... 7 Wrap ... 12 13 14 15 0 1 2 3 ... 7 No-wrap ... 12 13 14 15 12-13-14-15 13-14-15-16 14-15-16-17 15-16-17-18 12-13-14-15-16-1718-19 13-14-15-16-17-1819-20 14-15-16-17-18-1920-21 15-16-17-18-19-2021-22 7-8-9-10 7-8-9-10-11-12-1314 12-13-14-15 13-14-15-12 14-15-12-13 15-12-13-14 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 12-13-14-15-8-910-11 13-14-15-8-9-1011-12 14-15-8-9-10-1112-13 15-8-9-10-11-1213-14 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 7-4-5-6 7-0-1-2-3-4-5-6 N/A
Configuration Register
Burst type definition
Sequential Continuous Burst 4 words 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 words 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 16 words 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9...
7-8-9-10-11-1213...
12-13-14-15-1617... 13-14-15-16-1718... 14-15-16-17-1819... 15-16-17-18-1920... 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8--9-10-11-12-13-14-15-16 2-3-4-5--6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
7-8-9-10-11-12-13-14-15-16-17-18-19-2021-22
12-13-14-15-16-17-18-19-20-21-22-23-2425-26-27 13-14-15-16-17-18-19-20-21-22-23-24-2526-27-28 14-15-16-17-18-19-20-21-22-23-24-25-2627-28-29 15-16-17-18-19-20-21-22-23-24-25-26-2728-29-30
Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst)
41/106
Configuration Register Figure 5. X-Latency and data output configuration example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
M58LT256JST, M58LT256JSB
E
L
A23-A0 tDELAY
VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU
DQ15-DQ0 VALID DATA VALID DATA
AI08904
1. The settings shown are X-latency = 4, Data Output held for one clock cycle.
Figure 6.
E
Wait configuration example
K
L
A23-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI08905
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M58LT256JST, M58LT256JSB
Read modes
7
Read modes
Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchronous read operations.
7.1
Asynchronous Read mode
In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a page of data is internally read and stored in a Page Buffer. The page has a size of 8 words and is addressed by address inputs A0, A1 and A2. The first read operation within the Page has a longer access time (tAVQV, Random access time), subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150 ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 22: Asynchronous Read ac characteristics, Figure 9: Asynchronous Random Access Read ac waveforms, for details.
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Read modes
M58LT256JST, M58LT256JSB
7.2
Synchronous Burst Read mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a Synchronous Burst Read operation can be configured as 4 words, 8 words, 16 words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4 or 8 word boundary (Wrap) or overcome the boundary (No Wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a WAIT state will occur when crossing the first 16 word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 23: Synchronous Read ac characteristics, and Figure 11: Synchronous Burst Read ac waveforms, for details.
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M58LT256JST, M58LT256JSB
Read modes
7.2.1
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E, it will remain active and will not revert to high impedance when G goes High. So if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the M58LT256JST/B should not be directly connected to the system's READY signal. WAIT will revert to high-impedance when Chip Enable, E, goes High. See Table 23: Synchronous Read ac characteristics, and Figure 13: Synchronous Burst Read Suspend ac waveforms, for details.
7.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is asserted during the X-latency and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid. See Table 23: Synchronous Read ac characteristics, and Figure 11: Synchronous Burst Read ac waveforms, for details.
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Dual operations and multiple bank architecture
M58LT256JST, M58LT256JSB
8
Dual operations and multiple bank architecture
The multiple bank architecture of the M58LT256JST/B gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58LT256JST/B device. Dual operations between the Parameter Bank and either of the CFI, the OTP or the Electronic Signature memory space are not allowed. Table 15 shows which dual operations are allowed or not between the CFI, the OTP, the Electronic Signature locations and the memory array. Tables 13 and 14 show the dual operations possible in other banks and in the same bank. Table 13. Dual operations allowed in other banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
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M58LT256JST, M58LT256JSB Table 14.
Dual operations and multiple bank architecture
Dual operations allowed in same bank
Commands allowed in same bank
Status of bank
Read Array Yes -
(1) (1)
Read Status Register Yes Yes Yes Yes Yes
Read CFI query Yes Yes Yes Yes Yes
Read Electronic Signature Yes Yes Yes Yes Yes
Program, Buffer Program Yes - - - Yes(1)
Block Erase Yes - - - -
Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
-
Yes(2) Yes(2)
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. Not allowed in the Block that is being erased or in the word that is being programmed.
Table 15.
Dual operation limitations
Commands allowed Read Main blocks
Current status
Read CFI / OTP / Electronic Signature
Read Parameter Blocks
Located in Parameter Bank No
Not located in Parameter Bank Yes
Programming / Erasing Parameter Blocks Located in Parameter Bank
No
No
Yes
No
No
Yes
Programming / Erasing Main Not located in blocks Parameter Bank Programming OTP
Yes No
Yes No
Yes No
In different bank only No
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Block protection
M58LT256JST, M58LT256JSB
9
Block protection
The M58LT256JST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. This protection scheme has two levels of protection.

Protect/Unprotect - this first level allows software only control of block protection. VPP VPPLK - the second level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Protected and Unprotected. Appendix C, Figure 25, shows a flowchart for the protection operations.
9.1
Reading a block's protection status
The protection status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 7, will output the protection status of that block. The protection status is represented by DQ0. DQ0 indicates the Block Protect/Unprotect status and is set by the Protect command and cleared by the Unprotect command. The following sections explain the operation of the protection system.
9.2
Protected state
The default status of all blocks on power-up or after a hardware reset is Protected (state = 1). Protected blocks are fully protected from program or erase operations. Any program or erase operations attempted on a protected block will return an error in the Status Register. The status of a protected block can be changed to Unprotected using the appropriate software commands. An Unprotected block can be protected by issuing the Protect command.
9.3
Unprotected state
Unprotected blocks (state = 0), can be programmed or erased. All unprotected blocks return to the Protected state after a hardware reset or when the device is powered-down. The status of an unprotected block can be changed to Protected using the appropriate software commands. A protected block can be unprotected by issuing the Unprotect command.
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M58LT256JST, M58LT256JSB
Block protection
9.4
Protection operations during Erase Suspend
Changes to block protection status can be performed during an erase suspend by using the standard protection command sequences to unprotect or protect a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block protection during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Protect command sequence to a block and the protection status will be changed. After completing any desired protect, read, or program operations, resume the erase operation with the Erase Resume command. If a block is protected during an erase suspend of the same block, the erase operation will complete when the erase is resumed. Protection operations cannot be performed during a program suspend.
49/106
Program and Erase times and endurance cycles
M58LT256JST, M58LT256JSB
10
Program and Erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 16. Exact Erase times may change depending on the memory array condition. The best case is when all the bits in the block are at `0' (pre-programmed). The worst case is when all the bits in the block are at `1' (not pre-programmed). Usually, the system overhead is negligible with respect to the Erase time. In the M58LT256JST/B the maximum number of Program/Erase cycles depends on the VPP voltage supply used.
Table 16.
Program/Erase times and endurance cycles(1), (2)
Parameter Condition Min Typ 0.4 1 1.2 80 80 300 600 20 20 100,000 100,000 0.4 1 80 5 180 150 360 300 5.8 4.8 2.5 4 400 400 1200 1000 25 25 Typical after 100 kW/E cycles 1 3 Max 2.5 4 4 400 400 1200 Unit s s s s s s ms s s cycles cycles s s s s s s ms ms s s 1000 cycles 2500 cycles 2 0.5 ms ms
Parameter Block (16 kword) Erase Main Block Pre-programmed (64 kword) Not pre-programmed Single word Word Program Buffer Program
VPP = VDD
Program(3)
Buffer (32 words) (Buffer Program) Main block (64 kword) Program Erase
Suspend Latency
Main blocks Program/Erase Cycles (per Block) Parameter Blocks Erase Parameter Block (16 kword) Main Block (64 kword) Word Program Single word Buffer Enhanced Factory Program(4) VPP = VPPH Program(3) Buffer (32 words) Buffer Program Buffer Enhanced Factory Program
Main Block Buffer Program (64 kwords) Buffer Enhanced Factory Program Bank (16 Mbits) Buffer Program Buffer Enhanced Factory Program
Main blocks Program/Erase Cycles (per Block) Parameter Blocks Blank Check Main blocks Parameter Blocks
1. TA = -25 to 85 C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 3.6 V. 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device.
50/106
M58LT256JST, M58LT256JSB
Maximum rating
11
Maximum rating
Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 17.
Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage Supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH -25 -25 -65 -0.5 -0.2 -0.2 -0.2 Max 85 85 125 4.2 2.5 3.8 10 100 100 C C C V V V V mA hours Unit
51/106
DC and ac parameters
M58LT256JST, M58LT256JSB
12
DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 18: Operating and ac measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 18. Operating and ac measurement conditions
M58LT256JST/B Parameter Min VDD supply voltage VDDQ supply voltage VPP supply voltage (factory environment) VPP supply voltage (application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQ VDDQ/2 1.7 2.7 8.5 -0.4 -25 30 5 85 Max 2.0 3.6 9.5 VDDQ+0.4 85 V V V V C pF ns V V Units
Figure 7.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
52/106
M58LT256JST, M58LT256JSB Figure 8. AC measurement load circuit
VDDQ
DC and ac parameters
VDDQ VDD 22k DEVICE UNDER TEST 0.1F 0.1F CL 22k
CL includes JIG capacitance
AI12842
Table 19.
Symbol CIN COUT
Capacitance(1)
Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V Min 6 8 Max 8 12 Unit pF pF
1. Sampled only, not 100% tested.
53/106
DC and ac parameters Table 20.
Symbol ILI ILO
M58LT256JST, M58LT256JSB DC characteristics - currents
Parameter Test condition 0 V VIN VDDQ 0 V VOUT VDDQ E = VIL, G = VIH 4 word 13 16 18 22 23 50 50 50 35 35 35 35 48 Typ Max 1 1 15 19 20 25 27 110 110 110 50 50 50 50 65 Unit A A mA mA mA mA mA A A A mA mA mA mA mA
Input Leakage current Output Leakage current Supply current Asynchronous Read (f=5 MHz)
IDD1
Supply current Synchronous Read (f=52 MHz)
8 word 16 word Continuous
IDD2 IDD3 IDD4
Supply current (Reset) Supply current (Standby) Supply current (automatic standby) Supply current (Program)
RP = VSS 0.2 V E = VDD 0.2 V K = VSS E = VIL, G = VIH VPP = VPPH VPP = VDD
IDD5 (1) Supply current (Erase)
VPP = VPPH VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=52 MHz) in another Bank E = VDD 0.2 V K = VSS VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD
IDD6 (1), Supply current (2) (dual operations)
58
77
mA
IDD7(1)
Supply current Program/ Erase Suspended (standby) VPP supply current (Program)
50 8 0.2 8 0.2 0.2 0.2
110 22 5 22 5 5 5
A mA A mA A A A
IPP1(1) VPP supply current (Erase) IPP2 IPP3(1) VPP supply current (Read) VPP supply current (Standby)
1. Sampled only, not 100% tested. 2. VDD dual operation current is the sum of read and Program or Erase currents.
54/106
M58LT256JST, M58LT256JSB Table 21.
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO
DC and ac parameters
DC characteristics - voltages
Parameter Input Low voltage Input High voltage Output Low voltage Output High voltage VPP Program voltage-logic VPP Program voltage factory Program or Erase Lockout VDD Lock voltage IOL = 100 A IOH = -100 A Program, Erase Program, Erase VDDQ -0.1 2.7 8.5 3.3 9.0 3.6 9.5 0.4 1 Test condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V
55/106
56/106
DC and ac parameters Figure 9.
tAVAV VALID VALID tLHAX tAVQV tAXQX tAVLH
A0-A23
L(2) tLLLH tLLQV tELLH
E tELQV tELQX tEHQZ tEHQX
G tGLQV tGLQX Hi-Z tGLTV tELTV Hi-Z tGHTZ VALID tEHTZ tGHQX tGHQZ
Asynchronous Random Access Read ac waveforms
DQ0-DQ15
WAIT(1)
M58LT256JST, M58LT256JSB
Notes: 1. Write Enable, W, is High, WAIT is active Low. 2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
AI08906b
A3-A23 VALID ADDRESS tAVAV VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. tLHAX
M58LT256JST, M58LT256JSB
A0-A2
VALID ADDRESS
tAVLH
L
tLLLH tLLQV
tELLH
E tELQV tELQX
Figure 10. Asynchronous Page Read ac waveforms
G tGLTV tELTV
WAIT (1) tGLQV tGLQX VALID DATA Outputs Enabled VALID DATA tAVQV1
Hi-Z
DQ0-DQ15
VALID DATA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
Valid Address Latch
Valid Data
Standby
DC and ac parameters
57/106
Note 1. WAIT is active Low.
AI08907b
DC and ac parameters Table 22.
Symbol tAVAV tAVQV tAVQV1 tAXQX(1) tELTV tELQV Read timings
(2)
M58LT256JST, M58LT256JSB Asynchronous Read ac characteristics
M58LT256JST/B Alt tRC tACC tPAGE tOH Parameter 85 Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid tCE tLZ Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Wait Valid tOH tDF Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable High to Wait Hi-Z tAVADVH tELADVH tADVHAX Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Max Min Min Min Min Max 85 85 25 0 25 85 0 17 0 17 25 0 17 0 17 17 10 10 9 10 85 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tELQX(1) tEHTZ tEHQX tEHQZ
(1) (1)
tGLQV(2) tGLQX(1) tGLTV tGHQX
(1)
tGHQZ(1) tGHTZ tAVLH Latch timings tELLH tLHAX tLLLH tLLQV
tADVLADVH Latch Enable Pulse Width tADVLQV Latch Enable Low to Output Valid (Random)
1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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DQ0-DQ15 VALID tKHQV tKHQV tKHQX tKHQX VALID VALID NOT VALID VALID
Hi-Z
M58LT256JST, M58LT256JSB
A0-A23
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ
tLLKH
tAVKH
K(4)
tELKH
E tGHQX tGLQX tGHQZ
Figure 11. Synchronous Burst Read ac waveforms
G tGLTV tKHTV Note 2 tKHTX Note 2 tKHTX tKHTV Note 2 Valid Valid Data Flow Boundary Crossing Data tEHTZ
Hi-Z
WAIT X Latency
Address Latch
Standby
DC and ac parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
59/106
AI13723
DC and ac parameters Figure 12. Single Synchronous Read ac waveforms
A0-A23 VALID ADDRESS tAVKH L tLLKH K(2) tELKH tELQV E tGLQV tGLQX G tELQX DQ0-DQ15 Hi-Z tKHQV
M58LT256JST, M58LT256JSB
tGHTZ VALID tKHTV
tGLTV WAIT(1,2) Hi-Z
Ai13400
1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
60/106
Hi-Z
VALID VALID VALID VALID
DQ0-DQ15
M58LT256JST, M58LT256JSB
A0-A23
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
E tGLQX tGLQV tGHQZ tGLQV tGHQX tGHQZ
G tGLTV tGHTZ tGLTV tEHTZ
Figure 13. Synchronous Burst Read Suspend ac waveforms
Hi-Z
WAIT(2)
DC and ac parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
AI13724
61/106
DC and ac parameters Figure 14. Clock input ac waveform
tKHKL
M58LT256JST, M58LT256JSB
tKHKH
tf
tr
tKLKH
AI06981
Table 23.
Symbol tAVKH tELKH Synchronous Read timings tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock specifications tKHKH tKHKL tKLKH tf tr
Synchronous Read ac characteristics(1) (2)
M58LT256JST/B Alt tAVCLKH tELCLKH Parameter 85 Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z tCLKHAX tCLKHQV tCLKHQX tADVLCLKH tCLK Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=52 MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Min Min Min Max Min Max Min Min Min Min 9 9 20 17 10 17 3 9 19 6 ns ns ns ns ns ns ns ns ns ns Unit
Max
2
ns
1. Sampled only, not 100% tested. 2. For other timings please refer to Table 22: Asynchronous Read ac characteristics.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAV tWHAX VALID ADDRESS tLHAX tLLLH
A0-A23
M58LT256JST, M58LT256JSB
tAVLH
L tWHLL
tELLH
E tWHEH
tELWL
G tWHWL tWHGL
tGHWL
W tWLWH tWHDX COMMAND CMD or DATA tWHVPL tVPHWH tQVVPL STATUS REGISTER tWHEL tELQV
tDVWH
Figure 15. Write ac waveforms, Write Enable controlled
DQ0-DQ15
VPP tELKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
Ai13401
DC and ac parameters
SET-UP COMMAND
63/106
DC and ac parameters Table 24.
Symbol tAVAV tAVLH tAVWH(3) tDVWH tELLH tELWL Write Enable Controlled timings tELQV tELKV tGHWL tLHAX tLLLH tWHAV(2) tWHAX(2) tWHDX tWHEH tWHEL
(3)
M58LT256JST, M58LT256JSB Write ac characteristics, Write Enable controlled(1)
M58LT256JST/B Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High tDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High tCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid tAH tDH tCH Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low tWPH Write Enable High to Write Enable Low tWP Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low tVPS VPP High to Write Enable High Write Enable High to VPP Low Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 10 50 50 10 0 85 9 17 9 10 0 0 0 0 25 0 25 25 50 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tWHGL tWHLL(3) tWHWL tWLWH Protection timings 64/106 tQVVPL tVPHWH tWHVPL
1. Sampled only, not 100% tested. 2. Meaningful only if L is always kept Low. 3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL and tWHLL are 0 ns.
PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVEH tEHAX VALID ADDRESS tLHAX tLLLH
A0-A23
M58LT256JST, M58LT256JSB
tAVLH
L tELLH tEHWH
W tWLEL
G tGHEL tEHEL tEHGL
E tELEH tEHDX COMMAND CMD or DATA tEHVPL tVPHEH tQVVPL STATUS REGISTER tWHEL tELQV
tDVEH
Figure 16. Write ac waveforms, Chip Enable controlled
DQ0-DQ15
VPP tELKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
SET-UP COMMAND
DC and ac parameters
65/106
Ai13402
DC and ac parameters Table 25.
Symbol tAVAV tAVEH tAVLH tDVEH tEHAX Chip Enable Controlled timings tEHDX tEHEL tEHGL tEHWH tELKV tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL
(2)
M58LT256JST, M58LT256JSB Write ac characteristics, Chip Enable controlled(1)
M58LT256JST/B Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High tDS tAH tDH tCPH Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low tCH Chip Enable High to Write Enable High Chip Enable Low to Clock Valid tCP Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low tCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Output (Status Register) Valid to VPP Low tVPS VPP High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 50 10 50 0 0 25 0 0 9 50 10 85 17 9 10 25 0 200 0 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tWLEL Protection timings 66/106 tEHVPL tQVVPL tVPHEH
1. Sampled only, not 100% tested. 2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0 ns.
M58LT256JST, M58LT256JSB Figure 17. Reset and Power-up ac waveforms
DC and ac parameters
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-up Reset
AI06976
tPLPH
Table 26.
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3)
Reset and Power-up ac characteristics
Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low RP Pulse Width Supply voltages High to Reset High Test condition During Program During Erase Read Other conditions Min Min Min Min 85 25 25 80 200 Unit s s ns s
Min
30
ns
Min Min
50 150
ns s
1. The device Reset is possible but not guaranteed if tPLPH < 50 ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-up or Reset.
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Package mechanical
M58LT256JST, M58LT256JSB
13
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
1. Drawing is not to scale.
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M58LT256JST, M58LT256JSB Table 27.
Package mechanical
TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data
millimeters inches Max 1.200 0.300 0.800 0.350 10.000 7.000 9.900 - 0.500 10.100 - 0.100 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.200 0.350 0.0118 0.0315 0.0138 0.3898 - 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - 0.0079 Typ Min Max 0.0472 0.0138
Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE Min
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Part numbering
M58LT256JST, M58LT256JSB
14
Part numbering
Table 28.
Example: Device Type M58 Architecture L = Multilevel, Multiple Bank, Burst Mode Operating Voltage T = VDD = 1.7 V to 2.0 V, VDDQ = 2.7 V to 3.6 V Density 256 = 256 Mbit (x 16) Technology J = 90 nm technology, Multilevel design Security S = Secure Parameter Location T = Top Boot B = Bottom Boot Speed 8 = 85 ns Package ZA = TBGA64, 10 x 13 mm, 1 mm pitch Temperature Range 6 = -40 to 85 C Packing Option E = ECOPACK(R) Package, Standard Packing F = ECOPACK(R) Package, Tape & Reel Packing T = Tape & Reel Packing Blank = Standard packing
Ordering information scheme
M58LT256JST 8 ZA 6 E
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58LT256JST, M58LT256JSB
Block address tables
Appendix A
Block address tables
The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables 29 to 34. To calculate the Block Base Address from the Block Number: First it is necessary to calculate the Bank Number and the Block Number Offset. This can be achieved using the following formulas: Bank_Number = (Block_Number - 3) / 16 Block_Number_Offset = Block_Number - 3 - (Bank_Number x 16) If Bank_Number = 0, the Block Base Address can be directly read from Tables 29 and 32 (Parameter Bank Block Addresses) in the Block Number Offset row. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the Bank Number and the Block Number from the Block Base Address: If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block Number can be directly read from Tables 29 and 32 (Parameter Bank Block Addresses), in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M58LT256JST): Block_Number = ((NOT address) / 216) + 3 For the bottom configuration (M58LT256JSB): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = (Block_Number - 3) / 16 Block_Number_Offset = Block_Number - 3 - (Bank_Number x 16)
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Block address tables Table 29.
M58LT256JST, M58LT256JSB M58LT256JST - parameter bank block addresses
Size (kwords) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF FD0000-FDFFFF FC0000-FCFFFF FB0000-FBFFFF FA0000-FAFFFF F90000-F9FFFF F80000-F8FFFF F70000-F7FFFF F60000-F6FFFF F50000-F5FFFF F40000-F4FFFF F30000-F3FFFF F20000-F2FFFF F10000-F1FFFF F00000-F0FFFF
Block number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
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M58LT256JST, M58LT256JSB Table 30. M58LT256JST - main bank base addresses
Block numbers 19-34 35-50 51-66 67-82 83-98 99-114 115-130 131-146 147-162 163-178 179-194 195-210 211-226 227-242 243-258
Block address tables
Bank number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bank base address E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000 000000
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 31.
M58LT256JST - block addresses in main banks
Block base address offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000
Block number offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Block address tables Table 32.
M58LT256JST, M58LT256JSB M58LT256JSB - parameter bank block addresses
Size (kwords) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16 Address range 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
Block number 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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M58LT256JST, M58LT256JSB Table 33. M58LT256JSB - main bank base addresses
Block numbers 243-258 227-242 211-226 195-210 179-194 163-178 147-162 131-146 115-130 99-114 83-98 67-82 51-66 35-50 19-34
Block address tables
Bank number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bank base address F00000 E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 34.
M58LT256JSB - block addresses in main banks
Block base address offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000
Block number offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Common Flash Interface
M58LT256JST, M58LT256JSB
Appendix B
Common Flash Interface
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 4: Protection Register memory map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode. Table 35.
Offset 000h 010h 01Bh 027h P A Reserved CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Alternate algorithm-specific extended query table Security code area
Query structure overview
Sub-section name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the primary algorithm (optional) Additional information specific to the alternate algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 36, 37, 38 and 39. Query data is always presented on the lowest order data outputs.
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M58LT256JST, M58LT256JSB Table 36.
Offset 000h 001h 002h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah
Common Flash Interface
CFI query identification string
Sub-section name 0020h 885Eh 885Fh reserved 0051h 0052h 0059h 0001h 0000h Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm p = 10Ah Query Unique ASCII String "QRY" Manufacturer code Device code Reserved "Q" "R" "Y" M58LT256JST M58LT256JSB Description Value ST Top Bottom
offset = P = 000Ah Address for primary algorithm extended query table (see Table 39) 0001h 0000h 0000h value = A = 0000h Address for alternate algorithm extended query table 0000h Alternate vendor command set and control interface ID code second vendor - specified algorithm supported
NA
NA
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Common Flash Interface Table 37.
Offset
M58LT256JST, M58LT256JSB
CFI query system interface information
Data Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for Buffer Program = 2 s Typical time-out per individual block erase = Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2 times typical Maximum time-out for Buffer Program = 2n times typical
n n n
Value
01Bh
0017h
1.7 V
01Ch
0020h
2V
01Dh
0085h
8.5 V
01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h
0095h 0008h 0009h 000Ah 0000h 0001h 0001h 0002h 0000h
9.5 V 256 s 512 s
2n
ms
1s NA 512 s 1024 s 4s NA
Maximum time-out per individual block erase = 2 times typical Maximum time-out for chip erase = 2n times typical
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M58LT256JST, M58LT256JSB Table 38.
Offset 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh M58LT256JST 02Fh 030h 031h 032h 033h 034h 035h 038h 02Dh 02Eh M58LT256JSB 02Fh 030h 031h 032h 033h 034h 035h 038h
Common Flash Interface
Device geometry definition
Data 0019h 0001h 0000h 0006h 0000h 0002h 00FEh 0000h 0000h 0002h 0003h 0000h 0080h 0000h Description Device Size = 2n in number of bytes Flash Device Interface code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block regions Erase Block region 1 information Number of identical-size erase blocks = 00FEh+1 Erase Block region 1 information Block size in region 1 = 0200h * 256 Byte Erase Block region 2 information Number of identical-size erase blocks = 0003h+1 Erase Block region 2 information Block size in region 2 = 0080h * 256 Byte Value 32 Mbytes x 16 Async. 64 Bytes
2
255 128 Kbytes 4 32 Kbytes NA 4 32 Kbytes 255 128 Kbytes NA
Reserved Reserved for future erase block region information 0003h 0000h 0080h 0000h 00FEh 0000h 0000h 0002h Erase Block region 1 Information Number of identical-size erase block = 0003h+1 Erase Block region 1 information Block size in region 1 = 0080h * 256 bytes Erase Block region 2 information Number of identical-size erase block = 00FEh+1 Erase Block region 2 information Block size in region 2 = 0200h * 256 bytes
Reserved Reserved for future erase block region information
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Common Flash Interface Table 39.
Offset (P)h = 10Ah
M58LT256JST, M58LT256JSB
Primary algorithm-specific extended query table
Data 0050h 0052h Primary algorithm extended query table unique ASCII string "PRI" 0049h Description Value "P" "R" "I" "1" "3"
(P+3)h =10Dh (P+4)h = 10Eh (P+5)h = 10Fh
0031h Major version number, ASCII 0033h Minor version number, ASCII 00E6h Extended query table contents for primary algorithm. Address (P+5)h contains less significant byte. 0003h 0000h bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Protect/Unprotect supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block locking supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query
(P+7)h = 111h
(P+8)h = 112h
0000h
No Yes Yes No No Yes Yes Yes Yes Yes
(P+9)h = 113h
0001h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0'
Yes
(P+A)h = 114h
0001h Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Protect/Unprotect bit active (1 = Yes, 0 = No) bit 1 Block Protect Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance)
(P+B)h = 115h
0000h
Yes No
(P+C)h = 116h
0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage
1.8 V
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV
9V
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M58LT256JST, M58LT256JSB Table 40.
Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h
Common Flash Interface
Protection register information
Data 0002h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 Bytes 8 Bytes 89h Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16
0080h Protection Field 1: Protection Description 0000h Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address 0003h Bits 16-23 2n bytes in factory pre-programmed region 0003h Bits 24-31 2n bytes in user programmable region 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h
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Common Flash Interface Table 41.
Offset
M58LT256JST, M58LT256JSB
Burst Read information
Data Description Value
(P+1D)h = 127h
Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of 0004h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. 0004h Number of synchronous mode read configuration fields that follow.
16 bytes
(P+1E)h = 128h
4
(P+1F)h = 129h
Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of 0001h continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 0002h Synchronous mode read capability configuration 2 0003h Synchronous mode read capability configuration 3 0007h Synchronous mode read capability configuration 4
4
(P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch
8 16 Cont.
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M58LT256JST, M58LT256JSB Table 42. Bank and Erase block region information
M58LT256JSB
Common Flash Interface
M58LT256JST Offset (P+23)h = 12Dh Data 02h
Description Offset (P+23)h = 12Dh Data 02h Number of bank regions within the device
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Tables 29 to 34.
Table 43.
Bank and Erase block region 1 information
M58LT256JSB Description Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 01h Number of identical banks within bank region 1 00h Number of program or erase operations allowed in bank region 1: Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2). Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank region 1 (Erase Block Type 1) Minimum block erase cycles x 1000
M58LT256JST Offset Data
(P+24)h = 12Eh 0Fh (P+25)h = 12Fh 00h
(P+26)h = 130h
11h
(P+26)h = 130h
11h
(P+27)h = 131h
00h
(P+27)h = 131h
00h
(P+28)h = 132h
00h
(P+28)h = 132h
00h
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h 0Fh (P+2B)h = 135h 00h (P+2C)h = 136h 00h (P+2D)h = 137h 02h (P+2E)h = 138h 64h (P+2F)h = 139h 00h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
03h 00h 80h 00h 64h 00h
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Common Flash Interface Table 43.
M58LT256JST, M58LT256JSB
Bank and Erase block region 1 information (continued)
M58LT256JSB Description Offset Data Bank region 1 (Erase Block type 1): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank region 1 (Erase Block type 1): page mode and synchronous mode capabilities Bit 0: page-mode reads permitted Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved
M58LT256JST Offset Data
(P+30)h = 13Ah 02h
(P+30)h = 13Ah
02h
(P+31)h = 13Bh 03h
(P+31)h = 13Bh
03h
(P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h
0Eh Bank region 1 Erase Block type 2 information
Bits 0-15: n+1 = number of identical-sized 00h erase blocks
00h 02h 64h 00h Bits 16-31: n x 256 = number of bytes in erase block region Bank region 1 (Erase Block type 2) Minimum block erase cycles x 1000 Bank regions 1 (Erase Block Type 2): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank region 1 (Erase Block Type 2): page mode and synchronous mode capabilities Bit 0: page-mode reads permitted Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved
(P+38)h = 142h
02h
(P+39)h = 143h
03h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Tables 29 to 34. 3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
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M58LT256JST, M58LT256JSB Table 44. Bank and Erase block region 2 information
M58LT256JSB
Common Flash Interface
M58LT256JST Offset Data
Description Offset (P+3A)h = 144h (P+3B)h = 145h Data 0Fh Number of identical banks within bank region 2 (P+33)h = 13Dh 00h 00h Number of program or erase operations allowed in bank region 2: 11h Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming 00h Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing 00h Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Types of erase block regions in bank region 2 n = number of erase block regions with contiguous 01h same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) 0Fh Bank region 2 Erase Block type 1 information 00h Bits 0-15: n+1 = number of identical-sized erase blocks 00h Bits 16-31: n x 256 = number of bytes in erase 02h block region 64h Bank region 2 (Erase Block type 1) 00h Minimum block erase cycles x 1000 Bank region 2 (Erase Block type 1): bits per cell, internal ECC 02h Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank region 2 (Erase Block type 1): page mode and synchronous mode capabilities (defined in Table 41) Bit 0: page-mode reads permitted 03h Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved (P+32)h = 13Ch 01h
(P+34)h = 13Eh 11h
(P+3C)h = 146h
(P+35)h = 13Fh 00h
(P+3D)h = 147h
(P+36)h = 140h
00h
(P+3E)h = 148h
(P+37)h = 141h
02h
(P+3F)h = 149h
(P+38)h = 142h 0Eh (P+39)h = 143h 00h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh
(P+3A)h = 144h 00h (P+3B)h = 145h 02h (P+3C)h = 146h 64h (P+3D)h = 147h 00h
(P+3E)h = 148h 02h
(P+46)h = 150h
(P+3F)h = 149h 03h
(P+47)h = 151h
85/106
Common Flash Interface Table 44.
M58LT256JST, M58LT256JSB
Bank and Erase block region 2 information (continued)
M58LT256JSB Description Offset Data Bank region 2 Erase Block type 2 information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n x 256 = number of bytes in erase block region Bank region 2 (Erase Block type 2) Minimum block erase cycles x 1000 Bank region 2 (Erase Block Type 2): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank region 2 (Erase Block type 2): page mode and synchronous mode capabilities (defined in Table 41) Bit 0: page-mode reads permitted Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature space definitions Reserved
M58LT256JST Offset Data
(P+40)h = 14Ah 03h (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h = 14Eh 64h (P+45)h = 14Fh 00h
(P+46)h = 150h
02h
(P+47)h = 151h
03h
(P+48)h = 152h (P+49)h = 153h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Tables 29 to 34. 3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
86/106
M58LT256JST, M58LT256JSB
Flowcharts and pseudocodes
Appendix C
Flowcharts and pseudocodes
Figure 19. Program flowchart and pseudocode
Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Write Address & Data
Read Status Register (3)
SR7 = 1
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
87/106
Flowcharts and pseudocodes Figure 20. Blank Check flowchart and pseudocode
Start
M58LT256JST, M58LT256JSB
blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC);
Write Block Address & CBh
writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */
do { Read Status Register (1) status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR4 = 1 SR5 = 1 YES Command Sequence Error (2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; NO
SR5 = 0
NO
Blank Check Error (2)
if (status_register.SR5==1) /* Blank Check error */ error_handler () ;
End
}
ai10520c
1. Any address within the bank can equally be used. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
88/106
M58LT256JST, M58LT256JSB Figure 21. Buffer Program flowchart and pseudocode
Start
Flowcharts and pseudocodes
Buffer Program E8h Command, Start Address Read Status Register
Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ;
status_register=readFlash (Start_Address);
SR7 = 1 YES Write n(1), Start Address
NO
} while (status_register.SR7==0);
writeToFlash (Start_Address, n);
Write Buffer Data, Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/
X=0
x = 0;
X=n NO
YES
while (xWrite Next Buffer Data, Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++; X=X+1 } Program Buffer to Flash Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status Register
do {status_register=readFlash (Start_Address);
SR7 = 1 YES Full Status Register Check(3)
NO
} while (status_register.SR7==0);
full_status_register_check(); }
End
AI08913b
1. n + 1 is the number of data being programmed. 2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to buffer_Program[].address 3. Routine for Error Check by reading SR3, SR4 and SR1.
89/106
Flowcharts and pseudocodes
M58LT256JST, M58LT256JSB
Figure 22. Program Suspend & Resume flowchart and pseudocode
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
90/106
M58LT256JST, M58LT256JSB Figure 23. Block Erase flowchart and pseudocode
Flowcharts and pseudocodes
Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */
Write 20h (2)
Write Block Address & D0h
Read Status Register (2)
do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI10976
1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used.
91/106
Flowcharts and pseudocodes Figure 24. Erase Suspend & Resume flowchart and pseudocode
Start
M58LT256JST, M58LT256JSB
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh Read data from another block or Program or Block Protect/Unprotect Write D0h else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write 70h(1)
Erase Continues with Bank in Read Status Register Mode
AI12897b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
92/106
M58LT256JST, M58LT256JSB
Flowcharts and pseudocodes
Figure 25. Protect/Unprotect operation flowchart and pseudocode
Start
Write 60h (1)
protect_operation_command (address, protect_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (protect_operation==PROTECT) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (protect_operation==UNPROTECT) /*to unprotect the block*/ writeToFlash (address, 0xD0) ;
Write 01h, D0h
Write 90h (1)
writeToFlash (address, 0x90) ; /*see note (1) */
Read Block Protect State
Protection change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = protection_state_expected) error_handler () ; /*Check the protection state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI12895
1. Any address within the bank can equally be used.
93/106
Flowcharts and pseudocodes
M58LT256JST, M58LT256JSB
Figure 26. Protection Register Program flowchart and pseudocode
Start
Write C0h (3)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (3)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
94/106
M58LT256JST, M58LT256JSB
Flowcharts and pseudocodes
Figure 27. Buffer Enhanced Factory Program flowchart and pseudocode
Start Write 80h to Address WA1 SETUP PHASE
Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) {
writeToFlash (start_address, 0x80) ;
Write D0h to Address WA1
writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address);
Read Status Register
NO
SR7 = 0 YES
NO
SR4 = 1
Initialize count X=0 Write PDX Address WA1
if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Protected Block */ PROGRAM AND } VERIFY PHASE while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]);
Read Status Register SR3 and SR1for errors
Exit
Increment Count X=X+1
x++;
NO
X = 32 YES Read Status Register
}while (x<32) do {
status_register = readFlash (start_address);
NO
SR0 = 0 YES
}while (status_register.SR0==1)
NO
Last data? YES Write FFFFh to Address = NOT WA1
} while (not last data)
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
Read Status Register
do { status_register = readFlash (start_address)
NO
SR7 = 1
}while (status_register.SR7==0)
YES Full Status Register Check End
full_status_register_check();
}
AI12898
95/106
Command interface state tables
M58LT256JST, M58LT256JSB
Appendix D
Table 45.
Command interface state tables
Command Interface states - modify table, next state(1)
Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h)
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Blank Check setup (BCh)
Ready
Ready
Program Setup
BP Setup
Erase Setup
BEFP Setup
Blank Check setup Ready (unprotect block) OTP Busy
Ready
Protect/CR Setup
Ready (Protect Error)
Ready (Protect Error)
Setup Busy OTP IS in OTP busy Setup IS in Program Program Program Busy Busy Busy IS in Program Busy OTP Busy IS in OTP Busy OTP busy IS in OTP Busy
OTP Busy
OTP Busy
Program Busy Program Suspend
Busy
Program Busy
Program Busy
Program
IS in Program Busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm PS IS in PS PS IS in Program Suspend
Program Busy
PS
Program Busy
Program Suspend
Program Suspend Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) BP Busy IS in BP Busy BP Busy IS in BP Busy BP Busy BP Busy Ready (error) BP Suspend Buffer Program Busy
Buffer Program
Busy IS in BP Busy Suspend IS in BP Suspend
Buffer Program Busy BP BP BP IS in BP IS in BP Suspend Suspend Suspend Suspend Suspend
BP busy
Buffer Program Suspend
Buffer Program Suspend
96/106
M58LT256JST, M58LT256JSB Table 45.
Command interface state tables
Command Interface states - modify table, next state(1) (continued)
Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h) Erase Busy Erase Busy Ready (error) Erase Suspend Erase Busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (10/40h) (80h) (E8h) (20h)
Blank Check setup (BCh)
Setup Busy IS in Erase Busy Suspend IS in ES Setup IS in Program Program Busy in Busy in ES ES Erase Busy IS in Erase Busy
Ready (error) Erase Busy IS in Erase Busy
Erase
Erase Busy
Erase Program BP in ES Suspend in ES
IS in Erase Suspend
ES
Erase Busy
Erase Suspend
Erase Suspend Program Busy in Erase Suspend Program Busy in ES
Busy
IS in Program Busy in ES
Program Busy in ES
PS in ES
Program Busy in Erase Suspend
Program IS in in Erase Program Suspend busy in ES Suspend PS in ES IS in PS in ES Setup Buffer Load 1 IS in PS in PS in ES ES
Program busy in Erase Suspend
IS in Program Suspend in ES
PS in ES
Program Busy in ES
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N 0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load)
Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program Load 2 will fail at this point if any block address is different from the first address) Confirm Buffer Program in Erase Suspend BP Busy in ES Erase Suspend (sequence error) IS in BP Busy in ES BP busy in ES IS in BP busy in ES BP Busy in ES Erase Suspend (sequence error) BP Suspend in ES
Busy
BP Busy in ES
Buffer Program Busy in ES
IS in BP busy in ES
Buffer Program Busy in Erase Suspend
BP BP IS in BP BP Suspend Suspend Suspend Suspend IS in BP Suspend Suspend in ES in ES in Erase Suspend in ES in ES IS in BP Suspend in ES
BP Busy in Erase Suspend
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
97/106
Command interface state tables Table 45.
M58LT256JST, M58LT256JSB
Command Interface states - modify table, next state(1) (continued)
Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h) Blank Check busy Blank Check busy Erase Suspend (Protect Error) Ready (error) Erase Suspend BEFP Busy BEFP Busy(6) Erase Suspend (Protect Error) Ready (error)
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (10/40h) (80h) (E8h) (20h)
Blank Check setup (BCh)
Blank Check
Setup Busy
Ready (error)
Ready (error)
Protect/CR Setup in Erase Suspend Buffer EFP Setup Busy
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend. 2. At Power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E C is active, both cycles are ignored. 5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
98/106
M58LT256JST, M58LT256JSB Table 46.
Command interface state tables
Command Interface states - modify table, next output state(1) (2)
Command Input Erase Confirm P/E Resume, Block Blank Block Buffer Erase, BEFP Check (4) Setup Unprotect Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) (10/40h) Confirm(4)(5) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h)
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Protect/CR Setup Protect/CR Setup in Erase Suspend
Status Register
99/106
Command interface state tables Table 46.
M58LT256JST, M58LT256JSB
Command Interface states - modify table, next output state(1) (2) (continued)
Command Input Erase Confirm Block P/E Resume, Blank Block Buffer Erase, BEFP (4) Setup Check Unprotect Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) (10/40h) Confirm(4)(5) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h) Status Register
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged
Array
Status Register
Output Unchanged
Output Status Unchang Electronic Register ed Signature/ CFI
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. At Power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/E.C. is active, both cycles are ignored.
100/106
M58LT256JST, M58LT256JSB Table 47. Command interface states - lock table, next state(1)
Command Input Current CI State Protect/CR Setup(2) (60h) Protect/CR Setup OTP Setup(2) (C0h) OTP Setup Ready OTP Busy IS in OTP Busy OTP Busy Program Busy IS in Program Busy Program busy IS in PS Block Protect Confirm (01h) Set CR Confirm (03h)
Command interface state tables
Block Address (WA0)(3) (XXXXh) Ready
Illegal Command(4)
P/E C operation completed(5) N/A
Ready Protect/CR Setup Setup OTP Busy IS in OTP busy Setup Busy Program IS in Program busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm Buffer Program Busy IS in Buffer Program busy Suspend IS in BP Suspend Setup Busy Erase IS in Erase busy Suspend IS in ES
Ready (Protect error)
Ready (Protect error)
N/A N/A
OTP Busy
Ready IS Ready N/A
Program Busy
Ready IS Ready
Program Suspend N/A Program Suspend Buffer Program Load 1 (give word count load (N-1)); N/A see note (6) N/A N/A N/A Buffer Program Busy Buffer Program Busy Ready IS Ready
Buffer Program Load 2(6)
Exit
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) IS in BP Busy
IS in BP Suspend
Buffer Program Suspend N/A Buffer Program Suspend Ready (error) N/A Erase Busy Erase Busy Ready IS ready Erase Suspend N/A Erase Suspend
IS in Erase Busy
Protect/CR Setup in ES
IS in ES
101/106
Command interface state tables Table 47.
M58LT256JST, M58LT256JSB
Command interface states - lock table, next state(1) (continued)
Command Input
Current CI State
Protect/CR Setup(2) (60h)
OTP Setup(2) (C0h)
Block Protect Confirm (01h)
Set CR Confirm (03h)
Block Address (WA0)(3) (XXXXh)
Illegal Command(4)
P/E C operation completed(5) N/A ES IS in ES
Setup Busy Program in Erase Suspend IS in Program busy in ES Suspend IS in PS in ES Setup Buffer Load 1 IS in PS in ES IS in Program busy in ES
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend
N/A Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7) N/A
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Erase Suspend (sequence error) IS in BP busy in ES Buffer Program Busy in Erase Suspend BP busy in ES IS in BP suspend in ES Buffer Program Suspend in Erase Suspend
Buffer Program in Erase Suspend
Confirm Busy IS in BP busy in ES Suspend IS in BP Suspend in ES Setup
ES IS in ES
N/A Buffer Program Suspend in Erase Suspend Ready (error) Blank Check busy Erase Suspend (Protect error) Erase Suspend Ready (error) BEFP Busy(8) Exit BEFP Busy(8) Erase Suspend (Protect error) N/A Ready N/A N/A N/A
Blank Check
Blank Check busy
Protect/CR Setup in ES Setup BEFP Busy
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP address. 2. If the P/E C is active, both cycle are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. N/A: not available. In this case the state remains unchanged. 6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load) 7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend. 8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
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M58LT256JST, M58LT256JSB Table 48.
Command interface state tables
Command interface states - lock table, next output state (1) (2)
Command Input
Current CI State
Protect/CR Blank Check Blank OTP Setup(3)(6 Check setup Setup(3) confirm (C0h) 0h) (CBh) (BCh)
Block Protect Confirm (01h)
P. E./C. Illegal Set CR BEFP Confirm Exit(4) Command Operation (5) Completed (03h) (FFFFh)
Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Protect/CR Setup Status Register Protect/CR Setup in Erase Suspend Array Status Register Status Register Output Unchanged
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Command interface state tables Table 48.
M58LT256JST, M58LT256JSB
Command interface states - lock table, next output state (continued)(1) (2)
Command Input
Current CI State
Protect/CR Blank Check Blank OTP Setup(3)(6 Check setup Setup(3) confirm (C0h) 0h) (CBh) (BCh)
Block Protect Confirm (01h)
P. E./C. Illegal Set CR BEFP Confirm Exit(4) Command Operation (5) Completed (03h) (FFFFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged Status Register Output Unchanged Array Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. If the P/E.C. is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set.
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M58LT256JST, M58LT256JSB
Revision history
Revision history
Table 49.
Date 18-Jul-2006
Document revision history
Revision 0.1 Initial release. Description of CR2-CR0 011 value modified in Table 11: Configuration Register and Note 2 added. Table 12: Burst type definition modified. Timings modified in Table 16: Program/Erase times and endurance cycles,. VIO max and VDDQ max modified in Table 17: Absolute maximum ratings. Values changed in Table 20: DC characteristics - currents. VPP1 modified in Table 21: DC characteristics - voltages. Figure 24: Erase Suspend & Resume flowchart and pseudocode modified. Appendix D: Command interface state tables modified. Document status promoted from Target Specification to Preliminary Data. Small text changes. Wait (WAIT) signal behavior in relation to Output Enable modified. Section 5.4: Program Status bit (SR4) and Section 6.9: Burst length bits (CR2-CR0) modified. Device architecture corrected (see Table 2: Bank architecture, Figure 3: Memory map and Appendix A: Block address tables). IDD1 and IDD6 parameter values updated in Table 20: DC characteristics - currents. Figure 13: Synchronous Burst Read Suspend ac waveforms modified. tPLWL, tPLEL, tPLGL and tPLLL values modified under Other conditions (see Table 26: Reset and Power-up ac characteristics). tELTV timing removed from Figure 11: Synchronous Burst Read ac waveforms, Figure 13: Synchronous Burst Read Suspend ac waveforms and Table 23: Synchronous Read ac characteristics. tELTV timing modified in Table 22: Asynchronous Read ac characteristics. Appendix B: Common Flash Interface modified. Block Lock Down confirm (2Fh) removed from Table 47: Command interface states - lock table, next state and Table 48: Command interface states - lock table, next output state. Small text changes. Document status promoted from Preliminary Data to full Datasheet. Section 7.2: Synchronous Burst Read mode modified. 16 word boundary (wrap) feature removed from the document. Two packing options added in Table 28: Ordering information scheme. Small text changes. Changes
31-Oct-2006
0.2
18-Dec-2006
0.3
23-Feb-2007
1
27-Jun-2007
2
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M58LT256JST, M58LT256JSB
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