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AN994 APPLICATION NOTE L6384, L6385, L6386 & L6387 APPLICATION GUIDE
by F. Sandrini, U. Moriconi
The ST L638X is a versatile high voltage gate driver family. Realised in BCD Off-line technology, these devices are able to operate with high voltage rails up to 600V. The Gate Drivers provide all the functions and current capability necessary for high side and low side Power MOS and IGBT.
L6384-5-6-7 are High Voltage Drivers for High and Low Side. These devices can be used in all the applications where high voltage shifted control is necessary. These devices have a fairly high driver current capability and they are also provided with an internal patented circuitry which replaces the external bootstrap diode. This feature is achieved by means of a high voltage DMOS, synchronously driven with the low side gate driver. The L6384 (Internal diagram in fig. 1) is a half bridge driver with externally adjustable dead-time and shut down function. To disable the driver, the control pin (DT/SD at pin3) must be pulled down below 0.5V. The dead time can be set from 0.5s to 2.7s by a simple resistor between pin3 and ground. Available in Minidip and SO8 packages, this driver can be used in motor controls, resonant converters and lighting applications. In fig. 2 the schematic diagram of the evaluation circuit and the layout of the test PCB are shown. L6384 PIN DESCRIPTION
N. 1 2 3 Name IN(*) VCC DT/SD Type I I I Function Logic Input: it is in phase with HVG and in opposition of phase with LVG. It is compatible to Vcc voltage. Supply input voltage: there is an internal clamp [Typ. 15.6V] There is also an UVLO feature ( Typ. Vccth1 = 12V, Vccth2 = 10V). High impedence pin with two functionalities. When pulled to a voltage lower than Vdt [Typ.0.5V] the device is shut down. A voltage higher than Vdt sets the dead time between high side and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. Care must be taken to avoid spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. This pin can not be let floating for the same reason. The pin has not to be pulled through a low impedence to Vcc, because of the drop on the corrent source that feeds Rdt. The operative range is: V dt ... 270K Idt, that allows a dt range of 0.4 - 3.1s. Ground O Low side driver output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@Isink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedence also in SD conditions. Upper driver floating reference: layout care has to be taken to avoid undervoltage spikes on this pin
4 5
GND LVG
6
Vout
O
June 2002
1/17
AN994 APPLICATION NOTE
L6384 PIN DESCRIPTION (continued)
N. 7 Name HVG Type O Function High side driver output:the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max between this pin and Vout (@I sink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedence also in SD conditions. Bootstrap Supply Voltage: it is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
8
Vboot
(*) The pull-down internal resistor is typically some hundreds Kohm.
Figure 1. L6384 Internal Block Diagram.
H.V. VCC 2 8 BOOTSTRAP DRIVER UV DETECTION R IN 1 VCC Idt DT/SD 3 Vthi
D97IN518A
V BOOT
HVG DRIVER S 7
CBOOT HVG
LOGIC LEVEL SHIFTER DEAD TIME VCC
OUT 6
LOAD
5 LSG DRIVER
LVG
4
GND
Figure 2. L6384 Schematic diagram of the evaluation circuit.
D1 C5 CN1 C6 CN3
IN VCC DT/DS
1 2 3
7 8
HVG VBOOT
R2 Q1 C4 D2
R4
R5
L6384
6 OUT
L1
CN2
C1
C2
GND
4
R3 5 LVG Q2 D3
W1 C7
W2
R7
D98IN829
R6
2/17
AN994 APPLICATION NOTE
Figure 2a. L6384 - PCB and component layout of the fig. 2.
94mm
50mm
Silk
Comp. Layer
Back Layer
3/17
AN994 APPLICATION NOTE
The L6385 (Internal diagram in fig. 3) is a high and low side configurable driver. In fact, it is possible to control two separate inputs, thus the outputs can be switched independently. This device is provided with undervoltage detection in both low voltage side and high voltage bootstrapped supply. Delivered in 8pin packages, this driver has been especially designed for power supplies and motion control application. Fig. 4 shows the schematic diagram of the evaluation circuit and the layout of the relevant PCB. L6385 PIN DESCRIPTION
N. 1 2 3 4 5 Name LIN (*) HIN (*) VCC GND LVG Type I I I O Function Low Side Driver Logic Input: it is compatible to Vcc voltage. [Vil Max = 1.5V, Vih Min = 3.6V] High Side Driver Logic Input: it is compatible to Vcc voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Supply input voltage with UVLO ( Typ. Vccth1 = 9.6V, Vccth2 = 8.3V). Ground Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@Isink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low. Upper Driver Floating Reference: layout care has to be taken to avoid undervoltage spikes on this pin. High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max between this pin and Vout (@ Isink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low. Bootstrap Supply Voltage:it is the upper driver floating supply [with UVLO: typ. VBSth1 = 9.5V, VBSth2 = 8.2V]. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
6 7
Vout HVG
O O
8
Vboot
(*) The pull-down internal resistor is typically some hundreds Kohm.
Figure 3. L6385 Internal Block Diagram.
BOOTSTRAP DRIVER 8 Vboot H.V. R R HIN 2 LOGIC LEVEL SHIFTER S VCC LIN 1 LVG DRIVER HVG DRIVER 7 OUT 6 5 LVG TO LOAD HVG Cboot
VCC
3
UV DETECTION
UV DETECTION
4
GND
D97IN514B
Figure 4. L6385 Schematic diagram of the evaluation circuit.
+HV D1 C5 CN1 LIN HIN VCC C1 C2 GND R2 Q1 C4 6 5 VOUT R3 LVG Q2 D3 CN4 D2 CN2 CN3
1 2 3 4
7 8
HVG VBOOT
L6385
D98IN830
4/17
AN994 APPLICATION NOTE
Figure 5a. L6385 - PCB and component layout of the fig. 5.
80mm
50mm
Silk
Comp. Layer
Back Layer
5/17
AN994 APPLICATION NOTE
L6386 (Internal diagram in fig. 5). Configurable driver, the L6386 is based on the L6385 structure with added functions. This device is available in DIP14 or SO14. The added Shutdown function (active low) and the Current Sense Comparator (0.5V threshold) with Diagnostic Output, make this device particularly suitable for motion control with cycle-by-cycle current feedback. DIAG and CIN pins can be used to stop the device (e.g. acting on SD pin). Fig. 6 shows the schematic diagram of the evaluation circuit and the layout of the relevant PCB. L6386 PIN DESCRIPTION
N. 1 2 3 4 5 6 7 8 9 Name LIN (*) SD (*) HIN (*) VCC DIAG CIN SGND PGND LVG O Type I I I I O I Function Lower Driver Logic Input: it is compatible to Vcc voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Shut Down Logic Input: it is compatible to Vcc voltage. If it has to be pulled up the suggested resistor value is 5-10Kohm. [Vil Max = 1.5V, Vih Min = 3.6V] Low Side Driver Logic Input: it is compatible to V CC voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Low Side Driver Logic Input: it is compatible to Vcc voltage.[Vil Max = 1.5V, V ih Min = 3.6V] Diagnostic Output: Open Drain Comparator Input Ground reference for logic signals Power Ground reference for the Low Voltage Gate Driver Low Side Driver Output: Low side driver output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedence also in SD conditions. Not Connected O O Upper Driver Floating Driver: layout care has to be taken to avoid undervoltage spikes on this pin High Side Driver Output: High side driver output:the output stage can deliver 400mA ource and 650mA sink [Typ. Values] The circuit guarantees 0.3V max between this pin and Vout (@ Isink = 10mA) with V CC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedence also in SD conditions. Bootstrapped Supply Voltage: Bootstrap supply voltage: it is the upper driver floating supply [with UVLO: Typ. VBth1 = 11.9V, VBth2 = 9.9V]. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
10, 11 12 13
N.C. Vout HVG
14
Vboot
(*) The pull-down internal resistor is typically some hundreds Kohm.
6/17
AN994 APPLICATION NOTE
Figure 5. L6386 Internal Block Diagram.
BOOTSTRAP DRIVER 14 VCC 4 UV DETECTION UV DETECTION
Vboot H.V. R R HVG DRIVER 13 OUT V CC 12 LVG LVG DRIVER 9 PGND 8 VREF + 5 DIAG TO LOAD HVG CBOOT
HIN
3
LEVEL SHIFTER LOGIC
S
SD
2
LIN
1
SGND
7
6
CIN
D97IN520D
Figure 6. L6386 Schematic diagram of the evaluation circuit.
+HV D1 C5 CN1 LIN HIN VCC R1 JP1 DIAG C7 CIN 5 6 SD HVG VBOOT C4 12 D2 R2
CN3
1 3 4 2
13 14
CN2
L6386
8
OUT PGND R3
CN4
SGND
7
9
LVG D3 GND
R7 C1 C2 C6
D98IN831A
R4
R5
R6
7/17
AN994 APPLICATION NOTE
Figure 6a. L6386 - PCB and component layout of the fig. 6.
60mm
50mm
Silk
Comp. Layer
Back Layer
8/17
AN994 APPLICATION NOTE
L6387 (internal diagram fig.7) is based on L6385 structure. It has two separate inputs, but there is also an interlocking function to avoid undesired simultaneous turn on of both Power Switches (see Truth Table). The Vcc turn on and turn off thresholds have been lowered to 6V and 5.5V(Typ.). There is no UVLO on the upper driving section. L6387 PIN DESCRIPTION
N. 1 2 3 4 5 Name LIN (*) HIN (*) VCC GND LVG Type I I I O Function Low Side Driver Logic Input: it is compatible to Vcc voltage. [Vil Max = 1.5V, Vih Min = 3.6V] High Side Driver Logic Input: it is compatible to Vcc voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Supply input voltage [with very low UVLO: Vccth1 = 6V & Vccth2 = 5.5V (typ.). Ground Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@Isink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low. Upper Driver Floating Reference: layout care has to be taken to avoid undervoltage spikes on this pin. High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max between this pin and Vout (@ Isink = 10mA) with Vcc > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normally used to hold the pin low. Bootstrap Supply Voltage:it is the upper driver floating supply . The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
6 7
Vout HVG
O O
8
Vboot
(*) The pull-down internal resistor is typically some hundreds Kohm.
Figure 7. L6387 Internal Block Diagram.
BOOTSTRAP DRIVER
8
Vboot H.V. Cboot
VCC
3
UV DETECTION R
HVG DRIVER S VCC 7
HVG
HIN
2
LOGIC
LEVEL SHIFTER
OUT 6 5 LVG DRIVER LVG TO LOAD
LIN
1
4
GND
D00IN1135
L6387: TRUTH TABLE
INPUT OUTPUT HIN LIN HVG LVG 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0
9/17
AN994 APPLICATION NOTE
BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 8a). In the L6384-5-6-7 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 8b An internal charge pump (fig. 8b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : CEXT =
Qgate Vgate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A (e.g. L6385 and L6386 (L6384 100A)), so if HVG T ON is 5ms,CBOOT has to supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical L6384, L6385 and L6386 value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken into account. The following equation is useful to compute the drop on the bootstrap DMOS: Vdrop = Icharge Rdson Vdrop = Qgate Rdson Tcharge
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 6s. In fact: Vdrop = 30nC 125 0.8V 5s
Vdrop has to be considered when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time (e.g. Fig. 13,14,15), an external diode can be used, and this is the reason for which the external diode D1 is dotted in fig 2,4 and 6. Working at very low frequencies the high side driver is very long. So CBOOT voltage can drop because of of HVG steady state consumption. To avoid extremely large capacitor (> 1-2F) an external charge pump can be added (see fig 9 as example).The diodes used are bot high voltage ones: they are signal diodes because the high voltage drops on C1 and C2. It is mandatory the diodes to have a low parasitic capacitance, because C1 and C2 have to be greater than diodes capacitance. The oscillator has to work in order to balance the high voltage side consumption, and the minimum frequency is fixed by C1
10/17
AN994 APPLICATION NOTE
and C2 values (with C1,2 33pF f>250-300KHz). Moreover the oscillator has to be able to sustain the dV/dt of the OUT pin. Figure 8. Bootstrap Driver
DBOOT
VS
VBOOT H.V. HVG VOUT TO LOAD LVG CBOOT
VS
VBOOT H.V. HVG VOUT TO LOAD LVG C BOOT
a
b
D99IN1056
Figure 9. External Charge Pump
HV
IN VCC DT/SD
VBOOT
1 2 3 4
L6384
8 7 6 5
HVG OUT LVG 330pF Cboot 200nF
LOAD
GND
1N4148
1N4148 1N4148
1N4148
C1 33pF
C2 33pF
VCC HCF4069UB
Cx
11/17
AN994 APPLICATION NOTE
APPLICATION IDEAS Here below, follows a collection of application hints that highlight the versatility and flexibility of this family of High and Low side drivers. Moreover their simplicity and compactness make these devices a cost effective solution. For further information on these ICs, please refer to: AN1263: "Using the internal bootstrap current capability of the L6384, L6385 & L6386 in driving a six transistor inverter bridge" by D. Nolan. "L6384, L6385, L6386 & L6387 tricks and tips" by P. Meloncelli. AN1299: Figure 10. L6384 C three-phase motor control.
+HV
IN1 VS
1 2
7 8
L6384
6
SD/DT
3 4
5
+HV
2 VDD
7 8
C
IN2 SD/DT
1
L6384
6
POSITION/SPEED SENSE
3 4
5 MOTOR WINDING
+HV SD SD/DT
3
7 8
2 1
L6384
6 5
IN3
4
CURRENT FEEDBACK
D98IN823
12/17
AN994 APPLICATION NOTE
Figure 11. L6384 Dimmable lamp ballast.
+HV 5
4 16
VS
1 2
7
HVG
Q1 L
L6384
8 OUT
11
VCO
HC4046 15 3
6 BCD "OFF-LINE" 5 4
12
LVG
Q2
C
FEEDBACK
+
D98IN824
Figure 12. L6384 Half Bridge Converter
VOUT
~
EMI
GND 4 7 HVG
DT/ST IN
3 1
L6384
6 BCD "OFF-LINE" 2 VCC 5 OUT VBOOT CBOOT VOUT
8
LVG
7 6
12
11
14
10
13 9
L4990
8 5 2 15 4 3
AUX SUPPLY
FEEDBACK
OPTO
TL431
D99IN1063
13/17
AN994 APPLICATION NOTE
Figure 13. L6385 Horizontal deflection stage.
+HV
B+ STAGE
STP5NK40Z
VB+
VB+ VS SYNC PROCESSOR HVG B+ CONTROL HIN 3 7 8 VBOOT OUT H-YOKE +VCC
2
L6385
BCD "OFF-LINE"
6
CS STP16NF06
H-OUTPUT STAGE
LIN
1 4
5
LVG
H-YOKE STAGE
VB+
H-YOKE
CS BUH715
STP16NF06 H-YOKE STAGE
D98IN825
14/17
AN994 APPLICATION NOTE
Figure 14. L6385 Two switch forward converter.
~
EMI
4 7 HVG
L6385
2 1 BCD "OFF-LINE" 3 VCC 5 6 OUT CBOOT 8 VBOOT LVG VOUT
7 6
12
11
14
10
13
9
L4990
8 5 2 15 4 3
AUX SUPPLY
FEEDBACK
OPTO
TL431
D98IN826A
Figure 15. L6385 Asymmetrical half bridge.
+HV
VCC
3
7 6
HVG OUT VBOOT
2 IN 1
L6385
8
M
4
BCD "OFF-LINE"
5
LVG
D98IN827
15/17
AN994 APPLICATION NOTE
Figure 16. L6386 H-bridge with cycle by cycle control.
+HV VS
4 HIN SD LIN 3 2 1 5 DIAG GND
13
HVG
HVG
13
4 3 HIN SD LIN
L6386
12
OUT VBOOT
M TACHO
OUT VBOOT
12
L6386
14
2 1
14 BCD "OFF LINE" 8 CIN 6 9
LVG
LVG
BCD "OFF LINE"
6 CIN 8 5 GND
9
DIAG
SD
HIN
LIN
VDD
C
D98IN828A
16/17
AN994 APPLICATION NOTE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
17/17

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