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HYB18RL25632AC HYB18RL25616AC
Graphics & Speciality DRAMs
256 Mbit DDR Reduced Latency DRAM
Version 1.60 July 2003
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Edition Jun. 2002 This edition was realized using the software system FrameMaker. Published by Infineon Technologies, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Infineon Technologies 6/30/2002. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of Infineon Technologies, may only be used in life-support devices or systems2 with the express written approval of Infineon Technologies. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
HYB18RL25616/32AC Revision History: Current Version 1.60 Subjects (major changes since last revision) Previous Version: 1.42 29,30 29,30 31 36 23 16 15 23 23 34 29,30 29,30 31 36 23 16 15 23 23 34 Reversed scan reg order to match device Renumbered scan registers starting with 0 to n-1 Added numbers to the scan chain portion of Figure 27 added preliminary current values to the table. Suppressed note 4 for tQSQ, restored to min and max value instead of absolute Remove MRS only after power up restriction. Suppressed note that 2k NOPs not needed in HSTL mode, 2k NOPs are needed. changed tCKDQS from 2.7...3.7 to 2.9...3.9 ns. Increased tQSQ from +/-0.3ns to +/-0.35 ns VDDQ nominal changed to 1.85V, +/- 100mV Previous Version: 1.43
Previous Version: 1.44
Previous Version: 1.50
Version 1.60
Page 2
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 1.3 1.3.1 1.4 1.5 1.5.1 1.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Configuration Package and Ballout . . . . . . . . . . . . . . . . . . . . . . .6 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Clocks, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . .15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . .17 Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Write - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Read - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 x16 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 x32 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 JTAG TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 JTAG TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . .34 JTAG DC Operating Conditons . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 JTAG AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35 JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.2.1 2.5.2.2 2.5.3 2.5.3.1 2.5.3.2 2.5.4 2.5.4.1 2.5.4.2 2.6 2.6.1 2.6.2 2.6.2.1 2.6.2.2 2.6.3
3
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . 29
3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 3.4.1 3.4.2 3.5 3.6 3.7 3.8 3.9 3.10 3.11
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 4.2 4.3 4.4 4.5 4.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Recommended Power & DC Operation Ratings . . . . . . . . . . . . . . . .37 AC Operation Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 1 Overview
1.1
Features
256 Megabit (256M) 0.17m process technology Cyclic bank addressing for maximum data out bandwidth Organization 8M x 32, 16M x 16 in 8 banks Non-multiplexed addresses Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR Up to 600Mb/sec/pin data rate Programmable Read Latency (RL) of 5..6 Data valid signal (DVLD) activated as Read Data is available Data Mask signals (DM0 / DM1) to mask first and second part of write data burst IEEE 1149.1 compliant JTAG Boundary Scan Pseudo-HSTL 1.8V IO Supply Internal autoprecharge Refresh requirements: 32ms at 100C junction temperature (8k refresh for each bank, 64k refresh commands must be issued in total each 32ms) Package T-FBGA 144 2.5V VEXT, 1.8V VDD, 1.8V VDDQ Table 1 Key timing parameters (Configuration Example x32, x16 device) -3.3 300 26.7 8 6 -4.0 250 28.0 7 5 -5.0 200 25.0 5 5 Units MHz ns cycles cyles
Speed Sort Frequency tRC Read latency
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
1.2 General Description
The Infineon 256M Reduced Latency DRAM (RLDRAM) contains 8 banks x 32 Mb of memory accessible with 32bit or 16bit I/O's in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high data bandwidth. RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.
1.3
Ball Configuration Package and Ballout
T-FBGA 144 package 256 Mbit DDR Reduced Latency DRAM
Figure 1
BOTTOM VIEW
SIDE VIEW 1.20 max
12
11
10
9
8
7
6
5
4
3
2
1 A B
D E F G H J
18.5
17
K L M N P R T U V
4 0.8 8.8 11
Note: All dimensions in mm
Version 1.60
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O 0.51 typ
C
1
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Figure 2
Ballout of 256 Mbit Reduced Latency DRAM (x32 configuration)
1 A B C D E F G H J K L M N P R T U V
VSS
2
VEXT
3
VREF
4
VSS
5
6
7
8
9
VSS
10
VEXT
11
TMS
12
TCK
VSS
DQ8
DQ9
VSSQ
VSSQ
DQ1
DQ0
VSS
VSS
DQ10
DQ11
VDDQ
VDDQ
DQ3
DQ2
VSS
VSS
DQS1
DQS1#
VSSQ
VSSQ
DQS0#
DQS0
VSS
VSS
DQ12
DQ13
VDDQ
VDDQ
DQ5
DQ4
VSS
DM0
DQ14
DQ15
VSSQ
VSSQ
DQ7
DQ6
DVLD
A5
A6
A7
VDD
VDD
A2
A1
A0
A8
A9
VSS
VSS
VSS
VSS
A4
A3
AS#
BA2
VDD
VDD
VDD
VDD
BA0
CK
WE#
REF#
VDD
VDD
VDD
VDD
BA1
CK#
A18
CS#
VSS
VSS
VSS
VSS
A14
A13
A15
A16
A17
VDD
VDD
A12
A11
A10
DM1
DQ22
DQ23
VSSQ
VSSQ
DQ31
DQ30
NC
VSS
DQ20
DQ21
VDDQ VDD VSSQ
VDDQ
DQ29
DQ28
VSS
VSS
DQS2
DQS2#
VSSQ
DQS3#
DQS3
VSS
VSS
DQ18
DQ19
VDDQ
VDDQ
DQ27
DQ26
VSS
VSS
DQ16
DQ17
VSSQ
VSSQ
DQ25
DQ24
VSS
VSS
VEXT
VREF
VSS
VSS
VEXT
TDO
TDI
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Figure 3
Ballout of 256Mbit Reduced Latency DRAM (x16 configuration)
1 A B C D E F G H J K L M N P R T U V
VSS
2
VEXT
3
VREF
4
VSS
5
6
7
8
9
VSS
10
VEXT
11
TMS
12
TCK
VSS
NC
NC
VSSQ
VSSQ
DQ1
DQ0
VSS
VSS
NC
NC
VDDQ
VDDQ
DQ3
DQ2
VSS
VSS
NC
NC
VSSQ
VSSQ
DQS0#
DQS0
VSS
VSS
NC
NC
VDDQ
VDDQ
DQ5
DQ4
VSS
DM0
NC
NC
VSSQ
VSSQ
DQ7
DQ6
DVLD
A5
A6
A7
VDD
VDD
A2
A1
A0
A8
A9
VSS
VSS
VSS
VSS
A4
A3
AS#
BA2
VDD
VDD
VDD
VDD
BA0
CK
WE#
REF#
VDD
VDD
VDD
VDD
BA1
CK#
A19
CS#
VSS
VSS
VSS
VSS
A14
A13
A15
A16
A17
VDD
VDD
A12
A11
A10
DM1
NC
NC
VSSQ
VSSQ
DQ15
DQ14
A18
VSS
NC
NC
VDDQ VDD VSSQ
VDDQ
DQ13
DQ12
VSS
VSS
NC
NC
VSSQ
DQS1#
DQS1
VSS
VSS
NC
NC
VDDQ
VDDQ
DQ11
DQ10
VSS
VSS
NC
NC
VSSQ
VSSQ
DQ9
DQ8
VSS
VSS
VEXT
VREF
VSS
VSS
VEXT
TDO
TDI
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Note: NC : No Connect : These signals are internally connected and have parasitic characterisitcs of an IO. They may optionally be connected to ground for improved heat dissipation.
1.3.1
Ball Description Ball description
Type Input Detailed Function Input Clock: CK and CK# are differential clock inputs. Addresses and commands are latched on the rising edge of CK, input data is latched on the both edges of CK. CK# is ideally 180 degrees out of phase with CK. Chip Select: CS# enables the command decoder when low and disables it when high. When the command decoder is disabled new commands are ignored, but internal operations continue. Command Inputs: Sampled at the positive edge of CK. AS#, WE# and REF# define (together with CS#) the command to be executed. Address Inputs: A[19:0] define the row and column addresses for READ and WRITE operations. During an MODE REGISTER SET the address inputs A[17:0] define the register settings. The addresses are sampled at the rising edge of CK. In the x32 configuration, A[19] is not used. In the x16 configuration with BL2, A[19] is used. Bank select: Select to which internal bank a command is being applied.
Table 2
Ball
CK, CK#
CS# AS#, WE#, REF#
Input
Input
A[19:0]
Input
BA[0:2] DQ[31:0]
Input
Data Input / Output: The DQ signals form the 32 bit data bus. During READ commands the Input/ data is referenced to both edges of DQS/DQS#. During WRITE commands the data is Output sampled at both edges of CK. Data read strobes : DQSx and DQSx# are the differential data read strobes. During READs, they are transmitted by the RLDRAM and edge-aligned with data. DQSx is ideally Output 180 degrees out of phase with DQSx#. DQS0, DQS0# are aligned with DQ0-DQ7. DQS1, DQS1# are aligned with DQ8-DQ15. DQS2, DQS2# are aligned with DQ16-DQ23. DQS3, DQS3# are aligned with DQ24-DQ31. Output Data Valid: The DVLD indicates valid output data. DVLD is edge-aligned with DQSx, DQSx#. Data Mask: DM0 and DM1 are the input masks for WRITE data. The first half of the Input data burst is masked when DM0 is sampled HIGH along with the WRITE command. The second half of the input data burst is masked when DM1 is sampled HIGH along with the WRITE command. IEEE 1149.1 Clock Input: JEDEC standard 1.8V IO levels. These pin must be tied to VSS if the JTAG function is not used in the circuit. IEEE 1149.1 Test Inputs: JEDEC standard 1.8V IO levels. These pins may be left not connected if the JTAG function is not used in the circuit.
DQSx, DQSx#
DVLD
DM0, DM1
Input
TCK TMS, TDI TDO VREF VEXT VDD VDDQ VSS VSSQ
Input Input
Output IEEE 1149.1 Test Output: JEDEC standard 1.8V IO level tracking VDDQ. Supply Supply Supply Supply Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range. Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range. Power Supply: Isolated Output Buffer Supply. 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Supply Power Supply: GND Supply Power Supply: Isolated Output Buffer Supply. GND
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Table 2
Ball NC
Ball description
Type Detailed Function No Connect : These pins may be connected to ground to improve heat dissipation.
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
1.4 Functional Block Diagram
Functional Block Diagram 8M x 32 Configuration
Figure 4
A0-A18, B0, B1, B2
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array Bank 2
Column Decoder
Row Decoder Memory Array Bank 3
Sense Amp and Data Bus
Sense Amp and Data Bus
Sense Amp and Data Bus
Bank 0
Bank 1
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array Bank 6
Column Decoder
Sense Amp and Data Bus
Column Decoder
Row Decoder Memory Array Bank 7
Sense Amp and Data Bus
Sense Amp and Data Bus
Sense Amp and Data Bus
Bank 4
Bank 5
Output Data Valid
Data read strobe
Input Buffers
Output Buffers
Control Logic and Timing Generators
CK
Note:
When the BL4 setting is used, A18 is a "Don't Care"
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This specification is preliminary and subject to change without notice
VREF
WE#
REF#
AS#
DM0
DM1
CK#
CS#
DVLD
DQS[3:0], DQS#[3:0]
DQ0-DQ31
Sense Amp and Data Bus
Column Decoder
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Figure 5
Functional Block Diagram 16M x 16 Configuration
A0-A19, B0, B1, B2
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array Bank 2
Column Decoder
Row Decoder Memory Array Bank 3
Sense Amp and Data Bus
Sense Amp and Data Bus
Sense Amp and Data Bus
Bank 0
Bank 1
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array
Column Decoder
Row Decoder Memory Array Bank 6
Column Decoder
Sense Amp and Data Bus
Column Decoder
Row Decoder Memory Array Bank 7
Sense Amp and Data Bus
Sense Amp and Data Bus
Sense Amp and Data Bus
Bank 4
Bank 5
Output Data Valid
Data read strobe
Input Buffers
Output Buffers
Control Logic and Timing Generators
Note: 1 When the BL4 setting is used, A19 is a "Don't Care". Note: 2 In the 16Mx16 configuration, only DQS[1:0] & DQS#[1:0] are used
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This specification is preliminary and subject to change without notice
VREF
REF#
WE#
AS#
DM0
DM1
CK#
CS#
CK
DVLD
DQS[1:0], DQS#[1:0]
DQ0-DQ15
Sense Amp and Data Bus
Column Decoder
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
1.5
1.5.1
Commands
Command Table
According to the functional signal description the following command sequences are possible. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK. Table 3 Truth table
Operation No Operation Deselect4) Mode Register Set2) Read Write Auto Refresh Device State Any Any Idle Any Any Idle MRS READ WRITE Code NOP CS# L H L L L L AS# H X L L L H WE# REF# H X L H L H H X L H H L A[19:0]1)3) X X Valid Valid Valid X BA]2:0] X X X Valid Valid Valid DM]1:0] X X X X Valid X
Note: 1: X = "Don't Care" ; H = Logic HIGH; L = Logic LOW Note: 2: Only A[17:0] are used for the MRS command. Note: 3: See Table 4
Table 4
Address Width table
Data Width 32 A[18:0] A[17:0] 16 A[19:0] A[18:0]
Burst Length BL 2 BL 4
Note: 1: The x32 and x16 configurations have different ballouts (see Fig. 2 & Fig. 3)
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
1.5.2 Description of Commands Description of Commands
The NOP command is used to perform a no operation to the RLDRAM; this is equal to deselecting the chip. Use NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. The Mode Register is set via the address inputs A[17:0]. See the mode register description in the register description section. The MRS command can only be issued when all banks are idle and no bursts are in progress. The READ command is used to initiate a burst read access to a bank. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[19:0] selects the data location within the bank. The WR command is used to initiate a burst write access to a bank. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[19:0] selects the data location within the bank. Input data appearing on the DQs is written to the memory array subject to the DMx input logic levels appearing coincident with the WRITE command. If DM0 is registered LOW, the first half of the burst Write data will be written to the memory array, if registerd HIGH this data will be ignored i.e, this part of the data word will not be written. If DM1 is registered LOW the second half of the burst Write data will be written to the memory array, if registerd HIGH this data will be ignored i.e, this part of the data word will not be written. The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank. The value on the BA[2:0] inputs selects the bank. The refresh address is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AREF command. The RLDRAM requires 64k AREF cycles at an average periodic interval of 0.49 s1) (maximum). To improve efficiency a burst of eight AREF commands (One AREF for each bank) can be posted to the RLDRAM at an average periodic interval of 3.9s2).
Table 5
Command Description
DESEL / NOP
MRS
READ
WRITE
AREF
Note: 1: Actual refresh is 32ms/8K/8 = 0.488s Note: 2: Actual refresh is 32ms/8K = 3.90s
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2.1
Functional Description
Clocks, Commands and Addresses
Clock Command/Address Timings
Figure 6
tCK CK# CK CMD, ADDR Vaild Vaild
tCKH
tCKL
Vaild tAS, tCS tAH, tCH
Don't Care
Table 6
General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts
-3.3 -4.0 max min max min -5.0 max Units Symbol
Parameter Clock Clock Cycle Time Clock high level width Clock low level width Setup Times
min
tCK tCKH tCKL
3.3 0.45 0.45
0.55 0.55
4.0 0.45 0.45
0.55 0.55
5.0 0.45 0.45
0.55 0.55
ns tCK tCK ns
Address/Command input setup time tAS, tCS Hold Times Address/Command input hold time tAH, tCH
1.0
-
1.0
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and Address signals. Note: 2. The signal imput slew rate must be 1V/ns. Note: 3. CK/CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially).
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2.2 Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VREF) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF. There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when both voltages are at their nominal level. However, the pad supply must not be applied before the core supplies. Maintain all pins in NOP conditions. 2. Maintain stable conditions for 200 s minimum. 3. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS (Figure 7). 4. After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles. 5. After tRC the chip is ready for normal operation. Figure 7
VEXT VDD VDDQ VREF
Power Up Sequence
CK# CK Com. MRS MRS MRS RF RF RF A.C.
Add tMRSC
BA0
BA1
BA7
min. 200 s
min. 2048 6 x 2048 cycles cycles
MRS: RF: A.C.:
tRC
MRS command REFRESH Any command
Don't Care
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2.3 Mode Register Set Command (MRS)
Figure 8 Mode Register Set
CK# CK CS#
The mode register stores the data for controlling the operating modes of the memory. It programs the RLDRAM configuration, burst length, test mode and IO options. During a Mode Register Set command the address inputs A<17:0> are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the RLDRAM. The mode register may be set anytime as long as all command are completed, and the RLDRAM is in an idle state (no persistent commands). Figure 9 Mode Register Set Timing
AS#
WE#
CK# CK Command MRS NOP NOP A.C.
REF#
A[17:0]
COD
tMRSC
MRS: command A.C.: MRS Any command Don't Care
A[19:18]
BA<2:0>
COD: Code to be loaded into the register
Table 7
Timing Parameters MRS
-3.3 -4.0 -5.0 Units tCK Symbol tMRSC
Don't Care
Parameter Mode Register Set cycle time
min max min max min max 4 - 4 - 4 -
Notes
Figure 10 Mode Register Bitmap
A<17:7> A6 A5 A4 A3 A2 A1 A0
Reserved2
Test Mode
Driver Strength
Matched Mode
Burst Length
RLDRAM Configuration
A5 0 1
Driver Strength1 8mA (default) Do not use
A3 0 1
Burst Length 2 (default) 4
A2 0 0 0
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
RLDRAM configuration 3 (default) 1 2 3 4 Do not use Do not use Do not use
A6 0 1
Test Mode (default) test mode
A4 0 1
Matched Mode inactive (default) active3
0 1 1 1 1
Note: 1 HSTL compliant current specification Note: 2 Bits A<17:6> must be set to zero Note: 3 Automatic IO impedance calibration is activated in Matched Mode
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2.4 Configuration Table
The following table shows, for different operating frequencies, the different RLDRAM configurations that can be programmed into the Mode Register. The Read Latency (tRL) and the Write Latency (tWL) used by the RLDRAM for the two Burst Lengths (BL) are also indicated. Finally the minimum row cycle time (tRC) in clock cycles and in ns are shown as well. The shaded areas correspond to configurations that are not allowed. Table 8 RLDRAM configuration table
Configuration Frequency
tRC tRL tWL (BL2) tWL (BL4)
tRC
Unit
cycles cycles cycles cycles
ns ns ns ns ns ns ns ns ns ns ns ns
1
5 5 2 1
2
6 5 2 1
3
7 5 2 1
4
8 6 3 2
26.7 20 10 6.7
300 MHz (-3.3)
tRL tWL (BL2) tWL (BL4) tRC
28.0 20.0 8.0 4.0 25.0 25.0 10.0 5.0 30.0 25.0 10.0 5.0 35.0 25.0 10.0 5.0
32.0 24.0 12.0 8.0 40.0 30.0 15.0 10.0
250 MHz (-4.0)
tRL tWL (BL2) tWL (BL4) tRC
200 MHz (-5.0)
tRL tWL (BL2) tWL (BL4)
Note: 1: The speed sort -3.3 provides parts functional up to 300MHz in the configuration 4 only. The functionality of the configurations 1,2 and 3 is not guaranteed for speed sort -3.3. Note: 2: The speed sort -4.0 provides parts functional up to 250MHz in the configurations 3 and 4 only. The functionality of the configurations 1 and 2 is not guaranteed for speed sort -4.0. Note: 3: The speed sort -5.0 provides parts functional in all configurations.
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2.5
2.5.1
Writes (WR)
Write - Basic Information
CK# CK CS#
Figure 11 Write command
Write accesses are initiated with a WRITE command, as shown in Figure 11. Row and bank addresses are provided together with the WRITE command. During WRITE commands, data will be registered at both edges of CK according to the programmed burst length BL. The first valid data is registered with the first rising CK edge WL (Write Latency) cycles after the WRITE command has been issued. Any WRITE burst may be followed by a subsequent READ command. Figure 17 and Figure 18 illustrate the timing requirements for a WRITE followed by a READ for a burst of 2 and 4 respectively. Setup and hold time for incoming DQs relative to the CK edges are specified as tDS and tDH. The first or the second part of the incoming data burst is masked if the corresponding DMx signal is sampled HIGH along with the WRITE command. Setup and hold time for DM is the same as for addresses and commands.
AS#
WE#
REF#
DM[1:0]
DM
A[19:0]
A
BA[2:0]
BA
A: BA: DM: Don't Care
Address Bank Address Data Mask
Figure 12 Basic Write Burst Timing
CK# CK Write Latency tDS tDH tDS tDH
DQ
D0
D1
D2
D3
Don't Care
Table 9
WRITE Timing Parameters
-3.3 -4.0 min 0.5 0.5 max - - -5.0 min 0.5 0.5 max - - Units ns ns Notes Symbol tDS tDH
Parameter Data-in to CK Setup Time Data-in to CK Hold Time
min 0.5 0.5
max - -
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and Address signals. Note: 2. The signal imput slew rate must be 1V/ns. Note: 3. CK/CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially).
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2.5.2 Write - Cyclic Bank Access
2.5.2.1 Burst Length (BL) = 2
Figure 13 Write Burst Basic Sequence, BL = 2, WL = 3
0 CK# CK Com WR WR WR WR WR WR WR WR WR 1 2 3 4 5 6 7 8
Add
A BA0
A BA1 WL = 3
A BA2
A BA3
A BA4
A BA5
A BA6
A BA7
A BA0
DQ
D0a
D0b
D1a
D0d D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
A/BAx: WR: Dxy: WL:
address A of bank x WRITE Data part y to bank x Write Latency
Don't Care
2.5.2.2 Burst Length (BL) = 4
Figure 14 Write Burst Basic Sequence, BL = 4, WL = 2
0 CK# CK Com WR NOP WR NOP WR NOP WR NOP WR 1 2 3 4 5 6 7 8
Addr
A BA0 WL = 2
A BA1
A BA2
A BA3
A BA0
DQ
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
D3a
A / BAx: WR: Dxy: WL:
address A of bank x WRITE Data part y to bank x Write Latency
Don't Care
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2.5.3 Write Data Mask Timing
2.5.3.3 Burst Length (BL) = 2
Figure 15 Write Data Mask Timing, BL = 2, WL = 2
0 CK# CK Com WR WR WR WR WR WR WR WR WR 1 2 3 4 5 6 7 8
Add
A BA0
A BA1
A BA2
A BA3
A BA4
A BA5
A BA6
A BA7
A BA0
DM0
DM1 WL = 2
DQ
D0a
D0b
D1b D0d
D2a
D4a
D4b
D5a
D5b
D6a
Data not written into the memory
A/BAx: WR: Dxy: WL:
address A of bank x WRITE Data part y to bank x Write Latency
Don't Care
2.5.3.4 Burst Length (BL) = 4
Figure 16 Write Data Mask Timing, BL=4, WL = 1
0 CK# CK Com WR NOP WR NOP WR NOP WR NOP WR 1 2 3 4 5 6 7 8
Addr
A BA0
A BA1
A BA2
A BA3
A BA0
DM0 WL = 1 DM1 DQ D0a D0b D0c D0d D1c D1d D2a D2b
A / BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency
Data not written into the memory
Don't Care
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2.5.4 Write followed by Read
2.5.4.5 Burst Length (BL) = 2
Figure 17 Write followed by Read BL = 2, RL = 5, WL = 2
0 CK# CK Com WR RD RD NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
Addr
A BA0
A BA1 WL = 2
A BA2
RL = 5 tCKDQS DQ D0a D0b Q1a Q1b Q2a Q2b
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y of bank x Read Latency Don't Care
2.5.4.6 Burst Length (BL) = 4
Figure 18 Write followed by Read BL = 4, RL = 5, WL = 1
0 CK# CK Com WR RD NOP RD NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
Addr
A BA0 WL = 1
A BA1
A BA1 RL = 5 tCKDQS
DQ
D0a
D0b
D0c
D0d
Q1a
Q1b
Q1c
Q1d
Q2a
Q2b
Q2c
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y of bank x Read Latency Don't Care
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HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
2.6
2.6.1
Reads (RD)
Read - Basic Information
Figure 19 READ command
CK# CK CS#
Read accesses are initiated with a READ command, as shown in Figure 19. Row and bank addresses are provided with the READ command. During READ bursts the memory device drives the read data edge aligned with the DQS signal. After a programmable read latency, data is available at the outputs. The data valid signal indicates that valid read data will be present on the bus after 0.5clock cycles. The skew between DQS and CK is specified as tCKDQS. tQSQ is the skew between DQS edge and the last valid data edge. tQSQ is derived at each DQS clock edge and is not cumulative over time. After completion of a burst, assuming no other commands have been initiated, output data will go High-Z. Back to back READ commands are possible, producing a continuous flow of output data. The data valid window is derived for each DQS transition and is defined as: min(tDQSH, tDQSL) - 2* tQSQmax. Any READ burst may be followed by a subsequent WRITE command. Figure 23 shows the corresponding timing requirements for a READ followed by a WRITE. A READ to WRITE delay has to be buit in in order to prevent bus contention. Some systems having long line lengths or severe skews may need additional idle cycles inserted. Figure 20 Basic Read Burst Timing
tCKH CK# CK tCKDQS DQS DQS# tQSVLD DVLD tCKL tCK
AS#
WE#
REF#
A<19:0>
A
BA<2:0>
BA
A: BA: Don't Care
Address Bank Address
tDQSL
tDQSH
tQSVLD
DQ
D0 tQSQ
D1
D2 tQSQ
D3
data valid window
Don't Care
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Table 10 READ Timing Parameters for -2.5, -3-3 and -5.0 speed sorts Parameter Symbol -3.3 min max -4.0 min max -5.0 min max Units Notes
Read Cycle Timing Parameters for Data and Data Strobe DQS / DQS# high pulse width DQS / DQS# low pulse width DQS edge to Clock edge skew DQS edge to output data edge DQS edge to Data Out HiZ DQS edge to DVLD edge
tDQSH tDQSL tCKDQS tQSQ tQSQHZ tQSVLD
0.4 0.4 2.9 -0.35 -0.4
0.6 0.6 3.9 0.35 0.4 0.4
0.4 0.4 2.9 -0.35 -0.4
0.6 0.6 3.9 0.35 0.4 0.4
0.4 0.4 2.9 -0.35 -0.4
0.6 0.6 3.9 0.35 0.4 0.4
tCK tCK ns ns ns ns
4
Note: 1 All timings are measured relatively to the crossing point of CK/CK# (DQSx/DQSx#), and to the crossing point with VREF of the Command and Address signals. Note: 2. The signal imput slew rate must be 1V/ns. Note: 3. CK/CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). Note: 4. tDQSQ and tQSQHZ are absolute values.
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2.6.2 Read - Cyclic Bank Access
2.6.2.1 Burst Length (BL) = 2
Figure 21 Read Burst, BL = 2, RL = 5
0 CK# CK Com. RD RD RD RD RD RD RD RD RD 1 2 3 4 5 6 7 8
Addr.
A BA0
A BA1
A BA2
A BA3
A BA4
A BA5
A BA6
A BA7 tCKDQS
A BA0
RL = 5 DQS DQS# DQ
Q0a Q0b
Q1a
Q1b
Q2a
Q2b
Q3a
A / BAx: RD: Qxy: RL:
address A of bank x READ Data part y from bank x Read Latency
Don't Care
2.6.2.2 Burst Length (BL) = 4
Figure 22 Read Burst, BL = 4, RL = 5
0 CK# CK Com. RD NOP RD NOP RD NOP RD NOP RD 1 2 3 4 5 6 7 8
Addr.
A BA0
A BA1
A BA2
A BA3 tCKDQS
A BA0
RL = 5 DQS DQS# DQ
Q0a Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
A / BAx: RD: Qxy: RL:
address A of bank x READ Data part y from bank x Read Latency
Don't Care
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2.6.3 Read followed by Write
Figure 23 Read followed by Write, BL=2, RL = 5, WL = 2
0 CK# CK Com. RD NOP NOP NOP NOP WR WR NOP NOP 1 2 3 4 5 6 7 8
Addr.
A BA0 RL = 5
A BA1
A BA2 WL = 2 tCKDQS
DQ
Q0a
Q0b
D1a
D1b
D2a
D2b
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y from bank x Read Latency Don't Care
Figure 24 Read followed by Write, Write data on bus prior Read data, BL=2, RL=5, WL=2
0 CK# CK Com. RD WR NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8
Addr.
A BA0
A BA1 WL = 2 RL = 5 tCKDQS
DQ
D1a
D1b
Q0a
Q0b
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y from bank x Read Latency Don't Care
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Figure 25 Read followed by Write, BL=4, RL = 5, WL = 1
0 CK# CK Com. RD NOP NOP NOP NOP NOP NOP WR NOP NOP NOP 1 2 3 4 5 6 7 8 9 10
Addr.
A BA0 RL = 5 tCKDQS
A BA1 WL = 1
DQ
Q0a
Q0b
Q0c
Q0d
D1a
D1b D1c
D1d
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y from bank x Read Latency Don't Care
Figure 26 Read followed by Write, write data on system bus prior read data, BL=4, RL=5, WL=1
0 CK# CK Com. RD WR NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8
Addr.
A BA0
A BA1 WL = 1 RL = 5 tCKDQS
DQ
D1a
D1b
D1c
D1d
Q0a
Q0b
Q0c
Q0d
DQS DQS#
A/BAx: WR: Dxy: WL: address A of bank x WRITE Data part y to bank x Write Latency RD: Qxy: RL: READ Data part y from bank x Read Latency Don't Care
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HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port operates fully complient with IEEE Standard 1149.1-1990. It contains a TAP controller, instruction register, boundary scan register, bypass register, and ID code register. It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied low while TDI, TMS and TDO may be left unconnected. Upon power-up, the TAP will come up in a reset state which will not interfere with the normal operation of the device.
3.1
3.1.1
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. The pin must be tied low if the TAP is not used. 3.1.2 Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. 3.1.3 Test Data-In (TDI)
The TDI pin is used to serially input information into the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any register (see Figure 27). This pin may be left unconnected if the TAP is not used. 3.1.4 Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Figure 28). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see Figure 27). This pin may be left unconnected if the TAP is not used.
3.2
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and shifted out of the RLDRAM test circuitry (see Figure 27). Only one register is selected at a time through the instruction register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. 3.2.1 Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in Figure 27. Upon power-up, the instruction register is internally preloaded with the IDCODE instruction. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. 3.2.2 Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows data to be shifted through the RLDRAM with minimal delay. The bypass register is set LOW during the Capture-DR state when the BYPASS instruction is loaded in the instruction register.
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3.2.3 Boundary Scan Register
The boundary scan register is connected to all the IO pins on the RLDRAM. It allows to observe and control the data flowing into and out of the device, depending on the instruction being loaded in the instruction register. The boundary scan register is 104 bits long. The register is the same for the x16 and x32 configurations of the RLDRAM. Pins not used in the x16 configurations read a HIGH into the boundary scan register in the Capture-DR controller state. Differential inputs (CK/CK#) and outputs (DQSx/DQSx#) are equipped with two boundary scan cells each. Thus, the differential nature of these pins is not visible to the test circuitry. However, it is recommended that during testing differential signals are always applied to these pin pairs. 3.2.4 Identification (ID) Register
The ID register is loaded with a hardwired, vendor-specific, 32-bit code during the Capture-DR state when the IDCODE instruction is loaded in the instruction register. The code can be shifted out when the TAP controller is in the Shift-DR state. Two different codes are implemented for the x16 and x32 configurations of the RLDRAM (see Table 11). . Table 11 ID Register Definition
Revision Number Part Number Infineon JEDEC Code L S B
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x16 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 x32 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1
3.3
TAP Instructions
The TAP implements the 6 instructions BYPASS, EXTEST, SAMPLE/PRELOAD and IDCODE for user access (see Table 12). The implementation of these instructions fully complies with the IEEE standard. All other instructions are reserved and should not be used. Table 12 JTAG Instruction Register
Instruction Register Code Hex 00 x7 .. x0 0000 0000 EXTEST Selects the boundary scan register to be connected between TDI and TDO. Data received at input pins are sampled and loaded into the boundary scan register. Data driven by output pins are determined from values contained in the boundary scan register. Instruction Description
05
0000 0101
SAMPLE / PRELOAD Selects the boundary scan register to be connected between TDI and TDO. Data receivedat input pins are sampled and loaded int the boundary scan register. initial ouput data are shifted into the boundary scan register prior to an EXTEST intruction. Instruction does not interfere with the normal operation of the device. IDCODE BYPASS Selects the ID code register to be connected to TDI and TDO. Instructin does not interfere with the normal operation of the device. Selects the bypass register to be connected between TDI and TDO. Instruction does not interfere with the normal operation of the device.
21 FF
0010 0001 1111 1111
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3.4
3.4.1
Boundary Scan Exit Order
x16 Configuration
Scan Reg# 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
Reg Content Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb
Pin Descr . I/O I/O I/O I/O O O I/O I/O I/O I/O O I I I I I I I I I I I I I I I I/O I/O I/O I/O O O I/O I/O I/O I/O
Pin Name DQ1 DQ0 DQ3 DQ2 DQS0# DQS0 DQ4 DQ5 DQ6 DQ7 DVLD A1 A2 A0 A3 A4 B0 CK CK# B1 A14 A13 A10 A12 A11 A18 DQ31 DQ30 DQ29 DQ28 DQS3 DQS3# DQ26 DQ27 DQ24 DQ25
Ball # B10 B11 C10 C11 D10 D11 E11 E10 F11 F10 F12 G11 G10 G12 H12 H11 J11 J12 K12 K11 L11 L12 M12 M10 M11 N12 N10 N11 P10 P11 R11 R10 T11 T10 U11 U10
Ball # B3 B2 C3 C2 D3 D2 E2 E3 F2 F3 F1 G2 G3 G1 H1 H2 J2 J1 K1 K2 L2 L1 M1 M3 M2 N1 N3 N2 P3 P2 R2 R3 T2 T3 U2 U3
Pin Name DQ9 DQ8 DQ11 DQ10 DQS1# DQS1 DQ12 DQ13 DQ14 DQ15 DM0 A6 A7 A5 A8 A9 B2 AS# WE# REF# CS# A19 A15 A17 A16 DM1 DQ23 DQ22 DQ21 DQ20 DQS2 DQS2# DQ18 DQ19 DQ16 DQ17
Pin Descr . I/O I/O I/O I/O O O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I/O I/O I/O I/O O O I/O I/O I/O I/O
Reg Content Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data
Scan Reg # 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Note: Note: Note: Note:
1: Input pins are connected to Observe-Only Boundary Scan Register Cells. 2: Output pins are connected to Force-Only Boundary Scan Register Cells. 3: IO pins are connected to Control-and-Observe Boundary Scan Register Cells. 4: For BL 4 the content of the register 101 will be set to 0 if A19 is not connected. Otherwise, the register content will be equal to the logical value applied to pin A19.
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
3.4.2 x32 Configuration
Scan Reg# 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
Reg Content Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb
Pin Descr . I/O I/O I/O I/O O O I/O I/O I/O I/O O I I I I I I I I I I I I I I I I/O I/O I/O I/O O O I/O I/O I/O I/O
Pin Name DQ1 DQ0 DQ3 DQ2 DQS0# DQS0 DQ4 DQ5 DQ6 DQ7 DVLD A1 A2 A0 A3 A4 B0 CK CK# B1 A14 A13 A10 A12 A11 A18 DQ31 DQ30 DQ29 DQ28 DQS3 DQS3# DQ26 DQ27 DQ24 DQ25
Ball # B10 B11 C10 C11 D10 D11 E11 E10 F11 F10 F12 G11 G10 G12 H12 H11 J11 J12 K12 K11 L11 L12 M12 M10 M11 N12 N10 N11 P10 P11 R11 R10 T11 T10 U11 U10
Ball # B3 B2 C3 C2 D3 D2 E2 E3 F2 F3 F1 G2 G3 G1 H1 H2 J2 J1 K1 K2 L2 L1 M1 M3 M2 N1 N3 N2 P3 P2 R2 R3 T2 T3 U2 U3
Pin Name DQ9 DQ8 DQ11 DQ10 DQS1# DQS1 DQ12 DQ13 DQ14 DQ15 DM0 A6 A7 A5 A8 A9 B2 AS# WE# REF# CS# A19 A15 A17 A16 DM1 DQ23 DQ22 DQ21 DQ20 DQS2 DQS2# DQ18 DQ19 DQ16 DQ17
Pin Descr . I/O I/O I/O I/O O O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I/O I/O I/O I/O O O I/O I/O I/O I/O
Reg Content Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb Data Enb Data Data Data Enb Data Enb Data Enb Data Enb Data
Scan Reg # 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Note: Note: Note: Note:
1: Input pins are connected to Observe-Only Boundary Scan Register Cells. 2: Output pins are connected to Force-Only Boundary Scan Register Cells. 3: IO pins are connected to Control-and-Observe Boundary Scan Register Cells. 4: For BL 4 the content of the register 101 will be set to 0 if A18 is not connected. Otherwise, the register content will be equal to the logical value applied to pin A18.
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
3.5 TAP Operation
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the RLDRAM clock operates much faster. As a consequence, it is possible that an input or output will undergo a transition right at the moment when the TAP takes the snapshot in the Capture-DR state of the SAMPLE/PRELOAD instruction. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. To guarantee that the boundary scan register will capture the correct value of a signal, the signal must meet the TAP's setup and hold time ( tCS plus tCH) around the rising edge of TCK.
3.6
JTAG TAP Block Diagram
Figure 27 TAP Block Diagram
TMS TCK
Test Access Port (TAP) Controller
0
Bypass Register
TDI
7
6
5
4
3
2
1
0
TDO
Instruction Register
31 30
1
0
ID Code Register
103
0
102
1
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HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
3.7 JTAG TAP Controller State Diagram
Figure 28 TAP Controller State Diagram
TM S TCK T e s t A c c e s s P o r t (T A P ) C o n tr o lle r
0
B y p a s s R e g is te r
TDI
7
6
5
4
3
2
1
0
TDO
In s tr u c tio n R e g is te r
31
30
1
0
ID C o d e R e g is te r
103
0
102
1
3.8
JTAG DC Operating Conditons
Symbol Limit Values min. typ. max. VDDQ + 0.3 VREF - 0.15 VREF - tbd V V V V VREF + 0.15 VSSQ -0.3 VREF + tbd Unit Notes
Parameter
Input logic high voltage, VTIH DC Input logic low voltage, DC VTIL
Output logic high VTOH voltage (IOH = -tbd mA) Output logic low voltage VTOL (IOL = tbd mA)
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
3.9 JTAG AC Operating Conditions
Parameter Input logic high voltage, AC Input logic low voltage, AC Input Slew Rate Input and Output Timing Reference Level Symbol VTIH VTIL TTSL VREF min. VREF+0.3 VSSQ-0.3 1.0 typ. VDDQ/2 max. VDDQ+0.3 VREF-0.3 Unit V V V/ns V Notes
3.10
JTAG AC Electrical Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TCK Low to TDO Valid TDI Set Up Time TMS Set Up Time TDI Hold Time TMS Hold Time Symbol TTCK TTCKH TTCKL TTCKDO TTDIS TTMSS TTDIH TTMSH min. 20 10 10 5 5 5 5 max. 10 Unit ns ns ns ns ns ns ns ns Notes
3.11
JTAG Timing Diagram
TTCK TTCKH TTCKL
TCK TTMSH TTMSS
TMS TTDIH TTDIS
TDI TTCKDO
TDO
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 4
4.1
Electrical Characteristics
Absolute Maximum Ratings
Storage temperature range............................................- 55 to + 150 C Input/output pins voltage........................................- 0.3 to VDDQ + 0.3V Inputs and VREF voltage.......................................- 0.3 to VDDQ + 0.3V Power supply voltage VDD ............................................... - 0.3 to + 2.1V Power supply voltage VEXT ................................ ........... - 0.3 to + 2.8V Power supply voltage VDDQ ............................................ - 0.3 to + 2.1V Junction Temperature......................................................... 0C to 100C
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4.2
Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted. Table 13 Power & DC Operating Conditions Parameter Power Supply Voltages Power Supply Voltage for I/O Reference Voltage Input leakage current CLK Input leakage current Output leakage current VREF Current Matched Impedance 1.8V Input logic high voltage, DC Input logic low voltage, DC Output high voltage Output low voltage HSTL strong Input logic high voltage, DC Input logic low voltage, DC Output high voltage Output low voltage
Note: Note: Note: Note:
Symbol VEXT VDD VDDQ Vref IIL IILC IOL IREF
min. 2.38 1.75 1.75 0.49* VDDQ -5 -5 -5 -5
typ. 2.5 1.8 1.85 0.9
max. 2.63 1.85 1.95 0.51* VDDQ +5 +5 +5 +5
Unit Notes V V V V A A A A 1,2,3
VIH VIL VOH VOL
Vref + 0.15 VSSQ - 0.3 VDDQ -
- - -
VDDQ + 0.3 V Vref - 0.15 V 0 V V
VIH VIL VOH VOL
Vref + 0.1 VSSQ - 0.3 VDDQ-0.4 -
- - -
VDDQ + 0.3 V Vref - 0.1 V 0.4 V V
1. Typically the value of Vref is expected to be 0.5 * VDDQ of the transmitting device. Vref is expected to track variations in VDDQ 2. Peak to peak AC noise on Vref may not exceed 2% Vref (DC) 3. Vtt of the transmitting device must track Vref of the receiving device. 4. Recommanded on board decouping capacitors : VDDQ: 2 x 0.1F / device, VDD: 2 x 0.1F / device, VREF : 0.1F / device, VEXT: 0.1F / device.
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
4.3 AC Operation Ratings
Symbol min. typ. max. Unit Notes
Table 14 AC Operation Conditions for Matched Impedance mode Parameter Matched Impedance 1.8V Input logic high voltage, AC DDR Input logic low voltage, AC DDR Clock Differential Input Voltage (CLK/ CLK#) Clock Input Crossing Point (CLK/ CLK#) I/O Reference Voltage HSTL strong Input logic high voltage, AC DDR Input logic low voltage, AC DDR Clock Differential Input Voltage (CLK/ CLK#) Clock Input Crossing Point (CLK/ CLK#) I/O Reference Voltage VIH VIL VID VIX Vref Vref + 0.3 VSSQ - 0.3 0.6 Vref - 0.15 0.49*VDDQ - - - Vref VDDQ + 0.3 Vref - 0.3 VDDQ + 0.6 Vref + 0.15 0.51*VDDQ V V V V V VIH VIL VID VIX Vref Vref + 0.3 VSSQ - 0.3 0.6 Vref - 0.15 0.49*VDDQ - - - Vref VDDQ + 0.3 Vref - 0.3 VDDQ + 0.6 Vref + 0.15 0.51*VDDQ V V V V V
4.4
Output Test Conditions
Figure 29 Output Test Circuits
+ Vtt = 0.5 x V DDQ
50 Ohm
DQ
Test point 20 pF
DQ
Test point 10 pF
HSTL
Matched Impedance Mode
Note: VDDQ=1.8V 0.1V, TJ = 0 C to 100 C
4.5
Pin Capacitances
Table 15 Pin Capacitances Pin A<19:0>, BA<2:0>, CS#, AREF#, WE# CLK, CLK# DQ<31:0>, DQS0, DQS0#, DQS1, DQS1#, DVLD, DM Min 2.0 2.0 2.0 Typ. 3.0 3.0 3.0 Max 4.0 4.0 4.0 Unit pF pF pF
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HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
4.6 Operating Currents
Limit Values x16 VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT VDD VEXT tbd tbd 205 tbd 200 85 tbd tbd 500 75 415 115 tbd tbd 435 135 375 115 tbd tbd 150 75 120 75 tbd tbd 155 135 125 120 x32 tbd tbd tbd tbd 230 85 tbd tbd tbd tbd 480 115 tbd tbd tbd tbd 480 115 tbd tbd tbd tbd 135 80 tbd tbd tbd tbd 135 tbd
Table 16 IDD Specifications and Conditions (these values are preliminary and will change) Parameter Symbol/ Freq 300MHz 250MHz 200MHz 300MHz 250MHz 200MHz 300MHz 250MHz 200MHz 300MHz 250MHz Standby Current 200MHz 300MHz Auto Refresh Current 250MHz 200MHz Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA tCK=min All banks idle, CS=1 64k refresh commands/ 32ms tCK=min All banks idle, CS=1 address/data toggling one time/4 clk clock inputs Notes Burst Length = 2 tCK=min, tRC=min, 1 bank active, Address change one time during min tRC, Read/Write command cycling1.) Burst Length = 4 tCK=min, tRC=min, 4 banks interleave, address change with each bank activation, continuous read operation 1.) Burst Length = 2 tCK=min, tRC=min, 8banks interleave, address change with each bank activation, continuous read operation 1.)
IDD1 (*) Operating Current (Average Power Supply Current)
IDD4R (*) Operating Current (Average Power Supply Current)
IDD8 (*) Operating Current (Average Power Supply Current)
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