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Omni
General Description
ision
TM
Advanced Information Preliminary Datasheet
OV7660/OV7161 CMOS VGA (640x480) CAMERACHIPTM with OmniPixelTM Technology Applications
* * * * Cellular and Picture Phones Toys PC Multimedia Digital Still Cameras
The OV7660/OV7161 CAMERACHIPTM is a low voltage CMOS image sensor that provides the full functionality of a single-chip VGA camera and image processor in a small footprint package. The OV7660/OV7161 provides full-frame, sub-sampled or windowed 8-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. This product has an image array capable of operating at up to 30 frames per second (fps) in VGA with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision CAMERACHIPs use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise (FPN), smearing, blooming, etc., to produce a clean, fully stable color image.
Key Specifications
Array Element (VGA) Digital Core Power Supply Analog I/O Power Active Standby Requirements Temperature Operation Range Stable Image 664 x 492 1.8VDC 2.45V to 2.8V 2.5V to (VDD-A+0.3V) 40 mW without loading < 10 A -20C to 80C -10C to 60C * YUV/YCbCr 4:2:2 Output Formats (8-bit) * RGB 4:2:2 * Raw RGB Data Lens Size 1/5" Lens Chief Ray Angle ~20 VGA, CIF, Max Image QCIF, QQCIF 30 fps QVGA, Transfer Rate 60 fps QQVGA Sensitivity 1.0 V/Lux-sec S/N Ratio > 48 dB (AGC off, Gamma=1) Dynamic Range > 72 dB Scan Mode Progressive Electronics Exposure Up to 510:1 (for selected fps) Gamma Correction 0.45/0.55/1.00 Pixel Size 4.2 m x 4.2 m Dark Current 30 mV/s at 60C Well Capacity 35 K e Fixed Pattern Noise < 0.03% of VPEAK-TO-PEAK Image Area 2.76 mm x 2.05 mm Package Dimensions 4155 m x 3975 m
Features
* * * * High sensitivity for low-light operation Low operating voltage for embedded portable applications Standard SCCB interface VGA, QVGA, QQVGA, CIF, QCIF, QQCIF and windowed outputs with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats VarioPixelTM method for sub-sampling formats Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Brightness Control (ABC), and Automatic Black-Level Calibration (ABLC) Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), and anti-blooming
* *
Figure 1 OV7660/OV7161 Pin Diagram
*
A1 AVDD B1
A2 AGND B2 PWDN C2 DVDD D2 PCLK E2 XCLK1
A3 SIO_C B3 SIO_D
A4 D1 B4 D0
A5 D3 B5 D2
Ordering Information
Product OV07660-KL6A (Color) OV07161-KL6A (B&W with microlens) Package CSP-22 CSP-22
VREF C1 VSYNC D1 HREF E1 DOVDD
OV7660/OV7161
D3 RESET E3 DOGND D4 D7 E4 D6 D5 D5 E5 D4
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OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Functional Description
Figure 2 shows the functional block diagram of the OV7660/OV7161 image sensor. The OV7660/OV7161 includes: * Image Sensor Array * Analog Signal Processor * A/D Converters * Digital Signal Processor (DSP) * Output Formatter * Timing Generator * SCCB Interface * Digital Video Port
Figure 2 Functional Block Diagram
G Analog Processing R B Video Port
A/D
DSP
Formatter
D[7:0]
Column Sense Amp Row Select
Exposure/Gain Detect
White Balance Detect
Image Array (664 x 492) Registers
Clock
Video Timing Generator Exposure/Gain Control White Balance Control SCCB Interface
XCLK1
HREF
PCLK
VSYNC RESET
PWDN SIO_C SIO_D
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ision
Functional Description
Image Sensor Array
The OV7660/OV7161 sensor has an active image array of 640 columns x 480 rows (307,200 pixels). Figure 3 shows a cross-section of the image sensor array.
In addition to the A/D conversion, this block also has the following functions: * Digital Black-Level Calibration (BLC) * Optional U/V channel delay * Additional A/D range controls In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application.
Figure 3 Image Sensor Array
Microlens Glass
Digital Signal Processor (DSP)
Blue Green Red
Timing Generator
In general, the timing generator controls the following functions: * Array control and frame generation (7 different format outputs) * Internal timing signal generation and distribution * Frame rate timing * Automatic Exposure Control (AEC) * External timing outputs (VSYNC, HREF/HSYNC, and PCLK)
This block controls the interpolation from Raw data to RGB and some image quality control. * Edge enhancement (a two-dimensional high pass filter) * Color space converter (can change Raw data to RGB or YUV/YCbCr) * RGB matrix to eliminate color cross talk * Hue and saturation control * Programmable gamma control * Transfer 10-bit data to 8-bit
Output Formatter
This block controls all output and data formatting required prior to sending the image out.
Analog Signal Processor
This block performs all analog image functions including: * Automatic Gain Control (AGC) * Automatic White Balance (AWB)
Digital Video Port
Register bits COM2[1:0] increase IOL/IOH drive current and can be adjusted as a function of the customer's loading.
A/D Converters
After the Analog Processing block, the bayer pattern Raw signal is fed to a 10-bit analog-to-digital (A/D) converter shared by G and BR channels. This A/D converter operates at speeds up to 12 MHz and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate).
SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.
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OV7660/OV7161 Pin Description
Table 1
Pin Number A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5
a. b.
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Pin Description
Name AVDD AGND SIO_C D1a D3 VREF PWDN SIO_D D0 D2 VSYNC DVDD HREF PCLK RESET D7 D5 DOVDD XCLK1 DOGND D6 D4 Pin Type Power Power Input Output Output Reference Input (0)b I/O Output Output Output Power Output Output Input (0) Output Output Power Input Power Output Output Function/Description Analog power supply (+2.5 VDC) Analog ground SCCB serial interface clock input YUV/RGB video component output bit[1] YUV/RGB video component output bit[3] Reference voltage - connect to ground using a 0.1 F capacitor Power Down Mode Selection 0: Normal mode 1: Power down mode SCCB serial interface data I/O YUV/RGB video component output bit[0] YUV/RGB video component output bit[2] Vertical sync output Power supply (+1.8 VDC) for digital logic core HREF output Pixel clock output Clears all registers and resets them to their default values. YUV/RGB video component output bit[7] YUV/RGB video component output bit[5] Digital power supply for I/O (VDD-IO = 2.5 to (VDD-A+03.V)) System clock input Digital ground YUV/RGB video component output bit[6] YUV/RGB video component output bit[4]
D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB) Input (0) represents an internal pull-down resistor.
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ision
Electrical Characteristics
Electrical Characteristics
Table 2 Absolute Maximum Ratings
-40C to +95C VDD-A Supply Voltages (with respect to Ground) VDD-C VDD-IO All Input/Output Voltages (with respect to Ground) Lead-free Temperature, Surface-mount process ESD Rating, Human Body model NOTE: 4.5 V 3V 4.5 V -0.3V to VDD-IO+1V 245C 2000V
Ambient Storage Temperature
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.
Table 3
Symbol VDD-A VDD-C VDD-IO IDDA IDDS-SCCB IDDS-PWDN VIH VIL VOH VOL IOH IOL IL
a. b. c.
DC Characteristics (-20C < TA < 70C)
Parameter DC supply voltage - Analog DC supply voltage - Digital Core DC supply voltage - I/O power Active (Operating) Current Standby Current Standby Current Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Output current HIGH Output current LOW Input/Output Leakage GND to VDD-IO See Note c 8 15 1 CMOS 0.9 x VDD-IO 0.1 x VDD-IO Condition - - - See Note a See Note b CMOS 0.7 x VDD-IO 0.3 x VDD-IO Min 2.45 1.62 2.25 20 1 10 20 Typ 2.5 1.8 Max 2.8 1.98 VDD-A+0.3V Unit V V V mA mA A V V V V mA mA A
VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDA = {IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 7.5 fps YUV output, no I/O loading VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby Standard Output Loading = 25pF, 1.2K
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OV7660/OV7161
Table 4
Symbol
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Functional and AC Characteristics (-20C < TA < 70C)
Parameter A/D A/D AGC Differential Non-Linearity Integral Non-Linearity Range Red/Blue Adjustment Range Min Typ + 1/2 +1 18 12 Max Unit LSB LSB dB dB
Functional Characteristics
Inputs (PWDN, CLK, RESET) fCLK tCLK tCLK:DC tS:RESET tS:REG Input Clock Frequency Input Clock Period Clock Duty Cycle Setting time after software/hardware reset Settling time for register change (10 frames required) 10 21 45 24 42 50 48 100 55 1 300 MHz ns % ms ms
SCCB Timing (see Figure 4) fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 150 KHz s ns ns s ns ns s ns ns ns ns
Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10) tPDV tSU tHD tPHH tPHL PCLK[] to Data-out Valid D[7:0] Setup time D[7:0] Hold time PCLK[] to HREF[] PCLK[] to HREF[] * VDD: AC Conditions: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V 5ns, Maximum SCCB: 300ns, Maximum * Input Capacitance: 10pf * Output Loading: 25pF, 1.2K to 2.5V 24MHz * fCLK: Version 1.91, January 24, 2005 15 8 0 0 5 5 5 ns ns ns ns ns
* Rise/Fall Times: I/O:
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ision
Timing Specifications
Timing Specifications
Figure 4 SCCB Timing Diagram
tF tLOW SIO_C tSU:STA SIO_D IN t BUF tAA SIO_D OUT t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
Figure 5 Horizontal Timing
tPCLK PCLK
t PHL HREF tSU t HD D[7:0] Last Byte First Byte tPDV Last Byte (Row Data)
tPHL
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OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Figure 6 VGA Frame Timing
510 x tLINE VSYNC 4 x tLINE 11 tLINE 480 x tLINE tLINE = 784 tP 144 tP
15 tLINE
HREF 640 tP 80 tP HSYNC 45 tP 19 tP
D[7:0]
Invalid Data P0 - P639 Row 0 Row 1 Row 2 Row 479
Invalid Data
NOTE: For Raw data, tP = tPCLK For YUV/RGB, tP = 2 x tPCLK
Figure 7 QVGA Frame Timing
328 x tLINE VSYNC 3 x tLINE 12 x tLINE 240 x tLINE tLINE = 608 tP 288 tP HREF 320 tP 80 tP HSYNC 181 tP 27 tP 73 x tLINE
D[7:0]
Invalid Data P0 - P319 Row 0 NOTE: For Raw data, tP = tPCLK For YUV/RGB, tP = 2 x tPCLK Row 1 Row 2 Row 239
Invalid Data
Figure 8 QQVGA Frame Timing
328 x tLINE VSYNC 3 x tLINE 12 x tLINE 181 tP HREF 320 tP 80 tP HSYNC 288tP + 1tLINE 27 tP 120 x 2tLINE tLINE = 608 tP 288 tP 73 x tLINE
D[7:0]
Invalid Data P0 - P159 Row 0 Row 1 Row 119
Invalid Data
NOTE: For Raw data, tP = tPCLK / 2 For YUV/RGB, tP = tPCLK
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ision
Timing Specifications
Figure 9 CIF Frame Timing
328 x tLINE VSYNC 288 x tLINE tLINE = 608 tP 3 x tLINE HREF 352 tP 40 tP HSYNC 91 tP 125 tP 12 tLINE 256 tP 25 tLINE
D[7:0]
Invalid Data P0 - P351 Row 0 Row 1 Row 2 Row 287
Invalid Data
NOTE: For Raw data, tP = tPCLK For YUV/RGB, tP = 2 x tPCLK
Figure 10 QCIF Frame Timing
328 x tLINE VSYNC 144 x 2tLINE tLINE = 608 tP 3 x tLINE HREF 352 tP 40 tP HSYNC 256tP + 1tLINE 91 tP 125 tP 12 tLINE 256 tP 25 tLINE
D[7:0]
Invalid Data P0 - P175 Row 0 Row 1 Row 143
Invalid Data
NOTE: For Raw data, tP = tPCLK / 2 For YUV/RGB, tP = tPCLK
Figure 11 QQCIF Frame Timing
328 x tLINE VSYNC 3 x tLINE 12 x tLINE HREF 352 tP 40 tP HSYNC D[7:0] Invalid Data P0 - P87 NOTE: For Raw data, tP = tPCLK / 4 For YUV/RGB, tP = tPCLK / 2 Row 0 Row 1 Row 71 Invalid Data 256tP + 3tLINE 91 tP 125 tP 72 x 4tLINE tLINE = 608 tP 256 tP 25 tLINE
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OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Figure 12 RGB 565 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD D[7:0] Last Byte tPDV First Byte Last Byte (Row Data)
tPHL
First Byte D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] R0 G5 G3 R4
Second Byte G2 G0 B4 D[7] D[6] D[5] D[4] D[3] D[2] D[1] B0 D[0]
Figure 13 RGB 555 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD D[7:0] Last Byte tPDV First Byte Last Byte (Row Data)
tPHL
First Byte D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] R0 G4 G3 X R4
Second Byte G2 G0 B4 D[7] D[6] D[5] D[4] D[3] D[2] D[1] B0 D[0]
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ision
Timing Specifications
OV7660/OV7161 Light Response
Figure 14 OV7660/OV7161 Light Response
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OV7660/OV7161 Register Set
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Table 5 provides a list and description of the Device Control registers contained in the OV7660/OV7161. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.
Table 5
Address (Hex) 00
Device Control Register List
Register Name GAIN Default (Hex) 00 R/W RW Description AGC - Gain control gain setting * Range: [00] to [7F] AWB - Blue channel gain setting * Range: [00] to [FF] AWB - Red channel gain setting * Range: [00] to [FF] Vertical Frame Control Bit[7:6]: Bit[5]: Bit[4]: Bit[3:2]: Bit[1:0]: AGC[9:8] Fix gain1 Fix gain0 VREF end low 2 bits (high 8 bits at VSTOP[7:0] VREF start low 2 bits (high 8 bits at VSTRT[7:0]
01
BLUE
80
RW
02
RED
80
RW
03
VREF
00
RW
Common Control 1 Bit[7]: Bit[6]: Bit[5]: Reserved CCIR656 format QQVGA or QQCIF format. Effective only when QVGA or QCIF output is selected (register bit COM7[4] or COM7[3]) and related HREF skip mode based on format is selected (register COM1[3:2]) Reserved HREF skip option 00: No skip 01: YUV/RGB skip every other row for YUV/RGB, skip 2 rows for every 4 rows for Raw data 1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows for every 8 rows for Raw data AEC low 2 LSB (see registers AECHH for AEC[15:10] and AECH for AEC[9:2])
04
COM1
00
RW
Bit[4]: Bit[3:2]:
Bit[1:0]:
05 06
BAVE GEAVE
00 00
RW RW
U/B Average Level Automatically updated based on chip output format Y/Ge Average Level Automatically updated based on chip output format Exposure Value - AEC MSB 5 bits
07
AECHH
00
RW
Bit[7:6]: Bit[5:0]:
Reserved AEC[15:10] (see registers AECH for AEC[9:2] and COM1 for AEC[1:0])
08
RAVE
00
RW
V/R Average Level Automatically updated based on chip output format
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 2 Bit[7:5]: Bit[4]: Bit[3:2]: Bit[1:0]: Reserved Soft sleep mode Reserved Output Drive Capability 00: 1x 01: 2x 10: 2x 11: 4x Description
09
COM2
01
RW
0A 0B
PID VER
76 60
R R
Product ID Number MSB (Read only) Product ID Number LSB (Read only) Common Control 3 Bit[7]: Bit[6]: Bit[5]: Reserved Output data MSB and LSB swap Tri-state option for output clock at power-down period 0: Tri-state at this period 1: No tri-state at this period Tri-state option for output data at power-down period 0: Tri-state at this period 1: No tri-state at this period Horizontal average control x0: No average 01: 2 pixel average 11: 4 pixel average VarioPixel for QVGA, QQVGA, CIF, QCIF, and QQCIF Single frame output (used for Frame Exposure mode only)
Bit[4]: 0C COM3 00 RW Bit[3:2]:
Bit[1]: Bit[0]: 0D COM4 40 RW
Common Control 4 Bit[7:0]: Reserved
Common Control 5 0E COM5 01 RW Bit[7]: Bit[6:0]: System clock selection. If the system clock is 48 MHz, this bit should be set to high to get a higher frame rate Reserved
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OV7660/OV7161
Table 5
Address (Hex)
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 6 Bit[7]: Output of optical black line option 0: Disable HREF at optical black 1: Enable HREF at optical black BLC input selection 0: Use electrical black line as BLC signal 1: Use optical black line as BLC signal Reserved Enable bias for ADBLC ADBLC offset 0: Use 4-channel ADBLC 1: Use 2-channel ADBLC Reset all timing when format changes Enable ADBLC option Description
Bit[6]: 0F COM6 43 RW
Bit[5:4]: Bit[3]: Bit[2]:
Bit[1]: Bit[0]: 10 AECH 40 RW
Exposure Value Bit[7:0]: AEC[9:2] (see registers AECHH for AEC[15:10] and COM1 for AEC[1:0])
Data Format and Internal Clock Bit[7]: Digital PLL option 0: Disable double clock option, meaning the maximum PCLK can be as high as half input clock 1: Enable double clock option, meaning the maximum PCLK can be as high as input clock Use external clock directly (no clock pre-scale available) Internal clock pre-scalar F(internal clock) = F(input clock)/(Bit[5:0]+1) * Range: [0 0000] to [1 1111]
11
CLKRC
00
RW Bit[6]: Bit[5:0]:
Common Control 7 Bit[7]: SCCB Register Reset 0: No change 1: Resets all registers to default values Reserved Output format - CIF selection Output format - QVGA selection Output format - QCIF selection Output format - RGB selection Reserved Output format - Raw RGB (COM7[2] must be set high)
12
COM7
00
RW
Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]:
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 8 Bit[7]: Bit[6]: Enable fast AGC/AEC algorithm AEC - Step size limit 0: 1/16 x AEC 1: Step size = AEC Banding filter ON/OFF - In order to turn ON the banding filter, BD50ST (0x9D) or BD60ST (0x9E) must be set to a non-zero value. Reserved AGC Enable AWB Enable AEC Enable Description
13
COM8
8F
RW
Bit[5]:
Bit[4:3]: Bit[2]: Bit[1]: Bit[0]:
Common Control 9 Bit[7]: Bit[6:4]: Reserved Automatic Gain Ceiling - maximum AGC value 000: 2x 001: 4x 010 8x 011: 16x 100: 32x 101 64x 110: 128x 111: 128x Reserved Data format - VSYNC drop option 0: VSYNC always exists 1: VSYNC will drop when frame data drops Enable drop frame when AEC step is larger than VSYNC Freeze AGC/AEC
14
COM9
4A
RW
Bit[3]: Bit[2]:
Bit[1]: Bit[0]:
Common Control 10 Bit[7]: Bit[6]: Bit[5]: 15 COM10 00 RW Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: 16 17 18 RSVD HSTART HSTOP XX 11 61 - RW RW Reserved Output Format - Horizontal Frame (HREF column) start high 8-bit (low 3 bits are at HREF[2:0]) Output Format - Horizontal Frame (HREF column) end high 8-bit (low 3 bits are at HREF[5:3]) Reserved HREF changes to HSYNC PCLK output option 0: PCLK always output 1: No PCLK output when HREF is low PCLK reverse HREF reverse Reserved VSYNC negative HSYNC negative
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OV7660/OV7161
Table 5
Address (Hex) 19 1A
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Device Control Register List (Continued)
Register Name VSTRT VSTOP Default (Hex) 02 7A R/W RW RW Description Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at VREF[1:0]) Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at VREF[3:2]) Data Format - Pixel Delay Select (delays timing of the D[7:0] data relative to HREF in pixel units) * Range: [00] (no delay) to [FF] (256 pixel delay which accounts for whole array) Manufacturer ID Byte - High Manufacturer ID Byte - Low Mirror/VFlip Enable Bit[7]: Bit[6]: Bit[5]: 2x gain Reserved Mirror 0: Normal image 1: Mirror image VFlip enable 1: VFlip enable Reserved (Read only = 0x7F) (Read only = 0xA2)
1B
PSHFT
00
RW
1C 1D
MIDH MIDL
7F A2
R R
1E
MVFP
00
RW Bit[4]: Bit[3:0]:
1F
LAEC
00
RW
Reserved B Channel ADBLC Result Bit[7]:
20
BOS
80
RW Bit[6:0]:
Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range (high 7 bits)
Gb channel ADBLC result Bit[7]: 21 GBOS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
Gr channel ADBLC result Bit[7]: 22 GROS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
R channel ADBLC result Bit[7]: 23 ROS 80 RW Bit[6:0]: 24 25 16 AEW AEB 78 68 RW RW Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
AGC/AEC - Stable Operating Region (Upper Limit) AGC/AEC - Stable Operating Region (Lower Limit) Version 1.91, January 24, 2005
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ision
Register Set
Table 5
Address (Hex) 26
Device Control Register List (Continued)
Register Name VPT Default (Hex) D4 R/W RW Description AGC/AEC Fast Mode Operating Region Bit[7:4]: Bit[3:0]: High nibble of upper limit High nibble of lower limit
B Channel Signal Output Bias (effective only when COM6[3] = 1) Bit[7]: 27 BBIAS 80 RW Bit[6:0]: Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
Gb Channel Signal Output Bias (effective only when COM6[3] = 1) Bit[7]: 28 GbBIAS 80 RW Bit[6:0]: 29 RSVD XX - Reserved Dummy Pixel Insert MSB 2A EXHCH 00 RW Bit[7]: Bit[6:4]: Bit[3:2]: Bit[1:0]: Reserved 3 MSB for dummy pixel insert in horizontal direction HSYNC falling edge delay 2 MSB HSYNC rising edge delay 2 MSB Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
2B
EXHCL
00
RW
Dummy Pixel Insert LSB 8 LSB for dummy pixel insert in horizontal direction R Channel Signal Output Bias (effective only when COM6[3] = 1) Bit[7]:
2C
RBIAS
80
RW Bit[6:0]:
Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
2D 2E 2F 30 31
ADVFL ADVFH YAVE HSYST HSYEN
00 00 00 08 30
RW RW RW RW RW
LSB of insert dummy lines in vertical direction (1 bit equals 1 line) MSB of insert dummy lines in vertical direction Y/G Channel Average Value HSYNC Rising Edge Delay (low 8 bits) HSYNC Falling Edge Delay (low 8 bits) HREF Control
32
HREF
A4
RW
Bit[7:6]: HREF edge offset to data output Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP) Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART) Array Current Control Bit[7:0]: Reserved
33
CHLF
00
RW
34 35-36
ARBLM RSVD
03 XX
RW -
Array Reference Control Bit[7:0]: Reserved Proprietary to OmniVision Technologies 17 Reserved
Version 1.91, January 24, 2005
OV7660/OV7161
Table 5
Address (Hex)
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Device Control Register List (Continued)
Register Name Default (Hex) R/W ADC Control Bit[7:4]: Bit[3]: Reserved ADC range adjustment 0: 1x range 1: 1.5x range ADC range adjustment 000: 0.8x 100: 1x 111: 1.2x Description
37
ADC
04
RW Bit[2:0]:
ADC and Analog Common Mode Control 38 ACOM 12 RW Bit[7:4]: Bit[3:2]: Bit[1:0]: Reserved ADC offset positive to make output greater than zero Reserved
ADC Offset Control 39 OFON 00 RW Bit[7:4]: Bit[3]: Bit[2:0]: Reserved Line buffer power down - must be set to "1" before chip power down Reserved
Line Buffer Test Option Bit[7:5]: Bit[4]: Reserved UV output value 0: Use normal UV output 1: Use fixed UV value set in registers MANU and MANV as UV output instead of chip output Output sequence 00: Y U Y V 01: Y V Y U 10: V Y U Y 11: U Y V Y Reserved Data output window reset enable
3A
TSLB
0C
RW
Bit[3:2]:
Bit[1]: Bit[0]:
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ision
Register Set
Table 5
Address (Hex)
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 11 Bit[7]: Night mode 0: Night mode disable 1: Night mode enable - If the AGC gain goes over 2, then AGC gain drops to 0 and frame rate changes by half. COM11[6:5] limits the minimum frame rate. Also, ADVFH and ADVFL will be automatically updated. Night mode insert frame option 00: Normal frame rate 01: 1/2 frame rate 10: 1/4 frame rate 11: 1/8 frame rate Reserved Banding filter value select 0: Select BD60ST[7:0] (0x9E) as Banding Filter Value 1: Select BD50ST[7:0] (0x9D) as Banding Filter Value Reserved Description
Bit[6:5]: 3B COM11 00 RW
Bit[4]: Bit[3]:
Bit[2:0]:
Common Control 12 Bit[7]: 3C COM12 40 RW Bit[6:3]: Bit[2]: Bit[1:0]: HREF option 0: No HREF when VREF is low 1: Always has HREF Reserved Enable UV average Reserved
Common Control 13 Bit[7:6]: Gamma selection for signal 00: No gamma function 01: Gamma used for Y channel only 10: Gamma used for Raw data before interpolation 11: Not allowed Reserved Enable color matrix for RGB or YUV Enable Y channel delay option Output Y/UV delay
3D
COM13
99
RW Bit[5]: Bit[4]: Bit[3]: Bit[2:0]:
3E
COM14
0E
RW
Common Control 14 Bit[7:0]: Reserved
Edge Enhancement Adjustment 3F EDGE 88 RW Bit[7:2]: Bit[1:0]: Edge enhancement threshold[7:2] Edge enhancement factor[3:2] (see register DSPC2[7:6] for Edge enhancement factor[1:0])
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19
OV7660/OV7161
Table 5
Address (Hex)
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Device Control Register List (Continued)
Register Name Default (Hex) R/W Common Control 15 Bit[7:6]: Data format - output full range enable 0x: Output range: [10] to [F0] 10: Output range: [01] to [FE] 11: Output range: [00] to [FF] RGB 555/565 option (must set COM7[2] = 1 and COM7[0] = 0) x0: Normal RGB output 01: RGB 565 11: RGB 555 Reserved Description
40
COM15
C0
RW
Bit[5:4]:
Bit[3:0]:
Common Control 16 Bit[7:6]: Bit[5]: Bit[4]: 41 COM16 10 RW Reserved Enable edge enhancement for YUV output (effective only for YUV/RGB, no use for Raw data) Edge enhancement option 0: Edge enhancement factor = (EDGE[1:0], DSPC2[7:6]) 1: Edge enhancement factor = 2 x (EDGE[1:0], DSPC2[7:6]) Reserved Color matrix coefficient double option RB average option for interpolation
Bit[3:2]: Bit[1]: Bit[0]:
Common Control 17 42 COM17 08 RW Bit[7:3]: Bit[2]: Bit[1]: Bit[0]: Reserved Matrix Coefficient 1 Matrix Coefficient 2 Matrix Coefficient 3 Matrix Coefficient 4 Matrix Coefficient 5 Matrix Coefficient 6 Matrix Coefficient 7 Matrix Coefficient 8 Matrix Coefficient 9 Matrix Coefficient Sign for coefficient 9 to 2 58 59-61 MTXS RSVD 0F XX RW - 0: Plus 1: Minus Reserved Reserved Select single frame out Tri-state output after single frame out Reserved
43-4E 4F 50 51 52 53 54 55 56 57
RSVD MTX1 MTX2 MTX3 MTX4 MTX5 MTX6 MTX7 MTX8 MTX9
XX 58 48 10 28 48 70 40 40 40
- RW RW RW RW RW RW RW RW RW
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ision
Register Set
Table 5
Address (Hex) 62 63 64 65
Device Control Register List (Continued)
Register Name LCC1 LCC2 LCC3 LCC4 Default (Hex) 00 00 10 80 R/W RW RW RW RW Lens Correction Option 1 Lens Correction Option 2 Lens Correction Option 3 Lens Correction Option 4 Lens Correction Control Description
66
LCC5
00
RW
Bit[7:3]: Bit[2]: Bit[1]: Bit[0]:
Reserved Lens correction control select Reserved Lens correction enable
67 68
MANU MANV
80 80
RW RW
Manual U Value (effective only when register TSLB[4] is high) Manual V Value (effective only when register TSLB[4] is high) Manual Banding Filter MSB
69
HV
00
RW
Bit[7:6]: Bit[5:4]: Bit[3:1]: Bit[0]: Reserved
B channel pre-gain R channel pre-gain Reserved Matrix coefficient 1 sign
6A 6B 6C-7B 7C-8A 8B-91 92 93 94-9C 9D 9E 9F
GGAIN DBLV GSP GST RSVD DM_LNL DM_LNH RSVD BD50ST BD60ST RSVD
00 3A XX XX XX 00 00 XX 99 7F XX
RW RW RW RW - RW RW - RW RW -
Band Gap Reference Adjustment Bit[7:4]: Bit[3:0]: Gamma curve Gamma curve Reserved Dummy Line low 8 bits Dummy Line high 8 bits Reserved 50 Hz Banding Filter Value (effective only when COM8[5] is low and COM11[3] is high) 60 Hz Banding Filter Value (effective only when COM8[5] is low and COM11[3] is low) Reserved DSP Control 2 A0 DSPC2 00 RW Bit[7:6]: Bit[5:0]: A1-A5 RSVD XX - Reserved Edge enhancement factor[1:0] (see register EDGE[1:0] for Edge enhancement factor[3:2]) Reserved Reserved Band gap reference adjustment
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Version 1.91, January 24, 2005 Proprietary to OmniVision Technologies 21
OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
Package Specifications
The OV7660/OV7161 uses a 22-ball Chip Scale Package (CSP). Refer to Figure 15 for package information, Table 6 for package dimensions and Figure 16 for the array center on the chip.
Note: For OVT devices that contain lead, all part marking letters are upper case. For OVT devices that are lead-free, all part marking letters are lower case Figure 15 OV7660/OV7161 Package Specifications
A 1 2 3 4 5 S2 Pin Indicator S1 5 4 J1 3 2 1
A B J2 B C D E
A B C D E
Top View (Bumps Down) Glass Die C2
Center of BGA (Die) = Center of the package C3
Bottom View (Bumps Up)
C1
C Side View
Table 6
OV7660/OV7161 Package Dimensions
Parameter Symbol A B C C1 C2 C3 D N N1 N2 J1 J2 S1 S2 647.5 557.5 Minimum 4130 3950 760 150 605 400 320 Nominal 4155 3975 820 180 640 420 350 22 5 5 700 700 677.5 587.5 707.5 617.5 m m m m Maximum 4180 4000 880 210 675 440 380 Unit m m m m m m m
Package Body Dimension X Package Body Dimension Y Package Height Ball Height Package Body Thickness Thickness of Glass Surface to Wafer Ball Diameter Total Pin Count Pin Count X-axis Pin Count Y-axis Pins Pitch X-axis Pins Pitch Y-axis Edge-to-Pin Center Distance Analog X Edge-to-Pin Center Distance Analog Y 22
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ision
Package Specifications
Sensor Array Center
Figure 16 OV7660/OV7161 Sensor Array Center
A1
A2
A3
A4
A5
2755 m
2049 m
Array Center (189.8 m, 189.3 m)
Package Center (0,0)
Sensor Array
OV7660/OV7161
NOTES: 1. This drawing is not to scale and is for reference only. 2. As most optical assemblies invert and mirror the image, the chip is typically mounted with pins A1 to A5 oriented down on the PCB.
Version 1.91, January 24, 2005
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OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
IR Reflow Ramp Rate Requirements OV7660/OV7161 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters are lower case Figure 17 IR Reflow Ramp Rate Requirements
300.0 280.0 260.0 240.0 220.0 200.0 Temperature ( ) C 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0.0 -22 -2 18 38 0.6 58 78 1.1 98 118 1.6 138 158 2.2 178 198 Time (sec) -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 2.8 218 238 3.3 258 278 3.9 298 318 338 358 369 Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
Time (min.)
Table 7
Reflow Conditions
Condition Exposure Less than 3C per second Between 330 - 600 seconds At least 210 seconds At least 30 seconds (30 ~ 120 seconds) 245C Less than 6C per second No greater than 390 seconds
Average Ramp-up Rate (30C to 217C) > 100C > 150C > 217C Peak Temperature Cool-down Rate (Peak to 50C) Time from 30C to 255C
Environmental Specifications Table 8 OV7660/OV7161 Reliability Test Results
Parameter Temperature/Humidity Temperature Cycling (Air-to-Air) Highly Accelerated Stress Test (HAST) High Temperature Storage (HTS) High Temperature Static Bias (HTSB)
a.
Test Condition 85C/85% Relative Humidity, 1000 hrs.a -25C / +125C, 72 cycles/day, 1000 cyclesa 110C / 85% Relative Humidity, 168 hrs.a 150C, 1000 hrs.a 125C, 1000 hrs.a
Pre-Condition (Moisture Level II): 125C, 24h 85C/60% RH/168h IR Reflow 235C, 10 sec, 3 cycles
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ision
Package Specifications
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. 1341 Orleans Drive Sunnyvale, CA USA (408) 542-3000
Version 1.91, January 24, 2005
Proprietary to OmniVision Technologies
25
OV7660/OV7161
CMOS VGA (OmniPixelTM) CAMERACHIPTM
Omni
ision
26
Proprietary to OmniVision Technologies
Version 1.91, January 24, 2005

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