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TECHNICAL DATA
IW4043B
Quad 3-State R/S Latches
High-Voltage Silicon-Gate CMOS
The IW4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION IW4043BN Plastic IW4043BD SOIC TA = -55 to 125 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs S X R X L H L H OE L H H H H Outputs Q High Impedance No change L H H
w
w
w
.d
sh ta a
ee
u. t4
om c
L L H H
PIN 13 = NO CONNECTION PIN 16=VCC PIN 8= GND
X = don't care
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IW4043B
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN PD PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260
Unit V V V mA mW mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IW4043B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Test Conditions VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 18 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.4 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 12.0 Unit V
VIL
V
VOH
V
VOL
VIN=GND or VCC
V
IIN IOZ
VIN= GND or VCC
A A
Maximum Three State Output in High-Impedance Leakage Current State VIN= GND or VCC VOUT= GND or VCC Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current VIN= GND or VCC
ICC
5.0 10 15 20 5.0 10 15 5.0 5.0 10 15
1 2 4 20 0.64 1.6 4.2 -2 -0.64 -1.6 -4.2
1 2 4 20 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4
30 60 120 600 0.36 0.9 2.4
A
IOL
VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V
mA
IOH
Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V
mA -1.15 -0.36 -0.9 -2.4
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IW4043B
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k, Input tr=tf=20 ns)
VCC Symbol tPHL, tPLH Parameter Maximum Propagation Delay, SET or RESET to Q (Figure 1) Maximum Propagation Delay, Output Enable to Q (Figures 2,4) Maximum Propagation Delay, Output Enable to Q (Figures 2,4) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 300 140 100 230 110 80 180 100 70 200 100 80 Guaranteed Limit -55C 25C 300 140 100 230 110 80 180 100 70 200 100 80 7.5 125C 600 280 200 460 220 160 360 200 140 400 200 160 Unit ns
tPHZ, tPZH
ns
tPLZ, tPZL
ns
tTHL, tTLH
ns
CIN
pF
TIMING REQUIREMENTS (CL=50pF, RL=200 k, Input tr=tf=20 ns)
VCC Symbol tw Parameter Minimum Pulse Width, SET or RESET (Figure 3) V 5.0 10 15 160 80 40 Guaranteed Limit -55C 25C 160 80 40 125C 320 160 80 Unit ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
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IW4043B
TEST tPHZ tPLZ tPZH tPZL
IN VCC GND VCC GND
IN GND VCC GND VCC
A GND VCC GND VCC
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM ( 1/4 of the Device)
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IW4043B
N SUFFIX PLASTIC (MS - 001BB)
A 16 9 B 1 8
Dimensions, mm Symbol A B MIN 18.67 6.10 0.36 1.14 2.54 7.62 0 2.92 7.62 0.20 0.38 10 3.81 8.26 0.36 MAX 19.69 7.11 5.33 0.56 1.78
F
L
C D F
C -T- SEATING
PLANE
N G D 0.25 (0.010) M T K M H J
G H J K L M N
NOTES: 1. imensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AC)
A 16 9
Dimensions, mm Symbol. MIN 9.80 3.80 1.35 0.33 0.40 1.27 5.72 0 0.10 0.19 5.80 0.25 8 0.25 0.25 6.20 0.50 MAX 10.0 4.00 1.75 0.51 1.27
B P
H
A B C
C R x 45
1
G
8
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
H J K M P R
NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for B - 0.25 mm (0.010) per side.
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