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19-5651; Rev 0; 12/10
14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
General Description
The MAX5214/MAX5216 are pin-compatible, 14-bit and 16-bit digital-to-analog converters (DACs). The MAX5214/MAX5216 are single-channel, low-power, buffered voltage-output DACs. The devices use a precision external reference applied through the high resistance input for rail-to-rail operation and low system power consumption. The MAX5214/MAX5216 accept a wide 2.7V to 5.25V supply voltage range. Power consumption is extremely low to accommodate most low-power and low-voltage applications. These devices feature a 3-wire SPIK-/QSPIK-/MICROWIREK-/DSP-compatible serial interface to save board space and to reduce the complexity in isolated applications. The MAX5214/ MAX5216 minimize the digital noise feedthrough from input to output with SCLK and DIN input buffers powered down after completion of each serial input frame. On power-up, the MAX5214/MAX5216 reset the DAC output to zero, providing additional safety for applications that drive valves or other transducers that need to be off on power-up. The DAC output is buffered resulting in a low supply current of 80FA (max) and a low offset error of Q0.25mV. A zero level applied to the CLR pin asynchronously clears the contents of the input and DAC registers and sets the DAC output to zero independent of the serial interface. The MAX5214/ MAX5216 are available in an ultra-small (3mm x 3mm), 8-pin FMAX(R) package and are specified over the -40NC to +105NC extended industrial temperature range. S Low-Power Consumption (80A max) S 14-/16-Bit Resolution in a 3mm x 3mm, 8-Pin MAX Package S Relative Accuracy 0.25 LSB INL (MAX5214, 14-Bit) 1.0 LSB INL (MAX5216, 16-Bit) S Guaranteed Monotonic Over All Operating Ranges S Low Gain and Offset Error S Wide 2.7V to 5.25V Supply Range S Rail-to-Rail Buffered Output Operation S Safe Power-On Reset (POR) to Zero DAC Output S Fast 50MHz, 3-Wire, SPI/QSPI/MICROWIRECompatible Serial Interface S Schmitt-Trigger Inputs for Direct Optocoupler Interface S Asynchronous CLR Clears DAC Output to Code 0 S High Reference Input Resistance for Power Reduction S Buffered Voltage Output Directly Drives 10kI Loads
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Features
MAX5214/MAX5216
Ordering Information
PART MAX5214GUA+ MAX5216GUA+ PIN-PACKAGE 8 FMAX 8 FMAX RESOLUTION (BITS) 14 16
Applications
2-Wire Sensors Communication Systems Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control and Servo Loops Portable Instrumentation Programmable Voltage and Current Sources Automatic Test Equipment
Note: All devices are specified over the -40C to +105C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
VDD REF
POR CS SCLK DIN SERIAL-TOPARALLEL CONVERTER INPUT REGISTER DAC REGISTER 14-/16-BIT DAC
MAX5214 MAX5216
OUT
BUFFER
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
CLR GND
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
ABSOLUTE MAXIMUM RATINGS
VDD to GND.............................................................-0.3V to +6V REF, OUT, CLR to GND ..............................-0.3V to the lower of (VDD + 0.3V) and +6V SCLK, DIN, CS to GND ...........................................-0.3V to +6V Continuous Power Dissipation (TA = +70NC) FMAX (derate at 4.8mW/NC above +70NC) .................387mW
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Maximum Current into Any Input or Output .................... Q50mA Operating Temperature Range ........................ -40NC to +105NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
FMAX Junction-to-Ambient Thermal Resistance (BJA) ........206NC/W Junction-to-Case Thermal Resistance (BJC) ...............42NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V, VREF = 5V, CL = 100pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER STATIC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain Temperature Coefficient REFERENCE INPUT Reference-Input Voltage Range Reference-Input Impedance DAC OUTPUT No load (typical) Output Voltage Range 10kI load DC Output Impedance Capacitive Load (Note 5) Resistive Load (Note 5) Short-Circuit Current Power-Up Time 2 CL RL VDD = 5.25V From power-down mode Series resistance = 0I Series resistance = 1kI 5 -10 Q5 25 +10 0.2 0.1 0.1 15 VDD VDD 0.2 V VREF RREF 2 200 256 VDD V kI GE (Note 4) -0.06 N INL DNL OE MAX5214 MAX5216 MAX5214 (14-bit) (Note 3) MAX5216 (16-bit) (Note 3) MAX5214 (14-bit) (Note 3) MAX5216 (16-bit) (Note 3) (Note 4) 14 16 -1 -3 -1 -1 -1.25 Q0.25 Q1 Q0.1 Q0.1 Q0.25 Q0.5 -0.04 Q2 0 +1 +3 +1 +1 +1.25 Bits LSB LSB mV FV/NC %FS ppmFS/ NC SYMBOL CONDITIONS MIN TYP MAX UNITS
I nF FF kI mA Fs
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VREF = 5V, CL = 100pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN 0.7 x VDD 0.3 x VDD VIN = 0V or VDD Q0.1 0.15 Positive and negative 1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit BW Hex code = 2000 (MAX5214), Hex code = 8000 (MAX5216) Code = 0, all digital inputs from 0V to VDD, SCLK < 50MHz Major code transition 10kHz 0.1Hz to 10Hz VDD IDD No load; all digital inputs at 0V or VDD, supply current only; excludes reference input current, midscale No load, all digital inputs at 0V or VDD fSCLK tCH tCL tCSS0 tCSH0 tCSH1 tCSA tCSF tDS tDH tCSPW tCLPW tCSC 100 5 4.5 20 20 20 0 8 8 8 0 0 12 2.7 70 0.4 0.5 14 100 0.5 2 70 1.5 5.25 80 2 50 Q1 10 TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, CLR) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Hysteresis Voltage DYNAMIC PERFORMANCE (Note 5) Voltage-Output Slew Rate Voltage-Output Settling Time Reference -3dB Bandwidth Digital Feedthrough DAC Glitch Impulse Output Noise Integrated Output Noise POWER REQUIREMENTS Supply Voltage Supply Current Power-Down Supply Current Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time CS Fall to SCLK Fall Hold Time CS Rise to SCLK Fall Hold Time CS Rise to SCLK Fall SCLK Fall to CS Fall DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse-Width High CLR Pulse-Width Low CLR Rise to CS Fall Note Note Note Note Note 2: 3: 4: 5: 6: V FA FA MHz ns ns ns ns ns ns ns ns ns ns ns ns SR V/Fs Fs kHz nV*s nV*s nV/Hz FVP-P VIH VIL IIN CIN VHYS V V FA pF V
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MAX5214/MAX5216
TIMING CHARACTERISTICS (Notes 5 and 6) (Figures 1 and 2)
Static accuracy tested without load. Linearity is tested within 20mV of GND and VDD. Gain and offset is tested within 100mV of GND and VDD. Guaranteed by design; not production tested. All timing specifications measured with VIL = VGND, VIH = VDD. _______________________________________________________________________________________ 3
14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
DIN DIN15 DIN14 tDS SCLK tCSH0 CS tCSPW CLR tCLPW tCSC 1 2 tCSS0 3 4 DIN13 DIN12 tDH 5 tCH tCL DIN11 tCP 6 7 8 14 15 tCSA tCH1 16 DIN10 DIN9 DIN8 DIN2 DIN1 DIN0
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DIN15
1
tCSF
Figure 1. 16-Bit Serial-Interface Timing Diagram (MAX5214)
DIN
DIN23
DIN22 tDS
DIN21
DIN20 tDH
DIN19 tCP 5 tCH
DIN18
DIN17
DIN16
DIN2
DIN1
DIN0
DIN23
SCLK tCSH0
1
2 tCSS0
3
4
6
7
8
22
23 tCH1 tCSA
24
1
CS tCSPW CLR tCLPW tCSC
tCL tCSF
Figure 2. 24-Bit Serial-Interface Timing Diagram (MAX5216)
4
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
(TA = +25C, unless otherwise noted.)
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Typical Operating Characteristics
MAX5214/MAX5216
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5214 toc01a
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5216 VDD = 5V
MAX5214 toc01b
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
0.75 0.50 INL (LSB) 0.25 0 -0.25 -0.50 MIN MAX MAX5214
MAX5214 toc02a
1.0 0.8 0.6 0.4 INL (LSB) 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.2
MAX5214 VDD = 5V
3.0 2.0 1.0 INL (LSB) 0 -1.0 -2.0 -3.0
1.00
-0.75 -1.00 0 16,384 32,768 49,152 65,536 2.7 3.2 3.7 4.2 4.7 5.2 DIGITAL INPUT CODE (LSB) SUPPLY VOLTAGE (V)
4096
8192
12,288
16,384
DIGITAL INPUT CODE (LSB)
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5214 toc02b
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5214 toc03a
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5216 VDD = 5V MAX
MAX5214 toc03b
3 MAX5216 2 1 INL (LSB) 0 -1 -2 -3 2.7 3.2 3.7 4.2 4.7 MIN MAX
1.00 0.75 0.50 INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
MAX5214 VDD = 5V
3 2 1 INL (LSB) 0 -1 -2 -3 -40
MAX MIN
MIN
5.2
-40
-20
0
SUPPLY VOLTAGE (V)
20 40 60 TEMPERATURE (C)
80
100
-20
0
20 40 60 TEMPERATURE (C)
80
100
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.4 0.3 0.2 INL (LSB) INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 4096 8192 12,288 16,384 DIGITAL INPUT CODE (LSB) MAX5214 VDD = 5V
MAX5214 toc04a
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 16,384 32,768 49,152 65,536 DIGITAL INPUT CODE (LSB) MAX5216 VDD = 5V
MAX5214 toc04b
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) MAX MIN MAX5214
MAX5214 toc05a
0.5
0.5
0.5
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
(TA = +25C, unless otherwise noted.)
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Typical Operating Characteristics (continued)
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5214 toc05b
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
0.4 0.3 0.2 INL (LSB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 MAX INL (LSB) 0.1 MAX5214 VDD = 5V
MAX5214 toc06a
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 MIN MAX MAX5216 VDD = 5V
MAX5214 toc06b
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7 3.2 3.7 4.2 4.7 MIN MAX MAX5216
0.5
0.5
MIN
5.2
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5214 toc07a
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5214 toc07b
OFFSET ERROR vs. TEMPERATURE
MAX5214 VDD = 5V
MAX5214 toc08a
1.25 MAX5214 1.00 OFFSET ERROR (mV) 0.75 0.50 0.25 0 2.7 3.2 3.7 4.2 4.7
1.25 MAX5216 1.00 OFFSET ERROR (mV) 0.75 0.50 0.25 0
1.25 1.00 OFFSET ERROR (mV) 0.75 0.50 0.25 0
5.2
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
1.20 1.00 OFFSET ERROR (mV) 0.80 0.60 0.40 0.20 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MAX5214 toc08b
FULL-SCALE OUTPUT vs. SUPPLY VOLTAGE
MAX5214 toc09a
FULL-SCALE OUTPUT vs. SUPPLY VOLTAGE
MAX5216 VREF = 2.5V
MAX5214 toc09b
MAX5216 VDD = 5V
2.4995 2.4993 OUTPUT VOLTAGE (V) 2.4991 2.4989 2.4987 2.4985 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) MAX5214 VREF = 2.5V
2.4995 2.4993 OUTPUT VOLTAGE (V) 2.4991 2.4989 2.4987 2.4985 2.7 3.2 3.7 4.2 4.7
5.2
SUPPLY VOLTAGE (V)
6
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
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MAX5214/MAX5216
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5214 toc10a
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5216 VDD = 5V
MAX5214 toc10b
2.4990 2.4988 OUTPUT VOLTAGE (V) 2.4986 2.4984 2.4982 2.4980
MAX5214 VDD = 5V
2.4915 2.4913 OUTPUT VOLTAGE (V) 2.4911 2.4909 2.4907 2.4905
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX5214 toc11a
SUPPLY CURRENT vs. TEMPERATURE
78 76 SUPPLY CURRENT (A) 74 72 70 68 66 64 62 60
MAX5214 toc11b
80 78 76 SUPPLY CURRENT (A) 74 72 70 68 66 64 62 60
80
VDD = 5V
VDD = 5.25V
VDD = 5V
VDD = 5.25V
MAX5214 NO LOAD VDD = VREF VOUT = MIDSCALE
-40 -20 0
VDD = 2.7V
VDD = 4V
VDD = 2.7V MAX5216 NO LOAD VDD = VREF VOUT = MIDSCALE
-40 -20 0 20 40
VDD = 4V
20
40
60
80
100
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX5214 toc11c
SUPPLY CURRENT vs. TEMPERATURE
75 SUPPLY CURRENT (A) 70 65 60 55 50 45 40
-40 -20 0 20 40
MAX5214 toc11d
80 75 SUPPLY CURRENT (A) 70 65 60 55 50 45 40
-40 -20 0 20 40
80
VDD = 5V VDD = 4V
VDD = 5.25V
VDD = 4V
VDD = 5V
VDD = 5.25V
VDD = 2.7V
MAX5214 NO LOAD VDD = VREF VOUT = ZEROSCALE
60 80 100
VDD = 2.7V
MAX5216 NO LOAD VDD = VREF VOUT = ZEROSCALE
60 80 100
TEMPERATURE (C)
TEMPERATURE (C)
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
(TA = +25C, unless otherwise noted.)
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Typical Operating Characteristics (continued)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
78 76 SUPPLY CURRENT (A) 74 72 70 68 66 64 62 60 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
75 SUPPLY CURRENT (A) 70 65 60 55 50 45 40
2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
NO LOAD VDD = VREF VOUT = MIDSCALE MAX5214
NO LOAD VDD = VREF VOUT = ZEROSCALE
MAX5214
MAX5216
MAX5216
SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER-DOWN MODE)
MAX5214 toc13
VOUT vs. TIME (EXITING POWER-DOWN MODE)
MAX5214 toc14a
1.40
NO LOAD
1.20 SUPPLY CURRENT (A) 1.00 0.80 0.60 0.40 0.20 0 2.7 3.2 3.7 4.2 4.7
TA = +25C TA = -40C TA = +105C TA = +85C TA = 0C
MAX5216 RL = 10kI VDD = 5V VREF = 5V OUT = MIDSCALE 1V/div
0V
5.2
10s/div
SUPPLY VOLTAGE (V)
VOUT vs. TIME (EXITING POWER-DOWN MODE)
MAX5214 toc14b
MAJOR CODE TRANSITION (0x8000 TO 0x7FFF)
MAX5214 toc15a
MAX5214 RL = 10kI VDD = 5V VREF = 5V OUT = MIDSCALE 1V/div
MAX5216 VDD = 5V NO LOAD REF = 5V
MAX5214 toc12b
MAX5214 toc12a
80
80
OUT = MIDSCALE AC-COUPLED 1mV/div
0V
10s/div
4s/div
8
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
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MAX5214/MAX5216
MAJOR CODE TRANSITION (0x3FFF TO 0x8000)
MAX5214 toc15b
MAJOR CODE TRANSITION (0x2000 TO 0x1FFF)
MAX5214 toc15c
MAX5216 VDD = 5V REF = 5V NO LOAD
MAX5214 VDD = 5V REF = 5V NO LOAD
OUT = MIDSCALE AC-COUPLED 1mV/div
OUT = MIDSCALE AC-COUPLED 1mV/div
4s/div
4s/div
MAJOR CODE TRANSITION (0x1FFF TO 0x2000)
SETTLING TIME HIGH
MAX5214 toc16a
MAX5214 toc15d
MAX5214 VDD = 5V REF = 5V NO LOAD
MAX5216 VDD = 5V REF = 5V
3.75V
OUT = MIDSCALE AC-COUPLED 1mV/div
1.25V
4s/div
2s/div
SETTLING TIME LOW
MAX5214 toc16b
SETTLING TIME HIGH
MAX5214 toc16c
MAX5216 VDD = 5V REF = 5V
3.75V
MAX5214 VDD = 5V REF = 5V
3.75V
1.25V
1.25V
2s/div
2s/div
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
(TA = +25C, unless otherwise noted.)
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Typical Operating Characteristics (continued)
SETTLING TIME LOW
MAX5214 toc16d
DIGITAL FEEDTHROUGH
MAX5214 toc17
MAX5214 VDD = 5V REF = 5V 3.75V
VOUT AC-COUPLED 1mV/div
1.25V
VSCLK 5V/div 2s/div 40ns/div
OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX5214 toc18
SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
3000 2500 2000 1500 1000 500 0
MAX5214 toc19
2.55 2.50 OUTPUT VOLTAGE (V) 2.45 2.40 2.35 2.30 2.25 0 1 2 3 4 5
3500 DIGITAL SUPPLY CURRENT (A)
VDD = 5V LOW T0 HIGH VDDI = 5V HIGH T0 LOW VDDI = 2.7V LOW T0 HIGH VDDI = 2.7V HIGH T0 LOW
VDD = 5V VREF = 5V
6
0
1
2
3
4
5
OUTPUT CURRENT (mA)
DIGITAL INPUT VOLTAGE (V)
REFERENCE INPUT BANDWIDTH vs. FREQUENCY
MAX5214 toc20
5 0 ATTENUATION (dB) -5 -10 -15 -20 1 10 100
1000
INPUT FREQUENCY (kHz)
10
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
Pin Configuration
TOP VIEW
REF 1 CS 2 SCLK 3 8 GND VDD OUT CLR
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MAX5214/MAX5216
MAX5214 MAX5216
7 6 5
DIN 4
MAX
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME REF CS SCLK DIN CLR OUT VDD GND Active-Low Chip-Select Input Serial-Clock Input Data In Active-Low Asynchronous Digital-Clear Input. Drive CLR low to clear the contents of the input and DAC registers and set the DAC output to zero. Buffered DAC Output Supply Voltage. Bypass VDD with a 0.1FF capacitor to GND. Ground FUNCTION Reference Voltage Input. Bypass REF with a 0.1FF capacitor to GND.
Detailed Description
The MAX5214/MAX5216 are pin-compatible and software-compatible 14-bit and 16-bit DACs. The MAX5214/ MAX5216 are single-channel, low-power, high-reference input resistance, and buffered voltage-output DACs. The MAX5214/MAX5216 minimize the digital noise feedthrough from their inputs to their outputs by powering down the SCLK and DIN input buffers after completion of each data frame. The data frames are 16-bit for the MAX5214 and 24-bit for the MAX5216. On power-up, the MAX5214/MAX5216 reset the DAC output to zero, providing additional safety for applications that drive valves or other transducers which need to be off on power-up. The MAX5214/MAX5216 contain a segmented resistor string-type DAC, a serial-in/parallel-out shift register, a DAC register, power-on-reset (POR) circuit, CLR to asynchronously clear the device independent of the serial interface, and control logic. On the falling edge
of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. The MAX5214/MAX5216 include an internal buffer on the DAC output. The internal buffer provides improved load regulation and transition glitch suppression for the DAC output. The output buffer slews at 0.5V/Fs and drives up to 10kI in parallel with 100pF. The analog supply voltage (VDD) determines the maximum output voltage range of the device as VDD powers the output buffer. The external reference input features a typical input impedance of 256kI and accepts an input voltage from +2V to VDD. Connect an external voltage supply between REF and GND to apply an external reference.
Output Amplifier (OUT)
DAC Reference (REF)
Visit www.maxim-ic.com/products/references for a list of available voltage-reference devices.
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
The MAX5214/MAX5216 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSP. The interface provides three inputs: SCLK, CS, and DIN. The chip-select input (CS) frames the serial data loading at DIN. Following a chip-select input high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 16-bit for the MAX5214 and 24-bit for the MAX5216. The first 2 bits are the control bits followed by 14 data bits (MSB first) for the MAX5214 and 22 data bits (MSB first) for the MAX5216 as shown in Tables 1 and 2. The serial input register
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Serial Interface
transfers its contents to the input registers after loading 16/24 bits of data and updates the DAC output immediately after the data is received on the 16-/24-bit falling edge of the clock. To initiate a new data transfer, drive CS high and keep CS high for a minimum of 20ns before the next write sequence. The SCLK can be either high or low between CS write pulses. Figures 1 and 2 show the timing diagram for the complete 3-wire serial interface transmission. The MAX5216 DAC code is unipolar binary with VOUT = (code/65,535) x VREF. The MAX5214 DAC code is unipolar binary with VOUT = (code/16,383) x VREF. See Tables 1 and 2.
Table 1. Operating Mode Truth Table (MAX5214)
16-BIT WORD CONTROL BITS MSB D15 0 1 0 1 D14 0 0 1 1 D13 X 0 B13 D12 X X B12 D11 X A1 B11 D10 X A0 B10 D9 X X B9 D8 X X B8 X X B7 DATA BITS LSB D7 D6 X X B6 D5 X X B5 D4 X X B4 D3 X X B3 D2 X X B2 D1 X X B1 D0 X X B0 No operation Power-down (see Table 3) Write through FUNCTION
Reserved, Do Not Use
Table 2. Operating Mode Truth Table (MAX5216)
24-BIT WORD CONTROL BITS MSB D23 0 1 0 1 D22 0 0 1 1 DATA BITS LSB D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 X 0 X X X A1 X A0 X X X X X X B9 X X B8 X X B7 X X B6 X X B5 X X B4 D9 X X B3 D8 X X B2 D7 X X B1 D6 X X B0 D5- D0 X X X No operation Power-down (see Table 3) Write through FUNCTION
B15 B14 B13 B12 B11 B10
Reserved, Do Not Use
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
Writing to the Devices
1) Drive CS low, enabling the shift register. 2) Clock 16/24 bits of data into DIN (MSB first and LSB last), observing the specified setup and hold times. 3) After clocking in the last data bit, drive CS high. CS must remain high for 20ns before the next transmission is started. Figure 1 shows a write operation for the transmission of 16 bits. If CS is driven high at any point prior to receiving 16 bits, the transmission is discarded. Figure 2 shows a write operation for the transmission of 24 bits. If CS is driven high at any point prior to receiving 24 bits, the transmission is discarded. The MAX5214/MAX5216 feature an asynchronous activelow CLR logic input that sets the DAC output to zero. Driving CLR low clears the contents of both the input and DAC registers and also aborts the on-going SPI command. To allow a new SPI command, drive CLR high. The MAX5214/MAX5216 feature a software-controlled power-down mode. In power-down, the output disconnects from the buffer and is grounded with one of the three selectable internal resistors. See Table 3 for the selectable internal resistor values in power-down mode. The selected mode takes effect on the 16th SCLK falling edge of the MAX5214 and 24th SCLK falling edge of the MAX5216. The serial interface remains active in powerdown mode. In order to abort the power-down mode selection, pull CS high prior to the 16th (MAX5214) or 24th (MAX5216) SCLK falling edge. The contents of the DAC register remain valid while in power-down mode, allowing for the DAC to return to previous code by writing 0x8000 for the MAX5214 or 0x800000 for the MAX5216 (Table 3). A write to the write-through register causes the device to immediately exit power-down mode and transition to the requested code (see Tables 1 and 2).
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Power-Down Mode
MAX5214/MAX5216
Clear (CLR)
Table 3. Power-Down Modes
A1 0 0 1 1 A0 0 1 0 1 DESCRIPTION DAC powers up and returns to its previous code setting. DAC powers down; OUT is high impedance. DAC powers down; OUT connects to ground through an internal 100kI resistor. DAC powers down; OUT connects to ground through an internal 1kI resistor. Power-down DAC OPERATION CONDITION Normal operation
Table 4. MAX5216 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB g LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT (VOUT) VREF x (65,535/65,535) VREF x (32,768/65,535) = 1/2 VREF VREF x (1/65,535) 0V
Table 5. MAX5214 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB g LSB 1111 1111 1111 11XX 1000 0000 0000 00XX 0000 0000 0000 01XX 0000 0000 0000 00XX ANALOG OUTPUT (VOUT) VREF x (16,383/16,383) VREF x (8,192/16,383) = 1/2 VREF VREF x (1/16,383) 0V
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
Applications Information
When first power is applied to VDD, the input registers are set to zero so the DAC output is set to code zero. To optimize DAC linearity, wait until the supplies have settled. The MAX5214/MAX5216 output voltage range is 0 to VREF.
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Power-On Reset (POR)
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Offset Error
Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter's specified accuracy. Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.
Gain Error
Bypass VDD with high-quality 0.1F ceramic capacitors to a low-impedance ground as close as possible to the device. Minimize lead lengths to reduce lead inductance. Connect the GND to the analog ground plane. Digital and AC transient signals on GND can create noise at the output. Connect GND to the star ground for the DAC system. Refer the remote DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5214/MAX5216 GND. Carefully lay out the traces between channels to reduce AC cross-coupling. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another, especially clock signals. Avoid routing digital lines underneath the MAX5214/MAX5216 package.
Power Supplies and Bypassing Considerations
Settling Time
Layout Considerations
Digital Feedthrough
Definitions
INL is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic.
A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode.
Digital-to-Analog Glitch Impulse
Integral Nonlinearity (INL)
Digital-to-Analog Power-Up Glitch Impulse
Differential Nonlinearity (DNL)
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs
Typical Operating Circuit
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MAX5214/MAX5216
POWER SUPPLY IN 100pF 100nF 4.7F
MAX6029
OUT
VDD DAC CLR CS SCLK DIN GND OUT OUTPUT
C
MAX5214 MAX5216
REF
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 8 FMAX PACKAGE CODE U8+3 OUTLINE NO. 21-0036 LAND PATTERN NO. 90-0092
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14-/16-Bit, Low-Power, High-Performance, Buffered Single DACs MAX5214/MAX5216
REVISION NUMBER 0 REVISION DATE 12/10 Initial release DESCRIPTION
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Revision History
PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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