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EK7307 Objective DATA SHEET
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Eureka Microelectronics, Inc.
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EK7307
OBJECTIVE DATA SHEET 240-Output TFT Gate Driver IC
6F, NO.12, INNOVATION 1ST. RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. TEL 886-3-5799255 FAX 886-3-5799253
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DESCRIPTION The EK7307 is a 240-output TFT gate driver IC suitable for driving large/medium scale of TFT LCD panels. The special, COG and COF compatible, pad layout allows direct mounting on the glass. The logic inputs, the logic
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Objective-EK7307
240- Output TFT Gate Driver IC
FEATURES Output channels: Driver operating frequency: LCD supply voltage: Driver output levels: Driver "L" level is changeable Incorporates bi-directional shift register. Supports multi chip operation via output pins. Pulse width modulation function. COG and COF compatible pad layout Power and logic I/O pins on both sides Through Chip connection 240 outputs max. 1.2MHz max. VEE+43V two
outputs and the power supply pins are available on both sides and suitable for connecting multiple chips using the on chip connection as signal path.
BLOCK DIAGRAM
OUT1 OUT240
VGH VGL VEE
High voltage output and level shifters
VDD V SS
Low voltage logic and IO
OE
STV1
STV2
CPV
LR
Fig. 1 Block diagram
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PINNING INFORMATION Table 1. Pad description PAD Nr. 53 to 292 13 to 18, 327 to 332 7 t0 12, www..com 333 to 338, 346 to 349, 467 to 470 31 to 33, 38 to 41, 304 to 307 312 to 314 25 to 27 318 to 320 28 to 30 315 to 317 34 to 37 308 to 311 42 to 45 300 to 303 1 to 6 339 to 344 350 to 355 461 to 466 19 to 24 321 to 326 356 to 361 455 to 460 SYMBOL OUT1 - OUT240 VGL VEE VSS LR STV1 STV2 CPV OE I/O Start pulse input and output I I/O O Function TFT gate driver output Supply Supply Supply Shift direction selection signal
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DESCRIPTION Under the control of the shift register data, OE, and STV1 or STV2, the driver outputs are VGH or VGL and change their value at the rising edge of CPV Power supply for TFT driver output low level Negative power supply for Level shifters. Chip ground Logic ground, Reference of the voltages LR = "H" : OUT1 LR = "L" : OUT240 OUT240 (Shift left) OUT1 (Shift right) STV1 STV2
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LR = "H" Input Output LR = "L" Output Input Shift register clock The start pulse is sampled at the rising edge of CPV, input The carry pulse changes at the falling edge of CPV. Negative active When OE = "H" then the outputs are set to V GL independent of the input pin register data. This function is not synchronized with CPV. Supply Logic positive power
VDD
VGH
Supply
High voltage power and TFT driver output high level
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FUNCTIONAL DESCRIPTION Power supplies The TFT gate driver pins are either VGL or VGH.
VG H
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The TFT voltage, VGL and VEE, relative to the logic ground, can be a negative voltage value.
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VDD VS S
VG L
VE E
Fig. 2 Relative position of the different supply voltages Shift direction The input signals OE and the shift data control the value of the outputs (OUT1 till OUT240). Their value can be either VGH or VGL. The signal LR controls the shift direction of the shift register. The shift register takes its value from one of the input/output pins STV at the rising edge of the clock CPV and shifts the value to the other input/output pin STV where it is presented at the falling edge of CPV.
Table 2. LR shift direction relation LR Start pulse taken from: LR="H" STV1 LR="L" STV2
Data shift direction OUT1 OUT240 OUT240 OUT1
Output pulse given at: STV2 STV1
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OE function not synchronized with CPV.
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When the OE input is "H" than the outputs are driven to V GL regardless of the contents of the shift register. This function is
1
2
3
4
5
238
239
240
241
CPV
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STV1
OE
OUT1
OUT2
OUT3
OUT4
OUT240
STV2
Fig. 3 OE Functionality LR="H"
1
2
3
4
5
238
239
240
241
CPV
STV2
OE
OUT240
OUT239
OUT238
OUT237
OUT1
STV1
Fig. 4 OE Functionality LR= "L"
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CIRCUIT DIAGRAMS Input/Output Circuit
VGH VD D
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To Internal Circuit
VEE
VSS
(Applicable pins) LR, C P V , O E
Fig. 5 Input Circuit
To Internal Circuit
VG H
VD D Output Signal
I/O
Control Signal VE E VS S (Applicable pins) STV1, STV2
Fig. 6 Input/Output Circuit
V GH VGH Control Signal 1
O Control Signal 2
VEE
(Applicable pins) O U T 1 to OUT240
VEE
VGL
V EE
V EE
Fig. 7 TFT driver circuit
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PRECAUTIONS Precaution when connecting or disconnecting the power supply
Objective -EK7307
This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow, if voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The detail is as follows. When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power.
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RATINGS
Table 3. Absolute maximum Ratings In accordance with the Absolute Maximum Ratings System (IEC 134); See notes 1 and 2 Parameter Symbol Applicable Pins Ratings Supply voltage(1) VDD VDD VSS -0.3 to VSS+7.0 VGH VGH VEE -0.3 to VEE+45.0 VEE VEE VGH -45 to VGH+0.3 VEE -0.3 to VGH+0.3 Supply voltage(2) VGL VGL VEE -0.3 to VEE+7 VDD VDD VEE -0.3 to VEE+45.0 VSS VEE -0.3 to VGH+0.3 VSS VSS -0.3 to VDD+0.3 Input voltage VI OE, STV1 STV2, LR, CPV VEE -0.3 to VGH+0.3 Storage temperature Tstg -45 to +125 Notes: 1. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device 2. Parameters are valid over operating temperature range unless otherwise specified. Unit V V V V V V V Notes 1, 2
RECOMMENDED OPERATING CONDITIONS
Table 4. Recommended operating conditions
Parameter Supply voltage(1) Supply voltage(2) Supply voltage(3) Supply voltage(4) Operating temperature Notes: 1. All voltages are with respect to VSS unless otherwise noted (0 V). 2. Ensure that voltages are set such that VEEVSSON C
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ELECTRICAL CHARACTERISTICS
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Table 1. DC Characteristics
(VSS=0 V, VDD=+2.5V to +5.5V, VGH=+15.0 to +42.0 V, TOPR=-20 to +75 ) Applicable Parameter Symbol Conditions pins fCPV=15.7kHz fSTV=60Hz VDD=3.3V VDD Operating Supply Current IDD VEE=-15V VGH=15V www..com Output with no load Operating Supply Current IGH VGH Standby VDD=3.3V Standby quiescent IDS VDD Supply Current VEE=-15V VGG=15V Standby quiescent IGS VGH Supply Current Input pin H input voltage L input voltage Input leakage current H input voltage L input voltage H output voltage L output voltage Input leakage current VIH1 VIL1 VLI1 VIH3 VIL3 VOH VOL VLI2 IO = -100 A IO = 100 A Liquid crystal driving voltage input pin Out1 ~ Out240 = High VGL -100 100 A STV1, STV2 LR, CPV, OE Input/Output pin 0.8xVDD VDD 0.2xVDD VDD-0.4 0.4 V V V V Min. Typ. Max. Unit Note
800
A
300 600 100
A A A
0.8xVDD 0 -10
VDD 0.2xVDD 10
V V A
Liquid crystal driving voltage output pin Output leakage current VLO1 RONVGH Output ON resistance RONVGL VGH=15V VEE=-15V VOM=VGH-0.5V VOM is OUT1~OUT240 VGH=15V VEE=-15V VGL=-10v VOM=VGL+0.5V VOM is OUT1~OUT240 -50 600 OUT1 to OUT240 600 1000 50 1000 A
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Table 6. AC Characteristics (VSS= 0 V, VDD=+2.5V to +5.5V, VGH-VEE=+30.0 to +42.0 V, TOPR=-20 to +75 ) Parameter Symbol Conditions Clock period Pulse width of clock H level Pulse width of clock L level STV data set up time
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Min. 833 350 350 50 350
Typ.
Max.
Unit ns ns ns ns ns
tCPV tWH tWL tSU tH tpd1 tpd2 CL=50pF CL=300pF
data hold time
STV output delay time OUT 1 to 240 output delay time
300 800
ns ns
Timing Chart
tWL
tWH 80% 20% tSU 80% 20% tH 80% 20%
t CPV
CPV
20%
50%
50%
STV input tpd1
tpd1 60% 40%
STV output
tpd2
OUT1 to OUT240
60% 40%
OE
80% 20% tpd2 tpd2
OUT1 to OUT240
60% 40%
Fig. 8 Timing
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DEFINITIONS
Objective -EK7307
Data Sheet status Objective specification This data sheet contains target or goal specification for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specification. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS
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are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Eureka for any damages resulting from such improper use or sale.
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