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Product Specification
7.0" COLOR TFT-LCD MODULE
MODEL NAME: A070VW04 V0
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< <
>Preliminary Specification >Final Specification
Note: The content of this specification is subject to change.
(c) 2006 AU Optronics All Rights Reserved, Do Not Copy.
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Record of Revision
Version 0 Revise Date 2007/01/23 Page Draft. Content
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Contents
A. B. C. D. General Description ........................................................................................................ 3 Features ........................................................................................................................... 3 General Information ........................................................................................................ 4 Outline Dimension........................................................................................................... 5
1. TFT-LCD Module - Front View ...................................................................................................................5 2. TFT-LCD Module - Rear View.....................................................................................................................6
E.
Electrical Specifications ................................................................................................. 7
1. FPC Pin Assignment (HRS FH27-60S-0.4SH).........................................................................................7
2 Absolute Maximum Ratings ........................................................................................................................9
F.
Electrical Characteristics.............................................................................................. 10
1 TFT- LCD Typical Operation Condition (AGND = AGND2 = GND = GGND = 0V) ..................................10 2. Backlight Driving Conditions ...................................................................................................................10 3. AC Characteristics ....................................................................................................................................11 4. RGB Parallel Input Timing ........................................................................................................................11 5. Serial Control Interface AC Characteristic..............................................................................................13 6. Register Information .................................................................................................................................14 7. Register Table ............................................................................................................................................15 8. Register Description .................................................................................................................................15 9. Suggested Application Circuit .................................................................................................................19
G.
Optical specification ..................................................................................................... 21 Ratings of Ambient Environment ................................................................ 23
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I.
Packing Form................................................................................................................. 24
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A. General Description
A070VW04 is a amorphous transmissive type TFT (Thin Film Transistor) LCD (Liquid crystal Display). This model is composed of TFT-LCD, drive IC, FPC (flexible printed circuit), and backlight unit.The timing controller is embedded, so it is easily to design for consumer product.
B. Features
7-inch display size WVGA resolution and stripe dot arrangement Built in timing controller LED backlight Standby mode supported Up/Down, Left/Right reversion selection SYNC + DE Mode Parallel 18/24bits interface support 16 M color supported Wide viewing angle RoHS compliant green design
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C. General Information
NO. 1 2 3 4 5 6 7 8 9 10 Item Display Resolution Active Area Screen Size Pixel Pitch Color Configuration Color Depth Overall Dimension Weight Panel surface treatment Display Mode Unit dot mm inch mm --mm g --Specification 800RGB(H)x480(V) 152.40(H)x91.44(V) 7.0(Diagonal) 0.1905(H)x0.1905(V) R. G. B. Stripe 16.7M Colors 164(H) x 103(V) x 5.1(T) 153.5 +/- 10% Anti-Glare Normally White Note 1 Note 2 Note 3 Remark
Note 1: Below figure shows dot stripe arrangement.
.............................. ....... (1..........................480)
...
............
...
...
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.............................. ....... (1 2 3..................................2398 2399 2400)
Note 2: The full color display depends on 8-bit data signal
(pin 4~27).
Note 3: Not include blacklight cable and FPC. Refer next page to get further information.
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D. Outline Dimension
1. TFT-LCD Module - Front View
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2. TFT-LCD Module - Rear View
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E. Electrical Specifications
1. FPC Pin Assignment (HRS FH27-60S-0.4SH)
Pin no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 www..com 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol AGND2 AVDD2 VDD R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 DCLK DE HSYNC VSYNC SCL SDA CSB FBA I/O P P P I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Analog Ground Analog Power Digital Power Data input (LSB) Data input Data input Data input Data input Data input Data input Data input (MSB) Data input (LSB) Data input Data input Data input Data input Data input Data input Data input (MSB) Data input (LSB) Data input Data input Data input Data input Data input Data input Data input (MSB) Clock input Data enable signal Horizontal sync input. Negative polarity Vertical sync input. Negative polarity Serial communication clock input Serial communication data input Serial communication chip select DCDC feed back signal Description
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Version: Page: 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 www..com 60 VDD DRVA GND AGND1 AVDD1 VCOMin NC NC VCOM V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 NC VGH GVCC VGL GGND CAP P O P P P I O P P P P P P P P P P P P P P C Digital Power DCDC PWM signal Digital ground Analog ground Analog Power For external VCOM DC input (Optional) Not connect Not connect connect a capacitor Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Gamma correction voltage reference Not connect Positive power for TFT Digital Power Negative power for TFT Digital Ground Connected to a capacitor
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I: Input pin; P: Power pin; G: Ground pin; C: capacitor pin
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2 Absolute Maximum Ratings
Item Power voltage Operating temperature Storage temperature Symbol VCC AVDD Topa Condition GND=0 AGND=0 -Min. -0.5 -0.5 0 Max. 5 15 60 Unit V V Remark Note 1 Note 1 Ambient Temperature Ambient Temperature
Tstg
--
-10
70
Note 1: Functional operation should be restricted under normal ambient temperature.
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F. Electrical Characteristics
The following items are measured under stable condition and suggested application circuit.
1 TFT- LCD Typical Operation Condition (AGND = AGND2 = GND = GGND = 0V)
ITEM Symbol VCC Power supply AVDD VGH VGL Input Signal H Level L Level VIH VIL V1 ~ V5 V6 ~ V10 VCDC MIN. 3.3 TBD TBD TBD 0.7VCC GND AVDD/2 0.1 TBD TBD TBD TBD TBD TYP. MAX. 3.6 TBD TBD TBD VCC 0.3VCC AVDD - 0.1 AVDD/2 TBD UNIT V V V V V V V V V Remark
Input Reference Voltage VCOM
Note: Above every operation range is based on stable operation from suggested application circuit.
2. Backlight Driving Conditions
Parameter LED lightbar Current LED light bar Voltage LED Life Time Symbol IL VL LL Min. ----10,000 Typ. 160 12 --Max. ------Unit mA V Hr Remark ----Note 2, 3
Note 1: The LED driving condition is defined for LED module (21 LED).
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Note 2: Define "LED Lifetime": brightness is decreased to 50% of the initial value. LED Lifetime is restricted under normal condition, ambient temperature = 25 and LED lightbar voltage = 12V.
Note 3: If it uses larger LED lightbar voltage more than 12V, it maybe decreases the LED lifetime.
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3. AC Characteristics
PARAMETER Clock High time Clock Low time Clock rising time Clock falling time Hsync setup time Hsync hold time Vsync setup time Vsync hold time Data setup time Data hold time Data enable set-up time Data enable hold time
VIH VIL
SYMBOL TWCL TWCH TRCLK TACK THSU THHD TVSU TVHD TDSU TDHD TESU TEHD
CONDITIONS
MIN. 8 8 5 10 0 2 5 10 4 2
TYP. -
MAX. 1 1
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
Vs
RGB, DE, Hs CLK
TVPD
VIH VIL VIH VIL TDS, TES, THS TDH,THE,THH TCH TCL
Hs
VIH VIL
Figure 1 : Input timing details
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4. RGB Parallel Input Timing
a. Horizontal Timing
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX UNIT
DCLK frequency DCLK period Hsync Period (= THD + THBL) Active Area Horizontal blanking (= THF + THE) Hsync front porch Delay from Hsync to 1 data input (= THW + THB) Hsync pulse width Hsync back porch
st
FDCLK TDCLK TH THD THBL THF THE THW THB Function of HDL[5..0] settings
25 25 986 186
33 30.3 1056 800 256 40
40 40 1183 383 343 136 342
MHz ns DCLK DCLK CLK CLK DCLK CLK CLK
146 1 10
216 128 88
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b. Vertical Timing
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Vsync period (= TVD + TVBL) Active lines Vertical blanking (= TVF + Vsync front porch GD start pulse delay Vsync pulse width Hsync/ Vsync phase shift TVE)
TV TVD TVBL TVF TVE Function of VDL[3..0] settings TVW TVPD
497
505 480
512
Th Th
17
25 1
32 31 16 -
Th Th HS Th CLK
16 1 2
24 3 320
TH THW
HS DCLK
THF
THB
THE
R[7:0] G[7:0] B[7:0]
Rn-1
Rn
Invalid
R0
R1
R2
R3
Rn-1
Rn
Invalid
Gn-1
Gn
Invalid
G0
G1
G2
G3
Gn-1
Gn
Invalid
Bn-1
Bn
Invalid
THBL
B0
B1
B2
B3
THD
Bn-1
Bn
Invalid
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Figure 2
Horizontal input timing. (HV mode)
THBL
THD
DE DCLK
R[7:0] G[7:0] B[7:0]
Rn-1
Rn
Invalid
R0
R1
R2
R3
Rn-1
Rn
Invalid
Gn-1
Gn
Invalid
G0
G1
G2
G3
Gn-1
Gn
Invalid
Bn-1
Bn
Invalid
B0
B1
B2
B3
Bn-1
Bn
Invalid
Figure 3: Horizontal input timing. (DE mode)
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Vs
TVF
TVW TH
TVF
Hs
TVE
Line
Xn-1
Xn
X1
X2
X3
Xn-1
Xn
Invalid
TVBL
TVD
Figure 4: Vertical timing. (HV mode)
DE
Line
Xn-1
Xn
X1
X2
X3
Xn-1
Xn
Invalid
TVBL
TVD
Figure 5: Vertical timing. (DE mode)
5. Serial Control Interface AC Characteristic
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Serial clock SCL pulse duty Serial data setup time Serial data hold time Serial clock high/low CSB setup time
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TSCK TSCW TIST TIHD TSSW TCST TCHD TCD TCV TID CL=20pF
320 40 120 120 120 120 120 1 1 60 50 60
ns % ns ns ns ns ns us us ns
time
Chip select distinguish Delay from CSB to VSYNC Serial data output delay
Vsync
TCV
30%
CSB
TCST
30%
30%
TCHD D15 D14 TIHD TSSW D13 TSSW D2 D1 D0
TCD D15 D14 D13 D12
SDA
70% 30%
TIST
SCL
70% 30%
TSCK
Figure 6 : AC serial interface write mode timing
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CSB
30% TCST TCHD TCD
30%
SDA
70% 30%
D15
TIST TIHD
D14
D13
D12
D11
D10
D9
TID
D8
D7
D1
D0
TSSW TSSW
SCL
70% 30% TSCK
Figure 7 : AC serial interface read mode timing
6. Register Information
There is a total of 6 registers each containing several parameters. For a detailed description of the parameters refer to register table.The serial register has read/write function. D[15:12] are the register address, D[11] defines the read or write mode and D[10:0] are the data.
Figure 8: Serial interface write/read sequence
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1. At power-on, the default values specified for each parameter are taken. 2. If less than 16-bit data are read during the CS low time period, the data is cancelled. a. b. The write operation is cancelled. The read operation is interrupt.
3. If more than 16-bit data are read during the CS low time period, the last 16 bits are kept. a. b. c. Address & R/W are always defined form CSB falling edge. The write operation load last 11 bit data before CSB rising edge. The read operation is "D0" is output to SDA until CSB rising edge.
4. All items are set at the falling edge of the vertical sync, except R0[1:0]. 5. When GRB is activated through the serial interface, all registers are cleared, except the GRB value. 6. Register R/W setting: D11 = "L" write mode; D11 = "H" read mode.
7. The register setting values are valid when VCC already goes to high and after VSYNC starts. 8. It is suggested that VSYNC, HSYNC, DCLK always exists in the same time. But if HSYNC, DCLK stops, only VSYNC operating, the register setting is still valid. 9. If the chip goes to standby mode, the register value will still keep. MCU can wake up the chip only by changing standby mode value from low to high.
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10.The register setting values are rewritten by the influence of static electricity, a noise, etc. to unsuitable value, incorrect operating may occur. It is suggested that the SPI interface will setup as frequently as possible.
7. Register Table
Reg ADDRESS R/W D10 01 X X X X X X X 0 X 01 X X X 0 X 0 X EnGB5 (0) X EnGB4 (1) X EnGB3 (0) 1 0 1 D9 D8 01 D7 D6 DITH (1) VCOM_M (10) HDL DATA D5 U/D (0) D4 SHL (1) D3 SHDB1 (1) D2 0 D1 GRB (1) D0 STB (1) No. D15 D14 D13 D12 D11 R0 R1 R2 R3 R6 R15 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 R/W R/W R/W R/W R/W R/W
VCOM_LVL (2Fh)
EnGB12 EnGB11 EnGB10 (0) (1) (0) X X X
X : Reserved, please set to "0".
8. Register Description
R0 settings
Address Bit Description Default
0000
[10..0]
Bits 10-9 Bits7-8 Bit6 (DITH)
AUO Internal Use AUO Internal Use Dithering function. Vertical shift direction selection. Horizontal shift direction selection. AVDD DC-DC converter shutdown setting. AUO Internal Use Global reset. Standby mode setting.
01 01
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Bit5 (U/D) Bit4 (SHL) Bit3 (SHDB1) Bit2 Bit1 (GRB) Bit0 (STB)
0
Bit6
DITH function
0 1
DITH off. DITH on. (default)
Bit5
U/D function
0 1
Scan down; First line=Gn Scan up; First line=G1
Gn-1 G2 ...
...
G2
Last line=G1. (default) Last line=Gn.
Gn-1
Bit4
SHL function
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Y600
Bit3
SHDB1 function
0 1
AVDD DC-DC converter is off. AVDD DC-DC converter is on. (default)
Bit1
GRB function
0 1
The controller is reset. Reset all registers to default value. Normal operation. (default)
Bit0
STB function
0 1
T-CON, source driver and DC-DC converters are off, and all outputs are High-Z. Normal operation. (default)
R1 settings
Address Bit Description Default
0001
[8..0]
Bit9-8 Bit7-6 (VCOM_M) Bit5-0 (VCOM_LVL)
AUO Internal Use VCOM mode signal. VCOM level adjustment. Step 31.25mV/LSB @AVDD=12.5V (AVDD/400)
01
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Bit7-6
VCOM_M function.
00 01 1x
VCOM generator disabled. VCOM is generated externally. VCOM internal reference disabled. DC voltage of VCOM follows VCOMin signal. VCOM generator enabled. DC voltage of VCOM follows VCOM_LVL settings. (default)
NOTE: Please refer to to Figure40.
Bit5-0
VCOM_LVL function @V1=12.5V
00h 01h 2Fh 3Eh 3Fh
VCOM_LVL = V1/2-47*31.25mV = 4.78125V VCOM_LVL = V1/2-46*31.25mV = 4.8125V VCOM_LVL = V1/2 = 6.25V (default) VCOM_LVL = V1/2+15*31.25mV = 6.71875V VCOM_LVL = V1/2+16*31.25mV = 6.75V
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R2 settings
Address Bit Description Default
0010
[7..0]
Bit7-0 (HDL)
Horizontal start pulse adjustment function
Bit7-0
HDL function.
00h 80h FFh
THE = THEtyp - 128 CLK period. THE = THEtyp. (default) THE = THEtyp + 127 CLK period.
R3 settings
Address Bit Description Default
0011
6..0]
Bit6 Bit5 Bit4 Bit3-0 (VDL)
AUO Internal Use AUO Internal Use AUO Internal Use Vertical start pulse adjustment function
0 0 0
Bit3-0
VDL function.
0000 0001 0010 0011 0100
TVE = TVEtyp - 8 Hs period. TVE = TVEtyp - 7 Hs period. TVE = TVEtyp - 6 Hs period. TVE = TVEtyp - 5 Hs period. TVE = TVEtyp - 4 Hs period. = TVEtyp - 3 Hs period.
0101 www..comTVE 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
TVE = TVEtyp - 2 Hs period. TVE = TVEtyp - 1 Hs period. TVE = TVEtyp. (default) TVE = TVEtyp + 1 Hs period. TVE = TVEtyp + 2 Hs period. TVE = TVEtyp + 3 Hs period. TVE = TVEtyp + 4 Hs period. TVE = TVEtyp + 5 Hs period. TVE = TVEtyp + 6 Hs period. TVE = TVEtyp + 7 Hs period.
R6 settings
Address Bit Description Default
0110
[9..0]
Bit9
AUO Internal Use
0
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Version: Page: Bit8(EnGB12) Bit7(EnGB11) Bit6(EnGB10) Bit5 Bit4 Bit3(EnGB5) Bit2(EnGB4) Bit1(EnGB3) Bit0 Gamma buffer Enable for V12 Gamma buffer Enable for V11 Gamma buffer Enable for V10 AUO Internal Use AUO Internal Use Gamma buffer Enable for V5 Gamma buffer Enable for V4 Gamma buffer Enable for V3 AUO Internal Use 0 0 0
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Bitx
EnGBx function
0 1
Gamma buffer for VX is disable (High Z). Gamma buffer is enable. VX must be connected externally.
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R412 3.3V DM406 2 K C 1 A DAN217U C416 2.2uF/35V/X5R/0805 C420 3 R415 R416 C415 0.1uF/25V/X5R/0603 5V
3.3V 100K/5%/0603 R413
0/5%/0603
C417
C418
0.1uF/10V/X5R/0402
10uF/10V/X5R/0805
R414
L402 CXLP100
6.8K/5%/0603 U401 D404 1 3 SB07-03C R433 0/5%/0603 2 C430 22uF/16V/X5R/1206 EN R432 FB_1
C419
NO(0/5%/0603)
0/5%/0603
CXLP100-100(10uH)
1uF/35V/X5R/0603
C414
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9. Suggested Application Circuit
DM405 2 K C 1 A DAN217U 3 C413 0.1uF/25V/X5R/0603
+10V
AVDD2 261/5%/0603 R430 R427 110K/1%/0603 R428 C429 0/5%/0603 2.2uF/25V/X5R/0805 0/5%/0603 C428 27pF/50V/X5R/0603 R431 5.1K/5%/0603 VGH2
10nF/50V/X5R/0603
FB_2 FB_3 MP1530
1 2 3 4 5 6 7 8 /RDY FB1 COMP IN GND REF FB2 FB3 CT SW PGND IN3 GH IN2 GL EN
16 15 14 13 12 11 10 9
22nF/50V/X5R/0603
R417 10K/1%/0603
+15V
0.1uF/25V/X5R/0603
C421
R418 10K/1%/0603 DAN217U C424 3 R425 70K/1%/0603 0/5%/0603 R426 10K/1%/0603 R424 0.1uF/25V/X5R/0603 DM407 C K A
1 R429 2 10/1%/0603
R422 DAN217U R420 56K/1%/0603 0/5%/0603 0.1uF/25V/X5R/0603 DM408 C423 27pF/50V/X5R/0402 R419 C425 3 C K 2 C427 2.2uF/35V/X5R/0805 A 1
-7V
VGL2
1
0/5%/0603
C422 2.2uF/35V/X5R/0805
5.1k/1%/0603
R423
D405
NO(RB551V-30)
2
R421 10/1%/0603
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1uF/35V/X5R/0603
C426
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AVDD 3.3V
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R301 0/5%/0603 C303 C308 1.54K/1%/0603 R304 0/5%/0603 V2 R315 C304 C309 400/1%/0603 V7 0/5%/0603 C506 R314 850/1%/0603 1uF/16V/X5R/0603 1uF/16V/X5R/0603 R303 R313 VCOM 10uF/10V/X5R/K/0805 V1 V6
R302
AVDD
500/1%/0603
C301
10uF/16V/X5R/1206
0.1uF/16V/X5R/0402
C302
R305 520/1%/0603
1uF/16V/X5R/0603
R306 3.3V 0/5%/0603 R508 V3 10/5%/0603 C310 R317 C305 520/1%/0603 V8 AVDD DGND 0/5%/0603
R316
1uF/16V/X5R/0603
FBA DRVA
VCOMin VCOM
R307 400/1%/0603
1uF/16V/X5R/0603
R308 0/5%/0603 V4 R319 C306 C311 1.53K/1%/0603 V9 0/5%/0603
R318
1uF/16V/X5R/0603
R309 840/1%/0603 R310 0/5%/0603 V5 R321 C307 C322 500/1%/0603 V10 0/5%/0603 R320
V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 VGH VGL 3.3V DGND
1uF/16V/X5R/0603
1uF/16V/X5R/0603
1 2 3 R0 4 R1 5 R2 6 R3 7 R4 8 R5 9 R6 10 R7 11 G0 12 G1 13 G2 14 G3 15 G4 16 G5 17 G6 18 G7 19 B0 20 B1 21 B2 22 B3 23 B4 24 B5 25 B6 26 B7 27 DCLK 28 DE 29 HS 30 VS 31 SCL 32 SDA 33 CSB 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 AGND2 AVDD2 VDD R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 DCLK DE HSY NC VSYNC SCL SDA CSB FBA VDD DRVA GND AGND1 AVDD1 VCOMin NC NC VCOM V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 NC VGH VGL GVCC GGND CAP
CON60 C505 DGND
R311 2.4K/1%/0603 R312 0/5%/0603 0/5%/0603 R322
1uF/16V/X5R/0603
AVDD
R323
0/5%/0603
AVDD
VR301 EVM3RSX50B14 R515 VCOMin 0/5%/0603 R516 VCOM NO(10K/5%/0603)
3
2
U301A
+
1
4
-
NO(AD8565)
R324 0/5%/0603
5
0/5%/0603
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
10uF/10V/X5R/K/0805
R325
0.1uF/16V/X5R/K/0402
C323
C324
1uF/16V/X5R/0603
10uF/10V/X5R/K/0805
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G. Optical specification
Item Symbol Condition Min. Typ. Max. Unit Remark
Response Time Rise Fall Contrast ratio Viewing Angle Top Bottom Left Right Brightness White Chromaticity y
=0
Tr Tf CR
=0
-
12 18 400
20 30 -
ms ms
Note 3
At optimized viewing angle
200
Note 4
30 CR 10 50 50 50 YL X
=0 =0
40 60 60 60 200 0.30 0.32
0.35 0.37 cd/m
2
deg.
Note 5
150 0.25 0.27
Note 6
Note 1:Ambient temperature =25 , and LED lightbar voltage VL = 12 V. in the dark room. Note 2:To be measured on the center area of panel with a viewing cone of 1 by Topcon luminance meter BM-7, after 15 minutes operation. Note 3. Definition of response time: The output www..com signals of photo detector are measured when the input signals are changed from "black" to To be measured ------------------------------
"white"(falling time) and from "white" to "black"(rising time), respectively. The response time is defined as the time interval between the 10% and 90% of amplitudes. figure as below. Refer to
"White"
100% 90%
Signal(Relative value)
"Black"
"White"
10% 0%
Tr
Tf
Note 4.Definition of contrast ratio: Contrast ratio is calculated with the following formula.
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Contrast ratio (CR)=
Photo detector output when LCD is at "White" state Photo detector output when LCD is at "Black" state
Note 5. Definition of viewing angle, , Refer to figure as below.
Note 6. Measured at the center area of the panel when all the input terminals of LCD panel are electrically opened.
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ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
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H. Absolute Ratings of Ambient Environment
No. Test items Conditions Remark
1 2 3 4 5 6 7
High Temperature Storage Low Temperature Storage High Ttemperature Operation Low Temperature Operation High Temperature & High Humidity Heat Shock Electrostatic Discharge
Ta= 70 Ta= -10 Ta= 60 Ta= 0 Ta= 50 . 80% RH -10 ~60 , 50 cycle,
240Hrs 240Hrs 240Hrs 240Hrs 240Hrs 2Hrs/cycle Operation Non-operation Non-operation Non-operation JIS C7021, A-10 condition A : 15 minutes Non-operation
200V,200pF(0), once for each terminal Frequency range Stoke Sweep : 8~33.3Hz : 1.3mm :2.9G ,33.3~400Hz
8
Vibration
2 hours for each direction of X,Y,Z 4 hours for Y direction
9
Mechanical Shock
100G . 6ms, X,Y,Z 3 times for each direction
JIS C7021, A-7 condition C
Random vibration: 10
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Vibration (With Carton)
0.015G /Hz from 5~200Hz -6dB/Octave from 200~500Hz Height: 60cm 1 corner, 3 edges, 6 surfaces
2
IEC 68-34
11
Drop (With Carton)
Note 1: Ta: Ambient Temperature. Note 2: Note 2: In the standard conditions, there is not display function NG issue occurred. All the cosmetic specification is judged before the reliability stress.
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Version: Page:
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I. Packing Form
www..com
()
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
(5PCS) (30PCS)
)
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