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M68AW031A
256 Kbit (32K x8) 3.0V Asynchronous SRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.6V 32K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns, 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
Figure 1. Packages
SO28 (MS) 330m
TSOP28 (N) 8 x 13.4 mm
TSOP28 Reverse (NS) 8 x 13.4 mm
October 2004
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M68AW031A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Figure 6. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections (Normal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . 11 Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15.SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Outline . . . . . . . . 16 Table 10. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Mechanical Data . 16 Figure 16.TSOP28 - 28 Lead Normal Pinout Plastic Small Outline, Package Outline . . . . . . . . . . 17 Table 11. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data . . . 17 Figure 17.TSOP28 - 28 Lead Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . . 18 Table 12. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data. . . 18
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M68AW031A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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M68AW031A
SUMMARY DESCRIPTION
The M68AW031A is a 256 Kbit (262,144 bit) CMOS SRAM, organized as 32,768 bytes by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW031A is available in SO28 (28-lead Small Outline) and TSOP28 (28-lead Thin Small Outline, Standard and Reverse Pinout) packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A14 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground
VCC
DQ0-DQ7 E
15 A0-A14 W M68AW031A E G
8 DQ0-DQ7
G W VCC VSS
VSS
AI05935c
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M68AW031A
Figure 3. SO Connections Figure 5. TSOP Connections (Normal)
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS
1 28 2 27 3 26 4 25 5 24 6 23 7 22 M68AW031A 8 21 9 20 10 19 11 18 17 12 13 16 14 15
AI04836c
VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3
G A1 A2 A3 A4 W VCC A5 A6 A7 A8 A9 A10 A11
22
21
28 1
M68AW031A 15 (Normal) 14
7
8
AI05959D
A0 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A14 A13 A12
Figure 4. TSOP Connections (Reverse)
A11 A10 A9 A8 A7 A6 A5 VCC W A4 A3 A2 A1 G
22
21
28 1
M68AW031A 15 (Reverse) 14
7
8
AI05989D
A12 A13 A14 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E A0
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M68AW031A
Figure 6. Block Diagram
A14 ROW DECODER A7 MEMORY ARRAY
DQ7
I/O CIRCUITS COLUMN DECODER
DQ0
A0 E W
A6
G
AI05919
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M68AW031A
OPERATION
The M68AW031A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cyRead Mode The M68AW031A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data of the 262,144 locations in the static memory array, specified by the 15 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX but data lines will always be valid at tAVQV. See Figures 9, 10, 11 and Table 7. for details on Read mode AC timings and Characteristics. Write Mode The M68AW031A is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deTable 2. Operating Modes
Operation Deselected Read Write Output Disabled
Note: X = VIH or VIL.
cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (see Table 2.).
asserted during Address transitions for subsequent write cycles. When E (W) is Low, write cycle begins on the W (E)'s falling edge. Therefore, address setup time is referenced to Write Enable or Chip Enable as tAVWL and tAVEL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX and tEHDX respectively. See Figures 12, 10 and Table 8. for details on Write mode AC timings and Characteristics.
E VIH VIL VIL VIL
W X VIH VIL VIH
G X VIL X VIH
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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M68AW031A
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Symbol IO (1) TA TSTG TLEAD VCC VIO (4) PD
Note: 1. 2. 3. 4.
plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1s periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Output Current Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering(2) Supply Voltage Input or Output Voltage Power Dissipation
Value 20 -55 to 125 -65 to 150 260(3) -0.5 to 4.6 -0.5 to VCC +0.5 1
Unit mA C C C V V W
One output at time not to exceed 1 second duration. Compliant with the ECOPACK(R) 7191395 specification for Lead-free soldering processes. Not exceeding 250C for more than 30s, and peaking at 260C. Up to a maximum operating VCC of 3.6V only.
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M68AW031A
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 30pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AW031A 2.7 to 3.6V 0 to 70C
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL Output Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI05831
OUT
R2
0V
CL includes probe capacitance
AI05932
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M68AW031A
Table 5. Capacitance
Symbol CIN COUT Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 3.0V.
Table 6. DC Characteristics
Symbol ICC1 (1,2) Parameter Operating Supply Current Test Condition VCC = 3.6V, f = 1/ tAVAV, IOUT = 0mA 55ns 70ns 2 Min Typ Max 35 30 5 Unit mA mA mA
ICC2 (3)
Operating Supply Current
VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, f = 0, E VCC -0.2V or VIN = 0.2V or VIN = VCC -0.2V 0V VIN VCC 0V VOUT VCC -1 -1 2.2 -0.3 IOH = -1.0mA IOL = 2.1mA 2.4
ISB
Standby Supply Current CMOS
4
10
A
ILI ILO (4) VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
Average AC current, cycling at tAVAV minimum. E = VIL, VIN = VIL or VIH. E 0.2V, VIN 0.2V or VIN VCC -0.2V. Output disabled.
1 1 VCC + 0.3 0.6
A A V V V
0.4
V
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M68AW031A
Figure 9. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A14 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05939
Note: E = Low, G = Low, W = High.
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI05940
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms
E ICC ISB tPU 50% tPD
AI05956
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M68AW031A
Table 7. Read and Standby Mode AC Characteristics
M68AW031A Symbol tAVAV tAVQV tAXQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (1) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable High to Power Down Chip Enable Low to Power Up Parameter 55 Min Max Min Max Max Min Max Max Min Max Min 55 55 5 20 55 5 20 25 5 55 0 70 70 70 5 25 70 5 25 35 5 70 0 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M68AW031A
Figure 12. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVWH tELWH E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA (1) DATA INPUT tDVWH
AI05941
tWHAX
tWHQX
DATA (1)
Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.
Figure 13. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05942
tELEH
tEHAX
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M68AW031A
Table 8. Write Mode AC Characteristics
M68AW031A Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX(1) tWLEH tWLQZ(1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 55 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 55 45 0 45 0 25 25 0 0 45 45 0 0 5 45 20 45 70 70 60 0 60 0 30 30 0 0 60 60 0 0 5 60 25 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW031A
Figure 14. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V
VDR > 1.5V tCDR E VDR - 0.2V E tR
AI05905
Table 9. Low VCC Data Retention Characteristics
Symbol Parameter Test Condition VCC = 1.5V, E VCC -0.2V, f = 0 (3) 0 tAVAV E VCC -0.2V, f = 0 1.5 Min Typ Max 6 Unit A ns ns V ICCDR (1) Supply Current (Data Retention) Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at VIH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AW031A
PACKAGE MECHANICAL
Figure 15. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Outline
D
28 15
c E1 E
1 14
A1 A2 b SO-G
Note: Drawing is not to scale.
L L1
A ddd
e
Table 10. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b c D E E1 e L L1 18.110 11.811 8.407 1.270 0.914 1.702 - 0.711 1.499 0 - 1.117 1.905 10 2.489 0.406 0.200 0.360 18.618 12.116 0.7130 0.4650 0.3310 0.0500 0.0360 0.0670 - 0.0280 0.0590 0 - 0.0440 0.0750 10 0.100 2.362 2.620 0.0980 0.0160 0.0079 0.0142 0.7330 0.4770 Min Max 2.850 0.0039 0.0930 0.1031 Typ Min Max 0.1122 inches
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M68AW031A
Figure 16. TSOP28 - 28 Lead Normal Pinout Plastic Small Outline, Package Outline
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Note: Drawing is not to scale.
A1
L
Table 11. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 E e L N 0.550 13.200 11.700 7.900 - 0.500 0 28 0.950 0.170 0.100 Min Max 1.250 0.200 1.150 0.270 0.210 0.100 13.600 11.900 8.100 - 0.700 5 0.0217 0.5197 0.4606 0.3110 - 0.0197 0 28 0.0374 0.0067 0.0039 Typ Min Max 0.0492 0.0079 0.0453 0.0106 0.0083 0.0039 0.5354 0.4685 0.3189 - 0.0276 5 inches
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M68AW031A
Figure 17. TSOP28 - 28 Lead Reverse Pinout Plastic Small Outline, Package Outline
A2
7 8
e
1 28
E B
22 21
D1 D
A CP
DIE
C
TSOP-H
Note: Drawing is not to scale.
A1
L
Table 12. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 E e L a N 28 13.400 11.800 8.000 0.550 - - - - 0.300 0 0.220 0.100 0.210 0.100 - - - - 0.700 5 28 0.5276 0.4646 0.3150 0.0217 - - - - 0.0118 0 0.050 0.910 Min Max 1.200 0.150 1.050 0.0087 0.0039 0.0083 0.0039 - - - - 0.0276 5 0.0020 0.0358 Typ Min Max 0.0472 0.0059 0.0413 inches
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M68AW031A
PART NUMBERING
Table 13. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 031 = 256 Kbit (32K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55 ns 70 = 70 ns Package MS = SO28 N = TSOP28 8x13.4mm NS = TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 6 = -40 to 85 C 1 = 0 to 70 C Shipping U = Tube T = Tape and Reel F = Lead-free and RoHS Package, Tape & Reel Packing M68AW031 A L 70 MS 6 U
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AW031A
REVISION HISTORY
Table 14. Document Revision History
Date January 2002 07-Feb-2002 08-Feb-2002 06-Mar-2002 Version 1.0 2.0 3.0 4.0 First Issue TSOP28 Package Order Code clarified AC Measurement Load Circuit clarified (Figure 8.) Document status changed to Data Sheet Absolute Maximum Ratings table clarified (Table 3.) Operating and AC Measurement Conditions table clarified (Table 4.) DC Characteristics table clarified (Table 6.) Low VCC Data Retention AC Waveforms and Characteristics table clarified (Figure 14., Low VCC Data Retention AC Waveforms, Table 4.) TSOP28 8x13.4mm Standard pinout added (Figure 5, 12, and Table 13.) Block Diagram clarified (Figure 6.) TA clarified in Absolute Maximum Ratings (Table 3.) Operating and AC Measurement Conditions table clarified (Table 4.) ICC2 Max added in DC Characteristics (Table 6.) tPD, tPU clarified in Read and Standby Mode AC Characteristics (Table 7.) tWLEH, tWLWH clarified in Write Mode AC Characteristics (Table 8.) Load Capacitance (CL) changed from 100pF to 30pF (Table 4.) New part number added. Part number modified. Temperature range 1 added to Ordering Information Scheme. TSOP pin numbering corrected Value of ISB(typ) changed in DC Characteristics table SO28 package modified. Part numbering scheme updated. TLEAD parameter added in Table 3., Absolute Maximum Ratings. AC, DC Characteristics and waveforms grouped together. tPD maximum value and tPU minimum value updated in Table 7., Read and Standby Mode AC Characteristics. TSOP28 Normal and Reverse mechanical data and package outline differentiated. 55ns access time added in FEATURES SUMMARY, Table 6., DC Characteristics, Table 7., Read and Standby Mode AC Characteristics, Table 8., Write Mode AC Characteristics and Table 13., Ordering Information Scheme. Revision Details
20-May-2002
5.0
01-Jun-2002
6.0
09-Sep-2002 02-Oct-2002 09-Oct-2002 22-May-2003 02-Jul-2003
6.1 6.2 6.3 6.4 6.5
25-Nov-2003
6.6
12-Oct-2004
7.0
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M68AW031A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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