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NCP4640 50 mA, Wide Input Range, Voltage Regulator
The NCP4640 is a CMOS 50 mA linear voltage regulator with high input voltage and ultra-low supply current. It incorporates multiple protection features such as peak current limit, short circuit current limit and thermal shutdown to ensure a very robust device. A high maximum input voltage tolerance of 50 V and a wide temperature range make the NCP4640 suitable for a variety of demanding applications.
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* * * * * * * * * *
Operating Input Voltage Range: 4 V to 36 V Output Voltage Range: 2.0 to 12.0 V (0.1 steps) 2% Output Voltage Accuracy Output Current: min 50 mA (VIN = 8 V, VOUT = 5 V) Line Regulation: 0.05%/V Peak Current Limit Circuit Short Current Limit Circuit Thermal Shutdown Circuit Available in SOT-89-5 and SOIC6-TL Package These are Pb-Free Devices
SOIC6-TL CASE 751BR
XXX XMM 1
1 XXX XMM SOT-89 5 CASE 528AB
Typical Applications
* Power source for home appliances * Power source for car audio equipment, navigation system * Power source for notebooks, digital TVs, cordless phones and private * Power source for office equipment machines such as copiers,
printers, facsimiles, scanners, projectors, etc.
VIN C1 100n NCP4640x VIN CE VOUT GND VOUT C2 100n
XXXX MM
= Specific Device Code = Date Code
(Note: Microdot may be in either location)
LAN systems
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
Figure 1. Typical Application Schematic
(c) Semiconductor Components Industries, LLC, 2011
February, 2011 - Rev. 1
1
Publication Order Number: NCP4640/D
NCP4640
VIN Internal VR Vref
VOUT
CE
Current Limit Short Protection Thermal Shutdown GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No. SOT89 5 2 4 - 3 1 Pin No. SOIC6-TL 6 2 4 5 3 1 Pin Name VIN GND GND GND CE VOUT Input pin Ground pin, all ground pins must be connected together when it is mounted on board Ground pin, all ground pins must be connected together when it is mounted on board Ground pin, all ground pins must be connected together when it is mounted on board Chip enable pin ("H" active) Output pin Description
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NCP4640
ABSOLUTE MAXIMUM RATINGS
Rating Input Voltage Peak Input Voltage (Note 1) Output Voltage Chip Enable Input Output Current Power Dissipation SOT-89 Power Dissipation SOIC6-TL Junction Temperature Storage Temperature ESD Capability, Human Body Model (Note 2) ESD Capability, Machine Model (Note 2) TJ TSTG ESDHBM ESDMM Symbol VIN VIN VOUT VCE IOUT PD Value -0.3 to 50 60 -0.3 to VIN + 0.3 50 -0.3 to VIN + 0.3 50 150 900 1700 -40 to 150 -55 to 125 2000 200 C C V V Unit V V V V mA mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Duration time = 200 ms 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114) ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating Thermal Characteristics, SOT-89 Thermal Resistance, Junction-to-Air Thermal Characteristics, SOIC6-TL Thermal Resistance, Junction-to-Air Symbol RqJA RqJA Value 111 59 Unit C/W C/W
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NCP4640
ELECTRICAL CHARACTERISTICS TA = 25C
Parameter Operating Input Voltage Output Voltage Output Voltage Temp. Coefficient Line Regulation Load Regulation VIN = VOUT + 3 V, IOUT = 1 mA VIN = VOUT + 3 V, IOUT = 1 mA, TA = -40 to 105C VIN = VOUT + 1.5 V to 36 V, IOUT = 1 mA VIN = VOUT + 3 V, IOUT = 1 mA to 40 mA IOUT = 20 mA 2.0 V VOUT < 5.0 V 5.0 V VOUT < 12.0 V 2.0 V VOUT < 3.7 V 3.7 V VOUT < 4.0 V 4.0 V VOUT < 5.0 V 5.0 V VOUT < 12.0 V Output Current Short Current Limit Quiescent Current Standby Current CE Pin Threshold Voltage VIN = VOUT + 3 V VOUT = 0 V VIN = VOUT + 3 V, IOUT = 0 mA VIN = 36 V, VCE = 0 V CE Input Voltage "H" CE Input Voltage "L" Thermal Shutdown Temperature Thermal Shutdown Release Temperature Power Supply Rejection Ratio Output Noise Voltage VIN = 5.0 V, VOUT = 2.0 V, VIN PK-PK = 0.2 V, IOUT = 30 mA, f = 1 kHz VOUT = 2.0 V, IOUT = 30 mA, f = 10 Hz to 100 kHz IOUT ISC IQ ISTB VCEH VCEL TSD TSR PSRR VN 1.5 0 150 125 30 80 50 50 9 0.1 20 1 VIN 0.3 C C dB mVrms VDO 0.35 0.25 0.20 LineReg LoadReg Test Conditions Symbol VIN VOUT Min 4 x0.98 100 0.05 10 20 0.20 25 35 (Note 3) 0.60 0.40 0.35 mA mA mA mA V V Typ Max 36 x1.02 Unit V V ppm/C %/V mV
Dropout Voltage
3. Dropout voltage for 2.0 V VOUT < 3.7 V can be computed by this formula: VDO = 4 V - VOUTSET
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NCP4640
TYPICAL CHARACTERISTICS
2.5 2.0 1.5 1.0 0.5 0.0 VIN = 4.0 V 4.5 V 5.0 V 5.5 V VOUT (V) 2.0 1.5 1.0 0.5 0 50 100 IOUT (mA) 150 200 0.0 0 50 100 IOUT (mA) 150 200 VOUT (V) 3.5 3.0 2.5 6.0 V VIN = 6.5 V 5.0 V 5.5 V
Figure 3. Output Voltage vs. Output Current 2.0 V Version (TJ = 255C)
Figure 4. Output Voltage vs. Output Current 3.3 V Version (TJ = 255C)
9.0 8.0 7.0 6.0 VOUT (V) 5.0 4.0 3.0 2.0 1.0 0.0 0 50 100 IOUT (mA) 150 200 10 V 10.5 V 11 V 11.5 V VOUT (V)
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 50 100 IOUT (mA) 150 200 15.5 V 14 V 14.5 V 15 V
Figure 5. Output Voltage vs. Output Current 8.0 V Version (TJ = 255C)
Figure 6. Output Voltage vs. Output Current 12 V Version (TJ = 255C)
1.50 1.25 1.00 VDO (V) VDO (V) TJ = 25C 105C 0.75 0.50 0.25 -40C 0.00 0 10 20 30 IOUT (mA) 40 50
1.50 1.25 1.00 0.75 0.50 0.25 0.00 TJ = 25C 105C -40C 0 10 20 30 IOUT (mA) 40 50
Figure 7. Dropout Voltage vs. Output Current 8.0 V Version
Figure 8. Dropout Voltage vs. Output Current 12 V Version
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NCP4640
TYPICAL CHARACTERISTICS
2.10 2.08 2.06 2.04 VOUT (V) VOUT (V) 2.02 2.00 1.98 1.96 1.94 1.92 1.90 -40 -20 0 20 40 60 80 100 VIN = 5.0 V 3.40 3.38 3.36 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 -40 -20 0 20 40 60 80 100
VIN = 6.3 V
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Output Voltage vs. Temperature, 2.0 V Version
8.20 8.15 8.10 VOUT (V) VOUT (V) 8.05 8.00 7.95 7.90 7.85 7.80 -40 -20 0 20 40 60 80 100 VIN = 11 V 12.20 12.15 12.10 12.05 12.00 11.95 11.90 11.85 11.80 -40
Figure 10. Output Voltage vs. Temperature, 3.3 V Version
VIN = 15 V
-20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Output Voltage vs. Temperature, 8.0 V Version
14 12 10 IGND (mA) 8 6 4 2 0 -40 -20 0 20 40 60 80 100 3.3 V VOUT = 2.0 V IGND (mA) 8.0 V 12 V 16 14 12 10 8 6 4 2 0 0
Figure 12. Output Voltage vs. Temperature, 12 V Version
8.0 V 12 V
3.3 V
VOUT = 2.0 V
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Supply Current vs. Temperature
Figure 14. Supply Current vs. Input Voltage
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NCP4640
TYPICAL CHARACTERISTICS
2.5 2.0 1.5 1.0 0.5 0.0 1 mA 20 mA 3.5 3.0 2.5 1 mA VOUT (V) 2.0 1.5 1.0 IOUT = 40 mA 0.5 30 35 0.0 0 5 IOUT = 40 mA 20 mA VOUT (V)
0
5
10 15 20 25 VIN, INPUT VOLTAGE (V)
10 15 20 25 VIN, INPUT VOLTAGE (V)
30
35
Figure 15. Output Voltage vs. Input Voltage, 2.0 V Version
Figure 16. Output Voltage vs. Input Voltage, 3.3 V Version
9.0 8.0 7.0 6.0 VOUT (V) 5.0 4.0 3.0 2.0 1.0 0.0 0 5 20 mA IOUT = 40 mA 10 15 20 25 VIN, INPUT VOLTAGE (V) 30 35 VOUT (V) 1 mA
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 20 mA IOUT = 40 mA 5 10 15 20 25 VIN, INPUT VOLTAGE (V) 30 35 1 mA
Figure 17. Output Voltage vs. Input Voltage, 8.0 V Version
Figure 18. Output Voltage vs. Input Voltage, 12 V Version
100 90 80 70 PSRR (dB) PSRR (dB) 60 50 40 30 20 10 0 0.01 0.1 1 10 FREQUENCY (kHz) 100 IOUT = 1 mA 10 mA 30 mA 1000
100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 10 FREQUENCY (kHz) IOUT = 1 mA 10 mA 30 mA 100 1000
Figure 19. PSRR, 2.0 V Version, VIN = 5.0 V
Figure 20. PSRR, 3.3 V Version, VIN = 6.3 V
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NCP4640
TYPICAL CHARACTERISTICS
100 90 80 VN (mVrms/Hz) 1000 70 PSRR (dB) 60 50 40 30 20 10 0 0.01 0.1 1 10 100 IOUT = 1 mA 10 mA 30 mA 0 0.01 0.1 1 10 100 1000 4 3 2 1 5
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 21. PSRR, 3.3 V Version, VIN = 6.3 V
Figure 22. Output Voltage Noise, 2.0 V Version, VIN = 5.0 V, IOUT = 30 mA
45 40 35 VN (mVrms/Hz) 30 25 20 15 10 5
12 10 VN (mVrms/Hz) 8 6 4 2 0 0.01
0.1
1 10 FREQUENCY (kHz)
100
1000
0 0.01
0.1
1 10 FREQUENCY (kHz)
100
1000
Figure 23. Output Voltage Noise, 3.3 V Version, VIN = 6.3 V, IOUT = 30 mA
70 60 50 VN (mVrms/Hz) 40 30 20 10 0 0.01 0.1 1 10
Figure 24. Output Voltage Noise, 8.0 V Version, VIN = 11.0 V, IOUT = 30 mA
100
1000
FREQUENCY (kHz)
Figure 25. Output Voltage Noise, 12.0 V Version, VIN = 15.0 V, IOUT = 30 mA
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NCP4640
TYPICAL CHARACTERISTICS
6.5 6.0 5.5 VOUT (V) 5.0 2.10 2.05 2.00 1.95 1.90 0 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0 VIN (V)
Figure 26. Line Transients, 2.0 V Version, tR = tF = 50 ms, IOUT = 1 mA
8.0 7.5 7.0 VOUT (V) 6.5 3.5 3.4 3.3 3.2 3.1 0 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0 6.0 VIN (V) VIN (V) 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0
Figure 27. Line Transients, 3.3 V Version, tR = tF = 50 ms, IOUT = 1 mA
12.5 12.0 11.5 VOUT (V) 11.0 8.4 8.2 8.0 7.8 7.6 0
Figure 28. Line Transients, 8.0 V Version, tR = tF = 50 ms, IOUT = 1 mA
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NCP4640
TYPICAL CHARACTERISTICS
16.5 16.0 15.5 VOUT (V) 15.0 12.4 12.2 12.0 11.8 11.6 0 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0 VIN (V)
Figure 29. Line Transients, 12.0 V Version, tR = tF = 50 ms, IOUT = 1 mA
30 20 10 0 2.2 2.1 2.0 1.9 1.8 1.7 0 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0 IOUT (mA) VOUT (V)
Figure 30. Load Transients, 2.0 V Version, IOUT = 1 - 20 mA, tR = tF = 50 ms, VIN = 5.0 V
30 20 10 0 3.7 3.5 3.3 3.1 2.9 2.7 0 0.2 0.4 0.6 0.8 1.0 1.2 t (ms) 1.4 1.6 1.8 2.0 IOUT (mA) VOUT (V)
Figure 31. Load Transients, 3.3 V Version, IOUT = 1 - 20 mA, tR = tF = 50 ms, VIN = 6.3 V
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NCP4640
TYPICAL CHARACTERISTICS
30 20 10 8.6 VOUT (V) 8.4 8.2 8.0 7.8 7.6 7.4 7.2 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0 0 IOUT (mA)
Figure 32. Load Transients, 8.0 V Version, IOUT = 1 - 20 mA, tR = tF = 50 ms, VIN = 11.0 V
30 20 10 0 12.8 12.4 12.0 11.6 11.2 10.8 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0 IOUT (mA) VOUT (V)
Figure 33. Load Transients, 12.0 V Version, IOUT = 1 - 20 mA, tR = tF = 50 ms, VIN = 15.0 V
60 50 40 30 2.2 2.1 2.0 1.9 1.8 1.7 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0 IOUT (mA) VOUT (V) 20
Figure 34. Load Transients, 2.0 V Version, IOUT = 20 - 50 mA, tR = tF = 50 ms, VIN = 5.0 V
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NCP4640
TYPICAL CHARACTERISTICS
60 50 40 30 3.7 3.5 3.3 3.1 2.9 2.7 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0 IOUT (mA) VOUT (V)
Figure 35. Load Transients, 3.3 V Version, IOUT = 20 - 50 mA, tR = tF = 50 ms, VIN = 6.3 V
60 50 40 30 8.4 8.2 8.0 7.8 7.6 7.4 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0 IOUT (mA) IOUT (mA) VOUT (V) 20
Figure 36. Load Transients, 8.0 V Version, IOUT = 20 - 50 mA, tR = tF = 50 ms, VIN = 11.0 V
60 50 40 30 VOUT (V) 20 12.8 12.4 12.0 11.6 11.2 10.8 0 0.2 0.4 0.6 0.8 1.0 t (ms) 1.2 1.4 1.6 1.8 2.0
Figure 37. Load Transients, 12.0 V Version, IOUT = 20 - 50 mA, tR = tF = 50 ms, VIN = 15.0 V
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NCP4640
TYPICAL CHARACTERISTICS
8 Chip Enable 6 4 2 VOUT (V) 2.0 1.5 1.0 0.5 0 -0.5 0 50 100 150 200 250 300 350 400 450 500 t (ms) VCE (V) VCE (V) VCE (V) 0 IOUT = 1 mA IOUT = 20 mA IOUT = 50 mA
Figure 38. Start-up, 2.0 V Version, VIN = 5.0 V
Chip Enable
8 6 4 2 0
VOUT (V)
4 3 2 1 0 -1 0 50 100 150 200 250 300 350 400 450 500 t (ms) IOUT = 1 mA IOUT = 20 mA IOUT = 50 mA
Figure 39. Start-up, 3.3 V Version, VIN = 6.3 V
16 Chip Enable 12 8 4 VOUT (V) 0 8 6 4 2 0 -2 0 50 100 150 200 250 300 350 400 450 500 t (ms) IOUT = 1 mA IOUT = 20 mA
IOUT = 50 mA
Figure 40. Start-up, 8.0 V Version, VIN = 11.0 V
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NCP4640
TYPICAL CHARACTERISTICS
20 15 10 5 VOUT (V) 16 12 8 4 0 -4 0 50 IOUT = 1 mA IOUT = 50 mA IOUT = 20 mA VCE (V) 0
Chip Enable
100 150 200 250 300 350 400 450 500 t (ms)
Figure 41. Start-up, 12.0 V Version, VIN = 15.0 V
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NCP4640
APPLICATION INFORMATION A typical application circuit for NCP4640 series is shown in Figure 42.
VIN C1 100 n NCP4640x VIN CE GND VOUT C2 100n VOUT
connected to CE pin. Do not keep CE pin not connected or between VCEH and VCEL voltage levels. Otherwise output voltage would be unstable or indefinite and unexpected would flow internally.
Thermal
Figure 42. Typical Application Schematic Input Decoupling Capacitor (C1)
The device is stable without any input capacitance, but if input line is long and has high impedance or if more stable operation is needed, input capacitor C1 should be connected as close as possible to the IC. Recommended range of input capacitor value is 100 nF to 10 mF.
Output Decoupling Capacitor (C2)
As a power across the IC increase, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and also the ambient temperature affect the rate of temperature increase for the part. When the device has good thermal conductivity through the PCB the junction temperature will be relatively low in high power dissipation applications. The IC includes internal thermal shutdown circuit that stops operation of regulator, if junction temperature is higher than 150C. After that, when junction temperature decreases below 125C, the operation of voltage regulator would restart. While high power dissipation condition is, the regulator starts and stops repeatedly and protects itself against overheating.
PCB layout
The NCP4641 can work stable without output capacitor, but if faster response and higher stability reserve is needed, output capacitor should be connected as close as possible to the device. Recommended range of output capacitance is 100 nF to 10 mF. Larger values of output capacitance and lower ESR improves dynamic parameters.
Enable Operation
Pins number 2 and 4 of SOT89-5 package and pins number 2, 4 and 5 of SOIC6-TL must be wired to the GND plane while it is mounted on board. Make VIN and GND lines sufficient. If their impedance is high, noise pickup or unstable operation may result. Connect capacitors C1 and C2 as close as possible to the IC, and make wiring as short as possible.
The enable pin CE may be used for turning the regulator on and off. The device is activated when high level is
ORDERING INFORMATION
Device NCP4640H020T1G NCP4640H030T1G NCP4640H033T1G NCP4640H080T1G NCP4640H120T1G Nominal Output Voltage 2.0 V 3.0 V 3.3 V 8.0 V 12.0 V Description Enable High Enable High Enable High Enable High Enable High Marking N020 N030 N033 N080 N120 Package SOT89-5 (Pb-Free) SOT89-5 (Pb-Free) SOT89-5 (Pb-Free) SOT89-5 (Pb-Free) SOT89-5 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *To order other package and voltage variants, please contact your ON Semiconductor sales representative.
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NCP4640
PACKAGE DIMENSIONS
SOIC6 (HSOP6) CASE 751BR-01 ISSUE O
D b1
6 4
A A3 E
F
H
1 3
L2
4X
L DETAIL A
B D
b 0.12
C
SEATING PLANE
M
C A-B D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b AND b1 DO NOT INCLUDE DAMBAR PROTRUSION. ALLOWAQBLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DATUMS A AND B ARE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 A3 b b1 D E e H L L2 MILLIMETERS MIN MAX 1.45 1.85 0.05 0.25 0.19 0.30 0.30 0.50 1.57 1.77 4.72 5.32 3.70 4.10 3.81 BSC 5.70 6.30 0.40 0.60 0.25 BSC
6X
0.10 C
A1 A
e
C
SEATING PLANE
DETAIL A
RECOMMENDED SOLDERING FOOTPRINT*
3.81 PITCH
6X
1.05
6.40 1
2X
1.87
0.60
DIMENSIONS: MILLIMETERS
4X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP4640
PACKAGE DIMENSIONS
SOT-89, 5 LEAD CASE 528AB-01 ISSUE O
D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. LEAD THICKNESS INCLUDES LEAD FINISH. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. DIMENSIONS L, L2, L3, L4, L5, AND H ARE MEASURED AT DATUM PLANE C. DIM A b b1 c D D2 E e H L L2 L3 L4 L5 MILLIMETERS MIN MAX 1.40 1.60 0.32 0.52 0.37 0.57 0.30 0.50 4.40 4.60 1.40 1.80 2.40 2.60 1.40 1.60 4.25 4.45 1.10 1.50 0.80 1.20 0.95 1.35 0.65 1.05 0.20 0.60
E
H
1
TOP VIEW
A
c 0.10 C
C
SIDE VIEW e b1 L
1 2
e b
3
L2
4X
RECOMMENDED MOUNTING FOOTPRINT*
0.57 1.75 1.50 4.65 1.65
2X
L5
5 4
2.79
0.45
L3
L4
D2 BOTTOM VIEW 1.30 1
2X
1.50
0.62
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP4640/D

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