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| www..com Preliminary User's Manual V850ES/HG2 32-Bit Single-Chip Microcontrollers Hardware PD70F3706 PD70F3707 Document No. U17718EJ1V0UD00 (1st edition) Date Published December 2005 N CP(K) 2005 Printed in Japan www..com [MEMO] 2 Preliminary User's Manual U17718EJ1V0UD www..com NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Preliminary User's Manual U17718EJ1V0UD 3 www..com MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. * The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. * Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5D 02. 11-1 4 Preliminary User's Manual U17718EJ1V0UD www..com PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/HG2 and design application systems using the V850ES/HG2. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/HG2 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware * Pin functions * CPU function * On-chip peripheral functions * Flash memory programming * Electrical specifications (target) How to Read This Manual Architecture * Data types * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/HG2 Read this manual according to the CONTENTS. To find the details of a register where the name is known Use APPENDIX A REGISTER INDEX. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual available separately. To know the electrical specifications of the V850ES/HG2 See CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET). Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. Preliminary User's Manual U17718EJ1V0UD 5 www..com Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 6 Preliminary User's Manual U17718EJ1V0UD www..com Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/HG2 Document Name V850ES Architecture User's Manual V850ES/HG2 Hardware User's Manual Document No. U15943E This manual Documents related to development tools Document Name CA850 Ver. 3.00 C Compiler Package Operation C Language Assembly Language Link Directives PM+ Ver. 6.00 Project Manager ID850QB Ver. 3.10 Integrated Debugger SM850 Ver. 2.50 System Simulator SM850 Ver. 2.00 or Later System Simulator Operation Operation External Part User Open Interface Specification RX850 Ver. 3.20 or Later Real-Time OS Basics Installation Technical Task Debugger RX850 Pro Ver. 3.20 Real-Time OS Basics Installation Technical Task Debugger AZ850 Ver. 3.30 System Performance Analyzer PG-FP4 Flash Memory Programmer U13430E U17419E U13431E U17420E U13773E U17421E U13772E U17422E U17423E U15260E Document No. U17293E U17291E U17292E U17294E U17178E U17435E U16218E U14873E Preliminary User's Manual U17718EJ1V0UD 7 www..com CONTENTS CHAPTER 1 INTRODUCTION..................................................................................................................16 1.1 1.2 1.3 1.4 1.5 1.6 General .....................................................................................................................................16 Features....................................................................................................................................18 Application Fields....................................................................................................................18 Ordering Information...............................................................................................................19 Pin Configuration (Top View) .................................................................................................20 Function Block Configuration ................................................................................................22 1.6.1 1.6.2 Internal block diagram................................................................................................................22 Internal units ..............................................................................................................................23 CHAPTER 2 PIN FUNCTIONS ................................................................................................................25 2.1 2.2 2.3 2.4 2.5 Pin Function List......................................................................................................................25 Description of Pin Functions..................................................................................................30 Pin I/O Circuit Types and Recommended Connection of Unused Pins.............................37 Pin I/O Circuits .........................................................................................................................39 Cautions ...................................................................................................................................40 CHAPTER 3 CPU FUNCTION .................................................................................................................41 3.1 3.2 Features....................................................................................................................................41 CPU Register Set .....................................................................................................................42 3.2.1 3.2.2 Program register set ..................................................................................................................43 System register set ....................................................................................................................44 Specifying operation mode ........................................................................................................50 CPU address space ...................................................................................................................51 Wraparound of CPU address space ..........................................................................................52 Memory map..............................................................................................................................53 Areas .........................................................................................................................................55 Recommended use of address space........................................................................................57 Peripheral I/O registers ..............................................................................................................60 Special registers ........................................................................................................................69 Cautions.....................................................................................................................................73 3.3 3.4 Operation Modes .....................................................................................................................50 3.3.1 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 Address Space.........................................................................................................................51 CHAPTER 4 PORT FUNCTIONS ............................................................................................................76 4.1 4.2 4.3 Features....................................................................................................................................76 Basic Configuration of Ports..................................................................................................76 Port Functions .........................................................................................................................78 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Operation of port function ..........................................................................................................78 Notes on setting port pins ..........................................................................................................79 Port 0 .........................................................................................................................................80 Port 1 .........................................................................................................................................86 Port 3 .........................................................................................................................................90 Port 4 .........................................................................................................................................97 Port 5 .......................................................................................................................................100 8 Preliminary User's Manual U17718EJ1V0UD www..com 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 Port 7....................................................................................................................................... 106 Port 9....................................................................................................................................... 108 Port CM ................................................................................................................................... 117 Port CS.................................................................................................................................... 119 Port CT .................................................................................................................................... 121 Port DL .................................................................................................................................... 123 Port pins that function alternately as on-chip debug function................................................... 125 Register settings to use port pins as alternate-function pins.................................................... 126 4.4 4.5 Block Diagrams of Port.........................................................................................................131 Cautions .................................................................................................................................157 4.5.1 Cautions on setting port pins ................................................................................................... 157 CHAPTER 5 CLOCK GENERATION FUNCTION ...............................................................................158 5.1 5.2 5.3 5.4 Overview.................................................................................................................................158 Configuration .........................................................................................................................159 Registers ................................................................................................................................161 Operation................................................................................................................................166 5.4.1 5.4.2 Operation of each clock ........................................................................................................... 166 Clock output function ............................................................................................................... 166 Overview ................................................................................................................................. 167 Registers ................................................................................................................................. 167 Usage ...................................................................................................................................... 171 5.5 PLL Function..........................................................................................................................167 5.5.1 5.5.2 5.5.3 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................172 6.1 6.2 6.3 6.4 6.5 Overview.................................................................................................................................172 Functions ...............................................................................................................................172 Configuration .........................................................................................................................173 Registers ................................................................................................................................175 Operation................................................................................................................................189 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 190 External event count mode (TPnMD2 to TPnMD0 bits = 001)................................................. 200 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)..................................... 208 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 220 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 227 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 236 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 253 Timer output operations........................................................................................................... 259 6.6 6.7 6.8 Timer Tuned Operation Function ........................................................................................260 Selector Function ..................................................................................................................264 Cautions .................................................................................................................................266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................267 7.1 7.2 7.3 7.4 7.5 Overview.................................................................................................................................267 Functions ...............................................................................................................................267 Configuration .........................................................................................................................268 Registers ................................................................................................................................271 Operation................................................................................................................................289 Preliminary User's Manual U17718EJ1V0UD 9 www..com 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) ............................................................290 External event count mode (TQnMD2 to TQnMD0 bits = 001) ................................................299 External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010) ....................................308 One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011)..............................................321 PWM output mode (TQnMD2 to TQnMD0 bits = 100) .............................................................330 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ...................................................341 Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110)........................................361 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111) ....................................................367 Timer output operations ...........................................................................................................368 7.6 7.7 Timer Tuned Operation Function........................................................................................ 369 Cautions ................................................................................................................................ 373 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 374 8.1 8.2 8.3 8.4 Overview................................................................................................................................ 374 Configuration ........................................................................................................................ 375 Register ................................................................................................................................. 376 Operation............................................................................................................................... 377 8.4.1 8.4.2 Interval timer mode ..................................................................................................................377 Cautions...................................................................................................................................381 CHAPTER 9 WATCH TIMER FUNCTIONS ........................................................................................ 382 9.1 9.2 9.3 9.4 Functions............................................................................................................................... 382 Configuration ........................................................................................................................ 383 Registers ............................................................................................................................... 385 Operation............................................................................................................................... 389 9.4.1 9.4.2 9.4.3 Operation as watch timer .........................................................................................................389 Operation as interval timer.......................................................................................................390 Cautions...................................................................................................................................391 CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 392 10.1 10.2 10.3 10.4 Functions............................................................................................................................... 392 Configuration ........................................................................................................................ 393 Registers ............................................................................................................................... 394 Operation............................................................................................................................... 397 CHAPTER 11 A/D CONVERTER ......................................................................................................... 398 11.1 11.2 11.3 11.4 11.5 Overview................................................................................................................................ 398 Functions............................................................................................................................... 398 Configuration ........................................................................................................................ 399 Registers ............................................................................................................................... 402 Operation............................................................................................................................... 410 11.5.1 11.5.2 11.5.3 11.5.4 Basic operation ........................................................................................................................410 Trigger mode ...........................................................................................................................411 Operation mode .......................................................................................................................413 Power-fail compare mode ........................................................................................................417 11.6 11.7 Cautions ................................................................................................................................ 422 How to Read A/D Converter Characteristics Table........................................................... 426 10 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................430 12.1 12.2 12.3 12.4 12.5 Features..................................................................................................................................430 Configuration .........................................................................................................................431 Registers ................................................................................................................................433 Interrupt Request Signals.....................................................................................................439 Operation................................................................................................................................440 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.5.6 12.5.7 12.5.8 12.5.9 Data format.............................................................................................................................. 440 SBF transmission/reception format.......................................................................................... 442 SBF transmission .................................................................................................................... 444 SBF reception.......................................................................................................................... 445 UART transmission.................................................................................................................. 446 Continuous transmission procedure ........................................................................................ 447 UART reception ....................................................................................................................... 449 Reception errors ...................................................................................................................... 450 Parity types and operations ..................................................................................................... 452 12.5.10 Receive data noise filter .......................................................................................................... 453 12.6 12.7 Dedicated Baud Rate Generator ..........................................................................................454 Cautions .................................................................................................................................462 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................463 13.1 13.2 13.3 13.4 13.5 Features..................................................................................................................................463 Configuration .........................................................................................................................464 Registers ................................................................................................................................466 Interrupt Request Signals.....................................................................................................473 Operation................................................................................................................................474 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.5.6 13.5.7 13.5.8 Single transfer mode (master mode, transmission/reception mode)........................................ 474 Single transfer mode (master mode, reception mode)............................................................. 475 Continuous mode (master mode, transmission/reception mode)............................................. 476 Continuous mode (master mode, reception mode).................................................................. 477 Continuous reception mode (error).......................................................................................... 478 Continuous mode (slave mode, transmission/reception mode) ............................................... 479 Continuous mode (slave mode, reception mode) .................................................................... 480 Clock timing ............................................................................................................................. 481 13.6 13.7 13.8 13.9 Output Pin Status with Operation Disabled .......................................................................483 Operation Flow ......................................................................................................................484 Baud Rate Generator ............................................................................................................490 13.8.1 Baud rate generation ............................................................................................................... 491 Cautions .................................................................................................................................492 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) ....................................................................493 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Features..................................................................................................................................493 Configuration .........................................................................................................................494 Registers ................................................................................................................................495 Transfer Targets ....................................................................................................................503 Transfer Modes......................................................................................................................503 Transfer Types.......................................................................................................................504 DMA Channel Priorities ........................................................................................................505 Time Related to DMA Transfer.............................................................................................505 Preliminary User's Manual U17718EJ1V0UD 11 www..com 14.9 14.10 14.11 14.12 14.13 DMA Transfer Start Factors................................................................................................. 506 DMA Abort Factors............................................................................................................... 507 End of DMA Transfer............................................................................................................ 507 Operation Timing .................................................................................................................. 507 Cautions ................................................................................................................................ 512 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 516 15.1 15.2 Features................................................................................................................................. 516 Non-Maskable Interrupts ..................................................................................................... 520 15.2.1 15.2.2 15.2.3 Operation .................................................................................................................................522 Restore ....................................................................................................................................523 NP flag .....................................................................................................................................524 Operation .................................................................................................................................525 Restore ....................................................................................................................................527 Priorities of maskable interrupts...............................................................................................528 Interrupt control register (xxICn) ..............................................................................................532 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................534 In-service priority register (ISPR).............................................................................................536 ID flag ......................................................................................................................................537 Watchdog timer mode register 2 (WDTM2) .............................................................................537 Operation .................................................................................................................................538 Restore ....................................................................................................................................539 EP flag .....................................................................................................................................540 Illegal opcode definition ...........................................................................................................541 Debug trap ...............................................................................................................................543 Noise elimination .....................................................................................................................545 Edge detection.........................................................................................................................545 15.3 Maskable Interrupts.............................................................................................................. 525 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.4 Software Exception .............................................................................................................. 538 15.4.1 15.4.2 15.4.3 15.5 Exception Trap...................................................................................................................... 541 15.5.1 15.5.2 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10) ................................. 545 15.6.1 15.6.2 15.7 15.8 15.9 Interrupt Acknowledge Time of CPU .................................................................................. 552 Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 553 Cautions ................................................................................................................................ 553 CHAPTER 16 KEY INTERRUPT FUNCTION ..................................................................................... 554 16.1 16.2 16.3 Function................................................................................................................................. 554 Register ................................................................................................................................. 555 Cautions ................................................................................................................................ 555 CHAPTER 17 STANDBY FUNCTION .................................................................................................. 556 17.1 17.2 17.3 Overview................................................................................................................................ 556 Registers ............................................................................................................................... 558 HALT Mode............................................................................................................................ 561 17.3.1 17.3.2 Setting and operation status ....................................................................................................561 Releasing HALT mode.............................................................................................................561 Setting and operation status ....................................................................................................563 17.4 IDLE1 Mode ........................................................................................................................... 563 17.4.1 12 Preliminary User's Manual U17718EJ1V0UD www..com 17.4.2 Releasing IDLE1 mode............................................................................................................ 563 Setting and operation status .................................................................................................... 565 Releasing IDLE2 mode............................................................................................................ 565 Securing setup time when releasing IDLE2 mode ................................................................... 567 Setting and operation status .................................................................................................... 568 Releasing STOP mode............................................................................................................ 568 Securing oscillation stabilization time when releasing STOP mode......................................... 570 Setting and operation status .................................................................................................... 571 Releasing subclock operation mode ........................................................................................ 571 Setting and operation status .................................................................................................... 573 Releasing sub-IDLE mode....................................................................................................... 574 17.5 IDLE2 Mode ............................................................................................................................565 17.5.1 17.5.2 17.5.3 17.6 STOP Mode ............................................................................................................................568 17.6.1 17.6.2 17.6.3 17.7 Subclock Operation Mode ....................................................................................................571 17.7.1 17.7.2 17.8 Sub-IDLE Mode ......................................................................................................................573 17.8.1 17.8.2 CHAPTER 18 RESET FUNCTIONS......................................................................................................576 18.1 18.2 18.3 Overview.................................................................................................................................576 Registers to Check Reset Source........................................................................................577 Operation................................................................................................................................578 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 Reset operation via RESET pin ............................................................................................... 578 Reset operation by watchdog timer 2 ...................................................................................... 580 Reset operation by power-on clear circuit................................................................................ 581 Reset operation by low-voltage detector.................................................................................. 581 Reset operation by clock monitor ............................................................................................ 581 CHAPTER 19 CLOCK MONITOR .........................................................................................................582 19.1 19.2 19.3 19.4 Functions ...............................................................................................................................582 Configuration .........................................................................................................................582 Register ..................................................................................................................................583 Operation................................................................................................................................584 CHAPTER 20 POWER-ON CLEAR CIRCUIT .....................................................................................587 20.1 20.2 20.3 Function .................................................................................................................................587 Configuration .........................................................................................................................587 Operation................................................................................................................................588 CHAPTER 21 LOW-VOLTAGE DETECTOR........................................................................................589 21.1 21.2 21.3 21.4 Functions ...............................................................................................................................589 Configuration .........................................................................................................................589 Registers ................................................................................................................................590 Operation................................................................................................................................592 21.4.1 21.4.2 To use for internal reset signal ................................................................................................ 592 To use for interrupt .................................................................................................................. 594 21.5 21.6 RAM Retention Voltage Detection Operation.....................................................................595 Emulation Function...............................................................................................................596 CHAPTER 22 REGULATOR ..................................................................................................................597 13 Preliminary User's Manual U17718EJ1V0UD www..com 22.1 22.2 Overview................................................................................................................................ 597 Operation............................................................................................................................... 598 CHAPTER 23 FLASH MEMORY .......................................................................................................... 599 23.1 23.2 Features................................................................................................................................. 599 23.1.1 23.2.1 23.2.2 23.2.3 23.2.4 23.2.5 23.2.6 23.2.7 Erasure unit .............................................................................................................................600 Programming environment.......................................................................................................601 Communication mode ..............................................................................................................602 Flash memory control ..............................................................................................................607 Selection of communication mode ...........................................................................................608 Communication commands .....................................................................................................609 Pin connection .........................................................................................................................610 Recommended circuit example for writing ...............................................................................614 Overview..................................................................................................................................615 Features...................................................................................................................................616 Standard self programming flow ..............................................................................................617 Flash functions.........................................................................................................................618 Pin processing .........................................................................................................................618 Internal resources used ...........................................................................................................619 Rewriting by Dedicated Flash Programmer....................................................................... 601 23.3 Rewriting by Self Programming .......................................................................................... 615 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6 CHAPTER 24 OPTION BYTE FUNCTION .......................................................................................... 620 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 621 25.1 25.2 25.3 25.4 25.5 25.6 Features................................................................................................................................. 621 Connection Circuit Example................................................................................................ 622 Interface Signals ................................................................................................................... 623 Register ................................................................................................................................. 625 Operation............................................................................................................................... 626 ROM Security Function........................................................................................................ 627 25.6.1 25.6.2 Security ID ...............................................................................................................................627 Setting .....................................................................................................................................628 25.7 Cautions ................................................................................................................................ 629 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 630 26.1 26.2 26.3 26.4 Absolute Maximum Ratings ................................................................................................ 630 Capacitance........................................................................................................................... 632 Operating Conditions........................................................................................................... 632 Oscillator Characteristics .................................................................................................... 633 26.4.1 26.4.2 26.4.3 26.4.4 Main clock oscillator characteristics .........................................................................................633 Subclock oscillator characteristics ...........................................................................................634 PLL characteristics ..................................................................................................................635 Internal oscillator characteristics..............................................................................................635 26.5 26.6 Voltage Regulator Characteristics...................................................................................... 635 DC Characteristics ............................................................................................................... 636 26.6.1 26.6.2 I/O level ...................................................................................................................................636 Pin leakage current ..................................................................................................................637 14 Preliminary User's Manual U17718EJ1V0UD www..com 26.6.3 Supply current ......................................................................................................................... 638 26.7 26.8 Data Retention Characteristics............................................................................................639 AC Characteristics ................................................................................................................640 26.8.1 CLKOUT output timing ............................................................................................................ 641 26.9 Basic Operation.....................................................................................................................642 26.10 Flash Memory Programming Characteristics ....................................................................649 CHAPTER 27 PACKAGE DRAWING ...................................................................................................650 APPENDIX A REGISTER INDEX..........................................................................................................651 APPENDIX B INSTRUCTION SET LIST..............................................................................................660 B.1 B.2 Conventions...........................................................................................................................660 Instruction Set (in Alphabetical Order) ...............................................................................663 Preliminary User's Manual U17718EJ1V0UD 15 www..com CHAPTER 1 INTRODUCTION The V850ES/HG2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 General The V850ES/HG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, and an A/D converter. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/HG2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. Table 1-1 lists the products of the V850ES/HG2. 16 Preliminary User's Manual U17718EJ1V0UD CHAPTER 1 INTRODUCTION www..com Table 1-1. V850ES/HG2 Product List Part Number Internal memory Flash memory RAM Memory space Logical space PD70F3706 128 KB 12 KB 64 MB 32 bits x 32 registers Ceramic/crystal/external clock * In PLL mode: fX = 4 to 5 MHz * In clock through mode: fX = 4 to 5 MHz PD70F3707 256 KB General-purpose register Main clock (oscillation frequency) Subclock (oscillation frequency) Crystal/external clock: fXT = 32.768 kHz RC oscillation: 20 kHz Internal oscillator Minimum instruction execution time DSP function fR = 200 kHz (TYP.) 50 ns (main clock (fXX) = 20 MHz operation) 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz) I/O port Timer 16-bit timer/event counter P: 16-bit interval timer M: Watchdog timer 2: Watch timer: A/D converter Serial interface 4 channels 1 channel 1 channel 1 channel I/O: 84 16-bit timer/event counter Q: 2 channels 10-bit resolution x 16 channels CSIB: UARTA (for LIN): 2 channels 3 channels DMA controller Interrupt source Power save function Reset 4 channels (transfer target: on-chip peripheral I/O, internal RAM) External: 12 (12) Note , internal: 43 HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), POC circuit, low-voltage detector (LVI) On-chip debug function Operating power supply voltage Operating ambient temperature Package Provided (RUN/break) 3.5 to 5.5 V (A/D converter: 4.0 to 5.5 V) -40 to +85C 100-pin plastic LQFP (fine pitch) (14 x 14 mm) Note The figure in parentheses indicates the number of external interrupts that can release STOP mode. Preliminary User's Manual U17718EJ1V0UD 17 CHAPTER 1 INTRODUCTION www..com 1.2 Features Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz) General-purpose registers: CPU features: 32 bits x 32 registers Signed multiplication (16 x 16 32): 1 to 2 clocks Signed multiplication (32 x 32 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: * Internal memory: Interrupts and exceptions: 64 MB of linear address space (for programs and data) RAM: 12 KB Flash memory: 128 KB/256 KB (see Table 1-1) Non-maskable interrupts: 2 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer function: I/O ports: 84 1 channel 53 sources 32 sources 2 sources 16-bit interval timer M (TMM): 16-bit timer/event counter P (TMP): 4 channels 16-bit timer/event counter Q (TMQ): 2 channels Watch timer: Watchdog timer 2: Serial interface: 1 channel 1 channel Asynchronous serial interface A (UARTA) 3-wire variable-length serial interface B (CSIB) UARTA (supporting LIN): 3 channels CSIB: 2 channels A/D converter: DMA controller: On-chip debug function: Clock generator: 10-bit resolution: 16 channels 4 channels JTAG interface During main clock or subclock operation 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable Internal oscillation clock: Power-save functions: Package: 200 kHz (TYP.) HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode 100-pin plastic LQFP (fine pitch) (14 x 14) 1.3 Application Fields Consumer devices 18 Preliminary User's Manual U17718EJ1V0UD CHAPTER 1 INTRODUCTION www..com 1.4 Ordering Information Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) On-Chip Flash Memory 128 KB 256 KB PD70F3706GC-8EA-A PD70F3707GC-8EA-A Remark Products with -A at the end of the part number are lead-free products. Preliminary User's Manual U17718EJ1V0UD 19 CHAPTER 1 INTRODUCTION www..com 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 x 14) PD70F3706GC-8EA-A PD70F3707GC-8EA-A AVREF0 AVSS P10/INTP9 P11/INTP10 EVDD P00/TIP31/TOP31 P01/TIP30/TOP30 FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0/ADTRG P04/INTP1 P05/INTP2/DRST P06/INTP3 P40/SIB0 P41/SOB0 P42/SCKB0 P30/TXDA0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 P714/ANI14 P715/ANI15 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5/FLMD1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PDL4 PDL3 PDL2 PDL1 PDL0 BVDD BVSS PCT6 PCT4 PCT1 PCT0 PCM3 PCM2 PCM1/CLKOUT PCM0 PCS1 PCS0 P915/INTP6 P914/INTP5 P913/INTP4/PCL P912 P911 P910 P99/SCKB1 P98/SOB1 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (preliminary value) capacitor. 20 P31/RXDA0/INTP7 P32/ASCKA0/TOP01/TIP00/TOP00 P33/TIP01/TOP01 P34/TIP10/TOP10 P35/TIP11/TOP11 P36 P37 EVSS EVDD P38/TXDA2 P39/RXDA2/INTP8 P50/KR0/TIQ01/TOQ01 P51/KR1/TIQ02/TOQ02 P52/KR2/TIQ03/TOQ03/DDI P53/KR3/TIQ00/TOQ00/DDO P54/KR4/DCK P55/KR5/DMS P90/KR6/TXDA1 P91/KR7/RXDA1 P92/TIQ11/TOQ11 P93/TIQ12/TOQ12 P94/TIQ13/TOQ13 P95/TIQ10/TOQ10 P96/TIP21/TOP21 P97/SIB1/TIP20/TOP20 Preliminary User's Manual U17718EJ1V0UD CHAPTER 1 INTRODUCTION www..com Pin identification ADTRG: ANI0 to ANI15: ASCKA0: AVREF0: AVSS: BVDD: BVSS: CLKOUT: DCK: DDI: DDO: DMS: DRST: EVDD: EVSS: FLMD0, FLMD1: INTP0 to INTP10: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P70 to P715: P90 to P915: PCL: PCM0 to PCM3: A/D trigger input Analog input Asynchronous serial clock Analog reference voltage Analog VSS Power supply for bus interface Ground for bus interface Clock output Debug clock Debug data input Debug data output Debug mode select Debug reset Power supply for port Ground for port Flash programming mode External interrupt input Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 7 Port 9 Programmable clock output Port CM PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDL0 to PDL13: REGC: RESET: SCKB0, SCKB1: SIB0, SIB1: SOB0, SOB1: TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13: TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31, TOQ00 to TOQ03, TOQ10 to TOQ13: TXDA0 to TXDA2: VDD: VSS: X1, X2: XT1, XT2: Timer output Transmit data Power supply Ground Crystal for main clock Crystal for subclock Timer input Port CT Port DL Regulator control Reset Serial clock Serial input Serial output Port CS RXDA0 to RXDA2: Receive data Preliminary User's Manual U17718EJ1V0UD 21 CHAPTER 1 INTRODUCTION www..com 1.6 1.6.1 Function Block Configuration Internal block diagram Flash memory NMI INTP0 to INTP10 TIQ00 to TIQ03 TIQ10 to TIQ13 TOQ00 to TOQ03 TOQ10 to TOQ13 TIP00 to TIP30, TIP01 to TIP31 TOP00 to TOP30, TOP01 to TOP31 INTC Note 1 16-bit timer/ counter Q: 2 ch 16-bit timer/ counter P: 4 ch DMAC 16-bit interval timer M: 1 ch SIB0, SIB1 PC CPU Instruction queue Multiplier 16 x 16 32 BCU ALU RAM 12 KB 32-bit barrel shifter System registers General-purpose registers 32 bits x 32 Internal oscillator SOB0, SOB1 SCKB0, SCKB1 CSIB: 2 ch Port CG PLL RXDA0 to RXDA2 ASCK0 UARTA: 3 ch PCS0, PCS1 PCM0 to PCM3 PCT0, PCT1, PCT4, PCT6 PDL0 to PDL13 P90 to P915 P70 to P715 P50 to P55 P40 to P42 P30 to P39 P10, P11 P00 to P06 TXDA0 to TXDA2 PCL CLKOUT XT1 XT2 X1 X2 RESET CLM LVI POC VDD VSS REGC FLMD0 FLMD1 BVDD BVSS DRST On-chip debug function DMS DDI DCK DDO EVDD EVSS Watchdog timer 2 Watch timer Key return function Regulator A/D converter ANI0 to ANI15 AVSS AVREF0 ADTRG KR0 to KR7 Note PD70F3706: 128 KB PD70F3707: 256 KB 22 Preliminary User's Manual U17718EJ1V0UD CHAPTER 1 INTRODUCTION www..com 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) Bus control unit (BCU) The BCU controls the internal buses. (3) ROM This is a 256 KB/128 KB flash memory mapped to addresses 0000000H to 003FFFFH/0000000H to 001FFFFH. It can be accessed from the CPU in one clock during instruction fetch. (4) RAM This is a 12 KB RAM mapped to addresses 3FFC000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access. (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP10) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed. (6) Clock generator (CG) A main clock oscillator that generates the main clock oscillation frequency (fX) and a subclock oscillator that generates the subclock oscillation frequency (fXT) are available. As the main clock frequency (fXX), fX is used as is in the clock-through mode and is multiplied by four in the PLL mode. The CPU clock frequency (fCPU) can be selected from seven types: fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (7) Internal oscillator An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP.). An internal oscillator supplies the clock for watchdog timer 2 and timer M. (8) Timer/counter Four-channel 16-bit timer/event counter P (TMP), two-channel 16-bit timer/event counter Q (TMQ), and onechannel 16-bit interval timer M (TMM) are provided on chip. (9) Watch timer This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or the 32.768 kHz fBRG from prescaler 3). The watch timer can also be used as an interval timer for the main clock. Preliminary User's Manual U17718EJ1V0UD 23 CHAPTER 1 INTRODUCTION www..com (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the internal oscillation clock or the main clock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/HG2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA) and 3wire variable-length serial interface B (CSIB). In the case of UARTA, data is transferred via the TXDA0 to TXDA2 and RXDA0 to RXDA2 pins. In the case of CSIB, data is transferred via the SOB0, SOB1, SIB0, SIB1, SCKB0, and SCKB1 pins. (12) A/D converter This 10-bit A/D converter includes 16 analog input pins. Conversion is performed using the successive approximation method. (13) DMA controller A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. (14) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins (8 channels). (15) On-chip debug function An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (OCDM). (16) Ports The general-purpose port functions and control pin functions are provided. For details, see CHAPTER 4 PORT FUNCTIONS. 24 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 2 PIN FUNCTIONS This section explains the names and functions of the pins of the V850ES/HG2. 2.1 Pin Function List Three I/O buffer power supplies, AVREF0, BVDD, and EVDD, are available. The relationship between the power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF0 BVDD EVDD Port 7 Port CM, port CS, port CT, port DL Port 0, port 1, port 3, port 4, port 5, port 9, RESET Corresponding Pin (1) Port pins Table 2-2. List of Pins (Port Pins) (1/2) Pin Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 I/O Port 4 3-bit I/O port Input/output can be specified in 1-bit units. TXDA2 RXDA2/INTP8 SIB0 SOB0 SCKB0 I/O I/O Port 1 2-bit I/O port Input/output can be specified in 1-bit units. Port 3 10-bit I/O port Input/output can be specified in 1-bit units. TXDA0 RXDA0/INTP7 ASCKA0/TIP00/TOP00/TOP01 TIP01/TOP01 TIP10/TOP10 TIP11/TOP11 - - I/O I/O Port 0 7-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function TIP31/TOP31 TIP30/TOP30 NMI INTP0/ADTRG INTP1 INTP2/DRST INTP3 INTP9 INTP10 Preliminary User's Manual U17718EJ1V0UD 25 CHAPTER 2 PIN FUNCTIONS www..com Table 2-2. List of Pins (Port Pins) (2/2) Pin Name P50 P51 P52 P53 P54 P55 P70 to P715 I/O Port 7 16-bit I/O port Input/output can be specified in 1-bit units. P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 PCM0 PCM1 PCM2 PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 to PDL4 PDL5 PDL6 to PDL13 I/O Port DL 14-bit I/O port Input/output can be specified in 1-bit units. FLMD1 - I/O I/O Port CS 2-bit I/O port Input/output can be specified in 1-bit units. Port CT 4-bit I/O port Input/output can be specified in 1-bit units. - - - - - I/O Port CM 4-bit I/O port Input/output can be specified in 1-bit units. CLKOUT - - - - INTP4/PCL INTP5 INTP6 - I/O Port 9 16-bit I/O port Input/output can be specified in 1-bit units. KR6/TXDA1 KR7/RXDA1 TIQ11/TOQ11 TIQ12/TOQ12 TIQ13/TOQ13 TIQ10/TOQ10 TIP21/TOP21 SIB1/TIP20/TOP20 SOB1 SCKB1 - - - I/O I/O Port 5 6-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function KR0/TIQ01/TOQ01 KR1/TIQ02/TOQ02 KR2/TIQ03/TOQ03/DDI KR3/TIQ00/TOQ00/DDO KR4/DCK KR5/DMS ANI0 to ANI15 26 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com (2) Non-port pins Table 2-3. List of Pins (Non-Port Pins) (1/3) Pin Name NMI Note I/O Input External interrupt input Function P02 Alternate Function (non-maskable, with analog noise eliminated) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTP8 INTP9 INTP10 TIP00 TIP01 TIP10 TIP11 TIP20 TIP21 TIP30 TIP31 TOP00 TOP01 Output Input External event/clock input (TMP00) External event input (TMP01) External event/clock input (TMP10) External event input (TMP11) External event/clock input (TMP20) External event input (TMP21) External event/clock input (TMP30) External event input (TMP31) Timer output (TMP00) Timer output (TMP01) Input External interrupt request input (maskable, with analog noise eliminated) P03/ADTRG P04 P05/DRST P06 P913/PCL P914 P915 P31/RXDA0 P39/RXDA2 P10 P11 P32/ASCKA0/TOP00/TOP01 P33/TOP01 P34/TOP10 P35/TOP11 P97/SIB1/TOP20 P96/TOP21 P01/TOP30 P00/TOP31 P32/ASCKA0/TIP00/TOP01 P32/ASCKA0/TIP00/TOP00 P33/TIP01 TOP10 TOP11 TOP20 TOP21 TOP30 TOP31 TIQ00 TIQ01 TIQ02 TIQ03 TIQ10 Input Timer output (TMP10) Timer output (TMP11) Timer output (TMP20) Timer output (TMP21) Timer output (TMP30) Timer output (TMP31) External event/clock input (TMQ00) External event input (TMQ01) External event input (TMQ02) External event input (TMQ03) External event/clock input (TMQ10) P34/TIP10 P35/TIP11 P97/SIB1/TIP20 P96/TIP21 P01/TIP30 P00/TIP31 P53/KR3/TOQ00/DDO P50/KR0/TOQ01 P51/KR1/TOQ02 P52/KR2/TOQ03/DDI P95/TOQ10 Note The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using INTF0 and INTR0 registers. Preliminary User's Manual U17718EJ1V0UD 27 CHAPTER 2 PIN FUNCTIONS www..com Table 2-3. List of Pins (Non-Port Pins) (2/3) Pin Name TIQ11 TIQ12 TIQ13 TOQ00 TOQ01 TOQ02 TOQ03 TOQ10 TOQ11 TOQ12 TOQ13 SIB0 SIB1 SOB0 SOB1 SCKB0 SCKB1 RXDA0 RXDA1 RXDA2 TXDA0 TXDA1 TXDA2 ASCKA0 ANI0 to ANI15 AVREF0 Input Input Input - Input Input Output Input I/O Output Input Output I/O Input Function External event input (TMQ11) External event input (TMQ12) External event input (TMQ13) Timer output (TMQ00) Timer output (TMQ01) Timer output (TMQ02) Timer output (TMQ03) Timer output (TMQ10) Timer output (TMQ11) Timer output (TMQ12) Timer output (TMQ13) Serial receive data input (CSIB0) Serial receive data input (CSIB1) Serial transmit data output (CSIB0) Serial transmit data output (CSIB1) Serial clock I/O (CSIB0) Serial clock I/O (CSIB1) Serial receive data input (UARTA0) Serial receive data input (UARTA1) Serial receive data input (UARTA2) Serial transmit data output (UARTA0) Serial transmit data output (UARTA1) Serial transmit data output (UARTA2) Baud rate clock input to UARTA0 Analog voltage input to A/D converter Reference voltage input to A/D converter, positive power supply for alternate-function port 7 AVSS Ground potential for A/D and D/A converters (same potential as VSS) ADTRG KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 DMS DDI DDO Input Input Output Debug mode select Debug data input Debug data output A/D converter external trigger input Key interrupt input P03/INTP0 P50/TIQ01/TOQ01 P51/TIQ02/TOQ02 P52/TIQ03/TOQ03/DDI P53/TIQ00/TOQ00/DDO P54/DCK P55/DMS P90/TXDA1 P91/RXDA1 P55/KR5 P52/KR2/TIQ03/TOQ03 P53/KR3/TIQ00/TOQ00 - Alternate Function P92/TOQ11 P93/TOQ12 P94/TOQ13 P53/KR3/TIQ00/DDO P50/KR0/TIQ01 P51/KR1/TIQ02 P52/KR2/TIQ03/DDI P95/TIQ10 P92/TIQ11 P93/TIQ12 P94/TIQ13 P40 P97/TIP20/TOP20 P41 P98 P42 P99 P31/INTP7 P91/KR7 P39/INTP8 P30 P90/KR6 P38 P32/TIP00/TOP00/TOP01 P70 to P715 - 28 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com Table 2-3. List of Pins (Non-Port Pins) (3/3) Pin Name DCK DRST FLMD0 FLMD1 CLKOUT PCL REGC RESET X1 X2 XT1 XT2 VDD VSS BVDD BVSS EVDD Output Output - Input Input - Input - - - - - - - Positive power supply pin for internal circuitry Ground potential for internal circuitry Positive power supply pin for bus interface and alternate-function ports Ground potential for bus interface and alternate-function ports Positive power supply pin for external circuitry (same potential as VDD) EVSS Ground potential for external circuitry (same potential as VSS) - Subclock resonator connection Internal system clock output Clock output (timing output of X1 input clock and subclock) Regulator output stabilizing capacitor connection System reset input Main clock resonator connection I/O Input Input Input Debug clock input Debug reset input Flash programming mode setting pins PDL5 PCM1 P913/INTP4 - - - - - - - - - - - Function Alternate Function P54/KR4 P05/INTP2 - Preliminary User's Manual U17718EJ1V0UD 29 CHAPTER 2 PIN FUNCTIONS www..com 2.2 Description of Pin Functions (1) P00 to P06 (port 0) ... 3-state I/O P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input, timer/counter I/O, external trigger of the A/D converter, and debug reset input. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by the INTR0 and INTF0 registers. An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0). (a) Port mode P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0). (b) Control mode (i) NMI (Non-maskable interrupt request) ... input This pin inputs a non-maskable interrupt request signal. (ii) INTP0 to INTP3 (External interrupt input) ... input These pins input external interrupt request signals. (iii) TIP30, TIP31 (Timer input) ... input These pins input an external count clock to timer P3 (TMP3). (iv) TOP30, TOP31 (Timer output) ... output These pins output a pulse signal from timer P3 (TMP3). (v) ADTRG (A/D trigger input) ... input This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode register 0 (ADA0M0). (vi) DRST (Debug reset) ... input This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this signal when the debug function is not used. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. 30 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com (2) P10, P11 (port 1) ... 3-state I/O P10 and P11 function as a 2-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as external interrupt request signal input in the control mode. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by INTR1 and INTF1 registers. An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1). (a) Port mode P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1). (b) Control mode (i) INTP9, INTP10 (External interrupt input) ... input These pins input an external interrupt request signal. (3) P30 to P39 (port 3) ... 3-state I/O P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface I/O, and timer/counter I/O. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by the INTR3 and INTF3 registers. An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3). (a) Port mode P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3). (b) Control mode (i) RXDA0, RXDA2 (Receive data) ... input These pins input the serial receive data of UARTA0 and UARTA2. (ii) TXDA0, TXDA2 (Transmit data) ... output These pins output the serial transmit data of UARTA0 and UARTA2. (iii) ASCKA0 (Asynchronous serial clock) ... input This is an input pin for UARTA0. (iv) INTP7, INTP8 (External interrupt input) ... input These pins input an external interrupt request signal. (v) TIP00, TIP01, TIP10, TIP11 (Timer input) ... input These are input pins for timers P0 and P1 (TMP0 and TMP1). (vi) TOP00, TOP01, TOP10, TOP11 (Timer output) ... output These are output pins for timers P0 and P1 (TMP0 and TMP1). Preliminary User's Manual U17718EJ1V0UD 31 CHAPTER 2 PIN FUNCTIONS www..com (4) P40 to P42 (port 4) ... 3-state I/O P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port mode or control mode in 1-bit units. An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4). (a) Port mode P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4). (b) Control mode (i) SIB0 (Serial input) ... input This pin inputs the serial receive data of CSIB0. (ii) SOB0 (Serial output) ... output This pin outputs the serial transmit data of CSIB0. (iii) SCKB0 (serial clock) ... 3-state I/O This pin inputs/outputs the serial clock of CSIB0. (5) P50 to P55 (Port 5) ... 3-state I/O P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as timer/counter I/O, debug function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units. An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5). (a) Port mode P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5). (b) Control mode (i) KR0 to KR5 (Key return) ... input These pins input a key interrupt. Their operation is specified by using the key return mode register (KRM) in the input port mode. (ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) ... input These are input pins for timer Q0 (TMQ0). (iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) ... output These are output pins for timer Q0 (TMQ0). (iv) DDI (Debug data input) ... input This pin inputs debug data to the on-chip debug circuit. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. (v) DDO (Debug data output) ... output This pin outputs debug data from the on-chip debug circuit. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. 32 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com (vi) DCK (Debug clock input) ... input This pin inputs a debug clock to the on-chip debug circuit. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. (vii) DMS (Debug mode select) ... input This pin selects the debug mode of the on-chip debug circuit. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. (6) P70 to P715 (port 7) ... 3-state I/O P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as analog input to the A/D converter in the control mode. When using the analog input pins, however, set this port in the input mode. At this time, do not read the port. (a) Port mode P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode registers 7L and 7H (PM7L and PM7H). (b) Control mode P70 to P715 function alternately as the ANI0 to ANI15 pins. (i) ANI0 to ANI15 (Analog input 0 to 15) ... input These pins input an analog signal to the A/D converter. (7) P90 to P915 (port 9) ... 3-state I/O P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output, external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units. The valid edge of P913 to P915 is specified by INTR9H and INTF9H registers. An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9). (a) Port mode P90 to P915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (PM9). (b) Control mode (i) SIB1 (Serial input) ... input This pin inputs the serial receive data of CSIB1. (ii) SOB1 (Serial output) ... output This pin outputs the serial transmit data of CSIB1. (iii) SCKB1 (Serial clock) ... 3-state I/O This pin inputs/outputs the serial clock of CSIB1. (iv) RXDA1 (Receive data) ... input This pin inputs the serial receive data of UARTA1. Preliminary User's Manual U17718EJ1V0UD 33 CHAPTER 2 PIN FUNCTIONS www..com (v) TXDA1 (Transmit data) ... output This pin outputs the serial transmit data of UARTA1. (vi) TIP20, TIP21 (Timer input) ... input These are input pins for timer P2 (TMP2). (vii) TOP20, TOP21 (Timer output) ... output These are output pins for timer P2 (TMP2). (viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) ... input These are input pins for timer Q1 (TMQ1). (ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) ... output These are output pins for timer Q1 (TMQ1). (x) PCL (Clock output) ... output This pin outputs a clock. (xi) INTP4 to INTP6 (External interrupt input) ... input These pins input an external interrupt request signal. (xii) KR6, KR7 (Key return) ... input These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in the input port mode. (8) PCM0 to PCM3 (port CM) ... 3-state I/O PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, these pins operate as bus clock output in the control mode. (a) Port mode PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM (PMCM). (b) Control mode (i) CLKOUT (Clock output) ... output This pin outputs an internally generated bus clock. (9) PCS0, PCS1 (port CS) ... 3-state I/O PCS0 and PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units. (a) Port mode PCS0 and PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS (PMCS). 34 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com (10) PCT0, PCT1, PCT4, PCT6 (port CT) ... 3-state I/O PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port that can be set to input or output in 1-bit units. (a) Port mode PCT0, PCT1, PCT4, and PCT6 can be set in the input or output mode in 1-bit units, by using port mode register CT (PMCT). (11) PDL0 to PDL13 (port DL) ... 3-state I/O PDL0 to PDL13 function as a 14-bit I/O port that can be set to input or output in 1-bit units. PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to FLMD0). At this time, be sure to input a low level to the FLMD1 pin. (a) Port mode PDL0 to PDL13 can be set in the input or output mode in 1-bit units, by using port mode register DL (PMDL). (12) RESET (Reset) ... input RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin regardless of the operating clock, the system is reset, taking precedence over all the other operations. This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start. (13) X1, X2 (Crystal for main clock) These pins are used to connect the resonator that generates the system clock. (14) XT1, XT2 (Crystal for subclock) These pins are used to connect the resonator that generates the subclock. (15) AVSS (Ground for analog) This is a ground pin for the A/D converter and alternate-function ports. (16) AVREF0 (Analog reference voltage) ... input This pin supplies positive analog power to the A/D converter and alternate-function ports. It also supplies a reference voltage to the A/D converter. (17) EVDD (Power supply for port) This pin supplies positive power to the I/O ports and alternate-function pins. (18) EVSS (Ground for port) This is a ground pin for the I/O ports and alternate-function pins. (19) VDD (Power supply) This pin supplies positive power. Connect all the VDD pins to a positive power supply. Preliminary User's Manual U17718EJ1V0UD 35 CHAPTER 2 PIN FUNCTIONS www..com (20) VSS (Ground) This is a ground pin. Connect all the VSS pins to ground. (21) FLMD0 (Flash programming mode) ... input This is a signal input pin for flash memory programming mode. Connect this pin to VSS in the normal operation mode. (22) BVDD (Power supply for port) This pin supplies positive power to the I/O ports and alternate-function pins. (23) BVSS (Ground for port) This is a ground pin for the I/O ports and alternate-function pins. (24) REGC (Regulator control) ... input This pin connects a capacitor for the regulator. 36 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2) Pin I/O Circuit Type Recommended Connection P00/TIP31/TOP31 P01/TIP30/TOP30 P02/NMI P03/INTP0/ADTRG P04/INTP1 P05/INTP2/DRST 5-W Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open 5-AF Input: Independently connect to EVSS Output: Leave open P06/INTP3 5-W Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open P10/INTP9 P11/INTP10 P30/TXDA0 P31/RXDA0/INTP7 P32/ASCKA0/TIP00/TOP00/ TOP01 P33/TIP01/TOP01 P34/TIP10/TOP10 P35/TIP11/TOP11 P36 P37 P38/TXDA2 P39/RXDA2/INTP8 P40/SIB0 P41/SOB0 P42/SCKB0 P50/KR0/TIQ01/TOQ01 P51/KR1/TIQ02/TOQ02 P52/KR2/TIQ03/TOQ03/DDI P53/KR3/TIQ00/TOQ00/DDO P54/KR4/DCK P55/KR5/DMS P70/ANI0 to P79/ANI9 P710/ANI10, P711/ANI11 P712/ANI12 to P715/ANI15 P90/KR6/TXDA1 P91/KR7/RXDA1 P92/TIQ11/TOQ11 P93/TIQ12/TOQ12 P94/TIQ13/TOQ13 P95/TIQ10/TOQ10 5-W Input: Independently connect to EVDD or EVSS via a resistor 11-G Input: Independently connect to AVREF0 or AVSS via a resistor 5-W 5-W 5-A 5-W 5-W Input: Independently connect to EVDD or EVSS via a resistor Input: Independently connect to EVDD or EVSS via a resistor 5-A 5-A 5-W 5-W Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open Output: Leave open Output: Leave open Output: Leave open Output: Leave open Preliminary User's Manual U17718EJ1V0UD 37 CHAPTER 2 PIN FUNCTIONS www..com (2/2) Pin I/O Circuit Type P96/TIP21/TOP21 P97/SIB1/TIP20/TOP20 P98/SOB1 P99/SCKB1 P910 P911 P912 P913/INTP4/PCL P914/INTP5 P915/INTP6 PCM0 PCM1/CLKOUT PCM2 PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 to PDL4 PDL5/FLMD1 PDL6 to PDL13 AVREF0 AVSS FLMD0 REGC RESET X1 X2 XT1 XT2 VDD VSS BVDD BVSS EVDD EVSS Note Recommended Connection 5-W Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open 5-A 5-W 5-A 5-W Input: Independently connect to EVDD or EVSS via a resistor Output: Leave open 5 Input: Independently connect to BVDD or BVSS via a resistor Output: Leave open 5 Input: Independently connect to BVDD or BVSS via a resistor Output: Leave open Input: Independently connect to BVDD or BVSS via a resistor Output: Leave open 5 5 Input: Independently connect to BVDD or BVSS via a resistor Output: Leave open - - - - 2 - - 16 16 - - - - - - Directly connect to VDD - Directly connect to VSS - - - - Connect to VSS via a resistor Leave open - - - - - - Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin. 38 Preliminary User's Manual U17718EJ1V0UD CHAPTER 2 PIN FUNCTIONS www..com 2.4 Pin I/O Circuits Figure 2-1. Pin I/O Circuit Types (1/2) Type 2 Type 5-AF VDD Pull-up enable VDD Data P-ch P-ch IN/OUT Output disable Input enable N-ch IN Schmitt-triggered input with hysteresis characteristics Pull-down enable N-ch Type 5 Type 11-G AVREF0 VDD Data P-ch IN/OUT P-ch IN/OUT Output disable Comparator + _ Data N-ch P-ch AVSS N-ch Output disable N-ch Input enable VREF (Threshold voltage) Input enable AVSS Preliminary User's Manual U17718EJ1V0UD 39 CHAPTER 2 PIN FUNCTIONS www..com Figure 2-1. Pin I/O Circuit Types (2/2) Type 5-A VDD Type 16 Pull-up enable Data Feedback cut-off P-ch VDD P-ch IN/OUT P-ch Output disable Input enable N-ch XT1 XT2 Type 5-W VDD Pull-up enable VDD Data P-ch IN/OUT Output disable N-ch P-ch Input enable 2.5 Cautions Note that the following pin may temporarily output an undefined level, even during reset upon power application. P53/KR3/TIQ00/TOQ00/DDO pin 40 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 3 CPU FUNCTION The CPU of the V850ES/HG2 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 50 ns (at 20 MHz operation) Memory space Program (physical address) space: 64 MB linear Data (logical address) space: General-purpose registers: 32 bits x 32 registers Internal 32-bit architecture 5-stage pipeline control Multiplication/division instruction Saturation operation instruction 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 4 GB linear Preliminary User's Manual U17718EJ1V0UD 41 CHAPTER 3 CPU FUNCTION www..com 3.2 CPU Register Set The registers of the V850ES/HG2 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User's Manual. (1) Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 CTBP DBPC CTPC PSW (2) System register set 0 31 EIPC EIPSW 0 (Zero register) (Assembler-reserved register) (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) (Interrupt status saving register) (Interrupt status saving register) FEPC (NMI status saving register) FEPSW (NMI status saving register) ECR (Interrupt source register) (Program status word) (CALLT execution status saving register) CTPSW (CALLT execution status saving register) (Exception/debug trap status saving register) DBPSW (Exception/debug trap status saving register) (CALLT base pointer) (Element pointer (EP)) (Link pointer (LP)) 31 PC 0 (Program counter) 42 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. When using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does not use r2, it can be used as a register for variables. Table 3-1. Program Registers Name r0 r1 r2 r3 r4 r5 Zero register Assembler-reserved register Usage Always holds 0. Used as working register to create 32-bit immediate data Operation Register for address/data variable (if real-time OS does not use r2) Stack pointer Global pointer Text pointer Used to create a stack frame when a function is called Used to access a global variable in the data area Used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 r30 r31 PC Register for address/data variable Element pointer Link pointer Program counter Used as base pointer to access memory Used when the compiler calls a function Holds the instruction address during program execution Remark For furthers details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the CA850 (C Compiler Package) Assembly Language User's Manual. (2) Program counter (PC) The program counter holds the instruction address during program execution. The lower 26 bits of this register are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs. Bit 0 is fixed to 0. This means that execution cannot branch to an odd address. 31 PC Fixed to 0 26 25 Instruction address during program execution 10 0 Default value 00000000H Preliminary User's Manual U17718EJ1V0UD 43 CHAPTER 3 CPU FUNCTION www..com 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2. System Register Numbers System Register Number 0 1 2 3 4 5 6 to 15 Interrupt status saving register (EIPC) Note 1 System Register Name Operand Specification LDSR Instruction STSR Instruction x x Note 2 x Note 2 Interrupt status saving register (EIPSW) NMI status saving register (FEPC) Note 1 Note 1 NMI status saving register (FEPSW) Interrupt source register (ECR) Program status word (PSW) Note 1 Reserved for future function expansion (operation is not guaranteed if these registers are accessed) CALLT execution status saving register (CTPC) CALLT execution status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) Reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 17 18 19 20 21 to 31 Note 2 Note 2 x x Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction or illegal opcode and the DBRET instruction. Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when execution is returned to the main routine by the RETI instruction after interrupt servicing (this is because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0). Remark : Can be accessed x: Access prohibited 44 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs). The address of the instruction next to the instruction under execution, except some instructions (see 15.8 Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable interrupt occurs. The current contents of the PSW are saved to EIPSW. Because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always fixed to 0). The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction. 31 EIPC 26 25 (Saved PC contents) 0 Default value 0xxxxxxxH (x: Undefined) 87 (Saved PSW contents) 0 Default value 000000xxH (x: Undefined) 000000 31 EIPSW 000000000000000000000000 Preliminary User's Manual U17718EJ1V0UD 45 CHAPTER 3 CPU FUNCTION www..com (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs. The current contents of the PSW are saved to FEPSW. Because only one set of NMI status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always fixed to 0). The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction. 31 FEPC 26 25 (Saved PC contents) 0 Default value 0xxxxxxxH (x: Undefined) 87 (Saved PSW contents) 0 Default value 000000xxH (x: Undefined) 000000 31 FEPSW 000000000000000000000000 (3) Interrupt source register (ECR) The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs. This register holds the exception code of each interrupt source. Because this register is a read-only register, data cannot be written to this register using the LDSR instruction. 31 ECR FECC 16 15 EICC 0 Default value 00000000H Bit position 31 to 16 15 to 0 Bit name FECC EICC Meaning Exception code of non-maskable interrupt (NMI) Exception code of exception or maskable interrupt 46 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will not be acknowledged while the LDSR instruction is being executed. Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 PSW RFU 876543210 NP EP ID SAT CY OV S Z Default value 00000020H Bit position 31 to 8 7 Flag name RFU NP Reserved field. Fixed to 0. Meaning Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an NMI request is acknowledged, disabling multiple interrupts. 0: NMI is not being serviced. 1: NMI is being serviced. 6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception occurs. Even if this bit is set, interrupt requests are acknowledged. 0: Exception is not being processed. 1: Exception is being processed. 5 ID Indicates whether a maskable interrupt can be acknowledged. 0: Interrupt enabled 1: Interrupt disabled 4 SAT Note Indicates that the result of a saturation operation has overflowed and is saturated. Because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: Not saturated 1: Saturated 3 CY Indicates whether a carry or a borrow occurs as a result of an operation. 0: Carry or borrow does not occur. 1: Carry or borrow occurs. 2 OV Note Indicates whether an overflow occurs during operation. 0: Overflow does not occur. 1: Overflow occurs. 1 S Note Indicates whether the result of an operation is negative. 0: The result is positive or 0. 1: The result is negative. 0 Z Indicates whether the result of an operation is 0. 0: The result is not 0. 1: The result is 0. Remark Also read Note on the next page. Preliminary User's Manual U17718EJ1V0UD 47 CHAPTER 3 CPU FUNCTION www..com (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed. Status of operation result SAT Maximum positive value is exceeded Maximum negative value is exceeded Positive (maximum value is not exceeded) Negative (maximum value is not exceeded) 1 1 Holds value before operation 1 1 0 Flag status OV 0 1 0 1 S Result of operation of saturation processing 7FFFFFFFH 80000000H Operation result itself (5) CALLT execution status saving registers (CTPC and CTPSW) CTPC and CTPSW are CALLT execution status saving registers. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those of the program status word (PSW) are saved to CTPSW. The contents saved to CTPC are the address of the instruction next to CALLT. The current contents of the PSW are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0). 31 CTPC 26 25 (Saved PC contents) 0 Default value 0xxxxxxxH (x: Undefined) 87 (Saved PSW contents) 0 Default value 000000xxH (x: Undefined) 000000 31 CTPSW 000000000000000000000000 48 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. The current contents of the PSW are saved to DBPSW. This register can be read or written only during the interval between the execution of the DBTRAP instruction or illegal opcode and the DBRET instruction. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0). The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction. 31 DBPC 26 25 (Saved PC contents) 0 Default value 0xxxxxxxH (x: Undefined) 87 (Saved PSW contents) 0 Default value 000000xxH (x: Undefined) 000000 31 DBPSW 000000000000000000000000 (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0). Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 CTBP 26 25 (Base address) 0 0 Default value 0xxxxxxxH (x: Undefined) 000000 Preliminary User's Manual U17718EJ1V0UD 49 CHAPTER 3 CPU FUNCTION www..com 3.3 Operation Modes The V850ES/HG2 has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started. (2) Flash memory programming mode In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/HG2 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications and that is executed via an on-chip debug emulator. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. 3.3.1 Specifying operation mode Specify the operation mode by using the FLMD0 and FLMD1 pins. In the normal mode, input a low level to the FLMD0 pin when reset is released. In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. Operation When Reset Is Released FLMD0 L H H FLMD1 x L H Normal operation mode Flash memory programming mode Setting prohibited Operation Mode After Reset Remark L: Low-level input H: High-level input x: Don't care 50 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.4 3.4.1 Address Space CPU address space For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Image on Address Space Image 63 4 GB Data space Peripheral I/O area Image 1 Internal RAM area Program space Use-prohibited area Internal RAM area 64 MB Use-prohibited area Use-prohibited area 64 MB Image 0 Internal ROM area 1 MB Internal ROM area Preliminary User's Manual U17718EJ1V0UD 51 CHAPTER 3 CPU FUNCTION www..com 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses. That the highest address and the lowest address of the program space are contiguous in this way is called wraparound. Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O area, instructions cannot be fetched from this area. Therefore, do not execute an operation in which the result of a branch address calculation affects this area. 00000001H 00000000H Program space (+) direction 03FFFFFFH 03FFFFFEH Program space (-) direction (2) Data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous, and wraparound occurs at the boundary of these addresses. 00000001H 00000000H Data space (+) direction FFFFFFFFH FFFFFFFEH Data space (-) direction 52 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.4.3 Memory map The areas shown below are reserved in the V850ES/HG2. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH (80 KB) 03FEC000H 03FEBFFFH On-chip peripheral I/O area (4 KB) 03FFFFFFH 03FFF000H 03FFEFFFH Internal RAM area (60 KB) Use prohibited Note 1 03FF0000H 03FEFFFFH 03FEF000H 03FEEFFFH Use prohibited 03FEC000H Use prohibited 00100000H 000FFFFFH Internal ROM areaNote 2 (1 MB) 00000000H Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the same area as the on-chip peripheral I/O area. 2. Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM area. Preliminary User's Manual U17718EJ1V0UD 53 CHAPTER 3 CPU FUNCTION www..com Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Use prohibited (program fetch prohibited area) Internal RAM area (60 KB)Note 03FF0000H 03FEFFFFH Use prohibited (program fetch prohibited area) 01000000H 00FFFFFFH Use prohibited 00100000H 000FFFFFH 00000000H Internal ROM area (1 MB) Note For details, see 3.4.4 (2) Internal RAM area. 54 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.4.4 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (128 KB) 128 KB are allocated to addresses 0000000H to 001FFFFH in the PD70F3706. Accessing addresses 0020000H to 00FFFFFH is prohibited. Figure 3-4. Internal ROM Area (128 KB) 00FFFFFH Access-prohibited area 0020000H 001FFFFH Internal ROM area (128 KB) 0000000H (b) Internal ROM (256 KB) 256 KB are allocated to addresses 0000000H to 003FFFFH in the PD70F3707. Accessing addresses 00040000H to 000FFFFFH is prohibited. Figure 3-5. Internal ROM Area (256 KB) 00FFFFFH Access-prohibited area 0040000H 003FFFFH Internal ROM area (256 KB) 0000000H Preliminary User's Manual U17718EJ1V0UD 55 CHAPTER 3 CPU FUNCTION www..com (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (12 KB) 12 KB are allocated to addresses 03FFC000H to 03FFEFFFH in the V850ES/HG2. Accessing addresses 03FF0000H to 03FFBFFFH is prohibited. Figure 3-6. Internal RAM Area (12 KB) Physical address space 03FFEFFFH Internal RAM 03FFC000H 03FFBFFFH Logical address space FFFFEFFFH FFFFC000H FFFFBFFFH Access-prohibited area 03FF0000H FFFF0000H (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-7. On-Chip Peripheral I/O Area Physical address space Logical address space 03FFFFFFH FFFFFFFFH On-chip peripheral I/O area (4 KB) 03FFF000H FFFFF000H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the onchip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area. 56 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. 3. Addresses not defined as registers are reserved for future expansion. The operation is undefined and not guaranteed when these addresses are accessed. 3.4.5 Recommended use of address space The architecture of the V850ES/HG2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer 32 KB can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access addresses 03FFC000H to 03FFEFFFH (12 KB). Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid fetch) straddling the on-chip peripheral I/O area does not occur. Preliminary User's Manual U17718EJ1V0UD 57 CHAPTER 3 CPU FUNCTION www..com (2) Data space With the V850ES/HG2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H 32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers. Figure 3-8. Wraparound (PD70F3707) 0003FFFFH 00007FFFH Internal ROM area 32 KB (R = ) 0 0 0 0 0 0 0 0 H FFFFF000H FFFFEFFFH FFFFC000H FFFEBFFFH On-chip peripheral I/O area Internal RAM area 4 KB 12 KB Access-prohibited area 16 KB FFFF8000H 58 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com Figure 3-9. Recommended Memory Map Program space FFFFFFFFH Data space On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFFFFFFH FFFF0000H FFFEFFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFFC000H FFFFBFFFH FFFF0000H FFFEFFFFH Use prohibited 03FFF000H 03FFEFFFH 03FFC000H 03FFBFFFH 03FF0000H 03FEFFFFH Use prohibited Internal RAM 04000000H 03FFFFFFH Program space 64 MB Use prohibited 00100000H 000FFFFFH Internal ROM 00000000H 00100000H 000FFFFFH 00040000H 0003FFFFH 00000000H Internal ROM Internal ROM Remarks 1. indicates the recommended area. 2. This figure is the recommended memory map of the PD70F3707. Preliminary User's Manual U17718EJ1V0UD 59 CHAPTER 3 CPU FUNCTION www..com 3.4.6 Peripheral I/O registers (1/9) Address FFFFF004H FFFFF004H FFFFF005H FFFFF008H FFFFF00AH FFFFF00CH FFFFF024H FFFFF024H FFFFF025H FFFFF028H FFFFF02AH FFFFF02CH FFFFF04CH FFFFF06EH FFFFF080H FFFFF082H FFFFF084H FFFFF086H FFFFF088H FFFFF08AH FFFFF08CH FFFFF08EH FFFFF090H FFFFF092H FFFFF094H FFFFF096H FFFFF098H FFFFF09AH FFFFF09CH FFFFF09EH FFFFF0C0H FFFFF0C2H FFFFF0C4H FFFFF0C6H FFFFF0D0H FFFFF0D2H FFFFF0D4H FFFFF0D6H FFFFF0E0H FFFFF0E2H FFFFF0E4H FFFFF0E6H Port DL Port DLL Port DLH Port CS Port CT Port CM Function Register Name PDL Symbol R/W R/W Manipulatable Bits 1 8 16 Default Value Undefined Undefined Undefined Undefined Undefined Undefined FFFFH FFH FFH FFH FFH FFH 00H 77H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H 0000H 0000H 0000H 00H 00H 00H 00H PDLL PDLH PCS PCT PCM PMDL PMDLL PMDLH PMCS PMCT PMCM PMCCM VSWC DSA0L DSA0H DDA0L DDA0H DSA1L DSA1H DDA1L DDA1H DSA2L DSA2H DDA2L DDA2H DSA3L DSA3H DDA3L DDA3H DBC0 DBC1 DBC2 DBC3 DADC0 DADC1 DADC2 DADC3 DCHC0 DCHC1 DCHC2 DCHC3 Port mode register DL Port mode register DLL Port mode register DLH Port mode register CS Port mode register CT Port mode register CM Port mode control register CM System wait control register DMA source address register 0L DMA source address register 0H DMA destination address register 0L DMA destination address register 0H DMA source address register 1L DMA source address register 1H DMA destination address register 1L DMA destination address register 1H DMA source address register 2L DMA source address register 2H DMA destination address register 2L DMA destination address register 2H DMA source address register 3L DMA source address register 3H DMA destination address register 3L DMA destination address register 3H DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 60 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (2/9) Address FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF104H FFFFF104H FFFFF105H FFFFF106H FFFFF106H FFFFF107H FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH Function Register Name Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 2 Interrupt mask register 2L Interrupt mask register 2H Interrupt mask register 3 Interrupt mask register 3L Interrupt mask register 3H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Symbol IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR2 IMR2L IMR2H IMR3 IMR3L IMR3H LVIIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PIC7 TQ0OVIC TQ0CCIC0 TQ0CCIC1 TQ0CCIC2 TQ0CCIC3 TP0OVIC TP0CCIC0 TP0CCIC1 TP1OVIC TP1CCIC0 TP1CCIC1 TP2OVIC TP2CCIC0 TP2CCIC1 TP3OVIC TP3CCIC0 TP3CCIC1 TM0EQIC0 CB0RIC CB0TIC CB1RIC R/W R/W Manipulatable Bits 1 8 16 FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H Default Value Preliminary User's Manual U17718EJ1V0UD 61 CHAPTER 3 CPU FUNCTION www..com (3/9) Address FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF160H FFFFF162H FFFFF164H FFFFF166H FFFFF168H FFFFF16AH FFFFF16CH FFFFF16EH FFFFF170H FFFFF172H FFFFF174H FFFFF176H FFFFF178H FFFFF182H FFFFF184H FFFFF186H FFFFF188H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H FFFFF201H FFFFF202H FFFFF203H FFFFF204H FFFFF205H FFFFF210H FFFFF211H FFFFF212H FFFFF213H FFFFF214H FFFFF215H FFFFF216H FFFFF217H FFFFF218H FFFFF219H Function Register Name Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register In-service priority register Command register Power save control register A/D converter mode register 0 A/D converter mode register 1 A/D converter channel specification register A/D converter mode register 2 Power-fail compare mode register Power-fail compare threshold value register A/D conversion result register 0 A/D conversion result register 0H A/D conversion result register 1 A/D conversion result register 1H A/D conversion result register 2 A/D conversion result register 2H A/D conversion result register 3 A/D conversion result register 3H A/D conversion result register 4 A/D conversion result register 4H Symbol CB1TIC UA0RIC UA0TIC UA1RIC UA1TIC ADIC KRIC WTIIC WTIC PIC8 PIC9 PIC10 TQ1OVIC TQ1CCIC0 TQ1CCIC1 TQ1CCIC2 TQ1CCIC3 UA2RIC UA2TIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 ISPR PRCMD PSC ADA0M0 ADA0M1 ADA0S ADA0M2 ADA0PFM ADA0PFT ADA0CR0 ADA0CR0H ADA0CR1 ADA0CR1H ADA0CR2 ADA0CR2H ADA0CR3 ADA0CR3H ADA0CR4 ADA0CR4H R R W R/W R/W R/W Manipulatable Bits 1 8 16 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 00H Undefined 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default Value 62 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (4/9) Address FFFFF21AH FFFFF21BH FFFFF21CH FFFFF21DH FFFFF21EH FFFFF21FH FFFFF220H FFFFF221H FFFFF222H FFFFF223H FFFFF224H FFFFF225H FFFFF226H FFFFF227H FFFFF228H FFFFF229H FFFFF22AH FFFFF22BH FFFFF22CH FFFFF22DH FFFFF22EH FFFFF22FH FFFFF300H FFFFF308H FFFFF318H FFFFF400H FFFFF402H FFFFF406H FFFFF406H FFFFF407H FFFFF408H FFFFF40AH FFFFF40EH FFFFF40FH FFFFF412H FFFFF412H FFFFF413H FFFFF420H FFFFF422H FFFFF426H FFFFF426H FFFFF427H Function Register Name A/D conversion result register 5 A/D conversion result register 5H A/D conversion result register 6 A/D conversion result register 6H A/D conversion result register 7 A/D conversion result register 7H A/D conversion result register 8 A/D conversion result register 8H A/D conversion result register 9 A/D conversion result register 9H A/D conversion result register 10 A/D conversion result register 10H A/D conversion result register 11 A/D conversion result register 11H A/D conversion result register 12 A/D conversion result register 12H A/D conversion result register 13 A/D conversion result register 13H A/D conversion result register 14 A/D conversion result register 14H A/D conversion result register 15 A/D conversion result register 15H Key return mode register Selector operation control register 0 Noise elimination control register Port 0 Port 1 Port 3 Port 3L Port 3H Port 4 Port 5 Port 7L Port 7H Port 9 Port 9L Port 9H Port mode register 0 Port mode register 1 Port mode register 3 Port mode register 3L Port mode register 3H Symbol ADA0CR5 ADA0CR5H ADA0CR6 ADA0CR6H ADA0CR7 ADA0CR7H ADA0CR8 ADA0CR8H ADA0CR9 ADA0CR9H ADA0CR10 ADA0CR10H ADA0CR11 ADA0CR11H ADA0CR12 ADA0CR12H ADA0CR13 ADA0CR13H ADA0CR14 ADA0CR14H ADA0CR15 ADA0CR15H KRM SELCNT0 NFC P0 P1 P3 P3L P3H P4 P5 P7L P7H P9 P9L P9H PM0 PM1 PM3 PM3L PM3H R/W R/W R Manipulatable Bits 1 8 16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFH FFH FFFFH FFH FFH Default Value Preliminary User's Manual U17718EJ1V0UD 63 CHAPTER 3 CPU FUNCTION www..com (5/9) Address FFFFF428H FFFFF42AH FFFFF42EH FFFFF42FH FFFFF432H FFFFF432H FFFFF433H FFFFF440H FFFFF442H FFFFF446H FFFFF446H FFFFF448H FFFFF44AH FFFFF452H FFFFF452H FFFFF453H FFFFF460H FFFFF466H FFFFF46AH FFFFF472H FFFFF472H FFFFF473H FFFFF540H FFFFF541H FFFFF542H FFFFF543H FFFFF544H FFFFF545H FFFFF546H FFFFF548H FFFFF54AH FFFFF54CH FFFFF54EH FFFFF590H FFFFF591H FFFFF592H FFFFF593H FFFFF594H FFFFF595H FFFFF596H FFFFF598H FFFFF59AH Function Register Name Port mode register 4 Port mode register 5 Port mode register 7L Port mode register 7H Port mode register 9 Port mode register 9L Port mode register 9H Port mode control register 0 Port mode control register 1 Port mode control register 3 Port mode control register 3L Port mode control register 4 Port mode control register 5 Port mode control register 9 Port mode control register 9L Port mode control register 9H Port function control register 0 Port function control register 3L Port function control register 5 Port function control register 9 Port function control register 9L Port function control register 9H TMQ0 control register 0 TMQ0 control register 1 TMQ0 I/O control register 0 TMQ0 I/O control register 1 TMQ0 I/O control register 2 TMQ0 option register 0 TMQ0 capture/compare register 0 TMQ0 capture/compare register 1 TMQ0 capture/compare register 2 TMQ0 capture/compare register 3 TMQ0 counter read buffer register TMP0 control register 0 TMP0 control register 1 TMP0 I/O control register 0 TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register PM4 PM5 PM7L PM7H PM9 PM9L PM9H PMC0 PMC1 PMC3 PMC3L PMC4 PMC5 PMC9 PMC9L PMC9H PFC0 PFC3L PFC5 PFC9 PFC9L PFC9H TQ0CTL0 TQ0CTL1 TQ0IOC0 TQ0IOC1 TQ0IOC2 TQ0OPT0 TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 TQ0CNT TP0CTL0 TP0CTL1 TP0IOC0 TP0IOC1 TP0IOC2 TP0OPT0 TP0CCR0 TP0CCR1 TP0CNT R R R/W Symbol R/W R/W Manipulatable Bits 1 8 16 FFH FFH FFH FFH FFFFH FFH FFH 00H 00H 0000H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H Default Value 64 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (6/9) Address FFFFF5A0H FFFFF5A1H FFFFF5A2H FFFFF5A3H FFFFF5A4H FFFFF5A5H FFFFF5A6H FFFFF5A8H FFFFF5AAH FFFFF5B0H FFFFF5B1H FFFFF5B2H FFFFF5B3H FFFFF5B4H FFFFF5B5H FFFFF5B6H FFFFF5B8H FFFFF5BAH FFFFF5C0H FFFFF5C1H FFFFF5C2H FFFFF5C3H FFFFF5C4H FFFFF5C5H FFFFF5C6H FFFFF5C8H FFFFF5CAH FFFFF610H FFFFF611H FFFFF612H FFFFF613H FFFFF614H FFFFF615H FFFFF616H FFFFF618H FFFFF61AH FFFFF61CH FFFFF61EH FFFFF680H FFFFF690H FFFFF694H FFFFF6C0H Function Register Name TMP1 control register 0 TMP1 control register 1 TMP1 I/O control register 0 TMP1 I/O control register 1 TMP1 I/O control register 2 TMP1 option register 0 TMP1 capture/compare register 0 TMP1 capture/compare register 1 TMP1 counter read buffer register TMP2 control register 0 TMP2 control register 1 TMP2 I/O control register 0 TMP2 I/O control register 1 TMP2 I/O control register 2 TMP2 option register 0 TMP2 capture/compare register 0 TMP2 capture/compare register 1 TMP2 counter read buffer register TMP3 control register 0 TMP3 control register 1 TMP3 I/O control register 0 TMP3 I/O control register 1 TMP3 I/O control register 2 TMP3 option register 0 TMP3 capture/compare register 0 TMP3 capture/compare register 1 TMP3 counter read buffer register TMQ1 control register 0 TMQ1 control register 1 TMQ1 I/O control register 0 TMQ1 I/O control register 1 TMQ1 I/O control register 2 TMQ1 timer option register 0 TMQ1 capture/compare register 0 TMQ1 capture/compare register 1 TMQ1 capture/compare register 2 TMQ1 capture/compare register 3 TMQ1 counter read buffer register Watch timer operation mode register TMM0 control register 0 TMM0 compare register 0 Oscillation stabilization time select register Symbol TP1CTL0 TP1CTL1 TP1IOC0 TP1IOC1 TP1IOC2 TP1OPT0 TP1CCR0 TP1CCR1 TP1CNT TP2CTL0 TP2CTL1 TP2IOC0 TP2IOC1 TP2IOC2 TP2OPT0 TP2CCR0 TP2CCR1 TP2CNT TP3CTL0 TP3CTL1 TP3IOC0 TP3IOC1 TP3IOC2 TP3OPT0 TP3CCR0 TP3CCR1 TP3CNT TQ1CTL0 TQ1CTL1 TQ1IOC0 TQ1IOC1 TQ1IOC2 TQ1OPT0 TQ1CCR0 TQ1CCR1 TQ1CCR2 TQ1CCR3 TQ1CNT WTM TM0CTL0 TM0CMP0 OSTS R R/W R R/W R R/W R R/W R/W R/W Manipulatable Bits 1 8 16 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 0000H 0000H 00H 00H 0000H 06H Default Value Preliminary User's Manual U17718EJ1V0UD 65 CHAPTER 3 CPU FUNCTION www..com (7/9) Address FFFFF6C1H FFFFF6D0H FFFFF6D1H FFFFF706H FFFFF70AH FFFFF712H FFFFF712H FFFFF713H FFFFF802H FFFFF80CH FFFFF810H FFFFF812H FFFFF814H FFFFF816H FFFFF820H FFFFF824H FFFFF828H FFFFF82CH FFFFF82EH FFFFF82FH FFFFF870H FFFFF888H FFFFF890H FFFFF891H FFFFF892H FFFFF8B0H FFFFF8B1H FFFFF9FCH FFFFF9FEH FFFFFA00H FFFFFA01H FFFFFA02H FFFFFA03H FFFFFA04H FFFFFA06H FFFFFA07H FFFFFA10H FFFFFA11H FFFFFA12H FFFFFA13H FFFFFA14H Function Register Name PLL lockup time specification register Watchdog timer mode register 2 Watchdog timer enable register Port function control expansion register 3L Port function control expansion register 5 Port function control expansion register 9 Port function control expansion register 9L Port function control expansion register 9H System status register Internal oscillation mode register DMA trigger factor register 0 DMA trigger factor register 1 DMA trigger factor register 2 DMA trigger factor register 3 Power save mode register Lock register Processor clock control register PLL control register CPU operating clock status register Programmable clock mode register Clock monitor mode register Reset source flag register Low-voltage detection register Low-voltage detection level select register Internal RAM data status register Prescaler mode register 0 Prescaler compare register 0 On-chip debug mode register Peripheral emulation register 1 UARTA0 control register 0 UARTA0 control register 1 UARTA0 control register 2 UARTA0 option control register 0 UARTA0 status register UARTA0 receive data register UARTA0 transmit data register UARTA1 control register 0 UARTA1 control register 1 UARTA1 control register 2 UARTA1 option control register 0 UARTA1 status register Symbol PLLS WDTM2 WDTE PFCE3L PFCE5 PFCE9 PFCE9L PFCE9H SYS RCM DTFR0 DTFR1 DTFR2 DTFR3 PSMR LOCKR PCC PLLCTL CCLS PCLM CLM RESF LVIM LVIS RAMS PRSM0 PRSCM0 OCDM PEMU1 UA0CTL0 UA0CTL1 UA0CTL2 UA0OPT0 UA0STR UA0RX UA0TX UA1CTL0 UA1CTL1 UA1CTL2 UA1OPT0 UA1STR R R/W R R/W R R/W R/W R/W Manipulatable Bits 1 8 16 03H 67H 9AH 00H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 03H 01H 00H 00H 00H 00H 00H 00H 01H 00H 00H 01H 00H 10H 00H FFH 14H 00H FFH FFH 10H 00H FFH 14H 00H Default Value Caution For details of the OCDM register, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. Preliminary User's Manual U17718EJ1V0UD 66 CHAPTER 3 CPU FUNCTION www..com (8/9) Address FFFFFA16H FFFFFA17H FFFFFA20H FFFFFA21H FFFFFA22H FFFFFA23H FFFFFA24H FFFFFA26H FFFFFA27H FFFFFB00H FFFFFB04H FFFFFB08H FFFFFB0CH FFFFFB10H FFFFFB14H FFFFFB18H FFFFFB1CH FFFFFB50H FFFFFB54H FFFFFB58H FFFFFB5CH FFFFFB60H FFFFFB64H FFFFFB68H FFFFFB6CH FFFFFC00H FFFFFC02H FFFFFC06H FFFFFC06H FFFFFC13H FFFFFC20H FFFFFC22H FFFFFC26H FFFFFC26H FFFFFC33H FFFFFC40H FFFFFC42H FFFFFC46H FFFFFC46H FFFFFC47H FFFFFC48H FFFFFC4AH Function Register Name UARTA1 receive data register UARTA1 transmit data register UARTA2 control register 0 UARTA2 control register 1 UARTA2 control register 2 UARTA2 option control register 0 UARTA2 status register UARTA2 receive data register UARTA2 transmit data register TIP00 pin noise elimination control register TIP01 pin noise elimination control register TIP10 pin noise elimination control register TIP11 pin noise elimination control register TIP20 pin noise elimination control register TIP21 pin noise elimination control register TIP30 pin noise elimination control register TIP31 pin noise elimination control register TIQ00 pin noise elimination control register TIQ01 pin noise elimination control register TIQ02 pin noise elimination control register TIQ03 pin noise elimination control register TIQ10 pin noise elimination control register TIQ11 pin noise elimination control register TIQ12 pin noise elimination control register TIQ13 pin noise elimination control register External interrupt falling edge specification register 0 External interrupt falling edge specification register 1 External interrupt falling edge specification register 3 External interrupt falling edge specification register 3L Symbol UA1RX UA1TX UA2CTL0 UA2CTL1 UA2CTL2 UA2OPT0 UA2STR UA2RX UA2TX P00NFC P01NFC P10NFC P11NFC P20NFC P21NFC P30NFC P31NFC Q00NFC Q01NFC Q02NFC Q03NFC Q10NFC Q11NFC Q12NFC Q13NFC INTF0 INTF1 INTF3 INTF3L R R/W R/W R R/W Manipulatable Bits 1 8 16 FFH FFH 10H 00H FFH 14H 00H FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 00H Default Value External interrupt falling edge specification register 9H INTF9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 1 External interrupt rising edge specification register 3 External interrupt rising edge specification register 3L External interrupt rising edge specification register 9H Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 3L Pull-up resistor option register 3H Pull-up resistor option register 4 Pull-up resistor option register 5 INTR0 INTR1 INTR3 INTR3L INTR9H PU0 PU1 PU3 PU3L PU3H PU4 PU5 Preliminary User's Manual U17718EJ1V0UD 67 CHAPTER 3 CPU FUNCTION www..com (9/9) Address FFFFFC52H FFFFFC52H FFFFFC53H FFFFFD00H FFFFFD01H FFFFFD02H FFFFFD03H FFFFFD04H FFFFFD04H FFFFFD06H FFFFFD06H FFFFFD10H FFFFFD11H FFFFFD12H FFFFFD13H FFFFFD14H FFFFFD14H FFFFFD16H FFFFFD16H Function Register Name Pull-up resistor option register 9 Pull-up resistor option register 9L Pull-up resistor option register 9H CSIB0 control register 0 CSIB0 control register 1 CSIB0 control register 2 CSIB0 status register CSIB0 receive data register CSIB0 receive data register L CSIB0 transmit data register CSIB0 transmit data register L CSIB1 control register 0 CSIB1 control register 1 CSIB1 control register 2 CSIB1 status register CSIB1 receive data register CSIB1 receive data register L CSIB1 transmit data register CSIB1 transmit data register L Symbol PU9 PU9L PU9H CB0CTL0 CB0CTL1 CB0CTL2 CB0STR CB0RX CB0RXL CB0TX CB0TXL CB1CTL0 CB1CTL1 CB1CTL2 CB1STR CB1RX CB1RXL CB1TX CB1TXL R/W R R/W R R/W R/W Manipulatable Bits 1 8 16 0000H 00H 00H 01H 00H 00H 00H 0000H 00H 0000H 00H 01H 00H 00H 00H 0000H 00H 0000H 00H Default Value 68 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to an inadvertent program loop. The V850ES/HG2 has the following seven special registers. * Power save control register (PSC) * Processor clock control register (PCC) * Clock monitor mode register (CLM) * Reset source flag register (RESF) * Low-voltage detection register (LVIM) * Internal RAM data status register (RAMS) * On-chip debug mode register (OCDM) In addition, the PRCDM register is provided to protect against a write access to the special registers so that the application system does not inadvertently stop due to an inadvertent program loop. A write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the SYS register. Preliminary User's Manual U17718EJ1V0UD 69 CHAPTER 3 CPU FUNCTION www..com (1) Setting data to special registers Set data to the special registers in the following sequence. <1> <2> <3> <4> Disable DMA operation. Prepare data to be set to the special register in a general-purpose register. Write the data prepared in <2> to the PRCMD register. Write the setting data to the special register (by using the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) (<5> to <9> Insert NOP instructions (5 instructions).)Note <10> Enable DMA operation if necessary. [Example] With PSC register (setting standby mode) ST.B r11, PSMR[r0] <1>CLR1 0, DCHCn[r0] <2>MOV0x02, r10 <3>ST.B r10, PRCMD[r0] ; Write PRCMD register. <4>ST.B r10, PSC[r0] <5>NOPNote <6>NOPNote <7>NOPNote <8>NOP Note ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes). ; Disable DMA operation. n = 0 to 3 ; Set PSC register. ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Enable DMA operation. n = 0 to 3 <9>NOPNote <10>SET1 0, DCHCn[r0] (next instruction) There is no special sequence to read a special register. Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not acknowledged. This is because it is assumed that steps <3> and <4> above are performed by successive store instructions. If another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. Although dummy data is written to the PRCMD register, use the same general-purpose register used to set the special register (<4> in Example) to write data to the PRCMD register (<3> in Example). The same applies when a general-purpose register is used for addressing. 70 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to an inadvertent program loop. The first write access to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read). After reset: Undefined 7 PRCMD REG7 6 W Address: FFFFF1FCH 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0 REG6 Preliminary User's Manual U17718EJ1V0UD 71 CHAPTER 3 CPU FUNCTION www..com (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF802H SYS 0 0 0 0 0 0 0 PRERR PRERR 0 1 Detects protection error Protection error did not occur Protection error occurred The PRERR flag operates under the following conditions. (a) Set condition (PRERR flag = 1) (i) When data is written to a special register without writing anything to the PRCMD register (when <4> is executed without executing <3> in 3.4.7 (1) Setting data to special registers) (ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1) Setting data to special registers is not the setting of a special register) Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between an operation to write the PRCMD register and an operation to write a special register, the PRERR flag is not set, and the set data can be written to the special register. (b) Clear condition (PRERR flag = 0) (i) When 0 is written to the PRERR flag (ii) When the system is reset Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes precedence). 2. If data is written to the PRCMD register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is set to 1. 72 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com 3.4.8 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/HG2. * System wait control register (VSWC) * On-chip debug mode register (OCDM) * Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary. When using the external bus, set each pin to the alternate-function bus control pin mode by using the portrelated registers after setting the above registers. (a) System wait control register (VSWC) The VSWC register controls wait of bus access to the on-chip peripheral I/O registers. Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). VSWC register in accordance with the frequency used. The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H). Operating Frequency (fCLK) 32 kHz fCLK < 16.6 MHz 16.6 MHz fCLK 20 MHz Set Value of VSWC 00H 01H Number of Waits 0 (no waits) 1 The V850ES/HG2 requires wait cycles according to the operating frequency. Set the following value to the (b) On-chip debug mode register (OCDM) For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. (c) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2. Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to activate this operation. For details, see CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2. Preliminary User's Manual U17718EJ1V0UD 73 CHAPTER 3 CPU FUNCTION www..com (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction but enters the wait state. If this wait state occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. This must be taken into consideration if real-time processing is required. When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the wait states set by the VSWC register. The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this time are shown below. Peripheral Function 16-bit timer/event counter P (TMP) (n = 0 to 3) Register Name TPnCNT TPnCCR0, TPnCCR1 Read Write Read 16-bit timer/event counter Q (TMQ) (m = 0, 1) TQmCNT TQmCCR0 to TQmCCR3 Read Write Read Watchdog timer 2 (WDT2) A/D converter WDTM2 ADA0M0 ADA0CR0 to ADA0CR15 ADA0CR0H to ADA0CR15H Write (when WDT2 operating) Read Read Read Access 1 or 2 * 1st access: No wait * Continuous write: 3 or 4 1 or 2 1 or 2 * 1st access: No wait * Continuous write: 3 or 4 1 or 2 3 1 or 2 1 or 2 1 or 2 k Number of clocks necessary for access = 3 + i + j + (2 + j) x k Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated, it can only be cleared by a reset. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock Remark i: j: Values (0 or 1) of higher 4 bits of VSWC register Values (0 or 1) of lower 4 bits of VSWC register 74 Preliminary User's Manual U17718EJ1V0UD CHAPTER 3 CPU FUNCTION www..com (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: * sld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu sld.b, sld.h, sld.w, sld.bu, sld.hu * Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 * * * not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 If the decode operation of the mov instruction Preliminary User's Manual U17718EJ1V0UD 75 www..com CHAPTER 4 PORT FUNCTIONS 4.1 Features O I/O ports: 84 O Port pins function alternately as other peripheral-function I/O pins O Can be set in input or output mode in 1-bit units. 4.2 Basic Configuration of Ports The V850ES/HG2 has a total of 84 I/O ports, ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DL. The port configuration is shown below. Figure 4-1. Port Configuration P00 Port 0 P06 Port 1 P10 P11 P30 Port 3 P39 P40 Port 4 P42 P50 Port 5 P55 P70 Port 7 P715 P90 Port 9 P915 PCM0 Port CM PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 Port DL PDL13 Port CS Port CT 76 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Table 4-1. Configuration of Ports Item Control registers Configuration Port mode register (PMn: n = 0, 1, 3, 4, 5, 7L, 7H, 9, CM, CS, CT, or DL) Port mode control register (PMCn: n = 0, 1, 3, 4, 5, 9, or CM) Port function control register (PFCn: n = 0, 3L, 5, or 9) Port function control expansion register (PFCEn: n = 3L, 5, or 9) Pull-up resistor option register (PUn: n = 0, 1, 3, 4, 5, or 9) Ports 84 Table 4-2. Pin I/O Buffer Power Supplies Power Supply AVREF0 BVDD EVDD Port 7 Port CM, port CS, port CT, port DL Port 0, port 1, port 3, port 4, port 5, port 9, RESET Corresponding Pin Preliminary User's Manual U17718EJ1V0UD 77 CHAPTER 4 PORT FUNCTIONS www..com 4.3 4.3.1 Port Functions Operation of port function The operation of a port differs depending on setting of the input or output mode, as follows. (1) Writing to I/O port (a) In output mode A value can be written to the output latch by using a transfer instruction. The contents of the output latch are output from the pin. Once data has been written to the output latch, it is retained until new data is written to the output latch. (b) In input mode A value can be written to the output latch by using a transfer instruction. Because the output buffer is off, however, the status of the pin remains unchanged. Once data has been written to the output latch, it is retained until new data is written to the output latch. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. (2) Reading from I/O port (a) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (b) In input mode The status of the pin can be read by using a transfer instruction. The contents of the output latch are not changed. (3) Operation of I/O port (a) In output mode An operation is performed on the contents of the output latch and the result is written to the output latch. The contents of the output latch are output from the pin. Once data has been written to the output latch, it is retained until new data is written to the output latch. (b) In input mode The contents of the output latch become undefined. Because the output buffer is off, however, the status of the pin remains unchanged. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. 78 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.2 Notes on setting port pins (1) The number of ports and alternate functions differs depending on the product. Set the registers related to the unavailable ports and alternate functions to the value after reset. (2) Set the registers of the ports using the following procedure. <1> Set port function control register n (PFCn) and port function control expansion register n (PFCEn). <2> Set port mode control register n (PMCn). <3> Set external interrupt falling edge specification register n (INTFn) and external interrupt rising edge specification register n (INTRn). If the PFCn and PFCEn registers are set after the PMCn register was set, an unexpected peripheral function pin may be set while the PFCn and PFCEn registers are being set. (3) The PUnm bit (which connects an on-chip pull-up resistor) of the PUn register is valid only in the input mode (PMnm bit of PMn register = 1). In the output mode (PMnm bit of PMn register = 0), the on-chip pull-up register is disconnected by hardware. (4) Reading the pin level and port latch is controlled by the port mode register (PMn). The same applies when an alternate function is used. (5) The Schmitt (SHMT)-trigger input buffer does not operate as an SHMT buffer when it is read in the port mode. Preliminary User's Manual U17718EJ1V0UD 79 CHAPTER 4 PORT FUNCTIONS www..com 4.3.3 Port 0 Port 0 is a 7-bit port (P00 to P06) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 0 * The input/output data of the port can be specified in 1-bit units. Specified by port register 0 (P0) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 0 (PM0) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 0 (PMC0) * Control mode 1 or control mode 2 can be specified in 1-bit units. Specified by port function control register 0 (PFC0) * An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 0 (PU0) * The valid edge of the external interrupt (alternate function) can be specified in 1-bit units. Specified by external interrupt falling edge specification register 0 (INTF0) and external interrupt rising edge specification register 0 (INTR0) Port 0 functions alternately as the following pins. Table 4-3. Alternate-Function Pins of Port 0 Pin Name Port 0 P00 P01 P02 P03 P04 P05 P06 Alternate-Function Pin Name TP31/TOP31 TP30/TOP30 NMI Note 1 I/O I/O Remark - Block Type G-1 G-1 L-1 N-1 L-1 INTP0/ADTRG INTP1 INTP2/DRST INTP3 Note 2 AA-1 L-2 Notes 1. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using INTF0 and INTR0 registers. 2. The alternate function of the P05 pin is the on-chip debug function. After external reset, the P05/INTP2/DRST pin is initialized as the on-chip debug pin (DRST). To use the P05 pin as a port pin, not as an on-chip debug pin, the following actions must be taken. <1> Clear the OCDM.OCDM0 bit (special register) to 0. <2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken. When the on-chip debug function is not used, inputting a high level to the DRST pin before the above actions are taken may cause a malfunction (CPU deadlock). handling the P05 pin. When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not necessary to manipulate the OCDM.OCDM0 bit. Exercise utmost care in 80 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Because a pull-down resistor (30 k TYP.) is connected to the buffer of the P05/INTP2/DRST pin, the pin does not have to be fixed to the low level by an external source. The pull-down resistor is disconnected by clearing the OCDM0 bit to 0. Caution The P00 to P06 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (2) Registers (a) Port register 0 (P0) Port register 0 (P0) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 P0 0 R/W 6 P06 Address: FFFFF400H 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 P0n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 6) (b) Port mode register 0 (PM0) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PM0 1 R/W 6 PM06 Address: FFFFF420H 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 PM0n 0 1 Output mode Input mode Control of input/output mode (n = 0 to 6) Preliminary User's Manual U17718EJ1V0UD 81 CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 0 (PMC0) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1bit units. After reset: 00H 7 PMC0 0 R/W 6 PMC06 Address: FFFFF440H 5 PMC05 4 PMC04 3 PMC03 2 PMC02 1 PMC01 0 PMC00 PMC06 0 1 I/O port INTP3 input Specification of operation mode of P06 pin PMC05 0 1 I/O port INTP2/DRST input Specification of operation mode of P05 pin PMC04 0 1 I/O port INTP1 input Specification of operation mode of P04 pin PMC03 0 1 I/O port Specification of operation mode of P03 pin INTP0/ADTRG input PMC02 0 1 I/O port NMI input Specification of operation mode of P02 pin PMC01 0 1 I/O port TIP30/TOP30 I/O Specification of operation mode of P01 pin PMC00 0 1 I/O port TIP31/TOP31 I/O Specification of operation mode of P00 pin Caution The P05/INTP2/DRST pin functions as the DRST pin when the OCDM.OCDM0 bit is 1, regardless of the value of the PMC05 bit. 82 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (d) Port function control register 0 (PFC0) This is an 8-bit register that specifies control mode 1 or control mode 2. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PFC0 0 R/W 6 0 Address: FFFFF460H 5 0 4 0 3 PFC03 2 0 1 PFC01 0 PFC00 PFC03 0 1 Specification of operation mode when P03 pin is in control mode INTP0 input ADTRG input PFC01 0 1 Specification of operation mode when P01 pin is in control mode TIP30 input TOP30 output PFC00 0 1 Specification of operation mode when P00 pin is in control mode TIP31 input TOP31 output (e) Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PU0 0 R/W 6 PU06 Address: FFFFFC40H 5 PU05 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00 PU0n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 6) Not connected Connected Preliminary User's Manual U17718EJ1V0UD 83 CHAPTER 4 PORT FUNCTIONS www..com (f) External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF0n and INTR0n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. 3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION. After reset: 00H 7 INTF0 0 R/W 6 INTF06 Address: FFFFFC00H 5 INTF05 4 INTF04 3 INTF03 2 INTF02 1 0 0 0 Remark See Table 4-4 for how to specify a valid edge. (g) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF0n and INTR0n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. 3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION. After reset: 00H 7 INTR0 0 R/W 6 INTR06 Address: FFFFFC20H 5 INTR05 4 INTR04 3 INTR03 2 INTR02 1 0 0 0 Remark See Table 4-4 for how to specify a valid edge. 84 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Table 4-4. Valid Edge Specification INTF0n Bit 0 0 1 1 INTR0n Bit 0 1 0 1 Valid Edge Specification (n = 2 to 6) No edge detected Rising edge Falling edge Both edges Remark n = 2: Control of NMI pin n = 3: Control of INTP0 pin n = 4: Control of INTP1 pin n = 5: Control of INTP2 pin n = 6: Control of INTP3 pin Preliminary User's Manual U17718EJ1V0UD 85 CHAPTER 4 PORT FUNCTIONS www..com 4.3.4 Port 1 Port 1 is a 2-bit port (P10, P11) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 1 O The input/output data of the port can be specified in 1-bit units. Specified by port register 1 (P1) O The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 1 (PM1) O Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 1 (PMC1) O An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 1 (PU1) O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units. Specified by external interrupt falling edge specification register 1 (INTF1) and external interrupt rising edge specification register 1 (INTR1) Port 1 functions alternately as the following pins. Table 4-5. Alternate-Function Pins of Port 1 Pin Name Port 1 P10 P11 Alternate-Function Pin Name INTP9 INTP10 I/O I/O Remark - Block Type L-1 L-1 Caution The P10 and P11 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. 86 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 1 (P1) Port register 1 (P1) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 P1 0 R/W 6 0 Address: FFFFF402H 5 0 4 0 3 0 2 0 1 P11 0 P10 P1n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0, 1) (b) Port mode register 1 (PM1) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PM1 1 R/W 6 1 Address: FFFFF422H 5 1 4 1 3 1 2 1 1 PM11 0 PM10 PM1n 0 1 Output mode Input mode Control of input/output mode (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 87 CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 1 (PMC1) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1bit units. After reset: 00H 7 PMC1 0 R/W 6 0 Address: FFFFF442H 5 0 4 0 3 0 2 0 1 PMC11 0 PMC10 PMC11 0 1 I/O port INTP10 input Specification of operation mode of P11 pin PMC10 0 1 I/O port INTP9 input Specification of operation mode of P10 pin (d) Pull-up resistor option register 1 (PU1) This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PU1 0 R/W 6 0 Address: FFFFFC42H 5 0 4 0 3 0 2 0 1 PU11 0 PU10 PU1n 0 1 Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected 88 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (e) External interrupt falling edge specification register 1 (INTF1) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF1n and INTR1n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 7 INTF1 0 R/W 6 0 Address: FFFFFC02H 5 0 4 0 3 0 2 0 1 INTF11 0 INTF10 Remark See Table 4-6 for how to specify a valid edge. (f) External interrupt rising edge specification register 1 (INTR1) This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF1n and INTR1n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 7 INTR1 0 R/W 6 0 Address: FFFFFC22H 5 0 4 0 3 0 2 0 1 INTR11 0 INTR10 Remark See Table 4-6 for how to specify a valid edge. Table 4-6. Valid Edge Specification INTF1n Bit 0 0 1 1 INTR1n Bit 0 1 0 1 Valid Edge Specification (n = 0, 1) No edge detected Rising edge Falling edge Both edges Remark n = 0: Control of INTP9 pin n = 1: Control of INTP10 pin Preliminary User's Manual U17718EJ1V0UD 89 CHAPTER 4 PORT FUNCTIONS www..com 4.3.5 Port 3 Port 3 is a 10-bit port (P30 to P39) for which I/O settings can be controlled in 1-bit units. (1) Function of port 3 * The input/output data of the port can be specified in 1-bit units. Specified by port register 3 (P3) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 3 (PM3) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 3 (PMC3) * Control mode can be specified in 1-bit units. Specified by port function control register 3 (PFC3) and port function control expansion register 3L (PFCE3L) * An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 3 (PU3) * The valid edge of the external interrupt (alternate function) can be specified in 1-bit units. Specified by external interrupt falling edge specification register 3 (INTF3) and external interrupt rising edge specification register 3 (INTR3) Port 3 functions alternately as the following pins. Table 4-7. Alternate-Function Pins of Port 3 Pin Name Port 3 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 TXDA2 RXDA2/INTP8 Alternate-Function Pin Name TXDA0 RXDA0/INTP7 ASCKA0/TIP00/TOP00/TOP01 TIP01/TOP01 TIP10/TOP10 TIP11/TOP11 - - I/O I/O Remark - Block Type E-2 L-2 U-13 G-1 G-1 G-1 C-1 C-1 E-2 L-2 Caution The P31 to P35, and P39 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. 90 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 3 (P3) Port register 3 (P3) is a 16-bit register that controls reading the pin level and writing the output level. This register can be read or written in 16-bit units. If the higher 8 bits of the P3 register are used as the P3H register, and the lower 8 bits as the P3L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: Undefined 15 P3 (P3H Note R/W 14 0 6 P36 Address: FFFFF406H, FFFFF407H 13 0 5 P35 12 0 4 P34 11 0 3 P33 10 0 2 P32 9 P39 1 P31 8 P38 0 P30 ) 0 7 (P3L) P37 P3n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 9) Note To read or write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register. (b) Port mode register 3 (PM3) This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units. If the higher 8 bits of the PM3 register are used as the PM3H register, and the lower 8 bits as the PM3L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: FFFFH 15 PM3 (PM3H Note R/W 14 1 6 PM36 Address: FFFFF426H, FFFFF427H 13 1 5 PM35 12 1 4 PM34 11 1 3 PM33 10 1 2 PM32 9 PM39 1 PM31 8 PM38 0 PM30 ) 1 7 (PM3L) PM37 PM3n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 9) Note To read or write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM3H register. Preliminary User's Manual U17718EJ1V0UD 91 CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 3 (PMC3) This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit units. If the higher 8 bits of the PMC3 register are used as the PMC3H register, and the lower 8 bits as the PMC3L register, however, these registers can be read or written in 8-bit or 1-bit units. (1/2) After reset: 0000H 15 PMC3 (PMC3H Note 1 R/W 14 0 6 0 Address: FFFFF446H, FFFFF447H 13 0 5 PMC35 12 0 4 PMC34 11 0 3 PMC33 10 0 2 PMC32 9 PMC39 1 PMC31 8 PMC38 0 PMC30 ) 0 7 (PMC3L) 0 PMC39 0 1 I/O port Specification of operation mode of P39 pin RXDA2/INTP8 input Note 2 PMC38 0 1 I/O port TXDA2 output Specification of operation mode of P38 pin PMC35 0 1 I/O port TIP11/TOP11 I/O Specification of operation mode of P35 pin PMC34 0 1 I/O port TIP10/TOP10 I/O Specification of operation mode of P34 pin Notes 1. To read or write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC3H register. 2. The INTP8 pin functions alternately as the RXDA2 pin. To use as the RXDA2 pin, invalidate the edge detection function of the alternate-function INTP8 pin (by fixing the INTF3.INTF39 bit to 0 and the INTR3.INTR39 bit to 0). To use as the INTP8 pin, stop the reception operation of UARTA2 (by clearing the UA2CTL0.UA2RXE bit to 0). 92 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2/2) PMC33 0 1 I/O port TIP01/TOP01 I/O Specification of operation mode of P33 pin PMC32 0 1 I/O port Specification of operation mode of P32 pin ASCKA0/TIP00/TOP00/TOP01 I/O PMC31 0 1 I/O port Specification of operation mode of P31 pin RXDA0/INTP7 input Note PMC30 0 1 I/O port TXDA0 output Specification of operation mode of P30 pin Note The INTP7 pin functions alternately as the RXDA0 pin. To use as the RXDA0 pin, invalidate the edge detection function of the alternate-function INTP7 pin (by fixing the INTF3.INTF31 and INTR3.INTR31 bits to 0). To use as the INTP7 pin, stop the reception operation of UARTA0 (by clearing the UA0CTL0.UA0RXE bit to 0). (d) Port function control register 3L (PFC3L) This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PFC3L 0 R/W 6 0 Address: FFFFF466H 5 PFC35 4 PFC34 3 PFC33 2 PFC32 1 0 0 0 Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin. Preliminary User's Manual U17718EJ1V0UD 93 CHAPTER 4 PORT FUNCTIONS www..com (e) Port function control expansion register 3L (PFCE3L) This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PFCE3L 0 R/W 6 0 Address: FFFFF706H 5 0 4 0 3 0 2 PFCE32 1 0 0 0 Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin. (f) Setting of control mode of P3 pin PFC35 0 1 TIP11 input TOP11 output Specification of control mode of P35 pin PFC34 0 1 TIP10 input TOP10 output Specification of control mode of P34 pin PFC33 0 1 TIP01 input TOP01 output Specification of control mode of P33 pin PFCE32 0 0 1 1 PFC32 0 1 0 1 ASCKA0 input TOP01 output TIP00 input TOP00 output Specification of control mode of P32 pin 94 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www.DataShee (g) Pull-up resistor option register 3 (PU3) This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 16- or 1-bit units. If the higher 8 bits of the PU3 register are used as the PU3H register, and the lower 8 bits as the PU3L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: 00H 15 PU3 (PU3H Note R/W 14 0 6 PU36 Address: FFFFFC46H, FFFFFC47H 13 0 5 PU35 12 0 4 PU34 11 0 3 PU33 10 0 2 PU32 9 PU39 1 PU31 8 PU38 0 PU30 ) 0 7 (PU3L) PU37 PU3n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 9) Not connected Connected Note To read/write bits 8 to 15 of the PU3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU3H register. (h) External interrupt falling edge specification register 3 (INTF3) This is a 16-bit register that specifies detection of the falling edge of the external interrupt pin. It can be read or written in 16-bit units. If the higher 8 bits of the INTF3 register are used as the INTF3H register, and the lower 8 bits as the INTF3L register, however, these registers can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF3n and INTR3n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 15 INTF3 (INTF3H Note R/W 14 0 6 0 Address: FFFFFC06H, FFFFFC07H 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 INTF39 1 INTF31 8 0 0 0 ) 0 7 (INTF3L) 0 Note To read/write bits 8 to 15 of the INTF3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the INTF3H register. Remark See Table 4-8 for how to specify a valid edge. Preliminary User's Manual U17718EJ1V0UD 95 CHAPTER 4 PORT FUNCTIONS www..com (i) External interrupt rising edge specification register 3 (INTR3) This is a 16-bit register that specifies detection of the rising edge of the external interrupt pin. It can be read or written in 16-bit units. If the higher 8 bits of the INTR3 register are used as the INTR3H register, and the lower 8 bits as the INTR3L register, however, these registers can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF3n and INTR3n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 15 INTR3 (INTR3H Note R/W 14 0 6 0 Address: FFFFFC26H, FFFFFC27H 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 INTR39 1 INTR31 8 0 0 0 ) 0 7 (INTR3L) 0 Note To read/write bits 8 to 15 of the INTR3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the INTR3H register. Remark See Table 4-8 for how to specify a valid edge. Table 4-8. Valid Edge Specification INTF3n Bit 0 0 1 1 INTR3n Bit 0 1 0 1 Valid Edge Specification (n = 1, 9) No edge detected Rising edge Falling edge Both edges Remark n = 1: Control of INTP7 pin n = 9: Control of INTP8 pin 96 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.6 Port 4 Port 4 is a 3-bit port (P40 to P42) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 4 * The input/output data of the port can be specified in 1-bit units. Specified by port register 4 (P4) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 4 (PM4) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 4 (PMC4) * An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 4 (PU4) Port 4 functions alternately as the following pins. Table 4-9. Alternate-Function Pins of Port 4 Pin Name Port 4 P40 P41 P42 Alternate-Function Pin Name SIB0 SOB0 SCKB0 I/O I/O Remark - Block Type E-1 E-2 E-3 Caution The P40 and P42 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. Preliminary User's Manual U17718EJ1V0UD 97 CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 4 (P4) Port register 4 (P4) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 P4 0 R/W 6 0 Address: FFFFF408H 5 0 4 0 3 0 2 P42 1 P41 0 P40 P4n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 2) (b) Port mode register 4 (PM4) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PM4 1 R/W 6 1 Address: FFFFF428H 5 1 4 1 3 1 2 PM42 1 PM41 0 PM40 PM4n 0 1 Output mode Input mode Control of input/output mode (n = 0 to 2) 98 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 4 (PMC4) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1bit units. After reset: 00H 7 PMC4 0 R/W 6 0 Address: FFFFF448H 5 0 4 0 3 0 2 PMC42 1 PMC41 0 PMC40 PMC42 0 1 I/O port SCKB0 I/O Specification of operation mode of P42 pin PMC41 0 1 I/O port SOB0 output Specification of operation mode of P41 pin PMC40 0 1 I/O port SIB0 input Specification of operation mode of P40 pin (d) Pull-up resistor option register 4 (PU4) This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PU4 0 R/W 6 0 Address: FFFFFC48H 5 0 4 0 3 0 2 PU42 1 PU41 0 PU40 PU4n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 2) Not connected Connected Preliminary User's Manual U17718EJ1V0UD 99 CHAPTER 4 PORT FUNCTIONS www..com 4.3.7 Port 5 Port 5 is a 6-bit port (P50 to P55) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 5 * The input/output data of the port can be specified in 1-bit units. Specified by port register 5 (P5) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 5 (PM5) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 5 (PMC5) * Control mode can be specified in 1-bit units. Specified by port function control register 5 (PFC5) or port function control expansion register 5 (PFCE5) * An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 5 (PU5) Port 5 functions alternately as the following pins. Table 4-10. Alternate-Function Pins of Port 5 Pin Name Port 5 P50 P51 P52 P53 P54 P55 Alternate-Function Pin Name KR0/TIQ01/TOQ01 KR1/TIQ02/TOQ02 KR2/TIQ03/TOQ03/DDI Note I/O I/O Remark - Block Type U-4 U-4 U-5 U-6 G-2 G-2 KR3/TIQ00/TOQ00/DDO KR4/DCK Note Note KR5/DMS Note Note The DDI, DDO, DCK, and DMS pins are for the on-chip debug function. To use the DDI, DDO, DCK, and DMS pins as port pins, not as on-chip debug pins, the following actions must be taken. <1> Clear the OCDM0 bit of the OCDM register (special register) to 0. <2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken. When the on-chip debug function is not used, inputting a high level to the DRST pin before the above actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05 pin. When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not necessary to manipulate the OCDM.OCDM0 bit. Because a pull-down resistor (30 k TYP.) is connected to the buffer of the P05/INTP2/DRST pin, the pin does not have to be fixed to the low level by an external source. disconnected by clearing the OCDM0 bit to 0. Caution The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. The pull-down resistor is 100 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 5 (P5) Port register 5 (P5) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 P5 0 R/W 6 0 Address: FFFFF40AH 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 P5n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 5) (b) Port mode register 5 (PM5) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PM5 1 R/W 6 1 Address: FFFFF42AH 5 PM55 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50 PM5n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) Preliminary User's Manual U17718EJ1V0UD 101 CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 5 (PMC5) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1bit units. Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n and PFCE5.PFCE5n bits are the default values (0), the output becomes undefined. For this reason, first set the PFC5.PFC5n and PFCE5.PFCE5n bits, and then set the PMC5n bit to 1 to set the control mode. After reset: 00H 7 PMC5 0 R/W 6 0 Address: FFFFF44AH 5 PMC55 4 PMC54 3 PMC53 2 PMC52 1 PMC51 0 PMC50 PMC55 0 1 I/O port KR5 input Specification of operation mode of P55 pin PMC54 0 1 I/O port KR4 input Specification of operation mode of P54 pin PMC53 0 1 I/O port Specification of operation mode of P53 pin KR3/TIQ00/TOQ00 I/O PMC52 0 1 I/O port Specification of operation mode of P52 pin KR2/TIQ03/TOQ03 I/O PMC51 0 1 I/O port Specification of operation mode of P51 pin KR1/TIQ02/TOQ02 I/O PMC50 0 1 I/O port Specification of operation mode of P50 pin KR0/TIQ01/TOQ01 I/O 102 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (d) Port function control register 5 (PFC5) This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PFC5 0 R/W 6 0 Address: FFFFF46AH 5 PFC55 4 PFC54 3 PFC53 2 PFC52 1 PFC51 0 PFC50 Remark For how to specify a control mode, see 4.3.7 (2) (f) Setting of control mode of P5 pin. (e) Port function control expansion register 5 (PFCE5) This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PFCE5 0 R/W 6 0 Address: FFFFF70AH 5 0 4 0 3 PFCE53 2 PFCE52 1 PFCE51 0 PFCE50 Remark For how to specify a control mode, see 4.3.7 (2) (f) Setting of control mode of P5 pin. (f) Setting of control mode of P5 pin Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n and PFCE5.PFCE5n bits are the default values (0), the output becomes undefined. For this reason, first set the PFC5.PFC5n and PFCE5.PFCE5n bits, and then set the PMC5n bit to 1 to set the control mode. PFC55 0 1 Setting prohibited KR5 input Specification of control mode of P55 pin PFC54 0 1 Setting prohibited KR4 input Specification of control mode of P54 pin Preliminary User's Manual U17718EJ1V0UD 103 CHAPTER 4 PORT FUNCTIONS www..com PFCE53 0 0 1 1 PFC53 0 1 0 1 Setting prohibited TIQ00/KR3 Note Specification of control mode of P53 pin input TOQ00 output Setting prohibited PFCE52 0 0 1 1 PFC52 0 1 0 1 Setting prohibited TIQ03/KR2 Note Specification of control mode of P52 pin input TOQ03 output Setting prohibited PFCE51 0 0 1 1 PFC51 0 1 0 1 Setting prohibited TIQ02/KR1 Note Specification of control mode of P51 pin input TOQ02 output Setting prohibited PFCE50 0 0 1 1 PFC50 0 1 0 1 Setting prohibited TIQ01/KR0 Note Specification of control mode of P50 pin input TOQ01 output Setting prohibited Note The KRn pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key return detection function of the alternate-function KRn pin (by clearing the KRM.KRMn bit to 0). To use this pin as the KRn pin, invalidate the edge detection function of the alternate-function TIQ0m pin (n = 0 to 3, m = 0 to 3). Pin Name KR0/TIQ01 KR1/TIQ02 KR2/TIQ03 KR3/TIQ00 Use as TIQ0m Pin KRM0 bit of KRM register = 0 KRM1 bit of KRM register = 0 KRM2 bit of KRM register = 0 KRM3 bit of KRM register = 0 Use as KRn Pin TQ0TIG2, TQ0TIG3 bit of TQ0IOC1 register = 0 TQ0TIG4, TQ0TIG5 bit of TQ0IOC1 register = 0 TQ0TIG6, TQ0TIG7 bit of TQ0IOC1 register = 0 TQ0TIG0, TQ0TIG1 bit of TQ0IOC1 register = 0 TQ0EES0, TQ0EES1 bit of TQ0IOC2 register = 0 TQ0ETS0, TQ0ETS1 bit of TQ0IOC2 register = 0 104 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (g) Pull-up resistor option register 5 (PU5) This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 8-bit or 1-bit units. After reset: 00H 7 PU5 0 R/W 6 0 Address: FFFFFC4AH 5 PU55 4 PU54 3 PU53 2 PU52 1 PU51 0 PU50 PU5n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected Preliminary User's Manual U17718EJ1V0UD 105 CHAPTER 4 PORT FUNCTIONS www..com 4.3.8 Port 7 Port 7 is a 16-bit port (P70 to P715) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 7 * The input/output data of the port can be specified in 1-bit units. Specified by port registers 7H, 7L (P7H, P7L) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode registers 7H, 7L (PM7H, PM7L) Port 7 functions alternately as the following pins. Table 4-11. Alternate-Function Pins of Port 7 Pin Name Port 7 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 Alternate-Function Pin Name ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 I/O I/O Remark - Block Type A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 106 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 7H, port register 7L (P7H, P7L) Port registers 7H and 7L (P7H and P7L) are 8-bit registers that control reading the pin level and writing the output level. These registers can be read or written in 8-bit or 1-bit units. They cannot be accessed in 16-bit units. After reset: Undefined 7 P7H P715 7 P7L P77 R/W 6 P714 6 P76 Address: FFFFF40FH, FFFFF40EH 5 P713 5 P75 4 P712 4 P74 3 P711 3 P73 2 P710 2 P72 1 P79 1 P71 0 P78 0 P70 P7n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 15) Caution Do not read the P7H and P7L registers during A/D conversion. (b) Port mode registers 7H, 7L (PM7H, PM7L) These are 8-bit registers that specify an input or output mode. They can be read or written in 8-bit or 1-bit units. These registers cannot be accessed in 16-bit units. After reset: FFH 7 PM7H PM715 7 PM7L PM77 R/W 6 PM714 6 PM76 Address: FFFFF42FH, FFFFF42EH 5 PM713 5 PM75 4 PM712 4 PM74 3 PM711 3 PM73 2 PM710 2 PM72 1 PM79 1 PM71 0 PM78 0 PM70 PM7n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) Caution To use the alternate function of P7n (ANIn), set PM7n to 1. Preliminary User's Manual U17718EJ1V0UD 107 CHAPTER 4 PORT FUNCTIONS www..com 4.3.9 Port 9 Port 9 is a 9-bit or 16-bit port (P90 to P915) for which I/O settings can be controlled in 1-bit units. (1) Functions of port 9 * The input/output data of the port can be specified in 1-bit units. Specified by port register 9 (P9) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register 9 (PM9) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register 9 (PMC9) * Control mode can be specified in 1-bit units. Specified by port function control register 9 (PFC9) and port function control expansion register 9 (PFCE9) * An on-chip pull-up resistor can be connected in 1-bit units. Specified by pull-up resistor option register 9 (PU9) * The valid edge of the external interrupt (alternate function) can be specified in 1-bit units. Specified by external interrupt falling edge specification register 9H (INTF9H) and external interrupt rising edge specification register 9H (INTR9H) Port 9 functions alternately as the following pins. Table 4-12. Alternate-Function Pins of Port 9 Pin Name Port 9 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 INTP4/PCL INTP5 INTP6 Alternate-Function Pin Name KR6/TXDA1 KR7/RXDA1 TIQ11/TOQ11 TIQ12/TOQ12 TIQ13/TOQ13 TIQ10/TOQ10 TIP21/TOP21 SIB1/TIP20/TOP20 SOB1 SCKB1 - - - I/O I/O Remark - Block Type U-12 U-7 U-11 U-11 U-11 U-11 U-9 U-8 G-3 G-5 C-1 C-1 C-1 W-1 N-2 N-2 Caution The P90 to P97, P99, and P913 to P915 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. 108 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register 9 (P9) Port register 9 (P9) is a 16-bit register that controls reading the pin level and writing the output level. This register can be read or written in 16-bit units. If the higher 8 bits of the P9 register are used as the P9H register, and the lower 8 bits as the P9L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: Undefined 15 P9 (P9H Note R/W 14 P914 6 P96 Address: FFFFF412H, FFFFF413H 13 P913 5 P95 12 P912 4 P94 11 P911 3 P93 10 P910 2 P92 9 P99 1 P91 8 P98 0 P90 ) P915 7 (P9L) P97 P9n 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 15) Note To read or write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P9H register. (b) Port mode register 9 (PM9) This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units. If the higher 8 bits of the PM9 register are used as the PM9H register, and the lower 8 bits as the PM9L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: FFFFH 15 PM9 (PM9H Note R/W 14 PM914 6 PM96 Address: FFFFF432H, FFFFF433H 13 PM913 5 PM95 12 PM912 4 PM94 11 PM911 3 PM93 10 PM910 2 PM92 9 PM99 1 PM91 8 PM98 0 PM90 ) PM915 7 (PM9L) PM97 PM9n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) Note To read or write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM9H register. Preliminary User's Manual U17718EJ1V0UD 109 CHAPTER 4 PORT FUNCTIONS www..com (c) Port mode control register 9 (PMC9) This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit units. If the higher 8 bits of the PMC9 register are used as the PMC9H register, and the lower 8 bits as the PMC9L register, however, these registers can be read or written in 8-bit or 1-bit units. Caution If the control mode is specified by using the PMC9 register when the PFC9.PFC9n bit and the PFCE9.PFCE9n bit are the default values (0), the output becomes undefined. For this reason, first set the PFC9.PFC9n bit and the PFCE9.PFCE9n bit to 1, and then set the PMC9n bit to 1 to set the control mode. (1/2) After reset: 0000H 15 PMC9 (PMC9H Note R/W 14 PMC914 6 PMC96 Address: FFFFF452H, FFFFF453H 13 PMC913 5 PMC95 12 0 4 PMC94 11 0 3 PMC93 10 0 2 PMC92 9 PMC99 1 PMC91 8 PMC98 0 PMC90 ) PMC915 7 (PMC9L) PMC97 PMC915 0 1 I/O port INTP6 input Specification of operation mode of P915 pin PMC914 0 1 I/O port INTP5 input Specification of operation mode of P914 pin PMC913 0 1 I/O port INTP4/PCL I/O Specification of operation mode of P913 pin PMC99 0 1 I/O port SCKB1 I/O Specification of operation mode of P99 pin Note To read or write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC9H register. 110 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (2/2) PMC98 0 1 I/O port SOB1 output Specification of operation mode of P98 pin PMC97 0 1 I/O port Specification of operation mode of P97 pin SIB1/TIP20/TOP20 I/O PMC96 0 1 I/O port TIP21/TOP21 I/O Specification of operation mode of P96 pin PMC95 0 1 I/O port TIQ10/TOQ10 I/O Specification of operation mode of P95 pin PMC94 0 1 I/O port TIQ13/TOQ13 I/O Specification of operation mode of P94 pin PMC93 0 1 I/O port TIQ12/TOQ12 I/O Specification of operation mode of P93 pin PMC92 0 1 I/O port TIQ11/TOQ11 I/O Specification of operation mode of P92 pin PMC91 0 1 I/O port KR7/RXDA1 input Specification of operation mode of P91 pin PMC90 0 1 I/O port KR6/TXDA1 I/O Specification of operation mode of P90 pin Preliminary User's Manual U17718EJ1V0UD 111 CHAPTER 4 PORT FUNCTIONS www..com (d) Port function control register 9 (PFC9) This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units. If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: 0000H 15 PFC9 (PFC9H Note R/W 14 PFC914 6 PFC96 Address: FFFFF472H, FFFFF473H 13 PFC913 5 PFC95 12 0 4 PFC94 11 0 3 PFC93 10 0 2 PFC92 9 PFC99 1 PFC91 8 PFC98 0 PFC90 ) PFC915 7 (PFC9L) PFC97 Note To read or write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFC9H register. Remark For how to specify a control mode, see 4.3.9 (2) (f) Setting of control mode of P9 pin. (e) Port function control expansion register 9 (PFCE9) This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units. If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: 0000H 15 PFCE9 (PFCE9H Note R/W 14 0 6 PFCE96 Address: FFFFF712H, FFFFF713H 13 PFCE913 5 PFCE95 12 0 4 PFCE94 11 0 3 PFCE93 10 0 2 PFCE92 9 0 1 PFCE91 8 0 0 PFCE90 ) 0 7 (PFCE9L) PFCE97 Note To read or write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFCE9H register. Remark For how to specify a control mode, see 4.3.9 (2) (f) Setting of control mode of P9 pin. 112 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (f) Setting of control mode of P9 pin Caution If the control mode is specified by using the PMC9 register when the PFC9.PFC9n and PFCE9.PFCE9n bits are the default values (0), the output becomes undefined. For this reason, first set the PFC9.PFC9n and PFCE9.PFCE9n bits, and then set the PMC9n bit to 1 to set the control mode. PFC915 0 1 Setting prohibited INTP6 input Specification of control mode of P915 pin PFC914 0 1 Setting prohibited INTP5 input Specification of control mode of P914 pin PFCE913 0 0 1 1 PFC913 0 1 0 1 Specification of control mode of P913 pin Setting prohibited INTP4 input PCL output Setting prohibited PFC99 0 1 Setting prohibited SCKB1 I/O Specification of control mode of P99 pin PFC98 0 1 Setting prohibited SOB1 output Specification of control mode of P98 pin PFCE97 0 0 1 1 PFC97 0 1 0 1 Setting prohibited SIB1 input TIP20 input TOP20 output Specification of control mode of P97 pin PFCE96 0 0 1 1 PFC96 0 1 0 1 Setting prohibited Setting prohibited TIP21 input TOP21 output Specification of control mode of P96 pin Preliminary User's Manual U17718EJ1V0UD 113 CHAPTER 4 PORT FUNCTIONS www..com PFCE95 0 0 1 1 PFC95 0 1 0 1 Setting prohibited TIQ10 input TOQ10 output Setting prohibited Specification of control mode of P95 pin PFCE94 0 0 1 1 PFC94 0 1 0 1 Setting prohibited TIQ13 input TOQ13 output Setting prohibited Specification of control mode of P94 pin PFCE93 0 0 1 1 PFC93 0 1 0 1 Setting prohibited TIQ12 input TOQ12 output Setting prohibited Specification of control mode of P93 pin PFCE92 0 0 1 1 PFC92 0 1 0 1 Setting prohibited TIQ11 input TOQ11 output Setting prohibited Specification of control mode of P92 pin PFCE91 0 0 1 1 PFC91 0 1 0 1 Setting prohibited KR7 input Specification of control mode of P91 pin KR7/RXDA1 input Setting prohibited Note PFCE90 0 0 1 1 PFC90 0 1 0 1 Setting prohibited KR6 input TXDA1 output Setting prohibited Specification of control mode of P90 pin Note The KR7 pin and RXDA1 pin are alternate-function pins. When using the pin as the RXDA1 pin, disable KR7 pin key return detection. (Clear the KRM7 bit of the KRM register to 0.) Also, when using the pin as the KR7 pin, it is recommended to set the PFC91 bit to 1 and clear the PFCE91 bit to 0. 114 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com (g) Pull-up resistor option register 9 (PU9) This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in 16-bit units. If the higher 8 bits of the PU9 register are used as the PU9H register, and the lower 8 bits as the PU9L register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: 0000H 15 PU9 (PU9H Note R/W 14 PU914 6 PU96 Address: FFFFFC52H, FFFFFC53H 13 PU913 5 PU95 12 PU912 4 PU94 11 PU911 3 PU93 10 PU910 2 PU92 9 PU99 1 PU91 8 PU98 0 PU90 ) PU915 7 (PU9L) PU97 PU9n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 15) Not connected Connected Note To read/write bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU9H register. (h) External interrupt falling edge specification register 9H (INTF9H) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF9n and INTR9n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 7 INTF9H INTF915 R/W 6 INTF914 Address: FFFFFC13H 5 INTF913 4 0 3 0 2 0 1 0 0 0 Remark See Table 4-13 for how to specify a valid edge. Preliminary User's Manual U17718EJ1V0UD 115 CHAPTER 4 PORT FUNCTIONS www..com (i) External interrupt rising edge specification register 9H (INTR9H) This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be read or written in 8-bit or 1-bit units. Cautions 1. When the external interrupt function (alternate function) is switched to the port function, an edge may be detected. Set the port mode after clearing the INTF9n and INTR9n bits to 0. 2. An analog-delay-based noise eliminator is connected to the external interrupt input pin. After reset: 00H 7 INTR9H INTR915 R/W 6 INTR914 Address: FFFFFC33H 5 INTR913 4 0 3 0 2 0 1 0 0 0 Remark See Table 4-13 for how to specify a valid edge. Table 4-13. Valid Edge Specification INTF9n Bit 0 0 1 1 INTR9n Bit 0 1 0 1 Valid Edge Specification (n = 13 to 15) No edge detected Rising edge Falling edge Both edges Remark n = 13: Control of INTP4 pin n = 14: Control of INTP5 pin n = 15: Control of INTP6 pin 116 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.10 Port CM Port CM is a 4-bit port (PCM0 to PCM3) for which I/O settings can be controlled in 1-bit units. (1) Functions of port CM * The input/output data of the port can be specified in 1-bit units. Specified by port register CM (PCM) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register CM (PMCM) * Port mode or control mode (alternate function) can be specified in 1-bit units. Specified by port mode control register CM (PMCCM) Port CM functions alternately as the following pins. Table 4-14. Alternate-Function Pins of Port CM Pin Name Port CM PCM0 PCM1 PCM2 PCM3 CLKOUT - - Alternate-Function Pin Name - I/O I/O Remark - Block Type B-1 D-2 B-1 B-1 Preliminary User's Manual U17718EJ1V0UD 117 CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register CM (PCM) Port register CM (PCM) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 PCM 0 R/W 6 0 Address: FFFFF00CH 5 0 4 0 3 PCM3 2 PCM2 1 PCM1 0 PCM0 PCMn 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 3) (b) Port mode register CM (PMCM) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PMCM 1 R/W 6 1 Address: FFFFF02CH 5 1 4 1 3 PMCM3 2 PMCM2 1 PMCM1 0 PMCM0 PMCMn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 3) (c) Port mode control register CM (PMCCM) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1bit units. After reset: 00H 7 PMCCM 0 R/W 6 0 Address: FFFFF04CH 5 0 4 0 3 0 2 0 1 PMCCM1 0 0 PMCCM1 0 1 I/O port CLKOUT output Specification of operation mode of PCM1 pin 118 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.11 Port CS Port CS is a 2-bit port (PCS0, PCS1) for which I/O settings can be controlled in 1-bit units. (1) Functions of port CS * The input/output data of the port can be specified in 1-bit units. Specified by port register CS (PCS) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register CS (PMCS) Port CS functions alternately as the following pins. Table 4-15. Alternate-Function Pins of Port CS Pin Name Port CS PCS0 PCS1 Alternate-Function Pin Name - - I/O I/O Remark - Block Type B-1 B-1 Preliminary User's Manual U17718EJ1V0UD 119 CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register CS (PCS) Port register CS (PCS) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 PCS 0 R/W 6 0 Address: FFFFF008H 5 0 4 0 3 0 2 0 1 PCS1 0 PCS0 PCSn 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0, 1) (b) Port mode register CS (PMCS) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PMCS 1 R/W 6 1 Address: FFFFF028H 5 1 4 1 3 1 2 1 1 PMCS1 0 PMCS0 PMCSn 0 1 Output mode Input mode Control of I/O mode (n = 0, 1) 120 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.12 Port CT Port CT is a 4-bit port (PCT0, PCT1, PCT4, PCT6) for which I/O settings can be controlled in 1-bit units. (1) Functions of port CT * The input/output data of the port can be specified in 1-bit units. Specified by port register CT (PCT) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register CT (PMCT) Port CT functions alternately as the following pins. Table 4-16. Alternate-Function Pins of Port CT Pin Name Port CT PCT0 PCT1 PCT4 PCT6 Alternate-Function Pin Name - - - - I/O I/O Remark - Block Type B-1 B-1 B-1 B-1 Preliminary User's Manual U17718EJ1V0UD 121 CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register CT (PCT) Port register CT (PCT) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined 7 PCT 0 R/W 6 PCT6 Address: FFFFF00AH 5 0 4 PCT4 3 0 2 0 1 PCT1 0 PCT0 PCTn 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0, 1, 4, 6) (b) Port mode register CT (PMCT) This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit units. After reset: FFH 7 PMCT 1 R/W 6 PMCT6 Address: FFFFF02AH 5 1 4 PMCT4 3 1 2 1 1 PMCT1 0 PMCT0 PMCTn 0 1 Output mode Input mode Control of I/O mode (n = 0, 1, 4, 6) 122 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.13 Port DL Port DL is a 14-bit port (PDL0 to PDL13) for which I/O settings can be controlled in 1-bit units. (1) Function of port DL * The input/output data of the port can be specified in 1-bit units. Specified by port register DL (PDL) * The input/output mode of the port can be specified in 1-bit units. Specified by port mode register DL (PMDL) Port DL functions alternately as the following pins. Table 4-17. Alternate-Function Pins of Port DL Pin Name Port DL PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 FLMD1 Note Alternate-Function Pin Name - - - - - I/O I/O Remark - B-1 B-1 B-1 B-1 B-1 B-1 - - - - - - - - B-1 B-1 B-1 B-1 B-1 B-1 B-1 B-1 Note Because the FLMD1 pin is used in the flash programming mode, it does not have to be manipulated by using a port control register. For details, see CHAPTER 23 FLASH MEMORY. Preliminary User's Manual U17718EJ1V0UD 123 CHAPTER 4 PORT FUNCTIONS www..com (2) Registers (a) Port register DL (PDL) Port register DL (PDL) is a 16-bit register that controls reading the pin level and writing the output level. This register can be read or written in 16-bit units. If the higher 8 bits of the PDL register are used as the PDLH register, and the lower 8 bits as the PDLL register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: Undefined 15 PDL (PDLH Note R/W 14 0 6 PDL6 Address: FFFFF004H, FFFFF005H 13 PDL13 5 PDL5 12 PDL12 4 PDL4 11 PDL11 3 PDL3 10 PDL10 2 PDL2 9 PDL9 1 PDL1 8 PDL8 0 PDL0 ) 0 7 (PDLL) PDL7 PDLn 0 1 Output 0. Output 1. Control of output data (in output mode) (n = 0 to 13) Note To read or write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PDLH register. (b) Port mode register DL (PMDL) This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units. If the higher 8 bits of the PMDL register are used as the PMDLH register, and the lower 8 bits as the PMDLL register, however, these registers can be read or written in 8-bit or 1-bit units. After reset: FFFFH 15 PMDL (PMDLH Note R/W 14 1 6 PMDL6 Address: FFFFF024H, FFFFF025H 13 PMDL13 5 PMDL5 12 PMDL12 4 PMDL4 11 PMDL11 3 PMDL3 10 PMDL10 2 PMDL2 9 PMDL9 1 PMDL1 8 PMDL8 0 PMDL0 ) 1 7 (PMDLL) PMDL7 PMDLn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 13) Note To read or write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMDLH register. 124 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.3.14 Port pins that function alternately as on-chip debug function The pins shown in Table 4-18 function alternately as on-chip debug pins. After an external reset, these pins are initialized as on-chip debug pins (DRST, DDI, DDO, DCK, and DMS). Table 4-18. On-Chip Debug Pins Pin Name P05 P52 P53 P54 P55 Alternate Function Pin INTP2/DRST KR2/TIQ03/TOQ03/DDI KR3/TIQ00/TOQ00/DDO KR4/DCK KR5/DMS To use these pins as port pins, not as on-chip debug pins, the following actions must be taken after an external reset. <1> Clear the OCDM0 bit of the OCDM register (special register) to 0. <2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken. When the on-chip debug function is not used, inputting a high level to the DRST pin before the above actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05 pin. When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not necessary to manipulate the OCDM.OCDM0 bit. Because a pull-down resistor (30 k TYP) is connected to the buffer of the P05/INTP2/DRST pin, the pin does not have to be fixed to the low level by an external source. The pull-down resistor is disconnected by clearing the OCDM0 bit to 0. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. Preliminary User's Manual U17718EJ1V0UD 125 CHAPTER 4 PORT FUNCTIONS www..com 4.3.15 Register settings to use port pins as alternate-function pins Table 4-19. Using Port Pin as Alternate-Function Pin (1/5) Pin Name P00 Alternate-Function Pin Name TIP31 TOP31 P01 TIP30 TOP30 P02 P03 NMI INTP0 ADTRG P04 P05 Note PMn Register PMCn Register PFCm Register PFCEm Register Other Bits (Register) I/O Input Output Input Output Input Input Output Input Input Input Input Input Input Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required PMC00 = 1 PMC00 = 1 PMC01 = 1 PMC01 = 1 PMC02 = 1 PMC03 = 1 PMC03 = 1 PMC04 = 1 PMC05 = 1 Setting not required PMC06 = 1 PMC10 = 1 PMC11 = 1 PFC00 = 0 PFC00 = 1 PFC01 = 0 PFC01 = 1 - PFC03 = 0 PFC03 = 1 - - - - - - - - - - - - - - - - - - - INTx04 (INTx0) INTx05 (INTx0) OCDM0 (OCDM) = 1 INTx06 (INTx0) INTx10 (INTx1) INTx11 (INTx1) INTx03 (INTx0) INTP1 INTP2 DRST P06 P10 P11 INTP3 INTP9 INTP10 Note After an external reset, the P05/INTP2/DRST pin is initialized as an on-chip debug pin (DRST). To not use the P05/INTP2/DRST pin as an on-chip debug pin, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. Remarks 1. The port register (Pn) does not have to be set when the alternate function is used. 2. INTxn = INTFn, INTRn 126 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Table 4-19. Using Port Pin as Alternate-Function Pin (2/5) Pin Name P30 P31 Alternate-Function Pin Name TXDA0 RXDA0 INTP7 P32 ASCKA0 TOP01 TIP00 TOP00 P33 TIP01 TOP01 P34 TIP10 TOP10 P35 TIP11 TOP11 P38 P39 TXDA2 RXDA2 INTP8 P40 P41 P42 SIB0 SOB0 SCKB0 I/O Output Input Input Input Output Input Output Input Output Input Output Input Output Output Input Input Input Output I/O Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required PMC30 = 1 PMC31 = 1 PMC31 = 1 PMC32 = 1 PMC32 = 1 PMC32 = 1 PMC32 = 1 PMC33 = 1 PMC33 = 1 PMC34 = 1 PMC34 = 1 PMC35 = 1 PMC35 = 1 PMC38 = 1 PMC39 = 1 PMC39 = 1 PMC40 = 1 PMC41 = 1 PMC42 = 1 - - - PFC32 = 0 PFC32 = 1 PFC32 = 0 PFC32 = 1 PFC33 = 0 PFC33 = 1 PFC34 = 0 PFC34 = 1 PFC35 = 0 PFC35 = 1 - - - - - - - - - PFCE32 = 0 PFCE32 = 0 PFCE32 = 1 PFCE32 = 1 - - - - - - - - - - - - Note 2 Note 2, INTx39 (INTx3) Note 1 Note 1, INTx31 (INTx3) PMn Register PMCn Register PFCm Register PFCEm Register Other Bits (Register) Notes 1. The INTP7 pin functions alternately as the RXDA0 pin. To use this pin as the RXDA0 pin, invalidate the edge detection function of the alternate-function INTP7 pin (by clearing the INTF31 bit of the INTF3 register to 0 and the INTR31 bit of the INTR3 register to 0). To use this pin as the INTP7 pin, stop the reception operation of UARTA0 (by clearing the UA0RXE bit of the UA0CTL0 register to 0). 2. The INTP8 pin functions alternately as the RXDA2 pin. To use this pin as the RXDA2 pin, invalidate the edge detection function of the alternate-function INTP8 pin (by clearing the INTF39 bit of the INTF3 register to 0 and the INTR39 bit of the INTR3 register to 0). To use this pin as the INTP8 pin, stop the reception operation of UARTA2 (by clearing the UA2RXE bit of the UA2CTL0 register to 0). Remarks 1. The port register (Pn) does not have to be set when the alternate function is used. 2. INTxn = INTFn, INTRn Preliminary User's Manual U17718EJ1V0UD 127 CHAPTER 4 PORT FUNCTIONS www..com Table 4-19. Using Port Pin as Alternate-Function Pin (3/5) Pin Name P50 Alternate-Function Pin Name KR0 TIQ01 TOQ01 P51 KR1 TIQ02 TOQ02 P52 KR2 TIQ03 TOQ03 DDI P53 Note 2 PMn Register PMCn Register PFCm Register PFCEm Register Other Bits (Register) I/O Input Input Output Input Input Output Input Input Output Input Input Input Output Output Input Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required PMC50 = 1 PMC50 = 1 PMC50 = 1 PMC51 = 1 PMC51 = 1 PMC51 = 1 PMC52 = 1 PMC52 = 1 PMC52 = 1 Setting not required PMC53 = 1 PMC53 = 1 PMC53 = 1 Setting not required PMC54 = 1 Setting not required PMC55 = 1 Setting not required PFC50 = 1 PFC50 = 1 PFC50 = 0 PFC51 = 1 PFC51 = 1 PFC51 = 0 PFC52 = 1 PFC52 = 1 PFC52 = 0 Setting not required PFC53 = 1 PFC53 = 1 PFC53 = 0 Setting not required PFC54 = 1 Setting not required PFC55 = 1 Setting not required PFCE50 = 0 PFCE50 = 0 PFCE50 = 1 PFCE54 = 0 PFCE51 = 0 PFCE51 = 1 PFCE52 = 0 PFCE52 = 0 PFCE52 = 1 Setting not required PFCE53 = 0 PFCE53 = 0 PFCE53 = 1 Setting not required - - - - OCDM0 (OCDM) = 1 OCDM0 (OCDM) = 1 OCDM0 (OCDM) = 1 OCDM0 (OCDM) = 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 KR3 TIQ00 TOQ00 DDO Note 2 P54 KR4 DCK Note 2 Output Input P55 KR5 DMS Note 2 Output Notes 1. The KRn pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key return detection function of the alternate-function KRn pin (by clearing the KRMn bit of the KRM register to 0). To use this pin as the KRn pin, invalidate the edge detection function of the alternate-function TIQ0m pin (n = 0 to 3, m = 0 to 3). Pin Name KR0/TIQ01 KR1/TIQ02 KR2/TIQ03 KR3/TIQ00 When Used as TIQ0m Pin KRM0 bit of KRM register = 0 KRM1 bit of KRM register = 0 KRM2 bit of KRM register = 0 KRM3 bit of KRM register = 0 When Used as KRn Pin TQ0TIG2, TQ0TIG3 bits of TQ0IOC1 register = 0 TQ0TIG4, TQ0TIG5 bits of TQ0IOC1 register = 0 TQ0TIG6, TQ0TIG7 bits of TQ0IOC1 register = 0 TQ0TIG0, TQ0TIG1 bits of TQ0IOC1 register = 0 TQ0EES0, TQ0EES1 bits of TQ0IOC2 register = 0 TQ0ETS0, TQ0ETS1 bits of TQ0IOC2 register = 0 2. The DDI, DDO, DCK, and DMS pins are on-chip debug pins. To not use these pins as on-chip debug pins after an external reset, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n bit and the PFCE5.PFCE5n bit are the default values (0), the output becomes undefined. For this reason, first set the PFC5.PFC5n bit and the PFCE5.PFCE5n bit, and then set the PMC5n bit to 1 to set the control mode. Remarks 1. The port register (Pn) does not have to be set when the alternate function is used. 2. INTxn = INTFn, INTRn 128 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Table 4-19. Using Port Pin as Alternate-Function Pin (4/5) Pin Name P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 Alternate-Function Pin Name ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PM70 = 1 PM71 = 1 PM72 = 1 PM73 = 1 PM74 = 1 PM75 = 1 PM76 = 1 PM77 = 1 PM78 = 1 PM79 = 1 Note PMn Register PMCn Register PFCm Register PFCEm Register Other Bits (Register) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - Note Note Note Note Note Note Note Note Note PM710 = 1 PM711 = 1 PM712 = 1 PM713 = 1 PM714 = 1 PM715 = 1 Note Note Note Note Note Note Note Set PM7n to 1 to use the alternate function of P7n (ANIn). Caution If the control mode is specified by using the PMC6 register when the PFC6.PFC6n bit (n = 0 to 8) is the default value (0), the output becomes undefined. For this reason, first set the PFC6.PFC6n bit and then set the PMC6n bit to 1 to set the control mode. Remarks 1. The port register (Pn) does not have to be set when the alternate function is used. 2. INTxn = INTFn, INTRn Preliminary User's Manual U17718EJ1V0UD 129 CHAPTER 4 PORT FUNCTIONS www..com Table 4-19. Using Port Pin as Alternate-Function Pin (5/5) Pin Name P90 P91 Alternate-Function Pin Name KR6 TXDA1 KR7 Note 1 PMn Register Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required Setting not required PMCn Register PFCm Register PFCEm Register PMC90 = 1 PMC90 = 1 PMC91 = 1 PMC91 = 1 PMC92 = 1 PMC92 = 1 PMC93 = 1 PMC93 = 1 PMC94 = 1 PMC94 = 1 PMC95 = 1 PMC95 = 1 PMC96 = 1 PMC96 = 1 PMC97 = 1 PMC97 = 1 PMC97 = 1 PMC98 = 1 PMC99 = 1 PMC913 = 1 PMC913 = 1 PMC914 = 1 PMC915 = 1 PMCCM1 = 1 Setting not required PFC90 = 1 PFC90 = 0 PFC91 = 1 PFC91 = 0 PFC91 = 0 PFC92 = 1 PFC92 = 0 PFC93 = 1 PFC93 = 0 PFC94 = 1 PFC94 = 0 PFC95 = 1 PFC95 = 0 PFC96 = 0 PFC96 = 1 PFC97 = 1 PFC97 = 0 PFC97 = 1 PFC98 = 1 PFC99 = 1 PFC913 = 1 PFC913 = 0 PFC914 = 1 PFC915 = 1 - - PFCE90 = 0 PFCE90 = 1 PFCE91 = 0 PFCE91 = 1 PFCE91 = 1 PFCE92 = 0 PFCE92 = 1 PFCE93 = 0 PFCE93 = 1 PFCE94 = 0 PFCE94 = 1 PFCE95 = 0 PFCE95 = 1 PFCE96 = 1 PFCE96 = 1 PFCE97 = 0 PFCE97 = 1 PFCE97 = 1 - - PFCE913 = 0 PFCE913 = 1 - - - - Other Bits (Register) I/O Input Output Input Input Input Output Input Output Input Output Input Output Input Output Input Input Output Output I/O Input Output Input Input Output Input RXDA1 P92 P93 P94 P95 P96 P97 TIQ11 TOQ11 TIQ12 TOQ12 TIQ13 TOQ13 TIQ10 TOQ10 TIP21 TOP21 SIB1 TIP20 TOP20 P98 P99 P913 P914 P915 PCM1 PDL5 SOB1 SCKB1 INTP4 PCL INTP5 INTP6 CLKOUT FLMD1 INTx913 (INTx9H) INTx914 (INTx9H) INTx915 (INTx9H) Note 2 Notes 1. The KR7 pin and RXDA1 pin are alternate-function pins. When using the pin as the RXDA1 pin, disable KR7 pin key return detection. (Clear the KRM.KRM7 bit to 0.) Also, when using the pin as the KR7 pin, it is recommended to set the PFC91 bit to 1 and clear the PFCE91 bit to 0. 2. The FLMD1 pin does not have to be manipulated by using a port control register because it is used in the flash programming mode. For details, see CHAPTER 23 FLASH MEMORY. Caution If the control mode is specified by using the PMC9 register when the PFC9.PFC9n bit and the PFCE9.PFCE9n bit are the default values (0), the output becomes undefined. For this reason, first set the PFC9.PFC9n bit and the PFCE9.PFCE9n bit, and then set the PMC9n bit to 1 to set the control mode. Remarks 1. The port register (Pn) does not have to be set when the alternate function is used. 2. INTxn = INTFn, INTRn 130 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.4 Block Diagrams of Port Figure 4-2. Block Diagram of Type A-1 WRPM PMmn WRPORT Internal bus Pmn Pmn Selector Address Selector P-ch RD A/D input signal N-ch Preliminary User's Manual U17718EJ1V0UD 131 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-3. Block Diagram of Type B-1 WRPM PMmn WRPORT Internal bus Pmn Pmn Selector Address RD 132 Preliminary User's Manual U17718EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS www..com Figure 4-4. Block Diagram of Type C-1 WRPU PUmn WRPM P-ch PMmn Internal bus WRPORT Pmn Pmn Selector Address RD Selector Preliminary User's Manual U17718EJ1V0UD 133 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-5. Block Diagram of Type D-2 WRPMC PMCmn WRPM PMmn Internal bus Output signal when alternate function is used WRPORT Selector Pmn Pmn Selector Address RD 134 Preliminary User's Manual U17718EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS www..com Figure 4-6. Block Diagram of Type E-1 EVDD WRPU PUmn P-ch WRPMC PMCmn WRPM Internal bus PMmn WRPORT Pmn Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 135 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-7. Block Diagram of Type E-2 EVDD WRPU PUmn P-ch WRPMC PMCmn WRPM Internal bus PMmn WRPORT Selector Output signal when alternate function is used Pmn Pmn Selector Address RD 136 Preliminary User's Manual U17718EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS www..com Figure 4-8. Block Diagram of Type E-3 EVDD WRPU PUmn P-ch Output enable signal when alternate function is used WRPMC PMCmn WRPM Internal bus PMmn Selector Output signal when alternate function is used WRPORT Pmn Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 137 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-9. Block Diagram of Type G-1 EVDD WRPU PUmn P-ch WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn Selector Output signal when alternate function is used WRPORT Pmn Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 138 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-10. Block Diagram of Type G-2 EVDD WRPU PUmn P-ch On-chip debug mode signal WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn WRPORT Pmn Pmn Selector Selector Note Address RD Input signal when alternate function is used Noise elimination Input signal during on-chip debugging Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 139 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-11. Block Diagram of Type G-3 EVDD WRPU PUmn P-ch WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn Selector Output signal when alternate function is used WRPORT Pmn Pmn Selector Address RD 140 Preliminary User's Manual U17718EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS www..com Figure 4-12. Block Diagram of Type G-5 EVDD WRPU PUmn P-ch WRPFC PFCmn Output enable signal when alternate function is used WRPMC PMCmn Internal bus WRPM PMmn Selector Output signal when alternate function is used WRPORT Pmn Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 141 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-13. Block Diagram of Type L-1 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC PMCmn Internal bus WRPM PMmn WRPORT Pmn Pmn Selector Selector Note 2 Address RD Input signal when alternate function is used Edge detection Noise elimination Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. 142 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-14. Block Diagram of Type L-2 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC PMCmn Internal bus WRPM PMmn WRPORT Pmn Pmn Selector Selector Note 2 Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Edge detection Noise elimination Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 143 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-15. Block Diagram of Type N-1 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn WRPORT Pmn Pmn Selector Selector Note 2 Address RD Input signal 1 when alternate function is used Edge detection Selector Noise elimination Input signal 2 when alternate function is used Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. 144 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-16. Block Diagram of Type N-2 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn WRPORT Pmn Pmn Selector Selector Note 2 Address RD Input signal when alternate function is used Edge detection Noise elimination Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 145 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-17. Block Diagram of Type U-4 EVDD WRPU PUmn P-ch WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn WRPORT Pmn Selector Output signal when alternate function is used Pmn Selector Selector Note Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. 146 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-18. Block Diagram of Type U-5 EVDD WRPU PUmn P-ch On-chip debug mode signal WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn WRPORT Pmn Selector Output signal when alternate function is used Pmn Selector Selector Note Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Input signal during on-chip debugging Noise elimination Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 147 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-19. Block Diagram of Type U-6 EVDD WRPU PUmn P-ch WRPFCE On-chip debug mode signal PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Output signal when alternate function is used WRPORT Selector Pmn Output signal during on-chip debugging Selector Pmn Selector Selector Note Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. 148 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-20. Block Diagram of Type U-7 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn WRPORT Pmn Pmn Selector Selector Note Address RD Input signal 2-1 when alternate function is used Input signal 2-2 when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. Selector Input signal 1 when alternate function is used Noise elimination Preliminary User's Manual U17718EJ1V0UD 149 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-21. Block Diagram of Type U-8 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Output signal when alternate function is used WRPORT Pmn Selector Pmn Selector Selector Note Address RD Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode. 150 Preliminary User's Manual U17718EJ1V0UD Selector Input signal 1 when alternate function is used CHAPTER 4 PORT FUNCTIONS www..com Figure 4-22. Block Diagram of Type U-9 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Output signal when alternate function is used WRPORT Pmn Selector Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 151 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-23. Block Diagram of Type U-11 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Output signal when alternate function is used WRPORT Pmn Selector Pmn Selector Selector Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 152 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-24. Block Diagram of Type U-12 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector Output signal when alternate WRPORT function is used Pmn Pmn Selector Address Selector Note RD Input signal when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 153 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-25. Block Diagram of Type U-13 EVDD WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus P-ch PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used WRPORT Selector Pmn Pmn Selector Selector Note Address RD Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode. 154 Selector Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com Figure 4-26. Block Diagram of Type W-1 EVDD WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus P-ch PMCmn WRPM PMmn WRPORT Selector Output signal when alternate function is used Pmn Pmn Selector Selector Note 2 Address RD Input signal when alternate function is used Edge detection Noise elimination Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. Preliminary User's Manual U17718EJ1V0UD 155 CHAPTER 4 PORT FUNCTIONS www..com Figure 4-27. Block Diagram of Type AA-1 EVDD WRPU PUmn Reset signal by POC On-chip debug mode signal WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC Internal bus P-ch PMCmn WRPM PMmn WRPORT Pmn Pmn Selector Selector Note 2 Address RD Input signal during on-chip debugging Input signal when alternate function is used Edge detection Noise elimination N-ch EVSS Notes 1. See 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10). 2. Hysteresis characteristics are not available in port mode. 156 Preliminary User's Manual U17718EJ1V0UD CHAPTER 4 PORT FUNCTIONS www..com 4.5 4.5.1 Cautions Cautions on setting port pins (1) In the V850ES/HG2, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following. (a) Cautions on switching from port mode to alternate-function mode To switch from the port mode to alternate-function mode in the following order. <1> Set the PFn registerNote: <2> Set the PFCn and PFCEn registers: N-ch open-drain setting Alternate-function selection <3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode If the PMCn register is set first, note with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers, unexpected operations may occur. Note N-ch open-drain output pin only Caution Regardless of the port mode/alternate-function mode, the Pn register is read and written as follows. * Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read the pin states (PMn.PMnm bit = 1). * Pn register write: Write to the port output latch Preliminary User's Manual U17718EJ1V0UD 157 www..com CHAPTER 5 CLOCK GENERATION FUNCTION 5.1 Overview The following clock generation functions are available. Main clock oscillator * In clock-through mode fX = 4 to 5 MHz (fXX = 4 to 5 MHz) * In PLL mode fX = 4 to 5 MHz (fXX = 16 to 20 MHz) Subclock oscillator (crystal oscillation or RC oscillation selectable by option byte function) * 32.768 kHz (crystal resonator) * 20 kHz (RC oscillator) Multiply (x4) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable Internal oscillator * fR = 200 kHz (TYP.) Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function Programmable clock (PCL) output function Remark fX: fR: Main clock oscillation frequency Internal oscillation clock frequency fXX: Main clock frequency fXT: Subclock frequency 158 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com 5.2 Configuration Figure 5-1. Clock Generator FRC bit XT1 XT2 Subclock oscillator fXT fXT fBRG = fX/2 to fX/212 Timer M clock Watch timer clock, watchdog timer 2 clock Watch timer clock Prescaler 3 MCK MFRC bit bit X1 X2 Main clock oscillator Main clock oscillator stop control STOP mode fX IDLE control PLLON bit IDLE mode IDLE fXX control Prescaler 2 fXX/32 CK2 to CK0 bits CLS, CK3 bits Note Selector PLL Selector Selector PCK1, PCK0 bits SELPLL bit fXX/16 fXX/8 fXX/4 fXX/2 fXX Selector HALT mode HALT fCPU control fCLK CPU clock Internal system clock PCL Selector Internal oscillator RSTOP bit fR 1/8 divider fR/8 Watchdog timer 2 clock, timer M clock CLKOUT Port CM Prescaler 1 fXX to fXX/1024 Peripheral clock, watchdog timer 2 clock fX to fX/1024 Prescaler 4 Watchdog timer 2 clock Note The internal oscillation clock is selected when watchdog timer 2 overflows during the oscillation stabilization time. Remark fX: fXX: fXT: Main clock oscillation frequency Main clock frequency Subclock frequency fCLK: Internal system clock frequency fCPU: CPU clock frequency fBRG: Watch timer clock frequency fR: Internal oscillation clock frequency Preliminary User's Manual U17718EJ1V0UD 159 CHAPTER 5 CLOCK GENERATION FUNCTION www..com (1) Main clock oscillator The main resonator oscillates the following frequencies (fX). * In clock-through mode fX = 4 to 5 MHz * In PLL mode fX = 4 to 5 MHz (fXX = 16 to 20 MHz) (2) Subclock oscillator The sub-resonator oscillates a frequency (fXT) of 32.768 kHz or 20 kHz. (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Internal oscillator Oscillates a frequency (fR) of 200 kHz (TYP.). (5) Prescaler 1 This circuit generates the clock (fXX to fXX/1,024) to be supplied to the following on-chip peripheral functions: TMP0 to TMP3, TMQ0, TMQ1, TMM0, CSIB0, CSIB1, UARTA0 to UARTA2, ADC, and WDT2 (6) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin. (7) Prescaler 3 This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz) and supplies that clock to the watch timer block. For details, see CHAPTER 9 WATCH TIMER FUNCTIONS. (8) Prescaler 4 This circuit generates the clock (fX to fX/1,024) to be supplied to on-chip peripheral function. The block to be supplied is WDT2 only. (9) PLL This circuit multiplies the clock generated by the main clock oscillator (fX) by 4. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit. Whether the clock is multiplied by 4 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the PLLCTL.PLLON bit. 160 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com 5.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. Preliminary User's Manual U17718EJ1V0UD 161 CHAPTER 5 CLOCK GENERATION FUNCTION www..com After reset: 03H R/W Address: FFFFF828H PCC FRC FRC 0 1 MCK 0 1 MCK MFRC CLSNote CK3 CK2 CK1 CK0 Use of subclock on-chip feedback resistor Used Not used Main clock oscillator control Oscillation enabled Oscillation stopped * Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. * When the main clock is stopped and the device is operating with the subclock, clear (0) the MCK bit and secure the oscillation stabilization time by software before switching the CPU clock to the main clock or operating the on-chip peripheral functions. MFRC 0 1 CLSNote 0 1 CK3 0 0 0 0 0 0 0 1 Main clock operation Subclock operation CK2 0 0 0 0 1 1 1 x CK1 0 0 1 1 0 0 1 x CK0 0 1 0 1 0 1 x x fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 Setting prohibited fXT Clock selection (fCLK/fCPU) Used Not used Status of CPU clock (fCPU) Use of main clock on-chip feedback resistor Note The CLS bit is a read-only bit. Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. Remark x: don't care 162 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com (a) Example of setting main clock operation subclock operation <1> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit 1: Set the MCK bit to 1 only when stopping the main clock. Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip peripheral functions operating with the main clock. 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting bits CK2 to CK0 [Description example] _DMA_DISABLE: clrl st.b set1 tst1 bz st.b set1 setl Remark 0, DCHCn[r0] r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS r0, PRCMD[r0] 6, PCC[r0] 0, DCHCn[r0] -- MCK bit 1, main clock is stopped. -- DMA operation enabled. n = 0 to 3 -- CK3 bit 1 -- Wait until subclock operation starts. -- DMA operation disabled. n = 0 to 3 <1> _SET_SUB_RUN : <2> _CHECK_CLS : <3> _STOP_MAIN_CLOCK : _DMA_ENABLE: The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed loop. Preliminary User's Manual U17718EJ1V0UD 163 CHAPTER 5 CLOCK GENERATION FUNCTION www..com (b) Example of setting subclock operation main clock operation <1> MCK bit 0: <3> CK3 bit 0: <4> Main clock operation: Main clock starts oscillating Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. It takes the following time after the CK3 bit is set until main clock operation is started. Max.: 1/fXT (1/subclock frequency) Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. Caution Enable operation of the on-chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. If their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. [Description example] _DMA_DISABLE: clrl st.b clr1 <2> movea _WAIT_OST : nop nop nop addi cmp bne <3> st.b clr1 tst1 bnz setl Remark -1, r11, r11 r0, r11 _WAIT_OST r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 -- CK3 0 -- Wait until main clock operation starts. 0, DCHCn[r0] r0, PRCMD[r0] 6, PCC[r0] 0x55, r0, r11 -- DMA operation disabled. n = 0 to 3 -- Release of protection of special registers -- Main clock starts oscillating. -- Wait for oscillation stabilization time. <1> _START_MAIN_OSC : <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <4> _CHECK_CLS : _DMA_ENABLE: The description above is simply an example. Note that in <4> above, the CLS bit is read in a closed loop. 164 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF80CH RCM 0 0 0 0 0 0 0 RSTOP RSTOP 0 1 Oscillation/stop of internal oscillator Internal oscillator oscillation Internal oscillator stopped Cautions 1. The settings of the RCM register are valid by setting the option byte. For details, see CHAPTER 24 OPTION BYTE FUNCTION. 2. The internal oscillator cannot be stopped while the CPU is operating on the internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1. 3. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time, the RSTOP bit remains being set to 1. (3) CPU operation clock status register (CCLS) The CCLS register indicates the status of the CPU operation clock. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00HNote R Address: FFFFF82EH CCLS 0 0 0 0 0 0 0 CCLSF CCLSF 0 1 CPU operation clock status Operating on main clock (fX) or subclock (fXT). Operating on internal oscillation clock (fR). Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set to 1 and the reset value is 01H. Preliminary User's Manual U17718EJ1V0UD 165 CHAPTER 5 CLOCK GENERATION FUNCTION www..com 5.4 5.4.1 Operation Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock Register Setting and Operation Status CLK Bit = 0, MCK Bit = 0 During Reset Target Clock Main clock oscillator (fX) Subclock oscillator (fXT) CPU clock (fCPU) Internal system clock (fCLK) Main clock (in PLL mode, fXX) Peripheral clock (fXX to fXX/1,024) WT clock (main) WT clock (sub) WDT2 clock (internal oscillation) WDT2 clock (main) x x x x x x x x x x x x x x x Note 1 x x x x x Note 2 x x x x x x x x x x x x x x x x x x HALT Mode IDLE1, IDLE2 Mode STOP Mode PCC Register CLS Bit = 1, MCK Bit = 0 During Oscillation Stabilization Time Count CLS Bit = 1, MCK Bit = 1 Subclock Sub-IDLE Subclock Sub-IDLE Mode Mode Mode Mode x x x Notes 1. Oscillation starts after time 1/2 of the oscillation stabilization time, and the stable clock is supplied after lockup time. 2. Operable in the IDLE1 mode. Stopped in the IDLE2 mode. Remark : Operable x: Stopped 5.4.2 Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 5-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z. 166 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com 5.5 5.5.1 PLL Function Overview In the V850ES/HG2, an operating clock that is 4 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions. When PLL function is used: Clock-through mode: 5.5.2 Registers Input clock = 4 to 5 MHz (output: 16 to 20 MHz) Input clock = 4 to 5 MHz (output: 4 to 5 MHz) (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the PLL function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. After reset: 01H R/W Address: FFFFF82CH PLLCTL 0 0 0 0 0 0 SELPLL PLLON PLLON 0 1 PLL stopped PLL operation stop register PLL operating (After PLL operation starts, a lockup time is required for frequency stabilization) SELPLL 0 1 CPU operation clock selection register Clock-through mode PLL mode Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clockthrough mode). 2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not (unlocked), "0" is written to the SELPLL bit if data is written to it. Preliminary User's Manual U17718EJ1V0UD 167 CHAPTER 5 CLOCK GENERATION FUNCTION www..com (2) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R Address: FFFFF824H LOCKR 0 0 0 0 0 0 0 LOCK LOCK 0 1 Locked status Unlocked status PLL lock status check Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear conditions are as follows. [Set conditions] * Upon system resetNote * In IDLE2 or STOP mode * Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0) * Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of PCC.MCK bit to 1) Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the oscillation stabilization time has elapsed. [Clear conditions] * Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 17.2 (3) Oscillation stabilization time select register (OSTS))) * Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release, when the STOP mode was set in the PLL operating status * Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed from 0 to 1 * After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register) when the IDLE2 mode is set during PLL operation. 168 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com (3) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H. After reset: 03H R/W Address: FFFFF6C1H PLLS 0 0 0 0 0 0 PLLS1 PLLS0 PLLS1 0 0 1 1 PLLS0 0 1 0 1 2 /fX 211fX 212/fX 10 Selection of PLL lockup time 213/fX (default value) Cautions 1. Set so that the lockup time is 800 s or longer. 2. Do not change the PLLS register setting during the lockup period. Preliminary User's Manual U17718EJ1V0UD 169 CHAPTER 5 CLOCK GENERATION FUNCTION www..com (4) Programmable clock mode register (PCLM) The PCLM register is an 8-bit register used to control the PCL output. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W Address: FFFFF82FH PCLM 0 0 0 PCLE 0 0 PCK1 PCK0 PCLE 0 1 Selection of PCL pin output operation PCL pin output disabled (PCL pin is fixed to low level) PCL pin output enabled Caution Set the port-related control registers (PM, PMC, PFC, and PFCE registers, etc.) first, and then set the PCLE bit to 1. PCK1 0 0 1 1 PCK0 0 1 0 1 fXX/2 fXX/4 fXX/8 fXX/16 Selection of PLL output clock Caution Set the PCLE bit to 1 only during PLL operation. To stop the PLL, clear the PCLE bit to 0. 170 Preliminary User's Manual U17718EJ1V0UD CHAPTER 5 CLOCK GENERATION FUNCTION www..com 5.5.3 Usage (1) When PLL is used * After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). * To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0). * The PLL stops during transition to IDLE2 or STOP mode regardless of the setting and is restored from IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows. (a) When transiting to IDLE2 or STOP mode from the clock through mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer. * IDLE2 mode: Set the OSTS register so that the setup time is 350 s (min.) or longer. (b) When shifting to the IDLE 2 or STOP mode while remaining in the PLL operation mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer. * IDLE2 mode: Set the OSTS register so that the setup time is 800 s (min.) or longer. When shifting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary. (2) When PLL is not used * The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0). Preliminary User's Manual U17718EJ1V0UD 171 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/HG2 has four timer/event counter channels, TMP0 to TMP3. 6.1 Overview An outline of TMPn is shown below. * Clock selection: 8 ways * Capture/trigger input pins: 2 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 2 * Capture/compare match interrupt request signals: 2 * Timer output pins: 2 Remark n = 0 to 3 6.2 Functions TMPn has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement Remark n = 0 to 3 172 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.3 Configuration TMPn includes the following hardware. Table 6-1. Configuration of TMPn Item Timer register Registers 16-bit counter TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers Timer inputs Timer outputs Control registers Note 2 Configuration 2 (TIPn0 Note 1 , TIPn1 pins) 2 (TOPn0, TOPn1 pins) TMPn control registers 0, 1 (TPnCTL0, TPnCTL1) TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2) TMPn option register 0 (TPnOPT0) Notes 1. The TIPn0 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. When using the functions of the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 4-19 Using Port Pin as Alternate-Function Pin. Remark n = 0 to 3 Figure 6-1. Block Diagram of TMPn Internal bus Output controller fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128Note 1, fXTNote 2 TPnCNT Selector Selector 16-bit counter Clear INTTPnOV TOPn0 TOPn1 CCR0 buffer register CCR1 buffer register INTTPnCC0 INTTPnCC1 TIPn0 TIPn1 Edge detector TPnCCR0 TPnCCR1 Internal bus Notes 1. TMP0, TMP2 2. TMP1, TMP3 (Counting operation cannot be performed with the subclock when the main clock is stopped.) Remark fXX: Main clock frequency fXT: Subclock frequency Preliminary User's Manual U17718EJ1V0UD 173 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read. Reset sets the TPnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR0 register is used as a compare register, the value written to the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TPnCCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TPnCCR1 register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIPn0 and TIPn1 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TPnIOC1 and TPnIOC2 registers. (5) Output controller This circuit controls the output of the TOPn0 and TOPn1 pins. The output controller is controlled by the TPnIOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. 174 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.4 Registers The registers that control TMPn are as follows. * TMPn control register 0 (TPnCTL0) * TMPn control register 1 (TPnCTL1) * TMPn I/O control register 0 (TPnIOC0) * TMPn I/O control register 1 (TPnIOC1) * TMPn I/O control register 2 (TPnIOC2) * TMPn option register 0 (TPnOPT0) * TMPn capture/compare register 0 (TPnCCR0) * TMPn capture/compare register 1 (TPnCCR1) * TMPn counter read buffer register (TPnCNT) Remarks 1. When using the functions of the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 4-19 Using Port Pin as Alternate-Function Pin. 2. n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 175 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software. After reset: 00H R/W Address: TP0CTL0 FFFFF590H, TP1CTL0 FFFFF5A0H, TP2CTL0 FFFFF5B0H, TP3CTL0 FFFFF5C0H 7 TPnCTL0 (n = 0 to 3) TPnCE 0 1 TPnCE 6 0 5 0 4 0 3 0 2 1 0 TPnCKS2 TPnCKS1 TPnCKS0 TMPn operation control TMPn operation disabled (TMPn reset asynchronouslyNote 1). TMPn operation enabled. TMPn operation started. TPnCKS2 TPnCKS1 TPnCKS0 Internal count clock selection n = 0, 2 n = 1, 3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXTNote 2 Notes 1. TPn0PT0.TPnOVF bit, 16-bit counter, timer output (TOPn0, TOPn1 pins) 2. Counting operation cannot be performed with the subclock when the main clock is stopped. Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0. When the value of the TPnCE bit is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency fXT: Subclock frequency 176 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H R/W Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H 7 6 5 TPnEEE 4 0 3 0 2 1 0 TPnCTL1 (n = 0 to 3) TPnSYE TPnEST TPnMD2 TPnMD1 TPnMD0 TPnSYE 0 1 Tuned operation mode enable control Independent operation mode (asynchronous operation mode) Tuned operation mode (specification of slave operation) In this mode, timer P can operate in synchronization with a master timer. Master timer TMP0 TMP2 TMP1 TMP3 Slave timer - TMQ0 For the tuned operation mode, see 6.6 Timer Tuned Operation Function. Caution Be sure to clear the TP0SYE and TP2SYE bits to 0. TPnEST 0 1 Software trigger control - Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TPnEST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TPnEST bit as the trigger. Cautions 1. The TPnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. Be sure to clear bits 3 and 4 to "0". Preliminary User's Manual U17718EJ1V0UD 177 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2/2) TPnEEE 0 Count clock selection Disable operation with external event count input. (Perform counting with the count clock selected by the TPnCTL0.TPnCK0 to TPnCK2 bits.) Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.) 1 The TPnEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TPnMD2 TPnMD1 TPnMD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timer mode selection Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Setting prohibited Cautions 1. External event count input is selected in the external event count mode regardless of the value of the TPnEEE bit. 2. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TPnCE bit = 1. If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 178 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H, TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H 7 TPnIOC0 (n = 0 to 3) TPnOL1 0 1 0 6 0 5 0 4 0 3 2 1 TPnOL0 0 TPnOE0 TPnOL1 TPnOE1 TOPn1 pin output level setting TOPn1 pin output inversion disabled TOPn1 pin output inversion enabled TPnOE1 0 TOPn1 pin output setting Timer output disabled * When TPnOL1 bit = 0: Low level is output from the TOPn1 pin * When TPnOL1 bit = 1: High level is output from the TOPn1 pin Timer output enabled (a square wave is output from the TOPn1 pin). 1 TPnOL0 0 1 TOPn0 pin output level setting TOPn0 pin output inversion disabled TOPn0 pin output inversion enabled TPnOE0 0 TOPn0 pin output setting Timer output disabled * When TPnOL0 bit = 0: Low level is output from the TOPn0 pin * When TPnOL0 bit = 1: High level is output from the TOPn0 pin Timer output enabled (a square wave is output from the TOPn0 pin). 1 Cautions 1. Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) set the bits again. 2. Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits are 0, the TOPnm pin output level varies (m = 0, 1). If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then Preliminary User's Manual U17718EJ1V0UD 179 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0IOC1 FFFFF593H, TP1IOC1 FFFFF5A3H, TP2IOC1 FFFFF5B3H, TP3IOC1 FFFFF5C3H 7 TPnIOC1 (n = 0 to 3) TPnIS3 0 0 1 1 0 6 0 5 0 4 0 3 TPnIS3 2 TPnIS2 1 TPnIS1 0 TPnIS0 TPnIS2 0 1 0 1 Capture trigger input signal (TIPn1 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TPnIS1 0 0 1 1 TPnIS0 0 1 0 1 Capture trigger input signal (TIPn0 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) again. 2. The TPnIS3 to TPnIS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits 180 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0IOC2 FFFFF594H, TP1IOC2 FFFFF5A4H, TP2IOC2 FFFFF5B4H, TP3IOC2 FFFFF5C4H 7 TPnIOC2 (n = 0 to 3) 0 6 0 5 0 4 0 3 2 1 0 TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnEES1 TPnEES0 External event count input signal (TIPn0 pin) valid edge setting 0 0 1 1 0 1 0 1 No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges TPnETS1 TPnETS0 0 0 1 1 0 1 0 1 External trigger input signal (TIPn0 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 2. The TPnEES1 and TPnEES0 bits are valid only when the TPnCTL1.TPnEEE bit = 1 or when the external event count mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 001) has been set. 3. The TPnETS1 and TPnETS0 bits are valid only when the external trigger pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 010) or the one-shot pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 = 011) is set. Preliminary User's Manual U17718EJ1V0UD 181 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0OPT0 FFFFF595H, TP1OPT0 FFFFF5A5H, TP2OPT0 FFFFF5B5H, TP3OPT0 FFFFF5C5H 7 TPnOPT0 (n = 0 to 3) TPnCCS1 0 1 0 6 0 5 4 3 0 2 0 1 0 0 TPnOVF TPnCCS1 TPnCCS0 TPnCCR1 register capture/compare selection Compare register selected Capture register selected The TPnCCS1 bit setting is valid only in the free-running timer mode. TPnCCS0 0 1 TPnCCR0 register capture/compare selection Compare register selected Capture register selected The TPnCCS0 bit setting is valid only in the free-running timer mode. TPnOVF Set (1) Reset (0) TMPn overflow detection flag Overflow occurred TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0 * The TPnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTPnOV) is generated at the same time that the TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0 register are read when the TPnOVF bit = 1. * The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMPn. Cautions 1. Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 2. Be sure to clear bits 1 to 3, 6, and 7 to "0". 182 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit. In the pulse width measurement mode, the TPnCCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TPnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TPnCCR0 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TP0CCR0 FFFFF596H, TP1CCR0 FFFFF5A6H, TP2CCR0 FFFFF5B6H, TP3CCR0 FFFFF5C6H 15 TPnCCR0 (n = 0 to 3) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Preliminary User's Manual U17718EJ1V0UD 183 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. If TOPn0 pin output is enabled at this time, the output of the TOPn0 pin is inverted. When the TPnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TPnCCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR0 register if the valid edge of the capture trigger input pin (TIPn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn0) is detected. Even if the capture operation and reading the TPnCCR0 register conflict, the correct value of the TPnCCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 184 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit. In the pulse width measurement mode, the TPnCCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TPnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TPnCCR1 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TP0CCR1 FFFFF598H, TP1CCR1 FFFFF5A8H, TP2CCR1 FFFFF5B8H, TP3CCR1 FFFFF5C8H 15 TPnCCR1 (n = 0 to 3) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Preliminary User's Manual U17718EJ1V0UD 185 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. If TOPn1 pin output is enabled at this time, the output of the TOPn1 pin is inverted. (b) Function as capture register When the TPnCCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR1 register if the valid edge of the capture trigger input pin (TIPn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn1) is detected. Even if the capture operation and reading the TPnCCR1 register conflict, the correct value of the TPnCCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 186 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0. If the TPnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TPnCNT register is cleared to 0000H after reset, as the TPnCE bit is cleared to 0. Caution Accessing the TPnCNT register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R Address: TP0CNT FFFFF59AH, TP1CNT FFFFF5AAH, TP2CNT FFFFF5BAH, TP3CNT FFFFF5CAH 15 TPnCNT (n = 0 to 3) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Preliminary User's Manual U17718EJ1V0UD 187 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (10) TIPnm pin noise elimination control register (PnmNFC) The PnmNFC register is an 8-bit register that sets the digital noise filter of the timer P input pin for noise elimination. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: P00NFC : FFFFFB00H (TIP00 pin) P01NFC : FFFFFB04H (TIP01 pin) P10NFC : FFFFFB08H (TIP10 pin) P11NFC : FFFFFB0CH (TIP11 pin) P20NFC : FFFFFB10H (TIP20 pin) P21NFC : FFFFFB14H (TIP21 pin) P30NFC : FFFFFB18H (TIP30 pin) P31NFC : FFFFFB1CH (TIP31 pin) 7 PnmNFC (n = 0 to 3, m = 0, 1) NFSTS 0 1 0 6 NFSTS 5 0 4 0 3 0 2 NFC2 1 NFC1 0 NFC0 Setting of number of times of sampling by digital noise filter 3 times 2 times NFC2 NFC1 NFC0 n = 0, 2 Sampling clock n = 1, 3 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/32 fXX/64 Setting prohibited fXX/8 fXX/16 fXT Cautions 1. Be sure to clear bits 3 to 5 and 7 to "0". 2. A signal input to the timer input pin (TIPnm) before the PnmNFC register is set is output with digital noise eliminated. Therefore, set the sampling clock (NFC2 to NFC0) and the number of times of sampling (NFSTS) by using the PnmNFC register, wait for initialization time = (Sampling clock) x (Number of times of sampling), and enable the timer operation. Remark The width of the noise that can be accurately eliminated is (Sampling clock) x (Number of times of sampling - 1). Even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. 188 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5 Operation TMPn can perform the following operations. Operation TPnCTL1.TPnEST Bit TIPn0 Pin Capture/Compare Register Setting Compare only Compare only Compare only Compare only Compare only Switching enabled Capture only Compare Register Write Anytime write Anytime write Batch write Anytime write Batch write Anytime write Not applicable (Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode Note 1 Invalid Invalid Note 2 Invalid Invalid Valid Valid Invalid Invalid Invalid External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Valid Valid Invalid Invalid Note 2 Invalid Notes 1. To use the external event count mode, specify that the valid edge of the TIPn0 pin capture trigger input is not detected (by clearing the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TPnCTL1.TPnEEE bit to 0). Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 189 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0 pin. Usually, the TPnCCR1 register is not used in the interval timer mode. Figure 6-2. Configuration of Interval Timer Clear Count clock selection 16-bit counter Match signal Output controller TOPn0 pin INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark n = 0 to 3 Figure 6-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) D0 D0 D0 D0 D0 Remark n = 0 to 3 190 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TPnCCR0 register + 1) x Count clock cycle Remark n = 0 to 3 Figure 6-4. Register Setting for Interval Timer Mode Operation (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0 0/1Note 0 0 TPnMD2 TPnMD1 TPnMD0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count with external event count input signal Note This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and INTTPnCC1) are masked by the interrupt mask flags (TPnCCMK0 and TPnCCMK1) and timer output (TOPn1) is performed at the same time. However, set the TPnCCR0 and TPnCCR1 registers to the same value (see 6.5.1 (2) (d) Operation of TPnCCR1 register). Preliminary User's Manual U17718EJ1V0UD 191 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level with operation of TOPn0 pin disabled 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting of output level with operation of TOPn1 pin disabled 0: Low level 1: High level (d) TMPn counter read buffer register (TPnCNT) By reading the TPnCNT register, the count value of the 16-bit counter can be read. (e) TMPn capture/compare register 0 (TPnCCR0) If the TPnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TMPn capture/compare register 1 (TPnCCR1) Usually, the TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal (INTTPnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TPnCCMK1). Remarks 1. TMPn I/O control register 1 (TPnIOC1), TMPn I/O control register 2 (TPnIOC2), and TMPn option register 0 (TPnOPT0) are not used in the interval timer mode. 2. n = 0 to 3 192 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Interval timer mode operation flow Figure 6-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnCCR0 register Initial setting of these registers is performed before setting the TPnCE bit to 1. TPnCE bit = 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. TPnCE bit = 0 STOP Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 193 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal Interval time Count clock cycle Interval time Count clock cycle 0000H FFFFH 0000H 0000H 0000H 0000H Remark n = 0 to 3 194 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted. At this time, an overflow interrupt request signal (INTTPnOV) is not generated, nor is the overflow flag (TPnOPT0.TPnOVF bit) set to 1. FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle FFFFH Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 195 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TPnCE bit TPnCCR0 register TPnOL0 bit TOPn0 pin output INTTPnCC0 signal L D1 D2 D2 D1 D2 D2 Interval time (1) Interval time (NG) Interval time (2) Remarks 1. Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle 2. n = 0 to 3 If the value of the TPnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted. Therefore, the INTTPnCC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". 196 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (d) Operation of TPnCCR1 register Figure 6-6. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal Clear Output controller TOPn1 pin INTTPnCC1 signal Count clock selection 16-bit counter Match signal Output controller TOPn0 pin INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 197 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted. The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin. Figure 6-7. Timing Chart When D01 D11 FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal TPnCCR1 register TOPn1 pin output INTTPnCC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01 Remark n = 0 to 3 198 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed. Figure 6-8. Timing Chart When D01 < D11 Consequently, the FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal TPnCCR1 register TOPn1 pin output INTTPnCC1 signal L D11 D01 D01 D01 D01 Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 199 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted. The TOPn0 pin cannot be used. Usually, the TPnCCR1 register is not used in the external event count mode. Figure 6-9. Configuration in External Event Count Mode Clear TIPn0 pin (external event count input) Edge detector 16-bit counter Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark n = 0 to 3 Figure 6-10. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal External event count interval (D0 + 1) External event count interval (D0 + 1) External event count interval (D0 + 1) D0 D0 D0 D0 16-bit counter External event count input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal D0 - 1 D0 0000 0001 D0 Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 3 200 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated. The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TPnCCR0 register + 1) times. Figure 6-11. Register Setting for Operation in External Event Count Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0 0 0 0 TPnMD2 TPnMD1 TPnMD0 0 0 1 0, 0, 1: External event count mode (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0 TPnOE1 TPnOL0 0 0 TPnOE0 0 0: Disable TOPn0 pin output 0: Disable TOPn1 pin output (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input Preliminary User's Manual U17718EJ1V0UD 201 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare register 0 (TPnCCR0) If D0 is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTPnCC0) is generated when the number of external event counts reaches (D0 + 1). (g) TMPn capture/compare register 1 (TPnCCR1) Usually, the TPnCCR1 register is not used in the external event count mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. Therefore, mask the interrupt signal by using the interrupt mask flag (TPnCCMK1). Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the external event count mode. 2. n = 0 to 3 202 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) External event count mode operation flow Figure 6-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, Initial setting of these registers is performed before setting the TPnCE bit to 1. TPnCE bit = 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. TPnCE bit = 0 STOP Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 203 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TPnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 000, TPnCTL1.TPnEEE bit = 1). (a) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. TPnOPT0.TPnOVF bit is not set. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTPnCC0 signal is generated. At this time, the FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal External event count signal interval External event count signal interval External event count signal interval FFFFH Remark n = 0 to 3 204 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal D1 D2 D2 D1 D2 D2 External event count signal interval (1) (D1 + 1) External event count signal interval (NG) (10000H + D2 + 1) External event count signal interval (2) (D2 + 1) Remark n = 0 to 3 If the value of the TPnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTPnCC0 signal is generated. Therefore, the INTTPnCC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". Preliminary User's Manual U17718EJ1V0UD 205 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (c) Operation of TPnCCR1 register Figure 6-13. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal Clear INTTPnCC1 signal TIPn0 pin Edge detector 16-bit counter Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark n = 0 to 3 If the set value of the TPnCCR1 register is smaller than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. Figure 6-14. Timing Chart When D01 D11 FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01 Remark n = 0 to 3 206 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match. Figure 6-15. Timing Chart When D01 < D11 FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal L D11 D01 D01 D01 D01 Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 207 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOPn0 pin. Figure 6-16. Configuration in External Trigger Pulse Output Mode TPnCCR1 register TIPn0 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Transfer Output S controller R (RS-FF) TOPn1 pin INTTPnCC1 signal 16-bit counter Match signal Output controller TOPn0 pin INTTPnCC0 signal TPnCE bit CCR0 buffer register Transfer TPnCCR0 register Remark n = 0 to 3 208 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-17. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) D1 D0 D1 D1 D0 D1 D0 D1 D0 16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOPn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOPn0 pin is inverted. The TOPn1 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TPnCCR1 register) x Count clock cycle Cycle = (Set value of TPnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1) The compare match request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the trigger. Remark n = 0 to 3, m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 209 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clockNote 1 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0/1 0/1 0 0 TPnMD2 TPnMD1 TPnMD0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count with external event input signal Generate software trigger when 1 is written (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 2 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Settings of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Specifies active level of TOPn1 pin output 0: Active-high 1: Active-low * When TPnOL1 bit = 0 16-bit counter TOPn1 pin output * When TPnOL1 bit = 1 16-bit counter TOPn1 pin output Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1. 2. Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse output mode. 210 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the external trigger pulse output mode. 2. n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 211 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Operation flow in external trigger pulse output mode Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D10 D11 D01 D11 D01 D00 D10 <1> <2> <3> <4> <5> Remark n = 0 to 3 212 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. START Setting of TPnCCR1 register Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register Initial setting of these registers is performed before setting the TPnCE bit to 1. <4> TPnCCR0, TPnCCR1 register setting change flow The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting is enabled (TPnCE bit = 1). Trigger wait status TPnCE bit = 1 Setting of TPnCCR0 register When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. Setting of TPnCCR1 register <2> TPnCCR0 and TPnCCR1 register setting change flow <5> Count operation stop flow Setting of TPnCCR0 register TPnCCR1 register write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. TPnCE bit = 0 Counting is stopped. Setting of TPnCCR1 register STOP Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 213 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH D01 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 214 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write the same value to the TPnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has to be set. After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts with writing the TPnCCRm register. Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 215 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock 16-bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output D0 0000H D0 0000H D0 0000H FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark n = 0 to 3 To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register. If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output D0 D0 + 1 D0 D0 + 1 D0 D0 + 1 FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark n = 0 to 3 216 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIPn0 pin input) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output FFFF 0000 D1 - 1 0000 D1 Shortened Remark n = 0 to 3 If the trigger is detected immediately before the INTTPnCC1 signal is generated, the INTTPnCC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOPn1 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter External trigger input (TIPn0 pin input) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output FFFF 0000 D1 - 2 0000 0001 D1 - 1 D1 D1 Extended Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 217 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection. 16-bit counter External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn1 pin output FFFF 0000 D0 - 1 D0 0000 0000 D0 Extended Remark n = 0 to 3 If the trigger is detected immediately before the INTTPnCC0 signal is generated, the INTTPnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn1 pin output FFFF 0000 D0 - 1 D0 0000 0001 D0 Shortened Remark n = 0 to 3 218 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter TPnCCR1 register TOPn1 pin output INTTPnCC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2 Remark n = 0 to 3 Usually, the INTTPnCC1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the TPnCCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOPn1 pin. Preliminary User's Manual U17718EJ1V0UD 219 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOPn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 6-20. Configuration in One-Shot Pulse Output Mode TPnCCR1 register TIPn0 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) Transfer Output S controller R (RS-FF) TOPn1 pin INTTPnCC1 signal 16-bit counter Match signal TOPn0 pin INTTPnCC0 signal TPnCE bit CCR0 buffer register Transfer TPnCCR0 register Remark n = 0 to 3 220 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-21. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Active Delay level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) D1 D0 D1 D1 D0 D1 D0 When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TPnCCR1 register) x Count clock cycle Active level width = (Set value of TPnCCR0 register - Set value of TPnCCR1 register + 1) x Count clock cycle The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the trigger. Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 221 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clockNote 1 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0/1 0/1 0 0 TPnMD2 TPnMD1 TPnMD0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count external event input signal Generate software trigger when 1 is written (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 2 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Specifies active level of TOPn1 pin output 0: Active-high 1: Active-low * When TPnOL1 bit = 0 16-bit counter TOPn1 pin output * When TPnOL1 bit = 1 16-bit counter TOPn1 pin output Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1. 2. Clear this bit to 0 when the TOPn0 pin is not used in the one-shot pulse output mode. 222 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D1 - D0 + 1) x Count clock cycle Output delay period = (D1) x Count clock cycle Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the one-shot pulse output mode. 2. n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 223 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Operation flow in one-shot pulse output mode Figure 6-23. Software Processing Flow in One-Shot Pulse Output Mode FFFFH D00 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output D10 D11 D00 D01 D01 D10 D11 <1> <2> <3> <1> Count operation start flow <2> TPnCCR0, TPnCCR1 register setting change flow As rewriting the TPnCCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTPnCCR0 signal is recommended. START Setting of TPnCCR0, TPnCCR1 registers Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register Initial setting of these registers is performed before setting the TPnCE bit to 1. <3> Count operation stop flow Count operation is stopped TPnCE bit = 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). Trigger wait status TPnCE bit = 0 STOP Remark n = 0 to 3 m = 0, 1 224 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D00 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay (D10) Active level width (D00 - D10 + 1) Delay (D10) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) D10 D11 D00 D01 D10 D10 D00 D10 D00 D01 D11 When the TPnCCR0 register is rewritten from D00 to D01 and the TPnCCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TPnCCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTPnCC1 signal and asserts the TOPn1 pin. When the count value matches D01, the counter generates the INTTPnCC0 signal, deasserts the TOPn1 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 225 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter TPnCCR1 register TOPn1 pin output INTTPnCC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2 Remark n = 0 to 3 Usually, the INTTPnCC1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TPnCCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOPn1 pin. Remark n = 0 to 3 226 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin. Figure 6-24. Configuration in PWM Output Mode TPnCCR1 register Transfer CCR1 buffer register Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) TOPn1 pin INTTPnCC1 signal 16-bit counter Match signal Output controller TOPn0 pin INTTPnCC0 signal TPnCE bit CCR0 buffer register Transfer TPnCCR0 register Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 227 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-25. Basic Timing in PWM Output Mode FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 Active period (D10) Cycle (D00 + 1) Inactive period (D00 - D10 + 1) When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOPn1 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TPnCCR1 register) x Count clock cycle Cycle = (Set value of TPnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1) The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0 to 3, m = 0, 1 228 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-26. Setting of Registers in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clockNote 1 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0 0/1 0 0 TPnMD2 TPnMD1 TPnMD0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count external event input signal (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 2 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Specifies active level of TOPn1 pin output 0: Active-high 1: Active-low * When TPnOL1 bit = 0 16-bit counter TOPn1 pin output * When TPnOL1 bit = 1 16-bit counter TOPn1 pin output Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1. 2. Clear this bit to 0 when the TOPn0 pin is not used in the PWM output mode. Preliminary User's Manual U17718EJ1V0UD 229 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-26. Register Setting in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the PWM output mode. 2. n = 0 to 3 230 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Operation flow in PWM output mode Figure 6-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D10 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D11 D01 D11 D10 D01 D00 <1> <2> <3> <4> <5> Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 231 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register m is transferred to the CCRm buffer register. START Setting of TPnCCR1 register Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register Initial setting of these registers is performed before setting the TPnCE bit to 1. <4> TPnCCR0, TPnCCR1 register setting change flow The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting is enabled (TPnCE bit = 1). TPnCE bit = 1 Setting of TPnCCR0 register When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. Setting of TPnCCR1 register <2> TPnCCR0, TPnCCR1 register setting change flow <5> Count operation stop flow Setting of TPnCCR0 register TPnCCR1 write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. TPnCE bit = 0 Counting is stopped. Setting of TPnCCR1 register STOP Remark n = 0 to 3 m = 0, 1 232 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected. FFFFH D01 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register TPnCCR1 register CCR1 buffer register TOPn1 pin output INTTPnCC0 signal D00 D00 D10 D10 D11 D11 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 To transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level to the TPnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write the same value to the TPnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has to be set. After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts with writing the TPnCCRm register. Remark n = 0 to 3, m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 233 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock 16-bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output D00 0000H D00 0000H D00 0000H FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 Remark n = 0 to 3 To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register. If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output D00 D00 + 1 D00 D00 + 1 D00 D00 + 1 FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 Remark n = 0 to 3 234 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter TPnCCR1 register TOPn1 pin output INTTPnCC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2 Remark n = 0 to 3 Usually, the INTTPnCC1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TPnCCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOPn1 pin. Preliminary User's Manual U17718EJ1V0UD 235 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits. Figure 6-28. Configuration in Free-Running Timer Mode TPnCCR1 register (compare) Output controller TOPn1 pin output TPnCCR0 register (capture) Output controller TOPn0 pin output TPnCCS0, TPnCCS1 bits (capture/compare selection) Internal count clock TIPn0 pin (external event count input/ capture trigger input) Edge detector Count clock selection 16-bit counter INTTPnOV signal TPnCE bit Edge detector TPnCCR0 register (capture) 0 1 0 INTTPnCC1 signal INTTPnCC0 signal 1 TIPn1 pin (capture trigger input) Edge detector TPnCCR1 register (compare) Remark n = 0 to 3 m = 0, 1 236 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TPnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Figure 6-29. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH D00 16-bit counter D10 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D00 D01 D10 D11 D00 D01 D11 D01 D11 Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 237 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 6-30. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH D10 D00 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register INTTPnCC0 signal TIPn1 pin input TPnCCR1 register INTTPnCC1 signal INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D12 D13 D00 D01 D02 D03 D01 D02 D03 D11 D12 D13 Remark n = 0 to 3 238 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0 0/1 0 0 TPnMD2 TPnMD1 TPnMD0 1 0 1 1, 0, 1: Free-running mode 0: Operate with count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count on external event count input signal (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level with operation of TOPn0 pin disabled 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting of output level with operation of TOPn1 pin disabled 0: Low level 1: High level Preliminary User's Manual U17718EJ1V0UD 239 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIOC1 0 0 0 0 0/1 TPnIS2 0/1 TPnIS1 0/1 TPnIS0 0/1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input (e) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (f) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOPT0 0 0 0/1 0/1 0 0 0 TPnOVF 0/1 Overflow flag Specifies if TPnCCR0 register functions as capture or compare register Specifies if TPnCCR1 register functions as capture or compare register (g) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers function as capture registers or compare registers depending on the setting of the TPnOPT0.TPnCCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected. When the registers function as compare registers and when Dm is set to the TPnCCRm register, the INTTPnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOPnm pin is inverted. Remark n = 0 to 3 m = 0, 1 240 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 16-bit counter D10 0000H TPnCE bit TPnCCR0 register D00 Set value changed INTTPnCC0 signal TOPn0 pin output TPnCCR1 register D10 Set value changed INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit <1> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> <3> D11 D01 D10 D11 D00 D01 D11 D01 D11 Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 241 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnOPT0 register, TPnCCR0 register, TPnCCR1 register Initial setting of these registers is performed before setting the TPnCE bit to 1. TPnCE bit = 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). <2> Overflow flag clear flow Read TPnOPT0 register (check overflow flag). TPnOVF bit = 1 NO YES Execute instruction to clear TPnOVF bit (CLR TPnOVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TPnCE bit to 0. TPnCE bit = 0 STOP Remark n = 0 to 3 242 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) When using capture/compare register as capture register Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D00 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register INTTPnCC0 signal TIPn1 pin input TPnCCR1 register INTTPnCC1 signal INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> 0000 D10 D11 D12 0000 0000 D00 D01 D02 D03 0000 D01 D02 D03 D11 D12 <1> <3> Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 243 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC1 register, TPnOPT0 register Initial setting of these registers is performed before setting the TPnCE bit to 1. TPnCE bit = 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). <2> Overflow flag clear flow Read TPnOPT0 register (check overflow flag). TPnOVF bit = 1 NO YES Execute instruction to clear TPnOVF bit (CLR TPnOVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TPnCE bit to 0. TPnCE bit = 0 STOP Remark n = 0 to 3 244 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected. FFFFH D10 D00 16-bit counter D01 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn pin output D00 D01 D11 D02 D03 D12 D13 D04 D02 D03 D04 D05 Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output D10 D11 D12 D13 D14 Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TPnCCRm register must be re-set in the interrupt servicing that is executed when the INTTPnCCm signal is detected. The set value for re-setting the TPnCCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent time: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 245 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval. FFFFH D10 D00 16-bit counter D01 0000H TPnCE bit TIPn0 pin input TPnCCR0 register INTTPnCC0 signal 0000H D00 D11 D02 D03 D12 D13 D04 D01 D02 D03 D04 Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TIPn1 pin input TPnCCR1 register INTTPnCC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) 0000H D10 D11 D12 D13 INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TPnCCRm register in synchronization with the INTTPnCCm signal, and calculating the difference between the read value and the previously read value. Remark n = 0 to 3 m = 0, 1 246 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH D11 16-bit counter D00 0000H TPnCE bit TIPn0 pin input TPnCCR0 register TIPn1 pin input TPnCCR1 register INTTPnOV signal TPnOVF bit D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> Read the TPnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TPnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. Preliminary User's Manual U17718EJ1V0UD 247 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote TIPn0 pin input TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input TPnCCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> An overflow occurs. Set the TPnOVF0 and TPnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TPnCCR0 register. Read the TPnOVF0 flag. If the TPnOVF0 flag is 1, clear it to 0. Because the TPnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TPnCCR1 register. Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0 (the TPnOVF0 flag is cleared in <4>, and the TPnOVF1 flag remains 1). Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> 248 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote TIPn0 pin input TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input TPnCCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TPnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TPnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TPnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0. Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Preliminary User's Manual U17718EJ1V0UD 249 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter Dm1 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Dm0 Dm1 Dm0 The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TPnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. 250 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Example when capture trigger interval is long FFFFH 16-bit counter Dm1 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit Overflow counterNote 0H 1H 2H 0H Dm0 Dm1 Dm0 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TPnCCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Preliminary User's Manual U17718EJ1V0UD 251 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TPnOVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TPnOVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TPnOVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TPnOVF bit) H Read Write Remark n = 0 to 3 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. 252 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TPnCCRm register after a capture interrupt request signal (INTTPnCCm) occurs. Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify "No edge detected" by using the TPnIOC1 register for the unused pins. When an external clock is used as the count clock, measure the pulse width of the TIPn1 pin because the external clock is fixed to the TIPn0 pin. At this time, clear the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to 00 (capture trigger input (TIPn0 pin): No edge detected). Figure 6-34. Configuration in Pulse Width Measurement Mode Clear Internal count clock TIPn0 pin (external event count input/capture trigger input) Edge detector Count clock selection 16-bit counter INTTPnOV signal INTTPnCC0 signal TPnCE bit Edge detector TPnCCR0 register (capture) INTTPnCC1 signal TIPn1 pin (capture trigger input) Edge detector TPnCCR1 register (capture) Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 253 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnCCm signal INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction 0000H D0 D1 D2 D3 Remark n = 0 to 3 m = 0, 1 When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is later detected, the count value of the 16-bit counter is stored in the TPnCCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTPnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTPnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TPnOVF bit set (1) count + Captured value) x Count clock cycle Remark n = 0 to 3 m = 0, 1 254 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note Setting is invalid when the TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnSYE TPnCTL1 0 TPnEST TPnEEE 0 0/1 0 0 TPnMD2 TPnMD1 TPnMD0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count external event count input signal (c) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIOC1 0 0 0 0 0/1 TPnIS2 0/1 TPnIS1 0/1 TPnIS0 0/1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input Preliminary User's Manual U17718EJ1V0UD 255 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOPT0 0 0 0 0 0 0 0 TPnOVF 0/1 Overflow flag (f) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (g) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected. Remarks 1. TMPn I/O control register 0 (TPnIOC0) is not used in the pulse width measurement mode. 2. n = 0 to 3 m = 0, 1 256 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Operation flow in pulse width measurement mode Figure 6-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register INTTPnCC0 signal <1> <2> 0000H D0 D1 D2 0000H <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits), TPnCTL1 register, TPnIOC1 register, TPnIOC2 register, TPnOPT0 register Initial setting of these registers is performed before setting the TPnCE bit to 1. Set TPnCTL0 register (TPnCE bit = 1) The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. TPnCE bit = 0 STOP Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 257 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TPnOVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TPnOVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TPnOVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TPnOVF bit) H Read Write Remark n = 0 to 3 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. 258 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.5.8 Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 6-4. Timer Output Control in Each Mode Operation Mode Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode TOPn1 Pin Square wave output Square wave output External trigger pulse output One-shot pulse output PWM output Square wave output (only when compare function is used) - - Square wave output TOPn0 Pin Remark n = 0 to 3 Table 6-5. Truth Table of TOPn0 and TOPn1 Pins Under Control of Timer Output Control Bits TPnIOC0.TPnOLm Bit 0 TPnIOC0.TPnOEm Bit 0 1 TPnCTL0.TPnCE Bit x 0 1 x 0 1 Level of TOPnm Pin Low-level output Low-level output Low level immediately before counting, high level after counting is started 1 0 1 High-level output High-level output High level immediately before counting, low level after counting is started Remark n = 0 to 3 m = 0, 1 Preliminary User's Manual U17718EJ1V0UD 259 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.6 Timer Tuned Operation Function Timer P and timer Q have a timer tuned operation function. The timers that can be synchronized are listed in Table 6-6. Table 6-6. Tuned Operation Mode of Timers Master Timer TMP0 TMP2 TMP1 TMP3 Slave Timer - TMQ0 Cautions 1. The tuned operation mode is enabled or disabled by the TPmCTL1.TPmSYE and TQ0CTL1.TQ0SYE bits. For TMP2, either or both TMP3 and TMQ0 can be specified as slaves. 2. Set the tuned operation mode using the following procedure. <1> Set the TPmCTL1.TPmSYE and TQ0CTL1.TQ0SYE bits of the slave timer to enable the tuned operation. Set the TPmCTL1.TPmMD2 to TPmCTL1.TPmMD0 and TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits of the slave timer to the free-running mode. <2> Set the timer mode by using the TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits. At this time, do not set the TPnCTL1.TPnSYE bit of the master timer. <3> Set the compare register value of the master and slave timers. <4> Set the TPmCTL0.TPmCE and TQ0CTL0.TQ0CE bits of the slave timer to enable operation on the internal operating clock. <5> Set the TPnCTL0.TPnCE bit of the master timer to enable operation on the internal operating clock. Remark m = 1, 3 n = 0, 2 Tables 6-7 and 6-8 show the timer modes that can be used in the tuned operation mode (: Settable, x: Not settable). Table 6-7. Timer Modes Usable in Tuned Operation Mode Master Timer TMP0 TMP2 Free-Running Mode PWM Mode Triangular Wave PWM Mode x x 260 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Table 6-8. Timer Output Functions Tuned Channel Ch0 TMP0 (master) TMP1 (slave) Ch1 TMP2 (master) TMP3 (slave) TMQ0 (slave) TOP00 TOP01 TOP10 TOP11 TOP20 TOP21 TOP30 TOP31 TOQ00 TOQ01 to TOQ03 Timer Pin Free-Running Mode Tuning OFF PPG PPG PGP PPG PPG PPG PPG PPG PPG PPG Tuning ON PWM Mode Tuning OFF Toggle PWM Toggle PWM Toggle PWM Toggle PWM Toggle PWM Tuning ON PWM PWM PWM PWM Triangular Wave PWM Mode Tuning OFF N/A N/A N/A N/A N/A N/A N/A N/A Toggle Triangular wave PWM Tuning ON N/A N/A Remark The timing of transmitting data from the compare register of the master timer to the compare register of the slave timer is as follows. PPG: CPU write timing and TOQ00 (n = 0 to 3) Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0 Preliminary User's Manual U17718EJ1V0UD 261 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-38. Tuned Operation Image (TMP2, TMP3, TMQ0) Unit operation Tuned operation TMP2 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) TMP2 (master) + TMP3 (slave) + TMQ0 (slave) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) TMP3 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP31 (PWM output) 16-bit capture/compare 16-bit capture/compare TOP30 (PWM output) TOP31 (PWM output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOQ00 (PWM output) TOQ01 (PWM output) TOQ02 (PWM output) TOQ03 (PWM output) TMQ0 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOQ01 (PWM output) TOQ02 (PWM output) TOQ03 (PWM output) Five PWM outputs are available when PWM is operated as a single unit. Seven PWM outputs are available when PWM is operated in tuned operation mode. 262 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com Figure 6-39. Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0) FFFFH D60 TMP2 16-bit counter D10 0000H TP2CE TP3CE TQ0CE TP2CCR0 TP2CCR1 TP3CCR0 TP3CCR1 TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 INTTP2CC0 match interrupt INTTP2CC1 match interrupt INTTP3CC0 match interrupt INTTP3CC1 match interrupt INTTQ0CC0 match interrupt INTTQ0CC1 match interrupt INTTQ0CC2 match interrupt INTTQ0CC3 match interrupt TOP20 TOP21 TOP30 TOP31 TOQ00 TOQ01 TOQ02 TOQ03 D40 D30 D20 D50 D70 D00 D60 D40 D30 D10 D20 D50 D70 D00 D00 D10 D20 D30 D40 D50 D60 D70 Preliminary User's Manual U17718EJ1V0UD 263 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.7 Selector Function In the V850ES/HG2, the alternate-function pins of port and peripheral I/O (TMP, TMM0, or UARTA) can be used to select the capture trigger input of TMP. By using this function, the following is possible. * The TIP10 and TIP11 input signals of TMP1 can be selected from the port/timer alternate-function pins (TIP10 and TIP11 pins) and the UARTA reception alternate-function pins (RXDA0 and RXDA1). When the RXDA0 or RXDA1 signal of UARTA0 or UARTA1 is selected, the baud rate error of the UARTA LIN reception transfer can be calculated. * The TIP01 input signal of TMP0 can be selected from the port/timer alternate-function pin (TIP01 pin) and the INTTM0EQ0 signal of TMM0. Cautions 1. When using the selector function, set the capture trigger input of TMP before connecting the timer. 2. When setting the selector function, first disable the peripheral I/O to be connected (TMP, TMM0, or UARTA). The capture input for the selector function is specified by the following register. 264 Preliminary User's Manual U17718EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP0, TMP1, and TMP3. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF308H SELCNT0 0 0 ISEL05 ISEL04 ISEL03 ISEL02 0 0 ISEL05 0 1 TIP30 pin input RXDA2 pin input Selection of TIP30 input signal (TMP3) ISEL04 0 1 TIP11 pin input RXDA1 pin input Selection of TIP11 input signal (TMP1) ISEL03 0 1 TIP10 pin input RXDA0 pin input Selection of TIP10 input signal (TMP1) ISEL02Note 0 1 TIP01 pin input Selection of TIP01 input signal (TMP0) INTTM0EQ0 interrupt of TMM0 Note Use the INTTM0EQ0 interrupt signal as the TIP01 input signal under the following condition. TMM operation clock TMP operation clock x 4 Caution To set the ISEL02 to ISEL05 bits to 1, set the corresponding pin in the capture input mode. Preliminary User's Manual U17718EJ1V0UD 265 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) www..com 6.8 Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input immediately after the TPnCE bit is set to 1. (a) Free-running timer mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TPnCCR0 register 0000H FFFFH 0001H TPnCE bit TIPn0 pin input Capture trigger input Capture trigger input (b) Pulse width measurement mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TPnCCR0 register 0000H FFFFH 0002H TPnCE bit TIPn0 pin input Capture trigger input Capture trigger input 266 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/HG2 incorporates TMQ0 and TMQ1. 7.1 Overview An outline of TMQn is shown below. * Clock selection: 8 ways * Capture/trigger input pins: 4 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 4 * Capture/compare match interrupt request signals: 4 * Timer output pins: 4 Remark n = 0, 1 7.2 Functions TMQn has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement * Triangular wave PWM output * Timer tuned operation function Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.3 Configuration TMQ0 and TMQ1 include the following hardware. Table 7-1. Configuration of TMQ0 and TMQ1 Item Timer register Registers 16-bit counter TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) TMQn counter read buffer register (TQnCNT) CCR0 to CCR3 buffer registers Timer inputs Timer outputs Control registers Note 2 Note 1 Configuration 4 (TIQn0 to TIQn3 pins) 4 (TOQn0 to TOQn3 pins) TMQn control registers 0, 1 (TQnCTL0, TQnCTL1) TMQn I/O control registers 0 to 2 (TQnIOC0 to TQnIOC2) TMQn option register 0 (TQnOPT0) Notes 1. The TIQn0 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. When using the functions of the TIQn0 to TIQn3 and TOQn0 to TOQn3 pins, see Table 4-19 Using Port Pin as Alternate-Function Pin. Figure 7-1. Block Diagram of TMQ0 and TMQ1 Internal bus CCR0 buffer register CCR1 buffer register Output controller CCR2 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TQnCNT Selector Selector 16-bit counter Clear INTTQnOV TOQn0 TOQn1 TOQn2 TOQn3 INTTQnCC0 INTTQnCC1 INTTQnCC2 INTTQnCC3 Edge detector TIQn0 TIQn1 TIQn2 TIQn3 TQnCCR0 TQnCCR1 buffer register CCR3 buffer register TQnCCR2 TQnCCR3 Internal bus Remarks 1. fXX: Main clock frequency 2. n = 0, 1 268 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TQnCNT register. When the TQnCTL0.TQnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TQnCNT register is read at this time, 0000H is read. Reset sets the TQnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR0 register is used as a compare register, the value written to the TQnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQnCC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TQnCCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR1 register is used as a compare register, the value written to the TQnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TQnCCR1 register is cleared to 0000H. (4) CCR2 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR2 register is used as a compare register, the value written to the TQnCCR2 register is transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated. The CCR2 buffer register cannot be read or written directly. The CCR2 buffer register is cleared to 0000H after reset, as the TQnCCR2 register is cleared to 0000H. (5) CCR3 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR3 register is used as a compare register, the value written to the TQnCCR3 register is transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated. The CCR3 buffer register cannot be read or written directly. The CCR3 buffer register is cleared to 0000H after reset, as the TQnCCR3 register is cleared to 0000H. (6) Edge detector This circuit detects the valid edges input to the TIQn0 and TIQn3 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TQnIOC1 and TQnIOC2 registers. (7) Output controller This circuit controls the output of the TOQn0 to TOQn3 pins. The output controller is controlled by the TQnIOC0 register. Preliminary User's Manual U17718EJ1V0UD 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. 270 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.4 Registers The registers that control TMQn are as follows. * TMQn control register 0 (TQnCTL0) * TMQn control register 1 (TQnCTL1) * TMQn I/O control register 0 (TQnIOC0) * TMQn I/O control register 1 (TQnIOC1) * TMQn I/O control register 2 (TQnIOC2) * TMQn option register 0 (TQnOPT0) * TMQn capture/compare register 0 (TQnCCR0) * TMQn capture/compare register 1 (TQnCCR1) * TMQn capture/compare register 2 (TQnCCR2) * TMQn capture/compare register 3 (TQnCCR3) * TMQn counter read buffer register (TQnCNT) Remark When using the functions of the TIQn0 to TIQn3 and TOQn0 to TOQn3 pins, see Table 4-19 Using Port Pin as Alternate-Function Pin. Preliminary User's Manual U17718EJ1V0UD 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) TMQn control register 0 (TQnCTL0) The TQnCTL0 register is an 8-bit register that controls the operation of TMQn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQnCTL0 register by software. After reset: 00H 7 R/W 6 0 Address: 5 0 TQ0CTL0 FFFFF540H, TQ1CTL0 FFFFF610H 4 0 3 0 2 1 0 TQnCTL0 (n = 0, 1) TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnCE 0 1 TMQn operation control TMQn operation disabled (TMQn reset asynchronouslyNote). TMQn operation enabled. TMQn operation started. TQnCKS2 TQnCKS1 TQnCKS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Internal count clock selection Note TQnOPT0.TQnOVF bit, 16-bit counter, timer output (TOQn0 to TOQn3 pins) Cautions 1. Set the TQnCKS2 to TQnCKS0 bits when the TQnCE bit = 0. When the value of the TQnCE bit is changed from 0 to 1, the TQnCKS2 to TQnCKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency 272 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) TMQn control register 1 (TQnCTL1) The TQnCTL1 register is an 8-bit register that controls the operation of TMQn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H 7 R/W 6 Address: TQ0CTL1 FFFFF541H, TQ1CTL1 FFFFF611H 5 4 0 3 0 2 1 0 TQnCTL1 (n = 0, 1) TQnSYE TQnEST TQnEEE TQnMD2 TQnMD1 TQnMD0 TQnSYE 0 1 Tuned operation mode enable control Independent operation mode (asynchronous operation mode) Tuned operation mode (specification of slave operation) In this mode, timer P can operate in synchronization with a master timer. Master timer TMP2 TMP3 Slave timer TMQ0 For the tuned operation mode, see 7.6 Timer Tuned Operation Function. TQnEST 0 1 Software trigger control - Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TQnEST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TQnEST bit as the trigger. Cautions 1. The TQnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. Be sure to clear bits 3 and 4 to "0". Preliminary User's Manual U17718EJ1V0UD 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2/2) TQnEEE 0 Count clock selection Disable operation with external event count input. (Perform counting with the count clock selected by the TQnCTL0.TQnCK0 to TQnCK2 bits.) Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.) 1 The TQnEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TQnMD2 TQnMD1 TQnMD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timer mode selection Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Triangular wave PWM mode Cautions 1. External event count input is selected in the external event count mode regardless of the value of the TQnEEE bit. 2. Set the TQnEEE and TQnMD2 to TQnMD0 bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TQnCE bit = 1. If rewriting was mistakenly performed, clear the TQnCE bit to 0 and then set the bits again. 274 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (3) TMQn I/O control register 0 (TQnIOC0) The TQnIOC0 register is an 8-bit register that controls the timer output (TOQn0 to TOQn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W 6 Address: 5 TQ0IOC0 FFFFF542H, TQ1IOC0 FFFFF612H 4 3 2 1 0 TQnIOC0 (n = 0, 1) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnOLm 0 1 TOQnm pin output level setting (m = 0 to 3) TOQnm pin output inversion disabled TOQnm pin output inversion enabled TQnOEm 0 TOQnm pin output setting (m = 0 to 3) Timer output disabled * When TQnOLm bit = 0: Low level is output from the TOQnm pin * When TQnOLm bit = 1: High level is output from the TOQnm pin Timer output enabled (A square wave is output from the TOQnm pin). 1 Cautions 1. Rewrite the TQnOLm and TQnOEm bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) again. 2. Even if the TQnOLm bit is manipulated when the TQnCE and TQnOEm bits are 0, the TOQnm pin output level varies. Remark m = 0 to 3 If rewriting was mistakenly performed, clear the TQnCE bit to 0 and then set the bits Preliminary User's Manual U17718EJ1V0UD 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (4) TMQn I/O control register 1 (TQnIOC1) The TQnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQn0 to TIQn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W 6 TQnIS6 Address: 5 TQnIS5 TQ0IOC1 FFFFF543H, TQ1IOC1 FFFFF613H 4 TQnIS4 3 TQnIS3 2 TQnIS2 1 TQnIS1 0 TQnIOC1 (n = 0, 1) TQnIS7 TQnIS0 TQnIS7 0 0 1 1 TQnIS6 0 1 0 1 Capture trigger input signal (TIQn3 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TQnIS5 0 0 1 1 TQnIS4 0 1 0 1 Capture trigger input signal (TIQn2 pin) valid edge detection No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TQnIS3 0 0 1 1 TQnIS2 0 1 0 1 Capture trigger input signal (TIQn1 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TQnIS1 0 0 1 1 TQnIS0 0 1 0 1 Capture trigger input signal (TIQn0 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TQnIS7 to TQnIS0 bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) again. 2. The TQnIS7 to TQnIS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. If rewriting was mistakenly performed, clear the TQnCE bit to 0 and then set the bits 276 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (5) TMQn I/O control register 2 (TQnIOC2) The TQnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQn0 pin) and external trigger input signal (TIQn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W 6 0 Address: 5 0 TQ0IOC2 FFFFF544H, TQ1IOC2 FFFFF614H 4 0 3 2 1 0 TQnIOC2 (n = 0, 1) 0 TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnEES1 TQnEES0 External event count input signal (TIQn0 pin) valid edge setting 0 0 1 1 0 1 0 1 No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges TQnETS1 TQnETS0 0 0 1 1 0 1 0 1 External trigger input signal (TIQn0 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TQnEES1, TQnEES0, TQnETS1, and TQnETS0 bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) If rewriting was mistakenly performed, clear the TQnCE bit to 0 and then set the bits again. 2. The TQnEES1 and TQnEES0 bits are valid only when the TQnCTL1.TQnEEE bit = 1 or when the external event count mode (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 bits = 001) has been set. 3. The TQnETS1 and TQnETS0 bits are valid only when the external trigger pulse output mode (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 bits = 010) or the one-shot pulse output mode (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 = 011) is set. Preliminary User's Manual U17718EJ1V0UD 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (6) TMQn option register 0 (TQnOPT0) The TQnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W 6 Address: 5 TQ0OPT0 FFFFF545H, TQ1OPT0 FFFFF615H 4 3 0 2 0 1 0 0 TQnOPT0 (n = 0, 1) TQnCCS3 TQnCCS2 TQnCCS1 TQnCCS0 TQnOVF TQnCCSm 0 1 TQnCCRm register capture/compare selection Compare register selected Capture register selected The TQnCCSm bit setting is valid only in the free-running timer mode. TQnOVF Set (1) Reset (0) TMQn overflow detection Overflow occurred TQnOVF bit 0 written or TQnCTL0.TQnCE bit = 0 * The TQnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTQnOV) is generated at the same time that the TQnOVF bit is set to 1. The INTTQnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TQnOVF bit is not cleared even when the TQnOVF bit or the TQnOPT0 register are read when the TQnOVF bit = 1. * The TQnOVF bit can be both read and written, but the TQnOVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMQn. Cautions 1. Rewrite the TQnCCS3 to TQnCCS0 bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) again. 2. Be sure to clear bits 1 to 3 to "0". Remark m = 0 to 3 If rewriting was mistakenly performed, clear the TQnCE bit to 0 and then set the bits 278 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (7) TMQn capture/compare register 0 (TQnCCR0) The TQnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQnOPT0.TQnCCS0 bit. as a compare register. The TQnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQnCCR0 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. In the pulse width measurement mode, the TQnCCR0 register can be used only as a capture register. In any other mode, this register can be used only * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 9 TQ0CCR0 FFFFF546H, TQ1CCR0 FFFFF616H 8 7 6 5 4 3 2 1 0 TQnCCR0 (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (a) Function as compare register The TQnCCR0 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQnCC0) is generated. If TOQn0 pin output is enabled at this time, the output of the TOQn0 pin is inverted. When the TQnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, or triangular wave PWM mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TQnCCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQnCCR0 register if the valid edge of the capture trigger input pin (TIQn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQn0 pin) is detected. Even if the capture operation and reading the TQnCCR0 register conflict, the correct value of the TQnCCR0 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Triangular wave PWM mode Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register Compare register Batch write How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 280 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (8) TMQn capture/compare register 1 (TQnCCR1) The TQnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQnOPT0.TQnCCS1 bit. as a compare register. The TQnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQnCCR1 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. In the pulse width measurement mode, the TQnCCR1 register can be used only as a capture register. In any other mode, this register can be used only * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 9 TQ0CCR1 FFFFF548H, TQ1CCR1 FFFFF618H 8 7 6 5 4 3 2 1 0 TQnCCR1 (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (a) Function as compare register The TQnCCR1 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated. If TOQn1 pin output is enabled at this time, the output of the TOQn1 pin is inverted. (b) Function as capture register When the TQnCCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQnCCR1 register if the valid edge of the capture trigger input pin (TIQn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQn1 pin) is detected. Even if the capture operation and reading the TQnCCR1 register conflict, the correct value of the TQnCCR1 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Triangular wave PWM mode Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register Compare register Batch write How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 282 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (9) TMQn capture/compare register 2 (TQnCCR2) The TQnCCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQnOPT0.TQnCCS2 bit. as a compare register. The TQnCCR2 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQnCCR2 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. In the pulse width measurement mode, the TQnCCR2 register can be used only as a capture register. In any other mode, this register can be used only * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 9 TQ0CCR2 FFFFF54AH, TQ1CCR2 FFFFF61AH 8 7 6 5 4 3 2 1 0 TQnCCR2 (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (a) Function as compare register The TQnCCR2 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated. If TOQn2 pin output is enabled at this time, the output of the TOQn2 pin is inverted. (b) Function as capture register When the TQnCCR2 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQnCCR2 register if the valid edge of the capture trigger input pin (TIQn2 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQnCCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQn2 pin) is detected. Even if the capture operation and reading the TQnCCR2 register conflict, the correct value of the TQnCCR2 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Triangular wave PWM mode Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register Compare register Batch write How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 284 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (10) TMQn capture/compare register 3 (TQnCCR3) The TQnCCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQnOPT0.TQnCCS3 bit. as a compare register. The TQnCCR3 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQnCCR3 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. In the pulse width measurement mode, the TQnCCR3 register can be used only as a capture register. In any other mode, this register can be used only * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 9 TQ0CCR3 FFFFF54CH, TQ1CCR3 FFFFF61CH 8 7 6 5 4 3 2 1 0 TQnCCR3 (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 285 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (a) Function as compare register The TQnCCR3 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated. If TOQn3 pin output is enabled at this time, the output of the TOQn3 pin is inverted. (b) Function as capture register When the TQnCCR3 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQnCCR3 register if the valid edge of the capture trigger input pin (TIQn3 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQnCCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQn3 pin) is detected. Even if the capture operation and reading the TQnCCR3 register conflict, the correct value of the TQnCCR3 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Triangular wave PWM mode Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register Compare register Batch write How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 286 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (11) TMQn counter read buffer register (TQnCNT) The TQnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQnCTL0.TQnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TQnCNT register is cleared to 0000H when the TQnCE bit = 0. If the TQnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TQnCNT register is cleared to 0000H after reset, as the TQnCE bit is cleared to 0. Caution Accessing the TQnCNT register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R 13 12 Address: 11 10 TQ0CNT FFFFF54EH, TQ1CNT FFFFF61EH 9 8 7 6 5 4 3 2 1 0 TQnCNT (n = 0, 1) Preliminary User's Manual U17718EJ1V0UD 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (12) TIQnm pin noise elimination control register (QnmNFC) The QnmNFC register is an 8-bit register that sets the digital noise filter of the timer Q input pin for noise elimination. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: Q00NFC: FFFFFB50H (TIQ00 pin) Q01NFC: FFFFFB54H (TIQ01 pin) Q02NFC: FFFFFB58H (TIQ02 pin) Q03NFC: FFFFFB5CH (TIQ03 pin) Q10NFC: FFFFFB60H (TIQ10 pin) Q11NFC: FFFFFB64H (TIQ11 pin) Q12NFC: FFFFFB68H (TIQ12 pin) Q13NFC: FFFFFB6CH (TIQ13 pin) 5 0 4 0 3 0 2 NFC2 1 NFC1 0 NFC0 7 QnmNFC (n = 0, 1, m = 0 to 3) NFSTS 0 1 0 6 NFSTS Setting of number of times of sampling by digital noise filter 3 times 2 times NFC2 0 0 0 0 1 1 NFC1 0 0 1 1 0 0 Other than above NFC0 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/32 fXX/64 Setting prohibited Sampling clock Cautions 1. Be sure to clear bits 3 to 5 and 7 to "0". 2. A signal input to the timer input pin (TIQnm) before the QnmNFC register is set is output with digital noise eliminated. Therefore, set the sampling clock (NFC2 to NFC0) and the number of times of sampling (NFSTS) by using the QnmNFC register, wait for initialization time = (Sampling clock) x (Number of times of sampling), and enable the timer operation. Remark The width of the noise that can be accurately eliminated is (Sampling clock) x (Number of times of sampling - 1). Even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. 288 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5 Operation TMQn can perform the following operations. Operation TQnCTL1.TQnEST Bit TIQn0 Pin Capture/Compare Register Setting Compare only Compare only Compare only Compare only Compare only Switching enabled Capture only Compare only Compare Register Write Anytime write Anytime write Batch write Anytime write Batch write Anytime write Not applicable Batch write (Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode Note 1 Invalid Invalid Note 2 Invalid Invalid Valid Valid Invalid Invalid Invalid Invalid External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Triangular wave PWM mode Note 2 Valid Valid Invalid Invalid Note 2 Invalid Invalid Notes 1. To use the external event count mode, specify that the valid edge of the TIQn0 pin capture trigger input is not detected (by clearing the TQnIOC1.TQnIS1 and TQnIOC1.TQnIS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TQnCTL1.TQnEEE bit to 0). Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated at the specified interval if the TQnCTL0.TQnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOQn0 pin. Usually, the TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. Figure 7-2. Configuration of Interval Timer Clear Count clock selection 16-bit counter Match signal Output controller TOQn0 pin INTTQnCC0 signal TQnCE bit CCR0 buffer register TQnCCR0 register Remark n = 0, 1 Figure 7-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register TOQn0 pin output INTTQnCC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) D0 D0 D0 D0 D0 Remark n = 0, 1 290 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQn0 pin is inverted. Additionally, the set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOQn0 pin is inverted, and a compare match interrupt request signal (INTTQnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TQnCCR0 register + 1) x Count clock cycle Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0 0/1Note 0 0 TQnMD2 TQnMD1 TQnMD0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by bits TQnCKS0 to TQnCKS2 1: Count with external event count input signal Note This bit can be set to 1 only when the interrupt request signals (INTTQnCC0 and INTTQnCCk) are masked by the interrupt mask flags (TQnCCMK0 to TQnCCMKk) and the timer output (TOQnk) is performed at the same time. However, the TQnCCR0 and TQnCCRk registers must be set to the same value (see 7.5.1 (2) (d) Operation of TQnCCR1 to TQnCCR3 registers) (k = 1 to 3). Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of output level with operation of TOQn0 pin disabled 0: Low level 1: High level 0: Disable TOQn1 pin output 1: Enable TOQn1 pin output Setting of output level with operation of TOQn1 pin disabled 0: Low level 1: High level 0: Disable TOQn2 pin output 1: Enable TOQn2 pin output Setting of output level with operation of TOQn2 pin disabled 0: Low level 1: High level 0: Disable TOQn3 pin output 1: Enable TOQn3 pin output Setting of output level with operation of TOQn3 pin disabled 0: Low level 1: High level (d) TMQn counter read buffer register (TQnCNT) By reading the TQnCNT register, the count value of the 16-bit counter can be read. (e) TMQn capture/compare register 0 (TQnCCR0) If the TQnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3) Usually, the TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. However, the set value of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers. The compare match interrupt request signals (INTTQnCCR1 to INTTQnCCR3) is generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers. Therefore, mask the interrupt request by using the corresponding interrupt mask flags (TQnCCMK1 to TQnCCMK3). Remarks 1. TMQn I/O control register 1 (TQnIOC1), TMQn I/O control register 2 (TQnIOC2), and TMQn option register 0 (TQnOPT0) are not used in the interval timer mode. 2. n = 0, 1 292 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register TOQn0 pin output INTTQnCC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnCCR0 register Initial setting of these registers is performed before setting the TQnCE bit to 1. TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TQnCE bit to 0. TQnCE bit = 0 STOP Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 293 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) Interval timer mode operation timing (a) Operation if TQnCCR0 register is set to 0000H If the TQnCCR0 register is set to 0000H, the INTTQnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOQn0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TQnCE bit TQnCCR0 register TOQn0 pin output INTTQnCC0 signal Interval time Count clock cycle Interval time Count clock cycle 0000H FFFFH 0000H 0000H 0000H 0000H Remark n = 0, 1 (b) Operation if TQnCCR0 register is set to FFFFH If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTQnCC0 signal is generated and the output of the TOQn0 pin is inverted. At this time, an overflow interrupt request signal (INTTQnOV) is not generated, nor is the overflow flag (TQnOPT0.TQnOVF bit) set to 1. FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register TOQn0 pin output INTTQnCC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle FFFFH Remark n = 0, 1 294 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (c) Notes on rewriting TQnCCR0 register To change the value of the TQnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TQnCE bit TQnCCR0 register TQnOL0 bit TOQn0 pin output INTTQnCC0 signal L D1 D2 D2 D1 D2 D2 Interval time (1) Interval time (NG) Interval time (2) Remarks 1. Interval time (1): Interval time (2): 2. n = 0, 1 (D1 + 1) x Count clock cycle (D2 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle If the value of the TQnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TQnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTQnCC0 signal is generated and the output of the TOQn0 pin is inverted. Therefore, the INTTQnCC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". Preliminary User's Manual U17718EJ1V0UD 295 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (d) Operation of TQnCCR1 to TQnCCR3 registers Figure 7-6. Configuration of TQnCCR1 to TQnCCR3 Registers TQnCCR1 register CCR1 buffer register Match signal Output controller TOQn1 pin INTTQnCC1 signal TQnCCR2 register CCR2 buffer register Match signal Output controller TOQn2 pin INTTQnCC2 signal TQnCCR3 register CCR3 buffer register Match signal Clear Count clock selection Output controller TOQn3 pin INTTQnCC3 signal 16-bit counter Match signal Output controller TOQn0 pin INTTQnCC0 signal TQnCE bit CCR0 buffer register TQnCCR0 register Remark n = 0, 1 296 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com If the set value of the TQnCCRk register is less than the set value of the TQnCCR0 register, the INTTQnCCk signal is generated once per cycle. At the same time, the output of the TOPQnk pin is inverted. The TOQnk pin outputs a square wave with the same cycle as that output by the TOQn0 pin. Remark k = 1 to 3, n = 0, 1 Figure 7-7. Timing Chart When D01 Dk1 FFFFH 16-bit counter 0000H TQnCE bit D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 TQnCCR0 register D01 TOQn0 pin output INTTQnCC0 signal TQnCCR1 register D11 TOQn1 pin output INTTQnCC1 signal TQnCCR2 register D21 TOQn2 pin output INTTQnCC2 signal TQnCCR3 register D31 TOQn3 pin output INTTQnCC3 signal Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com If the set value of the TQnCCRk register is greater than the set value of the TQnCCR0 register, the count value of the 16-bit counter does not match the value of the TQnCCRk register. INTTQnCCk signal is not generated, nor is the output of the TOQnk pin changed. Remark k = 1 to 3, n = 0, 1 Figure 7-8. Timing Chart When D01 < Dk1 Consequently, the FFFFH 16-bit counter 0000H TQnCE bit D01 D01 D01 D01 TQnCCR0 register D01 TOQn0 pin output INTTQnCC0 signal TQnCCR1 register D11 TOQn1 pin output INTTQnCC1 signal L TQnCCR2 register D21 TOQn2 pin output INTTQnCC2 signal L TQnCCR3 register D31 TOQn3 pin output INTTQnCC3 signal L Remark n = 0, 1 298 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.2 External event count mode (TQnMD2 to TQnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TQnCTL0.TQnCE bit is set to 1, and an interrupt request signal (INTTQnCC0) is generated each time the specified number of edges have been counted. The TOQn0 pin cannot be used. Usually, the TQnCCR1 to TQnCCR3 registers are not used in the external event count mode. Figure 7-9. Configuration in External Event Count Mode Clear TIQn0 pin (external event count input) Edge detector 16-bit counter Match signal INTTQnCC0 signal TQnCE bit CCR0 buffer register TQnCCR0 register Remark n = 0, 1 Figure 7-10. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal External event count interval (D0 + 1) External event count interval (D0 + 1) External event count interval (D0 + 1) D0 D0 D0 D0 16-bit counter External event count input (TIQn0 pin input) TQnCCR0 register NTTQnCC0 signal D0 - 1 D0 0000 0001 D0 Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTQnCC0) is generated. The INTTQnCC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TQnCCR0 register + 1) times. Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0 0 0 0: Stop counting 1: Enable counting (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0 0 0 0 TQnMD2 TQnMD1 TQnMD0 0 0 1 0, 0, 1: External event count mode (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0 0 0 0 0 0 0 0 0: Disable TOQn0 pin output 0: Disable TOQn1 pin output 0: Disable TOQn2 pin output 0: Disable TOQn3 pin output (d) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input Remark n = 0, 1 300 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMQn counter read buffer register (TQnCNT) The count value of the 16-bit counter can be read by reading the TQnCNT register. (f) TMQn capture/compare register 0 (TQnCCR0) If D0 is set to the TQnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTQnCC0) is generated when the number of external event counts reaches (D0 + 1). (g) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3) Usually, the TQnCCR1 to TQnCCR3 registers are not used in the external event count mode. However, the set value of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTQnCC1 to INTTQnCC3) are generated. Therefore, mask the interrupt signal by using the interrupt mask flags (TQnCCMK1 to TQnCCMK3). Remarks 1. The TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not used in the external event count mode. 2. n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnIOC2 register, TQnCCR0 register Initial setting of these registers is performed before setting the TQnCE bit to 1. TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TQnCE bit to 0. TQnCE bit = 0 STOP Remark n = 0, 1 302 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TQnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 bits = 000, TQnCTL1.TQnEEE bit = 1). (a) Operation if TQnCCR0 register is set to FFFFH If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. TQnOPT0.TQnOVF bit is not set. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTQnCC0 signal is generated. At this time, the FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal External event count signal interval External event count signal interval External event count signal interval FFFFH Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) Notes on rewriting the TQnCCR0 register To change the value of the TQnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal D1 D2 D2 D1 D2 D2 External event count signal interval (1) (D1 + 1) External event count signal interval (NG) (10000H + D2 + 1) External event count signal interval (2) (D2 + 1) Remark n = 0, 1 If the value of the TQnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TQnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTQnCC0 signal is generated. Therefore, the INTTQnCC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". 304 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (c) Operation of TQnCCR1 to TQnCCR3 registers Figure 7-13. Configuration of TQnCCR1 to TQnCCR3 Registers TQnCCR1 register CCR1 buffer register Match signal INTTQnCC1 signal TQnCCR2 register CCR2 buffer register Match signal INTTQnCC2 signal TQnCCR3 register CCR3 buffer register Match signal Clear Edge detector INTTQnCC3 signal TIQn0 pin 16-bit counter Match signal INTTQnCC0 signal TQnCE bit CCR0 buffer register TQnCCR0 register Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com If the set value of the TQnCCRk register is smaller than the set value of the TQnCCR0 register, the INTTQnCCk signal is generated once per cycle. Remark k = 1 to 3 n = 0, 1 Figure 7-14. Timing Chart When D01 Dk1 FFFFH 16-bit counter 0000H TQnCE bit D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 TQnCCR0 register D01 INTTQnCC0 signal TQnCCR1 register D11 INTTQnCC1 signal TQnCCR2 register D21 INTTQnCC2 signal TQnCCR3 register D31 INTTQnCC3 signal Remark n = 0, 1 306 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com If the set value of the TQnCCRk register is greater than the set value of the TQnCCR0 register, the INTTQnCCk signal is not generated because the count value of the 16-bit counter and the value of the TQnCCRk register do not match. Remark k = 1 to 3, n = 0, 1 Figure 7-15. Timing Chart When D01 < Dk1 FFFFH 16-bit counter 0000H TQnCE bit D01 D01 D01 D01 TQnCCR0 register D01 INTTQnCC0 signal TQnCCR1 register D11 INTTQnCC1 signal L TQnCCR2 register D21 INTTQnCC2 signal L TQnCCR3 register D31 INTTQnCC3 signal L Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 307 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.3 External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQnCTL0.TQnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform from the TOQn1 to TOQn3 pins. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOQn0 pin. Figure 7-16. Configuration in External Trigger Pulse Output Mode TQnCCR1 register Transfer CCR1 buffer register Match signal Output S controller R (RS-FF) TOQn1 pin INTTQnCC1 signal TQnCCR2 register Transfer CCR2 buffer register Match signal S Output R controller TOQn2 pin INTTQnCC2 signal TQnCCR3 register TIQn0 pin Edge detector Transfer CCR3 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Output controller Output S controller R (RS-FF) TOQn3 pin INTTQnCC3 signal 16-bit counter Match signal TOQn0 pin INTTQnCC0 signal TQnCE bit CCR0 buffer register Transfer TQnCCR0 register Remark n = 0, 1 308 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH D3 16-bit counter D1 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register D2 D0 D2 D1 D3 D0 D2 D1 D1 D3 D0 D2 D1 D3 D0 D0 INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCR1 register D1 INTTQnCC1 signal TOQn1 pin output Active level width (D1) TQnCCR2 register Active level width (D1) Active level Active level width width (D1) (D1) D2 Active level width (D1) INTTQnCC2 signal TOQn2 pin output Active level width (D2) TQnCCR3 register Active level width (D2) D3 Active level width (D2) INTTQnCC3 signal TOQn3 pin output Active level width (D3) Active level width (D3) Active level width (D3) Wait Cycle (D0 + 1) for trigger Cycle (D0 + 1) Cycle (D0 + 1) Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 309 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 16-bit timer/event counter Q waits for a trigger when the TQnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQnk pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOQn0 pin is inverted. The TOQnk pin outputs a high-level regardless of the status (high/low) when a trigger is generated.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQnCCRk register) x Count clock cycle Cycle = (Set value of TQnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TQnCCRk register)/(Set value of TQnCCR0 register + 1) The compare match request signal (INTTQnCC0) is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTQnCCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The value set to the TQnCCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TQnCTL1.TQnEST bit) to 1 is used as the trigger. Remark k = 1 to 3, m = 0 to 3, n = 0, 1 Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1. Remark n = 0, 1 310 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0/1 0/1 0 0 TQnMD2 TQnMD1 TQnMD0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TQnCKS0 to TQnCKS2 bits 1: Count with external event input signal Generate software trigger when 1 is written (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of output level while operation of TOQn0 pin is disabled 0: Low level 1: High level 0: Disable TOQn1 pin output 1: Enable TOQn1 pin output Specification of active level of TOQn1 pin output 0: Active-high 1: Active-low 0: Disable TOQn2 pin output 1: Enable TOQn2 pin output Specification of active level of TOQn2 pin output 0: Active-high 1: Active-low 0: Disable TOQn3 pin output 1: Enable TOQn3 pin output Specification of active level of TOQn3 pin output 0: Active-high 1: Active-low * When TQnOLk bit = 0 16-bit counter TOQnk pin output * When TQnOLk bit = 1 16-bit counter TOQnk pin output Note Clear this bit to 0 when the TOQn0 pin is not used in the external trigger pulse output mode. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 311 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TMQn counter read buffer register (TQnCNT) The value of the 16-bit counter can be read by reading the TQnCNT register. (f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) If D0 is set to the TQnCCR0 register, D1 to the TQnCCR1 register, D2 to the TQnCCR2 register, and D3, to the TQnCCR3 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle TOQn1 pin PWM waveform active level width = D1 x Count clock cycle TOQn2 pin PWM waveform active level width = D2 x Count clock cycle TOQn3 pin PWM waveform active level width = D3 x Count clock cycle Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not used in the external trigger pulse output mode. 2. Updating TMQn capture/compare register 2 (TQnCCR2) and TMQn capture/compare register 3 (TQnCCR3) is validated by writing TMQn capture/compare register 1 (TQnCCR1). 3. n = 0, 1 312 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter D10 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register D00 D01 D00 D30 D20 D00 D31 D21 D11 D00 D00 D00 D00 D31 D31 D31 D21 D30 D21 D21 D11 D20 D11 D10 D10 CCR0 buffer register D00 D01 D00 INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCR1 register D10 D11 D11 D10 D10 D11 CCR1 buffer register D10 D11 D11 D10 D10 D11 INTTQnCC1 signal TOQn1 pin output D20 D21 D20 D21 TQnCCR2 register CCR2 buffer register D20 D21 D20 D21 INTTQnCC2 signal TOQn2 pin output TQnCCR3 register D30 D31 D30 D31 CCR3 buffer register D30 D31 D30 D31 INTTQnCC3 signal TOQn3 pin output <1> <2> <3> <4> <5> <6> <7> Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 313 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQnCCR1 to TQnCCR3 register setting change flow Writing of the TQnCCR1 register must be performed when the set duty factor is only changed after writing the TQnCCR2 and TQnCCR3 registers. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. START Setting of TQnCCR2, TQnCCR3 registers Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnIOC2 register, TQnCCR0 to TQnCCR3 registers Initial setting of these registers is performed before setting the TQnCE bit to 1. Setting of TQnCCR1 register TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting is enabled (TQnCE bit = 1). Trigger wait status <5> TQnCCR2, TQnCCR3 register setting change flow TQnCCR1 register writing of the same value is necessary only when the set duty factor of TOQn2 and TOQn3 pin outputs is changed. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR2, TQnCCR3 registers Setting of TQnCCR1 register <2> TQnCCR0 to TQnCCR3 register setting change flow Setting of TQnCCR0, TQnCCR2, and TQnCCR3 registers TQnCCR1 register Writing of the TQnCCR1 register must be performed after writing the TQnCCR0, TQnCCR2, and TQnCCR3 registers. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer registers. <6> TQnCCR1 register setting change flow Only writing of the TQnCCR1 register must be performed when the set duty factor is only changed. When counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR1 register <3> TQnCCR0 register setting change flow TQnCCR1 register writing of the same value is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR0 register <7> Count operation stop flow TQnCE bit = 0 Counting is stopped. Setting of TQnCCR1 register STOP Remark m = 0 to 3 n = 0, 1 314 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQnCCR1 register last. Rewrite the TQnCCRk register after writing the TQnCCR1 register after the INTTQnCC0 signal is detected. FFFFH 16-bit counter 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register CCR0 buffer register INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCR1 register CCR1 buffer register INTTQnCC1 signal TOQn1 pin output TQnCCR2 register CCR2 buffer register INTTQnCC2 signal TOQn2 pin output TQnCCR3 register CCR3 buffer register INTTQnCC3 signal TOQn3 pin output D30 D30 D20 D20 D21 D10 D10 D00 D00 D00 D00 D00 D31 D30 D30 D30 D21 D20 D20 D20 D11 D10 D10 D10 D01 D31 D21 D11 D01 D01 D01 D11 D11 D21 D31 D31 Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 315 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com In order to transfer data from the TQnCCRm register to the CCRm buffer register, the TQnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQnCCR0 register, set the active level width to the TQnCCR2 and TQnCCR3 registers, and then set an active level to the TQnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TQnCCR0 register, and then write the same value to the TQnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, first set an active level to the TQnCCR2 and TQnCCR3 registers and then set an active level to the TQnCCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOQn1 pin, only the TQnCCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOQn2 and TOQn3 pins, first set an active level width to the TQnCCR2 and TQnCCR3 registers, and then write the same value to the TQnCCR1 register. After data is written to the TQnCCR1 register, the value written to the TQnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TQnCCR0 to TQnCCR3 registers again after writing the TQnCCR1 register once, do so after the INTTQnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because timing of transferring data from the TQnCCRm register to the CCRm buffer register conflicts with writing the TQnCCRm register. Remark m = 0 to 3 n = 0, 1 316 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQnCCRk register to 0000H. If the set value of the TQnCCR0 register is FFFFH, the INTTQnCCk signal is generated periodically. Count clock 16-bit counter TQnCE bit TQnCCR0 register TQnCCRk register INTTQnCC0 signal INTTQnCCk signal TOQnk pin output L D0 0000H D0 0000H D0 0000H FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark k = 1 to 3 n = 0, 1 To output a 100% waveform, set a value of (set value of TQnCCR0 register + 1) to the TQnCCRk register. If the set value of the TQnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TQnCE bit TQnCCR0 register TQnCCRk register INTTQnCC0 signal INTTQnCCk signal TOQnk pin output D0 D0 + 1 D0 D0 + 1 D0 D0 + 1 FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark k = 1 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 317 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQnCCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQnk pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIQn0 pin input) CCRk buffer register INTTQnCCk signal TOQnk pin output FFFF 0000 Dk - 1 Dk 0000 Dk Shortened Remark k = 1 to 3 n = 0, 1 If the trigger is detected immediately before the INTTQnCCk signal is generated, the INTTQnCCk signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOQnk pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter External trigger input (TIQn0 pin input) CCRk buffer register INTTQnCCk signal TOQnk pin output FFFF 0000 Dk - 2 0000 0001 Dk - 1 Dk Dk Extended Remark k = 1 to 3 n = 0, 1 318 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQnk pin is extended by time from generation of the INTTQnCC0 signal to trigger detection. 16-bit counter External trigger input (TIQn0 pin input) CCR0 buffer register INTTQnCC0 signal TOQnk pin output FFFF 0000 D0 - 1 D0 0000 0000 D0 Extended Remark k = 1 to 3 n = 0, 1 If the trigger is detected immediately before the INTTQnCC0 signal is generated, the INTTQnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOQnk pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIQn0 pin input) CCR0 buffer register INTTQnCC0 signal TOQnk pin output FFFF 0000 D0 - 1 D0 0000 0001 D0 Shortened Remark k = 1 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 319 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (e) Generation timing of compare match interrupt request signal (INTTQnCCk) The timing of generation of the INTTQnCCk signal in the external trigger pulse output mode differs from the timing of other INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Count clock 16-bit counter CCRk buffer register TOQnk pin output INTTQnCCk signal Dk - 2 Dk - 1 Dk Dk Dk + 1 Dk + 2 Remark k = 1 to 3 n = 0, 1 Usually, the INTTQnCCk signal is generated in synchronization with the next count up after the count value of the 16-bit counter matches the value of the CCRk buffer register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOQnk pin. 320 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.4 One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQnCTL0.TQnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQn1 to TOQn3 pins. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOQn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 7-20. Configuration in One-Shot Pulse Output Mode TQnCCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOQn1 pin INTTQnCC1 signal TQnCCR2 register Transfer CCR2 buffer register Match signal Output S controller R (RS-FF) TOQn2 pin INTTQnCC2 signal TQnCCR3 register TIQn0 pin Edge detector Transfer CCR3 buffer register Software trigger generation Match signal Clear Count clock selection Count start control S Output controller R (RS-FF) S Output controller R (RS-FF) TOQn3 pin INTTQnCC3 signal 16-bit counter Match signal TOQn0 pin INTTQnCC0 signal TQnCE bit CCR0 buffer register Transfer TQnCCR0 register Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 321 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter D1 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register D3 D2 D0 D3 D2 D1 D0 D3 D2 D1 D0 D0 INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCR1 register D1 INTTQnCC1 signal TOQn1 pin output Active level width (D0 - D1 + 1) D2 Active level width (D0 - D1 + 1) Active level width (D0 - D1 + 1) Delay (D1) TQnCCR2 register Delay (D1) Delay (D1) INTTQnCC2 signal TOQn2 pin output Delay (D2) TQnCCR3 register Active level width (D0 - D2 + 1) D3 Delay (D2) Active level width (D0 - D2 + 1) Delay (D2) Active level width (D0 - D2 + 1) INTTQnCC3 signal TOQn3 pin output Delay (D3) Active level width (D0 - D3 + 1) Delay (D3) Active level width (D0 - D3 + 1) Delay (D3) Active level width (D0 - D3 + 1) Remark n = 0, 1 322 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQnk pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TQnCCRk register) x Count clock cycle Active level width = (Set value of TQnCCR0 register - Set value of TQnCCRk register + 1) x Count clock cycle The compare match interrupt request signal INTTQnCC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTQnCCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The valid edge of an external trigger input or setting the software trigger (TQnCTL1.TQnEST bit) to 1 is used as the trigger. Remark k = 1 to 3 n = 0, 1 Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0/1 0/1 0 0 TQnMD2 TQnMD1 TQnMD0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TQnCKS0 to TQnCKS2 bits 1: Count external event input signal Generate software trigger when 1 is written Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 323 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-22. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of output level while operation of TOQn0 pin is disabled 0: Low level 1: High level 0: Disable TOQn1 pin output 1: Enable TOQn1 pin output Specification of active level of TOQn1 pin output 0: Active-high 1: Active-low 0: Disable TOQn2 pin output 1: Enable TOQn2 pin output Specification of active level of TOQn2 pin output 0: Active-high 1: Active-low 0: Disable TOQn3 pin output 1: Enable TOQn3 pin output Specification of active level of TOQn3 pin output 0: Active-high 1: Active-low * When TQnOLk bit = 0 16-bit counter TOQnk pin output * When TQnOLk bit = 1 16-bit counter TOQnk pin output (d) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input Note Clear this bit to 0 when the TOQn0 pin is not used in the one-shot pulse output mode. Remark n = 0, 1 324 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-22. Register Setting in One-Shot Pulse Output Mode (3/3) (e) TMQn counter read buffer register (TQnCNT) The value of the 16-bit counter can be read by reading the TQnCNT register. (f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) If D0 is set to the TQnCCR0 register and Dk to the TQnCCRk register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (Dk - D0 + 1) x Count clock cycle Output delay period = (Dk) x Count clock cycle Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not used in the one-shot pulse output mode. 2. k = 1 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 325 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter D10 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register D00 D30 D20 D00 D01 D31 D11 D21 D01 INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCR1 register D10 D11 INTTQnCC1 signal TOQn1 pin output TQnCCR2 register D20 D21 INTTQnCC2 signal TOQn2 pin output TQnCCR3 register D30 D31 INTTQnCC3 signal TOQn3 pin output <1> <2> <3> Remark n = 0, 1 326 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TQnCCR0 to TQnCCR3 register setting change flow As rewriting the TQnCCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTQnCCR0 signal is recommended. START Setting of TQnCCR0 to TQnCCR3 registers Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnIOC2 register, TQnCCR0 to TQnCCR3 registers Initial setting of these registers is performed before setting the TQnCE bit to 1. <3> Count operation stop flow The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). Trigger wait status Count operation is stopped TQnCE bit = 0 TQnCE bit = 1 STOP Remark m = 0 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 327 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQnCCRm register To change the set value of the TQnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TQnCE bit External trigger input (TIQn0 pin input) TQnCCR0 register INTTQnCC0 signal TOQn0 pin output (only when software trigger is used) TQnCCRk register Dk0 Dk0 D00 Dk0 D00 D01 Dk1 Dk1 D01 D00 D01 Dk1 INTTQnCCk signal TOQnk pin output Delay (Dk0) Active level width (D00 - Dk0 + 1) Delay (10000H + Dk1) Active level width (D01 - Dk1 + 1) Delay (Dk1) Active level width (D01 - Dk1 + 1) When the TQnCCR0 register is rewritten from D00 to D01 and the TQnCCRk register from Dk0 to Dk1 where D00 > D01 and Dk0 > Dk1, if the TQnCCRk register is rewritten when the count value of the 16-bit counter is greater than Dk1 and less than Dk0 and if the TQnCCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches Dk1, the counter generates the INTTQnCCk signal and asserts the TOQnk pin. When the count value matches D01, the counter generates the INTTQnCC0 signal, deasserts the TOQnk pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark k = 1 to 3 n = 0, 1 328 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) Generation timing of compare match interrupt request signal (INTTQnCCk) The generation timing of the INTTQnCCk signal in the one-shot pulse output mode is different from other INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the 16-bit counter matches the value of the TQnCCRk register. Count clock 16-bit counter TQnCCRk register TOQnk pin output INTTQnCCk signal Dk - 2 Dk - 1 Dk Dk Dk + 1 Dk + 2 Usually, the INTTQnCCk signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TQnCCRk register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOQnk pin. Remark k = 1 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 329 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.5 PWM output mode (TQnMD2 to TQnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQn1 to TOQn3 pins when the TQnCTL0.TQnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOQn0 pin. Figure 7-24. Configuration in PWM Output Mode TQnCCR1 register Transfer CCR1 buffer register Match signal Output S controller R (RS-FF) TOQn1 pin INTTQnCC1 signal TQnCCR2 register Transfer CCR2 buffer register Match signal S Output controller R (RS-FF) TOQn2 pin INTTQnCC2 signal TQnCCR3 register Transfer CCR3 buffer register Match signal Clear Count clock selection Count start control Output controller Output S controller R (RS-FF) TOQn3 pin INTTQnCC3 signal 16-bit counter Match signal TOQn0 pin INTTQnCC0 signal TQnCE bit CCR0 buffer register Transfer TQnCCR0 register Remark n = 0, 1 330 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-25. Basic Timing in PWM Output Mode FFFFH D3 16-bit counter D1 0000H TQnCE bit D2 D0 D2 D1 D3 D0 D2 D1 D3 D0 D2 D1 D3 D0 TQnCCR0 register D0 INTTQnCC0 signal TOQn0 pin output TQnCCR1 register D1 INTTQnCC1 signal TOQn1 pin output Active level width (D1) TQnCCR2 register Active level width (D1) Active level width (D1) D2 Active level width (D1) INTTQnCC2 signal TOQn2 pin output Active level width (D2) TQnCCR3 register Active level width (D2) Active level width (D2) D3 Active level width (D2) INTTQnCC3 signal TOQn3 pin output Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 331 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQnk pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQnCCRk register) x Count clock cycle Cycle = (Set value of TQnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TQnCCRk register)/(Set value of TQnCCR0 register + 1) The PWM waveform can be changed by rewriting the TQnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTQnCC0) is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTQnCCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Remark k = 1 to 3, m = 0 to 3, n = 0, 1 Figure 7-26. Setting of Registers in PWM Output Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0 0/1 0 0 TQnMD2 TQnMD1 TQnMD0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TQnCKS0 to TQnCKS2 bits 1: Count external event input signal Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1. Remark n = 0, 1 332 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-26. Setting of Registers in PWM Output Mode (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of output level while operation of TOQn0 pin is disabled 0: Low level 1: High level 0: Disable TOQn1 pin output 1: Enable TOQn1 pin output Specification of active level of TOQn1 pin output 0: Active-high 1: Active-low 0: Disable TOQn2 pin output 1: Enable TOQn2 pin output Specification of active level of TOQn2 pin output 0: Active-high 1: Active-low 0: Disable TOQn3 pin output 1: Enable TOQn3 pin output Specification of active level of TOQn3 pin output 0: Active-high 1: Active-low * When TQnOLk bit = 0 16-bit counter TOQnk pin output * When TQnOLk bit = 1 16-bit counter TOQnk pin output (d) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TMQn counter read buffer register (TQnCNT) The value of the 16-bit counter can be read by reading the TQnCNT register. Note Clear this bit to 0 when the TOQn0 pin is not used in the PWM output mode. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 333 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-26. Register Setting in PWM Output Mode (3/3) (f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) If D0 is set to the TQnCCR0 register and Dk to the TQnCCRk register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = Dk x Count clock cycle Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not used in the PWM output mode. 2. Updating the TMQn capture/compare register 2 (TQnCCR2) and TMQn capture/compare register 3 (TQnCCR3) is validated by writing the TMQn capture/compare register 1 (TQnCCR1). 3. n = 0, 1 334 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Operation flow in PWM output mode Figure7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D10 0000H TQnCE bit D30 D20 D00 D31 D21 D11 D00 D00 D00 D00 D31 D31 D31 D21 D30 D21 D21 D11 D20 D11 D10 D10 TQnCCR0 register D00 D01 D00 CCR0 buffer register D00 D01 D00 INTTQnCC0 signal TOQn0 pin output TQnCCR1 register D10 D11 D11 D10 D10 D11 CCR1 buffer register D10 D11 D11 D10 D10 D11 INTTQnCC1 signal TOQn1 pin output TQnCCR2 register D20 D21 D20 D21 CCR2 buffer register D20 D21 D20 D21 INTTQnCC2 signal TOQn2 pin output TQnCCR3 register D30 D31 D30 D31 CCR3 buffer register D30 D31 D30 D31 INTTQnCC3 signal TOQn3 pin output <1> <2> <3> <4> <5> <6> <7> Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 335 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQnCCR1 to TQnCCR3 register setting change flow Setting of TQnCCR2, TQnCCR3 registers Only writing of the TQnCCR1 register must be performed when the set duty factor is only changed after writing the TQnCCR2 and TQnCCR3 registers. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnIOC2 register, TQnCCR0 to TQnCCR3 registers Initial setting of these registers is performed before setting the TQnCE bit to 1. Setting of TQnCCR1 register TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting is enabled (TQnCE bit = 1). <5> TQnCCR2, TQnCCR3 register setting change flow TQnCCR1 register writing of the same value is necessary only when the set duty factor of TOQn2 and TOQn3 pin outputs is changed. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR2, TQnCCR3 registers Setting of TQnCCR1 register <2> TQnCCR0 to TQnCCR3 register setting change flow Setting of TQnCCR0, TQnCCR2, and TQnCCR3 registers TQnCCR1 register Writing of the TQnCCR1 register must be performed after writing the TQnCCR0, TQnCCR2, and TQnCCR3 registers. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer registers. <6> TQnCCR1 register setting change flow Only writing of the TQnCCR1 register must be performed when the set duty factor is only changed. When counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR1 register <3> TQnCCR0 register setting change flow TQnCCR1 writing of the same value is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TQnCCRm register is transferred to the CCRm buffer register. Setting of TQnCCR0 register <7> Count operation stop flow TQnCE bit = 0 Counting is stopped. Setting of TQnCCR1 register STOP Remark k = 1 to 3 m = 0 to 3 n = 0, 1 336 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQnCCR1 register last. Rewrite the TQnCCRk register after writing the TQnCCR1 register after the INTTQnCC1 signal is detected. FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register CCR0 buffer register INTTQnCC0 signal TOQn0 pin output TQnCCR1 register CCR1 buffer register INTTQnCC1 signal TOQn1 pin output TQnCCR2 register CCR2 buffer register INTTQnCC2 signal TOQn2 pin output TQnCCR3 register CCR3 buffer register INTTQnCC3 signal TOQn3 pin output D30 D30 D20 D20 D21 D10 D10 D00 D00 D00 D00 D00 D31 D30 D30 D30 D21 D20 D20 D20 D11 D10 D10 D10 D01 D31 D21 D11 D01 D01 D01 D11 D11 D21 D31 D31 Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 337 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com To transfer data from the TQnCCRm register to the CCRm buffer register, the TQnCCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQnCCR0 register, set the active level width to the TQnCCR2 and TQnCCR3 registers, and then set an active level width to the TQnCCR1 register. To change only the active level width (duty factor) of PWM wave, first set the active level to the TQnCCR2 and TQnCCR3 registers, and then set an active level to the TQnCCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOQn1 pin, only the TQnCCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOQn2 and TOQn3 pins, first set an active level width to the TQnCCR2 and TQnCCR3 registers, and then write the same value to the TQnCCR1 register. After the TQnCCR1 register is written, the value written to the TQnCCRm register is transferred to the CCRm buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. To change only the cycle of the PWM waveform, first set a cycle to the TQnCCR0 register, and then write the same value to the TQnCCR1 register. To write the TQnCCR0 to TQnCCR3 registers again after writing the TQnCCR1 register once, do so after the INTTQnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TQnCCRm register to the CCRm buffer register conflicts with writing the TQnCCRm register. Remark m = 0 to 3 n = 0, 1 338 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQnCCRk register to 0000H. If the set value of the TQnCCR0 register is FFFFH, the INTTQnCCk signal is generated periodically. Count clock 16-bit counter TQnCE bit TQnCCR0 register TQnCCRk register INTTQnCC0 signal INTTQnCCk signal TOQnk pin output D0 0000H D0 0000H D0 0000H FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark k = 1 to 3 n = 0, 1 To output a 100% waveform, set a value of (set value of TQnCCR0 register + 1) to the TQnCCRk register. If the set value of the TQnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TQnCE bit TQnCCR0 register TQnCCRk register INTTQnCC0 signal INTTQnCCk signal TOQnk pin output D0 D0 + 1 D0 D0 + 1 D0 D0 + 1 FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 Remark k = 1 to 3 n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 339 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (c) Generation timing of compare match interrupt request signal (INTTQnCCk) The timing of generation of the INTTQnCCk signal in the PWM output mode differs from the timing of other INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the 16-bit counter matches the value of the TQnCCRk register. Count clock 16-bit counter CCRk buffer register TOQnk pin output INTTQnCCk signal Dk - 2 Dk - 1 Dk Dk Dk + 1 Dk + 2 Remark k = 1 to 3 n = 0, 1 Usually, the INTTQnCCk signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TQnCCRk register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOQnk pin. 340 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit is set to 1. At this time, the TQnCCRm register can be used as a compare register or a capture register, depending on the setting of the TQnOPT0.TQnCCS0 and TQnOPT0.TQnCCS1 bits. Remark m = 0 to 3 n = 0, 1 Figure 7-28. Configuration in Free-Running Timer Mode TQnCCR3 register (compare) TQnCCR2 register (compare) TQnCCR1 register (compare) TQnCCR0 register (compare) Output controller TOQn3 pin output Output controller TOQn2 pin output Output controller TOQn1 pin output Output controller TOQn0 pin output Internal count clock TIQn0pin (external event count input/ capture trigger input) Edge detector Count clock selection TQnCE bit 16-bit counter TQnCCS0, TQnCCS1 bits (capture/compare selection) INTTQnOV signal 0 1 TQnCCR0 register (capture) 0 1 0 TQnCCR1 register (capture) 1 0 1 TQnCCR2 register (capture) INTTQnCC3 signal Edge detector INTTQnCC2 signal TIQn1 pin (capture trigger input) Edge detector INTTQnCC1 signal TIQn2 pin (capture trigger input) Edge detector INTTQnCC0 signal TIQn3 pin (capture trigger input) Edge detector TQnCCR3 register (capture) Preliminary User's Manual U17718EJ1V0UD 341 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQn0 to TOQn3 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQnCCRm register, a compare match interrupt request signal (INTTQnCCm) is generated, and the output signal of the TOQnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TQnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal TOQn0 pin output TQnCCR1 register INTTQnCC1 signal TOQn1 pin output TQnCCR2 register INTTQnCC2 signal TOQn2 pin output TQnCCR3 register INTTQnCC3 signal TOQn3 pin output INTTQnOV signal TQnOVF bit D10 D00 D30 D20 D10 D11 D00 D30 D20 D01 D31 D21 D11 D01 D31 D21 D11 D00 D01 D11 D20 D21 D30 D31 Cleared to 0 by CLR instruction Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Remark n = 0, 1 342 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When the TQnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQnm pin is detected, the count value of the 16-bit counter is stored in the TQnCCRm register, and a capture interrupt request signal (INTTQnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TQnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH 16-bit counter D10 D30 D00 D20 D01 D31 D21 D11 D02 D12 D32 D22 D13 D03 D23 D33 0000H TQnCE bit TIQn0 pin input TQnCCR0 register INTTQnCC0 signal TIQn1 pin input TQnCCR1 register INTTQnCC1 signal TIQn2 pin input TQnCCR2 register INTTQnCC2 signal TIQn3 pin input TQnCCR3 register INTTQnCC3 signal INTTQnOV signal TQnOVF bit 0000 D30 D31 D32 D33 0000 D20 D21 D22 D23 0000 D10 D11 D12 D13 0000 D00 D01 D02 D03 Cleared to 0 by CLR instruction Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 343 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-31. Register Setting in Free-Running Timer Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1 (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0 0/1 0 0 TQnMD2 TQnMD1 TQnMD0 1 0 1 1, 0, 1: Free-running mode 0: Operate with count clock selected by TQnCKS0 to TQnCKS2 bits 1: Count on external event count input signal Remark n = 0, 1 344 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-31. Register Setting in Free-Running Timer Mode (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQnOL3 TQnOE3 TQnOL2 TQnOE2 TQnOL1 TQnOE1 TQnOL0 TQnOE0 TQnIOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of output level with operation of TOQn0 pin disabled 0: Low level 1: High level 0: Disable TOQn1 pin output 1: Enable TOQn1 pin output Setting of output level with operation of TOQn1 pin disabled 0: Low level 1: High level 0: Disable TOQn2 pin output 1: Enable TOQn2 pin output Setting of output level with operation of TOQn2 pin disabled 0: Low level 1: High level 0: Disable TOQn3 pin output 1: Enable TOQn3 pin output Setting of output level with operation of TOQn3 pin disabled 0: Low level 1: High level (d) TMQn I/O control register 1 (TQnIOC1) TQnIS7 TQnIOC1 0/1 TQnIS6 0/1 TQnIS5 0/1 TQnIS4 0/1 TQnIS3 0/1 TQnIS2 0/1 TQnIS1 0/1 TQnIS0 0/1 Select valid edge of TIQn0 pin input Select valid edge of TIQn1 pin input Select valid edge of TIQn2 pin input Select valid edge of TIQn3 pin input Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 345 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-31. Register Setting in Free-Running Timer Mode (3/3) (e) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (f) TMQn option register 0 (TQnOPT0) TQnCCS3 TQnCCS2 TQnCCS1 TQnCCS0 TQnOPT0 0/1 0/1 0/1 0/1 0 0 0 TQnOVF 0/1 Overflow flag Specifies if TQnCCR0 register functions as capture or compare register Specifies if TQnCCR1 register functions as capture or compare register Specifies if TQnCCR2 register functions as capture or compare register Specifies if TQnCCR3 register functions as capture or compare register (g) TMQn counter read buffer register (TQnCNT) The value of the 16-bit counter can be read by reading the TQnCNT register. (h) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) These registers function as capture registers or compare registers depending on the setting of the TQnOPT0.TQnCCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIQnm pin is detected. When the registers function as compare registers and when Dm is set to the TQnCCRm register, the INTTQnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOQnm pin is inverted. Remark m = 0 to 3 n = 0, 1 346 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 D30 D20 D10 D00 D30 D20 D10 D01 D31 D11 D21 D01 D31 D11 D21 16-bit counter D11 0000H TQnCE bit TQnCCR0 register D00 Set value changed D01 INTTQnCC0 signal TOQn0 pin output TQnCCR1 register D10 Set value changed D11 INTTQnCC1 signal TOQn1 pin output TQnCCR2 register D20 Set value changed D21 INTTQnCC2 signal TOQn2 pin output TQnCCR3 register D30 Set value changed D31 INTTQnCC3 signal TOQn3 pin output INTTQnOV signal TQnOVF bit <1> Cleared to 0 by CLR instruction <2> Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> <2> <3> Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 347 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC0 register, TQnIOC2 register, TQnOPT0 register, TQnCCR0 to TQnCCR3 registers Initial setting of these registers is performed before setting the TQnCE bit to 1. TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). <2> Overflow flag clear flow Read TQnOPT0 register (check overflow flag). TQnOVF bit = 1 NO YES Execute instruction to clear TQnOVF bit (CLR TQnOVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TQnCE bit to 0. TQnCE bit = 0 STOP Remark n = 0, 1 348 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter D10 D30 D00 D20 D01 D31 D21 D11 D02 D12 D32 D22 D13 D03 D23 D33 0000H TQnCE bit TIQn0 pin input TQnCCR0 register INTTQnCC0 signal TIQn1 pin input TQnCCR1 register INTTQnCC1 signal TIQn2 pin input TQnCCR2 register INTTQnCC2 signal TIQn3 pin input TQnCCR3 register INTTQnCC3 signal INTTQnOV signal TQnOVF bit 0000 D30 D31 D32 D33 0000 0000 D20 D21 D22 D23 0000 0000 D10 D11 D12 D13 0000 0000 D00 D01 D02 D03 0000 <1> Cleared to 0 by CLR instruction <2> Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> <2> <3> Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 349 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits) TQnCTL1 register, TQnIOC1 register, TQnOPT0 register Initial setting of these registers is performed before setting the TQnCE bit to 1. TQnCE bit = 1 The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). <2> Overflow flag clear flow Read TQnOPT0 register (check overflow flag). TQnOVF bit = 1 NO YES Execute instruction to clear TQnOVF bit (CLR TQnOVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TQnCE bit to 0. TQnCE bit = 0 STOP Remark n = 0, 1 350 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQnCCm signal has been detected. FFFFH D01 16-bit counter D20 D10 D00 D11 D30 D31 D22 D03 D12 D02 D21 D04 D13 D23 0000H TQnCE bit TQnCCR0 register D00 D01 D02 D03 D04 D05 INTTQnCC0 signal TOQn0 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (D01 - D00) (10000H + (D03 - D02) (D04 - D03) D02 - D01) TQnCCR1 register D10 D11 D12 D13 D14 INTTQnCC1 signal TOQn1 pin output Interval period (D10 + 1) TQnCCR2 register Interval period Interval period Interval period (D11 - D10) (10000H + D12 - D11) (D13 - D12) D21 D22 D23 D20 INTTQnCC2 signal TOQn2 pin output Interval period Interval period Interval period Interval period (D20 + 1) (10000H + D21 - D20) (D22 - D21) (10000H + D23 - D22) TQnCCR3 register D30 D31 D32 INTTQnCC3 signal TOQn3 pin output Interval period (D30 + 1) Interval period (10000H + D31 - D30) Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 351 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQnCCRm register must be re-set in the interrupt servicing that is executed when the INTTQnCCm signal is detected. The set value for re-setting the TQnCCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent time: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark m = 0 to 3 n = 0, 1 352 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQnCCm signal has been detected and for calculating an interval. FFFFH 16-bit counter D10 D30 D00 D20 D01 D31 D21 D11 D02 D12 D13 D32 D22 D03 D23 D33 0000H TQnCE bit TIQn0 pin input TQnCCR0 register INTTQnCC0 signal Pulse interval Pulse interval (D00 + 1) (10000H + D01 - D00) TIQn1 pin input TQnCCR1 register INTTQnCC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10 + 1) (10000H + (10000H + (D13 - D12) D11 - D10) D12 - D11) TIQn2 pin input TQnCCR2 register INTTQnCC2 signal Pulse interval (D20 + 1) Pulse interval (10000H + D21 - D20) Pulse interval (20000H + D22 - D21) Pulse interval (D23 - D22) 0000 D20 D21 D22 D23 0000 D10 D11 D12 D13 Pulse interval (10000H + D02 - D01) Pulse interval (10000H + D03 - D02) 0000 D00 D01 D02 D03 TIQn3 pin input TQnCCR3 register INTTQnCC3 signal Pulse interval Pulse interval (10000H + (D30 + 1) D31 - D30) INTTQnOV signal TQnOVF bit Pulse interval (10000H + D32 - D31) Pulse interval (10000H + D33 - D32) 0000 D30 D31 D32 D33 Cleared to 0 by CLR instruction Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 353 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQnCCRm register in synchronization with the INTTQnCCm signal, and calculating the difference between the read value and the previously read value. Remark m = 0 to 3 n = 0, 1 354 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH D11 16-bit counter D00 0000H TQnCE bit TIQn0 pin input TQnCCR0 register TIQn1 pin input TQnCCR1 register INTTQnOV signal TQnOVF bit D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input). <2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input). <3> Read the TQnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TQnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). Remark n = 0, 1 When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. Preliminary User's Manual U17718EJ1V0UD 355 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TQnCE bit INTTQnOV signal TQnOVF bit TQnOVF0 flagNote TIQn0 pin input TQnCCR0 register TQnOVF1 flagNote TIQn1 pin input TQnCCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TQnOVF0 and TQnOVF1 flags are set on the internal RAM by software. <1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input). <2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input). <3> An overflow occurs. Set the TQnOVF0 and TQnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TQnCCR0 register. Read the TQnOVF0 flag. If the TQnOVF0 flag is 1, clear it to 0. Because the TQnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TQnCCR1 register. Read the TQnOVF1 flag. If the TQnOVF1 flag is 1, clear it to 0 (the TQnOVF0 flag is cleared in <4>, and the TQnOVF1 flag remains 1). Because the TQnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Remark n = 0, 1 356 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TQnCE bit INTTQnOV signal TQnOVF bit TQnOVF0 flagNote TIQn0 pin input TQnCCR0 register TQnOVF1 flagNote TIQn1 pin input TQnCCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TQnOVF0 and TQnOVF1 flags are set on the internal RAM by software. <1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input). <2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TQnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TQnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TQnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TQnOVF1 flag. If the TQnOVF1 flag is 1, clear it to 0. Because the TQnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 357 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter Dm1 0000H TQnCE bit TIQnm pin input TQnCCRm register INTTQnOV signal TQnOVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Dm0 Dm1 Dm0 The following problem may occur when a long pulse width in the free-running timer mode. <1> Read the TQnCCRm register (setting of the default value of the TIQnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TQnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. Remark n = 0, 1 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. 358 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Example when capture trigger interval is long FFFFH 16-bit counter Dm1 0000H TQnCE bit TIQnm pin input TQnCCRm register INTTQnOV signal TQnOVF bit Overflow counterNote 0H 1H 2H 0H Dm0 Dm1 Dm0 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TQnCCRm register (setting of the default value of the TIQnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TQnCCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 359 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TQnOPT0 register. To accurately detect an overflow, read the TQnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TQnOVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TQnOVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TQnOVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TQnOVF bit) H Read Write Remark n = 0, 1 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. 360 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.7 Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit is set to 1. Each time the valid edge input to the TIQnm pin has been detected, the count value of the 16-bit counter is stored in the TQnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TQnCCRm register after a capture interrupt request signal (INTTQnCCm) occurs. Select either of the TIQn0 to TIQn3 pins as the capture trigger input pin. Specify "No edge detected" by using the TQnIOC1 register for the unused pins. When an external clock is used as the count clock, measure the pulse width of the TIQnk pin because the external clock is fixed to the TIQn0 pin. At this time, clear the TQnIOC1.TQnIS1 and TQnIOC1.TQnIS0 bits to 00 (capture trigger input (TIQn0 pin): No edge detected). Remark m = 0 to 3 n = 0, 1 k = 1 to 3 Figure 7-34. Configuration in Pulse Width Measurement Mode Internal count clock TIQn0 pin (external event count input/capture trigger input) Edge detector Count clock selection TQnCE bit Clear 16-bit counter INTTQnOV signal Edge detector TQnCCR0 register (capture) Edge detector TQnCCR1 register (capture) Edge detector TQnCCR2 register (capture) Edge detector TQnCCR3 register (capture) INTTQnCC0 signal INTTQnCC1 signal TIQn1 pin (capture trigger input) INTTQnCC2 signal TIQn2 pin (capture trigger input) INTTQnCC3 signal TIQn3 pin (capture trigger input) Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 361 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQnCE bit TIQnm pin input TQnCCRm register INTTQnCCm signal INTTQnOV signal TQnOVF bit Cleared to 0 by CLR instruction 0000H D0 D1 D2 D3 Remark m = 0 to 3 n = 0, 1 When the TQnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQnm pin is later detected, the count value of the 16-bit counter is stored in the TQnCCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTQnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIQnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTQnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TQnOVF bit set (1) count + Captured value) x Count clock cycle Remark m = 0 to 3, n = 0, 1 362 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCTL0 0/1 0 0 0 0 TQnCKS2 TQnCKS1 TQnCKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note Setting is invalid when the TQnEEE bit = 1. (b) TMQn control register 1 (TQnCTL1) TQnSYE TQnCTL1 0 TQnEST TQnEEE 0 0/1 0 0 TQnMD2 TQnMD1 TQnMD0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TQnCKS0 to TQnCKS2 bits 1: Count external event count input signal (c) TMQn I/O control register 1 (TQnIOC1) TQnIS7 TQnIOC1 0/1 TQnIS6 0/1 TQnIS5 0/1 TQnIS4 0/1 TQnIS3 0/1 TQnIS2 0/1 TQnIS1 0/1 TQnIS0 0/1 Select valid edge of TIQn0 pin input Select valid edge of TIQn1 pin input Select valid edge of TIQn2 pin input Select valid edge of TIQn3 pin input (d) TMQn I/O control register 2 (TQnIOC2) TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 363 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQn option register 0 (TQnOPT0) TQnCCS3 TQnCCS2TQnCCS1 TQnCCS0 TQnOPT0 0 0 0 0 0 0 0 TQnOVF 0/1 Overflow flag (f) TMQn counter read buffer register (TQnCNT) The value of the 16-bit counter can be read by reading the TQnCNT register. (g) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQnm pin is detected. Remarks 1. TMQn I/O control register 0 (TQnIOC0) is not used in the pulse width measurement mode. 2. m = 0 to 3 n = 0, 1 364 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQnCE bit TIQn0 pin input TQnCCR0 register INTTQnCC0 signal <1> <2> 0000H D0 D1 D2 0000H <1> Count operation start flow START Register initial setting TQnCTL0 register (TQnCKS0 to TQnCKS2 bits), TQnCTL1 register, TQnIOC1 register, TQnIOC2 register, TQnOPT0 register Initial setting of these registers is performed before setting the TQnCE bit to 1. Set TQnCTL0 register (TQnCE bit = 1) The TQnCKS0 to TQnCKS2 bits can be set at the same time when counting has been started (TQnCE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TQnCE bit to 0. TQnCE bit = 0 STOP Remark n = 0 to 2 Preliminary User's Manual U17718EJ1V0UD 365 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TQnOPT0 register. To accurately detect an overflow, read the TQnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TQnOVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TQnOVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TQnOVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TQnOVF bit) H Read Write Remark n = 0, 1 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. 366 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.8 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111) In the triangular wave PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor, and TMQn capture/compare register 0 (TQnCCR0) is used to set the cycle. By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output. The value of the TQnCCRm register can be rewritten when TQnCE = 1. To stop timer Q, clear TQnCE to 0. The waveform of PWM is output from the TOQnk pin. The TOQn0 pin produces a toggle output when the value of the 16-bit counter matches the value of the TQnCCR0 register and when the counter underflows. Caution In the PWM mode, the capture function of the TQnCCRm register cannot be used because this register can be used only as a compare register. Remark n = 0, 1, m = 0 to 3, k = 1 to 3 Figure 7-38. Timing of Basic Operation in Triangular Wave PWM Mode (TQnOE0 = 1, TQnOE1 = 1, TQnOE2 = 1, TQnOE3 = 1, TQnOL0 = 0, TQnOL1 = 0, TQnOL2 = 0, TQnOL3 = 0) TQnCE = 1 FFFFH D00 D30 D20 D10 D30 D20 D20 D10 D30 D00 D30 D20 D20 D10 D30 D00 D30 D20 16-bit counter TQnCCR0 0000H TQnCCR1 0000H TQnCCR2 0000H TQnCCR3 0000H INTTQnCC0 match interrupt INTTQnCC1 match interrupt INTTQnCC2 match interrupt INTTQnCC3 match interrupt INTTQnOV TOQn0 TOQn1 TOQn2 TOQn3 D00 D10 D20 D30 Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 367 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.5.9 Timer output operations The following table shows the operations and output levels of the TOQn0 to TOQn3 pins. Table 7-6. Timer Output Control in Each Mode Operation Mode Interval timer mode External event count mode External trigger pulse output mode TOQn0 Pin Square wave output Square wave output Square wave output External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode Free-running timer mode Pulse width measurement mode Triangular wave PWM output mode Square wave output Triangular PWM output PWM output - External trigger pulse output One-shot pulse output PWM output External trigger pulse output One-shot pulse output PWM output TOQn1 Pin TOQn2 Pin TOQn3 Pin Square wave output (only when compare function is used) - Triangular PWM output Triangular PWM output Table 7-7. Truth Table of TOQn0 to TOQn3 Pins Under Control of Timer Output Control Bits TQnIOC0.TQnOLm Bit 0 TQnIOC0.TQnOEm Bit 0 1 TQnCTL0.TQnCE Bit x 0 1 x 0 1 Level of TOQnm Pin Low-level output Low-level output Low level immediately before counting, high level after counting is started 1 0 1 High-level output High-level output High level immediately before counting, low level after counting is started Remark m = 0 to 3 n = 0, 1 368 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.6 Timer Tuned Operation Function Timer P and timer Q have a timer tuned operation function. The timers that can be synchronized are listed in Table 7-8. Table 7-8. Tuned Operation Mode of Timers Master Timer TMP0 TMP2 TMP1 TMP3 Slave Timer - TMQ0 Cautions 1. The tuned operation mode is enabled or disabled by the TPmCTL1.TPmSYE and TQ0CTL1.TQ0SYE bits. For TMQ2, either or both TMQ3 and TMQ0 can be specified as slaves. 2. Set the tuned operation mode using the following procedure. <1> Set the TPmCTL1.TPmSYE and TQ0CTL1.TQ0SYE bits of the slave timer to enable the tuned operation. Set the TPmCTL1.TPmMD2 to TPmCTL1.TPmMD0 and TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits of the slave timer to the free-running mode. <2> Set the timer mode by using the TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits. At this time, do not set the TPnCTL1.TPnSYE bit of the master timer. <3> Set the compare register value of the master and slave timers. <4> Set the TPmCTL0.TPmCE and TQ0CTL0.TQ0CE bits of the slave timer to enable operation on the internal operating clock. <5> Set the TPnCTL0.TPnCE bit of the master timer to enable operation on the internal operating clock. Remark m = 1, 3 n = 0, 2 Tables 7-9 and 7-10 show the timer modes that can be used in the tuned operation mode (: Settable, x: Not settable). Table 7-9. Timer Modes Usable in Tuned Operation Mode Master Timer TMP0 TMP2 Free-Running Mode PWM Mode Triangular Wave PWM Mode x x Preliminary User's Manual U17718EJ1V0UD 369 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Table 7-10. Timer Output Functions Tuned Channel Tuning OFF Ch0 TMP0 (master) TMP1 (slave) Ch1 TMP2 (master) TMP3 (slave) TMQ0 (slave) TOP00 TOP01 TOP10 TOP11 TOP20 TOP21 TOP30 TOP31 TOQ00 TOQ01 to TOQ03 PPG PPG PPG PPG PPG PPG PPG PPG PPG PPG Tuning ON Tuning OFF Toggle PWM Toggle PWM Toggle PWM Toggle PWM Toggle PWM Tuning ON PWM PWM PWM Timer Pin Free-Running Mode PWM Mode Triangular Wave PWM Mode Tuning OFF N/A N/A N/A N/A N/A N/A N/A N/A Toggle Triangular wave PWM Tuning ON N/A N/A Remark The timing of transmitting data from the compare register of the master timer to the compare register of the slave timer is as follows. PPG: CPU write timing and TOQ00 (n = 0, 1) Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0 370 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-39. Tuned Operation Image (TMP2, TMP3, TMQ0) Unit operation Tuned operation TMP2 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) TMP2 (master ) + TMP3 (slave) + TMQ0 (slave) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) TMP3 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOP31 (PWM output) 16-bit capture/compare 16-bit capture/compare TOP30 (PWM output) TOP31 (PWM output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOQ00 (PWM output) TOQ01 (PWM output) TOQ02 (PWM output) TOQ03 (PWM output) TMQ0 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOQ01 (PWM output) TOQ02 (PWM output) TOQ03 (PWM output) Five PWM outputs are available when PWM is operated as a single unit. Seven PWM outputs are available when PWM is operated in tuned operation mode. Preliminary User's Manual U17718EJ1V0UD 371 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com Figure 7-40. Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0) FFFFH D60 TMP2 16-bit counter D10 0000H TP2CE TP3CE TQ0CE TP2CCR0 TP2CCR1 TP3CCR0 TP3CCR1 TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 INTTP2CC0 match interrupt INTTP2CC1 match interrupt INTTP3CC0 match interrupt INTTP3CC1 match interrupt INTTQ0CC0 match interrupt INTTQ0CC1 match interrupt INTTQ0CC2 match interrupt INTTQ0CC3 match interrupt TOP20 TOP21 TOP30 TOP31 TOQ00 TOQ01 TOQ02 TOQ03 D40 D30 D20 D50 D70 D00 D60 D40 D30 D10 D20 D50 D70 D00 D00 D10 D20 D30 D40 D50 D60 D70 372 Preliminary User's Manual U17718EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) www..com 7.7 Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TQnCCR0, TQnCCR1, TQnCCR2, and TQnCCR3 registers if the capture trigger is input immediately after the TQnCE bit is set to 1. (a) Free-running timer mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TQnCCR0 register 0000H FFFFH 0001H TQnCE bit TIQn0 pin input Capture trigger input Capture trigger input (b) Pulse width measurement mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TQnCCR0 register 0000H FFFFH 0002H TQnCE bit TIQn0 pin input Capture trigger input Capture trigger input Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 373 www..com CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) 8.1 Overview * Interval function * 8 clocks selectable * 16-bit counter x 1 (The 16-bit counter cannot be read during timer count operation.) * Compare register x 1 (The compare register cannot be written during timer counter operation.) * Compare match interrupt x 1 Timer M supports only the clear & start mode. The free-running timer mode is not supported. 374 Preliminary User's Manual U17718EJ1V0UD CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com 8.2 Configuration TMM0 includes the following hardware. Table 8-1. Configuration of TMM0 Item Timer register Register Control register 16-bit counter TMM0 compare register 0 (TM0CMP0) TMM0 control register 0 (TM0CTL0) Configuration Figure 8-1. Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0 TM0CMP0 Match fXX fXX/2 fXX/4 fXX/64 fXX/512 INTWT fR/8 fXT INTTM0EQ0 Selector Controller 16-bit counter Clear Remark fXX: fR: fXT: Main clock frequency Internal oscillation clock frequency Subclock frequency INTWT: Watch timer interrupt request signal (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMM0 compare register 0 (TM0CMP0) The TM0CMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units. Reset sets this register to 0000H. The same value can always be written to the TM0CMP0 register by software. TM0CMP0 register rewrite is prohibited when the TM0CTL0.TM0CE bit = 1. After reset: 0000H 15 14 R/W 13 12 Address: FFFFF694H 11 10 9 8 7 6 5 4 3 2 1 0 TM0CMP0 Preliminary User's Manual U17718EJ1V0UD 375 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com 8.3 Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software. Rewriting this register, except the TM0CE bit, is prohibited while the timer is operating. After reset: 00H 7 R/W 6 0 Address: FFFFF690H 5 0 4 0 3 0 2 1 0 TM0CTL0 TM0CE TM0CKS2 TM0CKS1 TM0CKS0 TM0CE 0 1 Internal clock operation enable/disable specification TMM0 operation disabled (16-bit counter reset asynchronously). Operation clock application stopped. TMM0 operation enabled. Operation clock application started. TMM0 operation started. The internal clock control and internal circuit reset for TMM0 are performed asynchronously with the TM0CE bit. When the TM0CE bit is cleared to 0, the internal clock of TMM0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. TM0CKS2 TM0CKS1 TM0CKS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/64 fXX/512 INTWT fR/8 fXT Count clock selection Cautions 1. Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0. When changing the value of TM0CE from 0 to 1, it is not possible to set the value of the TM0CKS2 to TM0CKS0 bits simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency fR: Internal oscillation clock frequency fXT: Subclock frequency 376 Preliminary User's Manual U17718EJ1V0UD CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com 8.4 Operation Do not set the TM0CMP0 register to FFFFH. Caution 8.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the TM0CTL0.TM0CE bit is set to 1. Figure 8-2. Configuration of Interval Timer Clear Count clock selection 16-bit counter Match signal INTTM0EQ0 signal TM0CE bit TM0CMP0 register Figure 8-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1) D D D D D When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to 0000H and a compare match interrupt request signal (INTTM0EQ0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TM0CMP0 register + 1) x Count clock cycle Preliminary User's Manual U17718EJ1V0UD 377 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com Figure 8-4. Register Setting for Interval Timer Mode Operation (a) TMM0 control register 0 (TM0CTL0) TM0CE TM0CTL0 0/1 0 0 0 0 TM0CKS2 TM0CKS1 TM0CKS0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMM0 compare register 0 (TM0CMP0) If the TM0CMP0 register is set to D, the interval is as follows. Interval = (D + 1) x Count clock cycle 378 Preliminary User's Manual U17718EJ1V0UD CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal D D D D <1> <2> <1> Count operation start flow START Register initial setting TM0CTL0 register (TM0CKS0 to TM0CKS2 bits) TM0CMP0 register Initial setting of these registers is performed before setting the TM0CE bit to 1. TM0CE bit = 1 The TM0CKS0 to TM0CKS2 bits can be set at the same time when counting has been started (TM0CE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TM0CE bit to 0. TM0CE bit = 0 STOP Preliminary User's Manual U17718EJ1V0UD 379 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com (2) Interval timer mode operation timing Caution Do not set the TM0CMP0 register to FFFFH. (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TM0CE bit TM0CMP0 register INTTM0EQ0 signal Interval time Count clock cycle Interval time Count clock cycle 0000H FFFFH 0000H 0000H 0000H 0000H (b) Operation if TM0CMP0 register is set to N If the TM0CMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in synchronization with the next count-up timing and the INTTM0EQ0 signal is generated. FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal N N Interval time (N + 1) x count clock cycle Interval time (N + 1) x count clock cycle Interval time (N + 1) x count clock cycle Remark 0000H < N < FFFFH 380 Preliminary User's Manual U17718EJ1V0UD CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) www..com 8.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected. Selected Count Clock fXX fXX/2 fXX/4 fXX/64 fXX/512 INTWT fR/8 fXT Maximum Time Before Counting Start 2/fXX 6/fXX 24/fXX 128/fXX 1024/fXX Second rising edge of INTWT signal 16/fR 2/fXT (2) Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is operating. If these registers are rewritten while the TM0CE bit is 1, the operation cannot be guaranteed. If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set the registers. Preliminary User's Manual U17718EJ1V0UD 381 www..com CHAPTER 9 WATCH TIMER FUNCTIONS 9.1 Functions The watch timer has the following functions. * Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. * Interval timer: An interrupt request signal (INTWTI) is generated at set intervals. The watch timer and interval timer functions can be used at the same time. 382 Preliminary User's Manual U17718EJ1V0UD CHAPTER 9 WATCH TIMER FUNCTIONS www..com 9.2 Configuration The block diagram of the watch timer is shown below. Figure 9-1. Block Diagram of Watch Timer Internal bus PRSM0 register BGCE0 BGCS01 BGCS00 Clear Clock control 3-bit prescaler fX/8 fX/4 fX/2 fX 2 PRSCM0 register Match Selector fX 1/2 fBGCS 8-bit counter Selector Clear Selector 5-bit counter Selector INTWT fBRG fXT fW 11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Clear Selector INTWTI 3 WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fX: fBGCS: fBRG: fXT: fW: Main clock oscillation frequency Watch timer source clock frequency Watch timer count clock frequency Subclock frequency Watch timer clock frequency INTWT: Watch timer interrupt request signal INTWTI: Interval timer interrupt request signal Preliminary User's Manual U17718EJ1V0UD 383 CHAPTER 9 WATCH TIMER FUNCTIONS www..com (1) Clock control This block controls supplying and stopping the operating clock (fX) when the watch timer operates on the main clock. (2) 3-bit prescaler This prescaler divides fX to generate fX/2, fX/4, or fX/8. (3) 8-bit counter This 8-bit counter counts the source clock (fBGCS). (4) 11-bit prescaler This prescaler divides fW to generate a clock of fW/24 to fW/211. (5) 5-bit counter This counter counts fW or fW/29, and generates a watch timer interrupt request signal at intervals of 24/fW, 25/fW, 212/fW, or 214/fW. (6) Selector The watch timer has the following five selectors. * Selector that selects one of fX, fX/2, fX/4, or fX/8 as the source clock of the watch timer * Selector that selects the main clock (fX) or subclock (fXT) as the clock of the watch timer * Selector that selects fW or fW/29 as the count clock frequency of the 5-bit counter 4 13 5 14 * Selector that selects 2 /fW, 2 /fW, 2 /fW, or 2 /fW as the INTWT signal generation time interval * Selector that selects 24/fW to 211/fW as the interval timer interrupt request signal (INTWTI) generation time interval (7) PRSCM register This is an 8-bit compare register that sets the interval time. (8) PRSM register This register controls clock supply to the watch timer. (9) WTM register This is an 8-bit register that controls the operation of the watch timer/interval timer, and sets the interrupt request signal generation interval. 384 Preliminary User's Manual U17718EJ1V0UD CHAPTER 9 WATCH TIMER FUNCTIONS www..com 9.3 Registers The following registers are provided for the watch timer. * Prescaler mode register 0 (PRSM0) * Prescaler compare register 0 (PRSCM0) * Watch timer operation mode register (WTM) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF8B0H PRSM0 0 0 0 BGCE0 0 0 BGCS01 BGCS00 BGCE0 0 1 Disabled Enabled Main clock operation enable BGCS01 BGCS00 Selection of watch timer source clock (fBGCS) 5 MHz 4 MHz 250 ns 500 ns 1 s 2 s 0 0 1 1 0 1 0 1 fX fX/2 fX/4 fX/8 200 ns 400 ns 800 ns 1.6 s Cautions 1. Do not change the values of the BGCS00 and BGCS01 bits during watch timer operation. 2. Set the PRSM0 register before setting the BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. Preliminary User's Manual U17718EJ1V0UD 385 CHAPTER 9 WATCH TIMER FUNCTIONS www..com (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF8B1H PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register during watch timer operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. The calculation for fBRG is shown below. fBRG = fBGCS/2N Remark fBGCS: Watch timer source clock set by the PRSM0 register N: Set value of PRSCM0 register = 1 to 256 However, N = 256 only when PRSCM0 register is set to 00H. 386 Preliminary User's Manual U17718EJ1V0UD CHAPTER 9 WATCH TIMER FUNCTIONS www..com (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. Set the PRSM0 register before setting the WTM register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H R/W Address: FFFFF680H WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selection of interval time of prescaler 24/fW (488 s: fW = fXT) 25/fW (977 s: fW = fXT) 26/fW (1.95 ms: fW = fXT) 27/fW (3.91 ms: fW = fXT) 28/fW (7.81 ms: fW = fXT) 29/fW (15.6 ms: fW = fXT) 210/fW (31.3 ms: fW = fXT) 211/fW (62.5 ms: fW = fXT) 24/fW (488 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 26/fW (1.95 ms: fW = fBRG) 27/fW (3.90 ms: fW = fBRG) 28/fW (7.81 ms: fW = fBRG) 29/fW (15.6 ms: fW = fBRG) 210/fW (31.2 ms: fW = fBRG) 211/fW (62.5 ms: fW = fBRG) Preliminary User's Manual U17718EJ1V0UD 387 CHAPTER 9 WATCH TIMER FUNCTIONS www..com (2/2) WTM7 0 0 0 0 1 1 1 1 WTM3 0 0 1 1 0 0 1 1 WTM2 0 1 0 1 0 1 0 1 14 Selection of set time of watch flag 2 /fW (0.5 s: fW = fXT) 213/fW (0.25 s: fW = fXT) 25/fW (977 s: fW = fXT) 24/fW (488 s: fW = fXT) 214/fW (0.5 s: fW = fBRG) 213/fW (0.25 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 24/fW (488 s: fW = fBRG) WTM1 0 1 Control of 5-bit counter operation Clears after operation stops Starts WTM0 0 1 Watch timer operation enable Stops operation (clears both prescaler and 5-bit counter) Enables operation Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply to operation with fW = 32.768 kHz 3. fXT: Subclock frequency 4. fBRG: Watch timer count clock frequency 388 Preliminary User's Manual U17718EJ1V0UD CHAPTER 9 WATCH TIMER FUNCTIONS www..com 9.4 9.4.1 Operation Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock. The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11. When the WTM0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. The time of the watch timer can be adjusted by clearing the WTM1 bit to 0 and then the 5-bit counter when operating at the same time as the interval timer. At this time, an error of up to 15.6 ms may occur for the watch timer, but the interval timer is not affected. If the main clock is used as the count clock of the watch timer, set the count clock using the PRSM0.BGCS01 and BGCS00 bits, the 8-bit comparison value using the PRSCM0 register, and the count clock frequency (fBRG) of the watch timer to 32.768 kHz. When the PRSM0.BGCE0 bit is set (1), fBRG is supplied to the watch timer. fBRG can be calculated by the following expression. fBRG = fX/(2m+1 x N) To set fBRG to 32.768 kHz, perform the following calculation and set the BGCS01 and BGCS00 bits and the PRSCM0 register. <1> Set N = fX/65,536. Set m = 0. <2> When the value resulting from rounding up the first decimal place of N is even, set N before the roundup as N/2 and m as m + 1. <3> Repeat <2> until N is odd or m = 3. <4> Set the value resulting from rounding up the first decimal place of N to the PRSCM0 register and m to the BGCS01 and BGCS00 bits. Example: When fX = 4.00 MHz <1> N = 4,000,000/65,536 = 61.03..., m = 0 <2>, <3> Because N (round up the first decimal place) is odd, N = 61, m = 0. <4> Set value of PRSCM0 register: 3DH (61), set value of BGCS01 and BGCS00 bits: 00 At this time, the actual fBRG frequency is as follows. fBRG = fX/(2m+1 x N) = 4,000,000/(2 x 61) = 32.787 kHz Remark m: Division value (set value of BGCS01 and BGCS00 bits) = 0 to 3 N: Set value of PRSCM0 register = 1 to 256 However, N = 256 only when PRSCM0 register is set to 00H. fX: Main clock oscillation frequency Preliminary User's Manual U17718EJ1V0UD 389 CHAPTER 9 WATCH TIMER FUNCTIONS www..com 9.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a preset count value. The interval time can be selected by the WTM4 to WTM7 bits of the WTM register. Table 9-1. Interval Time of Interval Timer WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 x 1/fw 4 Interval Time 488 s (operating at fW = fXT = 32.768 kHz) 977 s (operating at fW = fXT = 32.768 kHz) 1.95 ms (operating at fW = fXT = 32.768 kHz) 3.91 ms (operating at fW = fXT = 32.768 kHz) 7.81 ms (operating at fW = fXT = 32.768 kHz) 15.6 ms (operating at fW = fXT = 32.768 kHz) 31.3 ms (operating at fW = fXT = 32.768 kHz) 62.5 ms (operating at fW = fXT = 32.768 kHz) 488 s (operating at fW = fBRG = 32.768 kHz) 977 s (operating at fW = fBRG = 32.768 kHz) 1.95 ms (operating at fW = fBRG = 32.768 kHz) 3.91 ms (operating at fW = fBRG = 32.768 kHz) 7.81 ms (operating at fW = fBRG = 32.768 kHz) 15.6 ms (operating at fW = fBRG = 32.768 kHz) 31.3 ms (operating at fW = fBRG = 32.768 kHz) 62.5 ms (operating at fW = fBRG = 32.768 kHz) 2 x 1/fw 5 2 x 1/fw 6 2 x 1/fw 7 2 x 1/fw 8 2 x 1/fw 9 2 x 1/fw 10 2 x 1/fw 11 2 x 1/fw 4 2 x 1/fw 5 2 x 1/fw 6 2 x 1/fw 7 2 x 1/fw 8 2 x 1/fw 9 2 x 1/fw 10 2 x 1/fw 11 Remark fW: Watch timer clock frequency 390 Preliminary User's Manual U17718EJ1V0UD CHAPTER 9 WATCH TIMER FUNCTIONS www..com Figure 9-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nT Interval time (T) nT Overflow Overflow Remarks 1. When 0.5 seconds of the watch timer interrupt time is set. 2. fW: Watch timer clock frequency Values in parentheses apply to operation with fW = 32.768 kHz. n: Number of interval timer operations 9.4.3 Cautions Some time is required before the first watch timer interrupt request signal (INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 1). Figure 9-3. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Cycle = 0.5 s) It takes 0.515625 seconds (max.) for the first INTWT signal to be generated (29 x 1/32768 = 0.015625 seconds longer (max.)). The INTWT signal is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT Preliminary User's Manual U17718EJ1V0UD 391 www..com CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 10.1 Functions Watchdog timer 2 has the following functions. * Default-start watchdog timerNote 1 Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)Note 2 * Input selectable from main clock and internal oscillation clock as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes only once, even if the default settings (reset mode, interval time: fR/219) do not need to be changed. 2. For the non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), see 15.2.2 (2) INTWDT2 signal. 392 Preliminary User's Manual U17718EJ1V0UD CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 www..com 10.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 10-1. Block Diagram of Watchdog Timer 2 fXX/29 fR/23 Clock input controller 2 fXX/216 to fXX/223, fR/212 to fR/219 16-bit counter Selector Output controller INTWDT2 WDT2RES (internal reset signal) Clear 3 3 Watchdog timer enable register (WDTE) 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Watchdog timer mode register 2 (WDTM2) Internal bus Remark fXX: fR: INTWDT2: Main clock frequency Internal oscillation clock frequency Non-maskable interrupt request signal from watchdog timer 2 WDTRES2: Watchdog timer 2 reset signal Watchdog timer 2 includes the following hardware. Table 10-1. Configuration of Watchdog Timer 2 Item Control registers Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) Preliminary User's Manual U17718EJ1V0UD 393 CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 www..com 10.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 67H R/W Address: FFFFF6D0H WDTM2 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 WDM21 0 0 1 WDM20 0 1 - Selection of operation mode of watchdog timer 2Note Stops operation Non-maskable interrupt request mode (generation of INTWDT2 signal) Reset mode (generation of WDT2RES signal) Note If the OPB1 bit is set to 1 by using the option byte function (see CHAPTER 24), the reset mode is fixed. Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 10-2 Watchdog Timer 2 Clock Selection. 2. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly generated and the counter is reset. 3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or write a value other than ACH to the WDTE register once. 4. To stop the operation of watchdog timer 2, write 1FH to the WDTM2 register. If the OPB1 bit is set to 1 by using the option byte function (see CHAPTER 24), however, watchdog timer 2 cannot be stopped by any means other than reset. 394 Preliminary User's Manual U17718EJ1V0UD CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 www..com Table 10-2. Watchdog Timer 2 Clock Selection WDCS24 0 0 0 0 0 0 0 0 WDCS23 0 0 0 0 0 0 0 0 WDCS22 0 0 0 0 1 1 1 1 WDCS21 0 0 1 1 0 0 1 1 WDCS20 Selected Clock 0 1 0 1 0 1 0 1 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 19 18 17 16 15 14 13 12 100 kHz (MIN.) 41.0 ms 81.9 ms 163.8 ms 327.7 ms 655.4 ms 1,310.7 ms 2,621.4 ms 5,242.9 ms fXX = 4 MHz 200 kHz (TYP.) 20.5 ms 41.0 ms 81.9 ms 163.8 ms 327.7 ms 655.4 ms 1,310.7 ms 2,621.4 ms 400 kHz (MAX.) 10.2 ms 20.5 ms 41.0 ms 81.9 ms 163.8 ms 327.7 ms 655.4 ms 1,310.7 ms fXX = 5 MHz 13.1 ms 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1,677.7 ms 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 23 22 21 20 19 18 17 16 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1,048.6 ms 2,097.2 ms Operation stopped Caution If the OPB1 bit is set to 1 by using the option byte function, the clock is fixed to the internal oscillation clock (fR) (212/fR to 219/fR can be selected). For details, see CHAPTER 24 OPTION BYTE FUNCTION. Preliminary User's Manual U17718EJ1V0UD 395 CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 www..com (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH. After reset: 9AH R/W Address: FFFFF6D1H WDTE Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or write a value other than ACH to the WDTE register once. 4. The read value of the WDTE register is "9AH" (which differs from written value "ACH"). 396 Preliminary User's Manual U17718EJ1V0UD CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 www..com 10.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped. The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time interval. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation has started, write ACH to WDTE within the loop detection time interval. If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a nonmaskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and WDTM2.WDM20 bits. When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock. To not use watchdog timer 2, write 1FH to the WDTM2 register. For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 15.2.2 (2) From INTWDT2 signal. Preliminary User's Manual U17718EJ1V0UD 397 www..com CHAPTER 11 A/D CONVERTER 11.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 16 analog input signal channels (ANI0 to ANI15). The A/D converter has the following features. 10-bit resolution 24 channels Successive approximation method Operating voltage: AVREF0 = 4.0 to 5.5 V Analog input voltage: 0 V to AVREF0 The following functions are provided as operation modes. * Continuous select mode * Continuous scan mode * One-shot scan mode The following functions are provided as trigger modes. * Software trigger mode * External trigger mode (external, 1) * Timer trigger mode Power-fail monitor function (conversion result compare function) 11.2 Functions (1) 10-bit resolution A/D conversion An analog input channel is selected from ANI0 to ANI15, and an A/D conversion operation is repeated at a resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is generated. (2) Power-fail detection function This function is used to detect a drop in the battery voltage. The result of A/D conversion (the value of the ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated only when a specified comparison condition is satisfied (n = 0 to 15). 398 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com 11.3 Configuration The block diagram of the A/D converter is shown below. Figure 11-1. Block Diagram of A/D Converter AVREF0 ANI0 ANI1 ANI2 : : ANI13 ANI14 ANI15 Sample & hold circuit ADA0CE bit Voltage comparator & Compare voltage generation DAC Selector ADA0CE bit AVSS SAR ADA0TMD1 bit ADA0TMD0 bit INTAD Selector INTTP2CC0 INTTP2CC1 ADTRG Edge detection Controller ADA0CR0 ADA0CR1 ADA0CR2 : : ADA0CR14 ADA0M1 ADA0M2 ADA0S ADA0CR15 Controller ADA0PFE bit ADA0PFC bit ADA0ETS0 bit ADA0ETS1 bit ADA0M0 Voltage comparator ADA0PFT ADA0PFM Internal bus The A/D converter includes the following hardware. Table 11-1. Configuration of A/D Converter Item Analog inputs Registers 16 channels (ANI0 to ANI15 pins) Successive approximation register (SAR) A/D conversion result registers 0 to 15 (ADA0CR0 to ADA0CR15) A/D conversion result registers 0H to 15H (ADCR0H to ADCR15H): Only higher 8 bits can be read Control registers A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2) A/D converter channel specification register 0 (ADA0S) Power fail compare mode register (ADA0PFM) Power fail compare threshold value register (ADA0PFT) Configuration Preliminary User's Manual U17718EJ1V0UD 399 CHAPTER 11 A/D CONVERTER www..com (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR register are transferred to the ADA0CRn register. Remark n = 0 to 15 (2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH) The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 16 registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input. (The lower 6 bits are fixed to 0.) (3) A/D converter mode register 0 (ADA0M0) This register specifies the operation mode and controls the conversion operation by the A/D converter. (4) A/D converter mode register 1 (ADA0M1) This register sets the conversion time of the analog input signal to be converted. (5) A/D converter mode register 2 (ADA0M2) This register sets the hardware trigger mode. (6) A/D converter channel specification register (ADA0S) This register sets the input port that inputs the analog voltage to be converted. (7) Power-fail compare mode register (ADA0PFM) This register sets the power-fail monitor mode. (8) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADA0CRnH). (9) Controller The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and generates the INTAD signal only when a specified comparison condition is satisfied. (10) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (11) Voltage comparator The voltage comparator compares a voltage value that has been sampled and held with the voltage value of the compare voltage generation DAC. 400 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (13) ANI0 to ANI15 pins These are analog input pins for the 16 A/D converter channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins. Cautions 1. Make sure that the voltages input to the ANI0 to ANI15 pins do not exceed the rated values. In particular if a voltage of AVREF0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. 2. The analog input pins (ANI0 to ANI15) function alternately as input port pins (P70 to P715). If any of ANI0 to ANI15 is selected to execute A/D conversion, do not execute an input instruction to port 7 during conversion. If executed, the conversion resolution may be degraded. (14) AVREF0 pin This is the pin used to input the reference voltage of the A/D converter. Always make the potential at this pin the same as that at the VDD pin even when the A/D converter is not used. The signals input to the ANI0 to ANI15 pins are converted to digital signals based on the voltage applied between the AVREF0 and AVSS pins. (15) AVSS pin This is the ground pin of the A/D converter. Always make the potential at this pin the same as that at the VSS pin even when the A/D converter is not used. Preliminary User's Manual U17718EJ1V0UD 401 CHAPTER 11 A/D CONVERTER www..com 11.4 Registers The A/D converter is controlled by the following registers. * A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) * A/D converter channel specification register 0 (ADA0S) * Power-fail compare mode register (ADA0PFM) The following registers are also used. * A/D conversion result register n (ADA0CRn) * A/D conversion result register nH (ADA0CRnH) * Power-fail compare threshold value register (ADA0PFT) (1) A/D converter mode register 0 (ADA0M0) The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations. This register can be read or written in 8-bit or 1-bit units. However, ADA0EF bit is read-only. Reset sets this register to 00H. Caution Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock 402 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com After reset: 00H R/W Address: FFFFF200H ADA0M0 ADA0CE 0 ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD ADA0EF ADA0CE 0 1 Stops A/D conversion Enables A/D conversion A/D conversion control ADA0MD1 ADA0MD0 0 0 1 1 0 1 0 1 Specification of A/D converter operation mode Continuous select mode Continuous scan mode Setting prohibited One-shot scan mode ADA0ETS1 ADA0ETS0 Specification of external trigger (ADTRG pin) input valid edge 0 0 1 1 0 1 0 1 No edge detection Falling edge detection Rising edge detection Detection of both rising and falling edges ADA0TMD 0 1 Software trigger mode Trigger mode specification External trigger mode/timer trigger mode ADA0EF 0 1 A/D converter status display A/D conversion stopped A/D conversion in progress Cautions 1. Write operations to bit 0 are ignored. 2. Changing the ADA0M1 register value is prohibited while A/D conversion is enabled (ADA0CE bit = 1). 3. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written during A/D conversion (ADA0EF bit = 1), the following will be performed according to the mode. * In software trigger mode A/D conversion is stopped and started again from the beginning. * In hardware trigger mode A/D conversion is stopped, and the trigger standby state is set. 4. When not using the A/D converter, stop the operation by setting the ADA0CE bit to 0 to reduce the power consumption. 5. The resolution for the first conversion of the data of the input pin immediately after the start of A/D conversion may be degraded. For details, see 11.6 (7) AVREF0 pin. Preliminary User's Manual U17718EJ1V0UD 403 CHAPTER 11 A/D CONVERTER www..com (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that controls the conversion time specification. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 ADA0M1 ADA0HS1 R/W 6 0 Address: FFFFF201H 5 0 4 0 3 2 1 0 ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0 Cautions 1. Be sure to clear bits 6 to 4 to "0". 2. Be sure to set the ADA0HS1 bit to "1". Remark For A/D conversion time setting examples, see Table 11-2. Table 11-2. Conversion Mode Setting Example ADA0HS1 ADA0FR3 to ADA0FR0 3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 31/fXX 62/fXX 93/fXX 124/fXX 155/fXX 186/fXX 217/fXX 248/fXX 279/fXX 310/fXX 341/fXX 372/fXX 403/fXX 434/fXX 465/fXX 496/fXX A/D Conversion Time Setting prohibited Setting prohibited 7.75 s 3.10 s 4.65 s 6.20 s 7.75 s 9.30 s 10.85 s 12.40 s 13.95 s 15.50 s 3.88 s 5.81 s 7.75 s 9.69 s 11.63 s 13.56 s 15.50 s 15.50 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz A/D Stabilization Time 16/fXX 31/fXX 47/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX 50/fXX Note Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Note When the ADA0CE bit of the ADA0M0 register is changed from 0 to 1 to secure the A/D converter stabilization time, the first A/D conversion starts after one of the above clock values is input. 404 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 ADA0M2 0 R/W 6 0 Address: FFFFF203H 5 0 4 0 3 0 2 0 1 0 ADA0TMD1 ADA0TMD0 ADA0TMD1 ADA0TMD0 0 0 1 1 0 1 0 1 Specification of hardware trigger mode External trigger mode (when ADTRG pin valid edge detected) Timer trigger mode 0 (when INTTP2CC0 interrupt request generated) Timer trigger mode 1 (when INTTP2CC1 interrupt request generated) Setting prohibited Caution Be sure to clear bits 7 to 2 to "0". Preliminary User's Manual U17718EJ1V0UD 405 CHAPTER 11 A/D CONVERTER www..com (4) A/D converter channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 ADA0S 0 R/W 6 0 Address: FFFFF202H 5 0 4 0 3 ADA0S3 2 ADA0S2 1 ADA0S1 0 ADA0S0 ADA0S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADA0S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADA0S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADA0S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Select mode ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 Setting prohibited Scan mode ANI0 ANI0, ANI1 ANI0 to ANI2 ANI0 to ANI3 ANI0 to ANI4 ANI0 to ANI5 ANI0 to ANI6 ANI0 to ANI7 ANI0 to ANI8 ANI0 to ANI9 ANI0 to ANI10 ANI0 to ANI11 ANI0 to ANI12 ANI0 to ANI13 ANI0 to ANI14 ANI0 to ANI15 Other than above 406 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www.DataShee (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read from the higher 10 bits of the ADA0CRn register, and 0 is read from the lower 6 bits. The higher 8 bits of the conversion result are read from the ADA0CRnH register. Caution Accessing the ADA0CRn and ADA0CRnH registers is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: Undefined R Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H, ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H, ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH, ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH, ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H, ADA0CR10 FFFFF224H, ADA0CR11 FFFFF226H, ADA0CR12 FFFFF228H, ADA0CR13 FFFFF22AH, ADA0CR14 FFFFF22CH, ADA0CR15 FFFFF22EH 15 14 13 12 11 10 9 8 7 6 5 0 4 0 3 0 2 0 1 0 0 0 ADA0CRn AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 After reset: Undefined R Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H, ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H, ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH, ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH, ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H, ADA0CR10H FFFFF225H, ADA0CR11H FFFFF227H, ADA0CR12H FFFFF229H, ADA0CR13H FFFFF22BH, ADA0CR14H FFFFF22DH, ADA0CR15H FFFFF22FH 7 ADA0CRnH 6 AD8 5 AD7 4 AD6 3 AD5 2 AD4 1 AD3 0 AD2 AD9 Remark Caution n = 0 to 15 A write operation to the ADA0M0 and ADA0S registers may cause the contents of the ADA0CRn register to become undefined. After the conversion, read the conversion result before writing to the ADA0M0 and ADA0S registers. Correct conversion results may not be read if a sequence other than the above is used. Preliminary User's Manual U17718EJ1V0UD 407 CHAPTER 11 A/D CONVERTER www..com The relationship between the analog voltage input to the analog input pins (ANI0 to ANI23) and the A/D conversion result (ADA0CRn register) is as follows. VIN AVREF0 SAR = INT ( x 1,024 + 0.5) ADA0CR Or, Note = SAR x 64 (SAR - 0.5) x AVREF0 1,024 VIN < (SAR + 0.5) x AVREF0 1,024 INT( ): VIN: AVREF0: Function that returns the integer of the value in ( ) Analog input voltage AVREF0 pin voltage ADA0CR: Value of ADA0CRn register Note The lower 6 bits of the ADA0CRn register are fixed to 0. The following shows the relationship between the analog input voltage and the A/D conversion results. Figure 11-2. Relationship Between Analog Input Voltage and A/D Conversion Results SAR ADA0CRn 1,023 FFC0H 1,022 FF80H A/D conversion results 1,021 FF40H 3 00C0H 2 0080H 1 0040H 0 0000H 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 1 2,048 1,024 2,048 1,024 2,048 Input voltage/AVREF0 408 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 ADA0PFM R/W 6 Address: FFFFF204H 5 0 4 0 3 0 2 0 1 0 0 0 ADA0PFE ADA0PFC ADA0PFE 0 1 Selection of power-fail compare enable/disable Power-fail compare disabled Power-fail compare enabled ADA0PFC 0 1 Selection of power-fail compare mode Generates an interrupt request signal (INTAD) when ADA0CRnH ADA0PFT Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the value of the ADA0CRnH register specified by the ADA0S register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register and the INTAD signal is generated. If it does not match, however, the interrupt signal is not generated. 2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the contents of the ADA0CR0H register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, however, the INTAD signal is not generated. Regardless of the comparison result, the scan operation is continued and the conversion result is stored in the ADA0CRn register until the scan operation is completed. However, the INTAD signal is not generated after the scan operation has been completed. (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 ADA0PFT R/W 6 Address: FFFFF205H 5 4 3 2 1 0 Preliminary User's Manual U17718EJ1V0UD 409 CHAPTER 11 A/D CONVERTER www..com 11.5 Operation 11.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode. <2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until A/D conversion is complete. <4> Set bit 9 of the successive approximation register (SAR) to set the compare voltage generation DAC to (1/2) AVREF0. <5> The voltage difference between the compare voltage generation DAC and the analog input voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the SAR register remains set. If it is lower than (1/2) AVREF0, the MSB is reset. <6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the value of bit 9, to which a result has been already set, the compare voltage generation DAC is selected as follows. * Bit 9 = 1: (3/4) AVREF0 * Bit 9 = 0: (1/4) AVREF0 This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. Analog input voltage Compare voltage: Bit 8 = 1 Analog input voltage Compare voltage: Bit 8 = 0 <7> This comparison is continued to bit 0 of the SAR register. <8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal (INTAD) is generated. 410 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com 11.5.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits. (1) Software trigger mode When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI15) specified by the ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated. If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous select/scan mode, the next conversion is started, unless the ADA0CE bit is cleared to 0 after completion of the first conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan mode. When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress). If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is aborted and started again from the beginning. (2) External trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI15) specified by the ADA0S register is started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits for the trigger, and starts conversion after the external trigger has been input. When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of whether the continuous select, continuous scan, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation, the conversion is not aborted, and the A/D converter waits for the trigger again. Preliminary User's Manual U17718EJ1V0UD 411 CHAPTER 11 A/D CONVERTER www..com (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI15) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer. The INTTP2CC0 or INTTP2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. When conversion is completed, regardless of whether the continuous select, continuous scan, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is stopped and the A/D converter waits for the trigger again. 412 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com 11.5.3 Operation mode Three operation modes are available as the modes in which to set the ANI0 to ANI15 pins: continuous select mode, continuous scan mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 15). Figure 11-3. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H) ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A/D conversion Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) Data 7 (ANI1) ADA0CR1 Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values. The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated, and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0 (n = 0 to 15). Preliminary User's Manual U17718EJ1V0UD 413 CHAPTER 11 A/D CONVERTER www..com Figure 11-4. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 7 Data 3 ANI2 Data 5 Data 6 ANI3 Data 4 A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) Data 7 (ANI2) ADA0CRn Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 . . . . ANI13 ANI14 ANI15 A/D converter ADA0CRn register ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 . . . ADA0CR13 ADA0CR14 ADA0CR15 414 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (3) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values. Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated. A/D conversion is stopped after it has been completed (n = 0 to 15). Preliminary User's Manual U17718EJ1V0UD 415 CHAPTER 11 A/D CONVERTER www..com Figure 11-5. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 7 ANI2 Data 3 Data 5 Data 6 ANI3 Data 4 A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) ADA0CRn Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) INTAD Conversion start Set ADA0CE bit = 1 Conversion end (b) Block diagram Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 . . . . ANI13 ANI14 ANI15 A/D converter ADA0CRn register ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 . . . ADA0CR13 ADA0CR14 ADA0CR15 416 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com 11.5.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. * When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter). * When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH ADA0PFT. * When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH < ADA0PFT. Remark n = 0 to 15 In the power-fail compare mode, three modes are available as modes in which to set the ANI0 to ANI15 pins: continuous select mode, continuous scan mode, and one-shot scan mode. Preliminary User's Manual U17718EJ1V0UD 417 CHAPTER 11 A/D CONVERTER www..com (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 15). Figure 11-6. Timing Example of Continuous Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A/D conversion Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) Data 7 (ANI1) ADA0CR1 Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 6 (ANI1) INTAD ADA0PFT unmatch Conversion start Set ADA0CE bit = 1 ADA0PFT unmatch ADA0PFT match ADA0PFT ADA0PFT match match Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the ADA0CE bit is cleared to 0. 418 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com Figure 11-7. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 7 Data 3 ANI2 Data 5 Data 6 ANI3 Data 4 A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) Data 7 (ANI2) ADA0CRn Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) INTAD ADA0PFT match Conversion start Set ADA0CE bit = 1 ADA0PFT unmatch (b) Block diagram Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 . . . . ANI13 ANI14 ANI15 A/D converter ADA0CRn register ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 . . . ADA0CR13 ADA0CR14 ADA0CR15 Preliminary User's Manual U17718EJ1V0UD 419 CHAPTER 11 A/D CONVERTER www..com (3) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD0 signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of converting the signals on the analog input pins specified by the ADA0S register are sequentially stored. The conversion is stopped after it has been completed. 420 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com Figure 11-8. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 7 ANI2 Data 3 Data 5 Data 6 ANI3 Data 4 A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) ADA0CRn Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) INTAD ADA0PFT match Conversion start Set ADA0CE bit = 1 Conversion end (b) Block diagram Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 . . . . ANI13 ANI14 ANI15 A/D converter ADA0CRn register ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 . . . ADA0CR13 ADA0CR14 ADA0CR15 Preliminary User's Manual U17718EJ1V0UD 421 CHAPTER 11 A/D CONVERTER www..com 11.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI15 pins Input the voltage within the specified range to the ANI0 to ANI15 pins. If a voltage equal to or higher than AVREF0 or equal to or lower than AVSS (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) Countermeasures against noise To maintain the 10-bit resolution, the ANI0 to ANI15 pins must be effectively protected from noise. The influence of noise increases as the output impedance of the analog input source becomes higher. To lower the noise, connecting an external capacitor as shown in Figure 11-9 is recommended. Figure 11-9. Processing of Analog Input Pin Clamp with a diode with a low VF (0.3 V or less) if noise equal to or higher than AVREF0 or equal to or lower than AVSS may be generated. VDD AVREF0 ANI0 to ANI15 AVSS VSS (4) Alternate I/O The analog input pins (ANI0 to ANI15) function alternately as port pins. When selecting one of the ANI0 to ANI15 pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. Also the conversion resolution may drop at the pins set as output port pins during A/D conversion if the current flows due to the effect of the external circuit connected to the port pins. If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D conversion value may not be as expected due to the influence of coupling noise. Therefore, do not apply a pulse to a pin adjacent to the pin undergoing A/D conversion. 422 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the ADIF flag may be set even though the A/D conversion of the newly selected analog input pin has not been completed. When A/D conversion is stopped, clear the ADIF flag before resuming conversion. Figure 11-10. Generation Timing of A/D Conversion End Interrupt Request ADA0S rewriting (ANIn conversion start) ADA0S rewriting (ANIm conversion start) ADIF is set, but ANIm conversion does not end A/D conversion ANIn ANIn ANIm ANIm ADA0CRn ANIn ANIn ANIm ANIm INTAD Remark n = 0 to 15 m = 0 to 15 (6) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 11-11. Internal Equivalent Circuit of ANIn Pin RIN ANIn CIN RIN TBD CIN TBD Remark n = 0 to 15 Preliminary User's Manual U17718EJ1V0UD 423 CHAPTER 11 A/D CONVERTER www..com (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as VDD to the AVREF0 pin as shown in Figure 11-12. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to the AVREF0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop. To avoid this, it is recommended to connect a capacitor across the AVREF0 and AVSS pins to suppress the reference voltage fluctuation as shown in Figure 11-12. (c) If the source supplying power to the AVREF0 pin has a high DC resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the A/D conversion current. Figure 11-12. AVREF0 Pin Processing Example Note AVREF0 Main power supply AVSS Note Parasitic inductance (8) Reading ADA0CRn result When the ADA0M0 to ADA0M2 or ADA0S register is written, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to ADA0M2 and ADA0S registers. The correct conversion result may not be read at a timing different from the above. (9) A/D conversion result If there is noise at the analog input pins and at the reference voltage input pins, that noise may generate an illegal conversion result. Software processing will be needed to avoid a negative effect on the system from this illegal conversion result. An example of this software processing is shown below. * Take the average result of a number of A/D conversions and use that as the A/D conversion result. * Execute a number of A/D conversions consecutively and use those results, omitting any exceptional results that may have been obtained. * If an A/D conversion result that is judged to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 424 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (10) Variation of A/D conversion results The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. To reduce the variation, take counteractive measures with the program such as averaging the A/D conversion results. (11) A/D conversion result hysteresis characteristics The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. As a result, the following phenomena may occur. * When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. Thus, even if the conversion is performed at the same potential, the result may vary. * When switching the analog input channel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions. Thus, even if the conversion is performed at the same potential, the result may vary. Preliminary User's Manual U17718EJ1V0UD 425 CHAPTER 11 A/D CONVERTER www..com 11.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%FSR = (Maximum value of convertible analog input voltage - Minimum value of convertible analog input voltage)/100 = (AVREF0 - 0)/100 = AVREF0/100 When the resolution is 10 bits, 1 LSB is as follows: 1 LSB = 1/210 = 1/1,024 = 0.098%FSR The accuracy is determined by the overall error, independently of the resolution. (2) Overall error This is the maximum value of the difference between an actually measured value and a theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. The overall error in the characteristics table does not include the quantization error. Figure 11-13. Overall Error 1......1 Ideal line Digital output Overall error 0......0 0 Analog input AVREF0 426 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (3) Quantization error This is an error of 1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of 1/2 LSB into the same digital codes, a quantization error is unavoidable. This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. Figure 11-14. Quantization Error 1......1 Digital output 1/2 LSB 1/2 LSB Quantization error 0......0 0 Analog input AVREF0 (4) Zero-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0...000 to 0...001 (1/2 LSB). Figure 11-15. Zero-Scale Error 111 Digital output (lower 3 bits) Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 AVREF0 Analog input (LSB) Preliminary User's Manual U17718EJ1V0UD 427 CHAPTER 11 A/D CONVERTER www..com (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1...110 to 1...111 (full scale - 3/2 LSB). Figure 11-16. Full-Scale Error Full-scale error Digital output (lower 3 bits) 111 100 011 010 000 0 AVREF0 - 3 AVREF0 - 2 AVREF0 - 1 AVREF0 Analog input (LSB) (6) Differential linearity error Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually measured value and its theoretical value when a specific code is output. This indicates the basic characteristics of the A/D conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from AVSS to AVREF0. When the input voltage is increased or decreased, or when two or more channels are used, see 11.7 (2) Overall error. Figure 11-17. Differential Linearity Error 1......1 Ideal width of 1 LSB Digital output Differential linearity error 0......0 AVREF0 Analog input 428 Preliminary User's Manual U17718EJ1V0UD CHAPTER 11 A/D CONVERTER www..com (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 11-18. Integral Linearity Error 1......1 Ideal line Digital output Integral linearity error 0......0 0 Analog input AVREF0 (8) Conversion time This is the time required to obtain a digital output after each trigger has been generated. The conversion time in the characteristics table includes the sampling time. (9) Sampling time This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit. Figure 11-19. Sampling Time Sampling time Conversion time Preliminary User's Manual U17718EJ1V0UD 429 www..com CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) The V850ES/HG2 includes asynchronous serial interface A (UARTA). 12.1 Features Transfer rate: 300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTAn receive data register (UAnRX) Internal UARTAn transmit data register (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin Reception error output function * Parity error * Framing error * Overrun error Interrupt sources: 2 * Reception complete interrupt (INTUAnR): An interrupt is generated in the reception enabled status by ORing three types of reception errors. It is also generated when receive data is transferred from the receive shift register to the receive data register after completion of serial transfer. * Transmission enable interrupt (INTUAnT): This interrupt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. Character length: 7, 8 bits Parity function: Odd, even, 0, none Transmission stop bit: 1, 2 bits On-chip dedicated baud rate generator MSB-/LSB-first transfer selectable Transmit/receive data inverted input/output possible SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format possible * 13 to 20 bits selectable for SBF transmission * Recognition of 11 bits or more possible for SBF reception * SBF reception flag provided Remark n = 0 to 2 430 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.2 Configuration The block diagram of the UARTAn is shown below. Figure 12-1. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR UAnRX Reception unit Transmission unit UAnTX Receive shift register Reception controller Transmission controller Transmit shift register Filter Baud rate generator Baud rate generator Selector TXDAn RXDAn Selector Clock selector fXX to fXX/210 ASCKA0Note UAnCTL1 UAnCTL2 UAnCTL0 UAnSTR UAnOTP0 Internal bus Note UARTA0 only Remarks 1. n = 0 to 2 2. For the configuration of the baud rate generator, see Figure 12-13. UARTAn includes the following hardware units. Table 12-1. Configuration of UARTAn Item Registers Configuration UARTAn control register 0 (UAnCTL0) UARTAn control register 1 (UAnCTL1) UARTAn control register 2 (UAnCTL2) UARTAn option control register 0 (UAnOPT0) UARTAn status register (UAnSTR) UARTAn receive shift register UARTAn receive data register (UAnRX) UARTAn transmit shift register UARTAn transmit data register (UAnTX) Preliminary User's Manual U17718EJ1V0UD 431 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn. (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register used to control serial transfer for the UARTAn. (5) UARTAn status register (UAnSTR) The UAnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the UAnSTR register. (6) UARTAn receive shift register This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the UAnRX register. This register cannot be manipulated directly. (7) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the highest bit (when data is received LSB first). In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the UAnRX register in synchronization with the completion of shift-in processing of 1 frame. Transfer to the UAnRX register also causes the reception complete interrupt request signal (INTUAnR) to be output. (8) UARTAn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX register into serial data. When 1 byte of data is transferred from the UAnTX register, the shift register data is output from the TXDAn pin. This register cannot be manipulated directly. (9) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal (INTUAnT) is generated. 432 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.3 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H. (1/2) After reset: 10H R/W Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H, UA2CTL0 FFFFFA20H 7 6 5 4 3 2 1 UAnCL 0 UAnCTL0 (n = 0 to 2) UAnPWR UAnTXE UAnRXE UAnDIR UAnPS1 UAnPS0 UAnSL UAnPWR 0 1 UARTAn operation control Disable UARTAn operation (UARTAn reset asynchronously) Enable UARTAn operation The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if UAnOPT0.UAnTDL bit = 1). UAnTXE 0 1 Transmission operation enable Disable transmission operation Enable transmission operation * To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1. To stop, transmission clear the UAnTXE bit to 0 and then UAnPWR bit to 0. * To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of the base clock, and then set the UAnTXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 12.6 (1) (a) Base clock). UAnRXE 0 1 Reception operation enable Disable reception operation Enable reception operation * To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1. To stop reception, clear the UAnRXE bit to 0 and then UAnPWR bit to 0. * To initialize the reception unit, clear the UAnRXE bit to 0, wait for two periods of the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 12.6 (1) (a) Base clock). Preliminary User's Manual U17718EJ1V0UD 433 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (2/2) UAnDIR 0 1 MSB-first transfer LSB-first transfer Transfer direction selection This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. UAnPS1 UAnPS0 Parity selection during transmission Parity selection during reception 0 0 1 1 0 1 0 1 No parity output 0 parity output Odd parity output Even parity output Reception with no parity Reception with 0 parity Odd parity check Even parity check * This register is rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. * If "Reception with 0 parity" is selected during reception, a parity check is not performed. Therefore, the UAnSTR.UAnPE bit is not set. * When transmission and reception are performed in the LIN format, clear the UAnPS1 and UAnPS0 bits to 00. UAnCL 0 1 Specification of data character length of 1 frame of transmit/receive data 7 bits 8 bits This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. UAnSL 0 1 1 bit 2 bits Specification of length of stop bit for transmit data This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. Remark For details of parity, see 12.5.9 Parity types and operations. 434 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (2) UARTAn control register 1 (UAnCTL1) For details, see 12.6 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 12.6 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H. (1/2) After reset: 14H R/W Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H, UA2OPT0 FFFFFA23H 7 6 5 4 3 2 1 0 UAnOPT0 (n = 0 to 2) UAnSRF UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL UAnSRF 0 1 SBF reception flag When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set. Also upon normal end of SBF reception. During SBF reception * SBF (Sync Break Field) reception is judged during LIN communication. * The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF reception is started again. UAnSRT 0 1 SBF reception trigger SBF reception trigger - * This is the SBF reception trigger bit during LIN communication, and when read, "0" is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF reception. * Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1. UAnSTT 0 1 SBF transmission trigger SBF transmission trigger - * This is the SBF transmission trigger bit during LIN communication, and when read, "0" is always read. * Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1. Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1). Preliminary User's Manual U17718EJ1V0UD 435 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (2/2) UAnSLS2 UAnSLS1 UAnSLS0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 SBF transmit length selection 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0. UAnTDL 0 1 Transmit data level bit Normal output of transfer data Inverted output of transfer data * The output level of the TXDAn pin can be inverted using the UAnTDL bit. * This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0. UAnRDL 0 1 Receive data level bit Normal input of transfer data Inverted input of transfer data * The input level of the RXDAn pin can be inverted using the UAnRDL bit. * This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0. (5) UARTAn status register (UAnSTR) The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the UAnPE, UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). The initialization conditions are shown below. Register/Bit UAnSTR register * Reset * UAnCTL0.UAnPWR = 0 UAnTSF bit UAnPE, UAnFE, UAnOVE bits * UAnCTL0.UAnTXE = 0 * 0 write * UAnCTL0.UAnRXE = 0 Initialization Conditions 436 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com After reset: 00H R/W Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H 7 6 0 5 0 4 0 3 0 2 UAnPE 1 UAnFE 0 UAnSTR (n = 0 to 2) UAnTSF UAnOVE UAnTSF 0 Transfer status flag * When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. * When, following transfer completion, there was no next data transfer from UAnTX register Write to UAnTX register 1 The UAnTSF bit is always 1 when performing continuous transmission. When initializing the transmission unit, check that the UAnTSF bit = 0 before performing initialization. The transmit data is not guaranteed when initialization is performed while the UAnTSF bit = 1. UAnPE 0 1 Parity error flag * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set. * When 0 has been written When parity of data and parity bit do not match during reception. * The operation of the UAnPE bit is controlled by the settings of the UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits. * The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UAnFE 0 1 Framing error flag * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set * When 0 has been written When no stop bit is detected during reception * Only the first bit of the receive data stop bits is checked, regardless of the value of the UAnCTL0.UAnSL bit. * The UAnFE bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UAnOVE 0 1 Overrun error flag * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set. * When 0 has been written When receive data has been set to the UAnRX register and the next receive operation is completed before that receive data has been read * When an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. * The UAnOVE bit can be both read and written, but it can only be cleared by writing 0 to it. When 1 is written to this bit, the value is retained. Preliminary User's Manual U17718EJ1V0UD 437 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data. During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the UAnRX register and the MSB always becomes 0. During MSB-first reception, the receive data is transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0. When an overrun error (UAnOVE) occurs, the receive data at this time is not transferred to the UAnRX register and is discarded. This register is read-only, in 8-bit units. In addition to reset input, the UAnRX register can be set to FFH by clearing the UAnCTL0.UAnPWR bit to 0. After reset: FFH R Address: UA0RX FFFFFA06H, UA1RX FFFFFA16H, UA2RX FFFFFA26H 7 6 5 4 3 2 1 0 UAnRX (n = 0 to 2) (7) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit register used to set transmit data. This register can be read or written in 8-bit units. Reset sets this register to FFH. After reset: FFH R/W Address: UA0TX FFFFFA07H, UA1TX FFFFFA17H, UA2TX FFFFFA27H 7 6 5 4 3 2 1 0 UAnTX (n = 0 to 2) 438 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.4 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. * Reception complete interrupt request signal (INTUAnR) * Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal. Table 12-2. Interrupts and Their Default Priorities Interrupt Reception complete Transmission enable Priority High Low (1) Reception complete interrupt request signal (INTUAnR) A reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the UAnRX register in the reception enabled status. When a reception complete interrupt request signal is received and the data is read, read the UAnSTR register and check that the reception result is not an error. No reception complete interrupt request signal is generated in the reception disabled status. (2) Transmission enable interrupt request signal (INTUAnT) If transmit data is transferred from the UAnTX register to the UARTAn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. Preliminary User's Manual U17718EJ1V0UD 439 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5 Operation 12.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 12-2, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UAnCTL0 register. Moreover, control of UART output/inverted output for the TXDAn bit is performed using the UAnOPT0.UAnTDL bit. * Start bit..................1 bit * Character bits ........7 bits/8 bits * Parity bit ................Even parity/odd parity/0 parity/no parity * Stop bit ..................1 bit/2 bits 440 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com Figure 12-2. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inversion 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity Stop bit bit Stop bit (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Preliminary User's Manual U17718EJ1V0UD 441 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.2 SBF transmission/reception format The V850ES/HG2 has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 12-3 and 12-4 outline the transmission and reception manipulations of LIN. Figure 12-3. LIN Transmission Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field DATA field Check SUM field LIN bus Note 3 8 bits Note 1 Note 2 13 bits 55H transmission Data transmission Data transmission Data transmission Data transmission TXDAn (output) SBF transmissionNote 4 INTUAnT interrupt Notes 1. The interval between each field is controlled by software. 2. SBF output is performed by hardware. The output width is the bit length set by the If even finer output width adjustments are UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits. bits. 3. 80H transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. A transmission enable interrupt request signal (INTUAnT) is output at the start of each transmission. The INTUAnT signal is also output at the start of each SBF transmission. required, such adjustments can be performed using the UAnCTLn.UAnBRS7 to UAnCTLn.UAnBRS0 442 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com Figure 12-4. LIN Reception Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field DATA field Check SUM field LIN bus Note 2 13 bits SF reception ID reception Data transmission Data Note 5 transmission Data transmission RXDAn (input) Disable Enable SBF reception Note 3 Reception interrupt (INTUAnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes 1. The wakeup signal is sent by the pin edge detector, UARTAn is enabled, and the SBF reception mode is set. 2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal is output, and the mode returns to the SBF reception mode. 3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF reception complete interrupt. Moreover, error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing and UARTAn receive shift register and data transfer of the UAnRX register are not performed. The UARTAn receive shift register holds the initial value, FFH. 4. The RXDAn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. The value of the UAnCTL2 register obtained by correcting the baud rate error after dropping UARTA enable is set again, causing the status to become the reception status. 5. Check-sum field distinctions are made by software. UARTAn is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. Preliminary User's Manual U17718EJ1V0UD 443 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is output. A transmission enable interrupt request signal (INTUAnT) is generated upon SBF transmission start. Following the end of SBF transmission, the UAnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to the UAnTX register, or until the SBF transmission trigger (UAnSTT bit) is set. Figure 12-5. SBF Transmission TXDAn 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop bit INTUAnT interrupt Setting of UAnSTT bit 444 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed. Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception complete interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF reception ends. Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing is not performed. Moreover, data transfer of the UARTAn receive shift register and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to. The UAnSRF bit is not cleared at this time. Figure 12-6. SBF Reception (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) RXDAn 1 2 3 4 5 6 7 8 9 10 11 11.5 UAnSRF INTUAnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDAn 1 2 3 4 5 6 7 8 9 10 10.5 UAnSRF INTUAnR interrupt Preliminary User's Manual U17718EJ1V0UD 445 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added. Since the CTS (transmit enable signal) input pin is not provided in UARTAn, use a port to check that reception is enabled at the transmit destination. The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit operation. A transmission enable interrupt request signal (INTUAnT) is generated upon completion of transmission of the data of the UAnTX register to the UARTAn transmit shift register, and thereafter the contents of the UARTAn transmit shift register are output to the TXDAn pin. Write of the next transmit data to the UAnTX register is enabled after the INTUAnT signal is generated. Figure 12-7. UART Transmission TXDAn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUAnT Remarks 1. LSB first 2. n = 0 to 2 446 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT). An efficient communication rate is realized by writing the data to be transmitted next to the UAnTX register during transfer. During continuous transmission, do not write the next transmit data to the UAnTX register before a transmit request interrupt signal (INTUAnT) is generated after transmit data is written to the UAnTX register and transferred to the UARTAn transmit shift register. If a value is written to the UAnTX register before a transmit request interrupt signal is generated, the previously set transmit data is overwritten by the latest transmit data. Caution When initializing transmissions during the execution of continuous transmissions, make sure that the UAnSTR.UAnTSF bit is 0, then perform the initialization. Transmit data that is initialized when the UAnTSF bit is 1 cannot be guaranteed. In the case of continuous transmission, the communication rate from the stop bit to the start bit of the next data is extended by two operating clocks from the normal rate. Figure 12-8. Continuous Transmission Processing Flow Start Register settings UAnTX write Occurrence of transmission interrupt? Yes No Required number of writes performed? Yes No End Preliminary User's Manual U17718EJ1V0UD 447 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com Figure 12-9. Continuous Transmission Operation Timing (a) Transmission start TXDAn Start Data (1) Parity Stop Start Data (2) Parity Stop Start UAnTX Data (1) Data (2) Data (3) Transmission shift register Data (1) Data (2) INTUAnT UAnTSF (b) Transmission end TXDAn Parity Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop UAnTX Data (n - 1) Data (n) Transmission shift register Data (n - 1) Data (n) FF INTUAnT UAnTSF UAnPWR or UAnTXE bit 448 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is recognized if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive operation starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate. When the reception complete interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data of the UARTAn receive shift register is written to the UAnRX register. However, if an overrun error (UAnSTR.UAnOVE bit) occurs, the receive data at this time is not written to the UAnRX register and is discarded. Even if a parity error (UAnSTR.UAnPE bit) or a framing error (UAnSTR.UAnFE bit) occurs during reception, reception continues until the reception position of the first stop bit, and INTUAnR is output following reception completion. Figure 12-10. UART Reception RXDAn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUAnR UAnRX Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. The operation during reception is performed assuming that there is only one stop bit. A second stop bit is ignored. 3. When reception is completed, read the UAnRX register after the reception complete interrupt request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If the UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read value of the UAnRX register cannot be guaranteed. 4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data stored in the UAnRX register. To complete reception without waiting INTUAnR signal generation, be sure to clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag (UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0. Preliminary User's Manual U17718EJ1V0UD 449 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs. It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register. Clear the reception error flag by writing 0 to it after reading it. * Receive data read flow START INTUAnR signal generated? Yes No Read UAnRX register Read UAnSTR register No Error occurs? Yes Error processing END Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors. * Reception error causes Error Flag UAnPE UAnFE UAnOVE Reception Error Parity error Framing error Overrun error Cause Received parity bit does not match the setting Stop bit not detected Reception of next data completed before data was read from receive buffer 450 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com When reception errors occur, perform the following procedures depending upon the kind of error. * Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit. * Framing error A baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing each other, and then start the communication again. * Overrun error Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was needed, do a retransmission. Caution If a receive error interrupt occurs during continuous reception, read the contents of the UAnSTR register must be read before the next reception is completed, then perform error processing. Preliminary User's Manual U17718EJ1V0UD 451 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.9 Parity types and operations Caution When using the LIN function, fix the UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected. (a) Even parity (i) During transmission The number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so as to be an even number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 1 * Even number of bits whose value is "1" among transmit data: 0 (ii) During reception The number of bits whose value is "1" among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) Odd parity (i) During transmission Opposite to even parity, the number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 0 * Even number of bits whose value is "1" among transmit data: 1 (ii) During reception The number of bits whose value is "1" among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity During transmission, the parity bit is always made 0, regardless of the transmit data. During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (d) No parity No parity bit is added to the transmit data. Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit. 452 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.5.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 12-12). See 12.6 (1) (a) Base clock regarding the base clock. Moreover, since the circuit is as shown in Figure 12-11, the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. Figure 12-11. Noise Filter Circuit Base clock (fUCLK) RXDAn In Q Internal signal A In Q Internal signal B In Q Internal signal C Match detector LD_EN Figure 12-12. Timing of RXDAn Signal Judged as Noise Base clock RXDAn (input) Internal signal A Internal signal B Match Mismatch (judged as noise) Match Mismatch (judged as noise) Internal signal C Preliminary User's Manual U17718EJ1V0UD 453 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.6 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception. (1) Baud rate generator configuration Figure 12-13. Configuration of Baud Rate Generator UAnPWR fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 ASCKA0Note UAnPWR, UAnTXEn bits (or UAnRXE bit) Selector fUCLK 8-bit counter Match detector 1/2 Baud rate UAnCTL1: UAnCKS3 to UAnCKS0 UAnCTL2: UAnBRS7 to UAnBRS0 Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited. Remarks 1. n = 0 to 2 2. fXX: Main clock frequency 3. fUCLK: Base clock frequency (a) Base clock When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (fUCLK). (b) Serial clock generation A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 2). The base clock is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits. The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits. 454 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register. After reset: 00H R/W Address: UA0CTL1 FFFFFA01H, UA1CTL1 FFFFFA11H, UA2CTL1 FFFFFA21H 7 6 0 5 0 4 0 3 2 1 0 UAnCTL1 (n = 0 to 2) 0 UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0 UAnCKS3 UAnCKS2 UAnCKS1UAnCKS0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 Base clock (fUCLK) selection fXX/1,024 External clockNote (ASCKA0 pin) Setting prohibited Other than above Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited. Remark fXX: Main clock frequency Preliminary User's Manual U17718EJ1V0UD 455 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to 00 before rewriting the UAnCTL2 register. After reset FFH R/W Address: UA0CTL2 FFFFFA02H, UA1CTL2 FFFFFA12H, UA2CTL2 FFFFFA22H 7 6 5 4 3 2 1 0 UAnCTL2 (n = 0 to 2) UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0 UAn BRS7 0 0 0 0 : 1 1 1 1 UAn BRS6 0 0 0 0 : 1 1 1 1 UAn BRS5 0 0 0 0 : 1 1 1 1 UAn BRS4 0 0 0 0 : 1 1 1 1 UAn BRS3 0 0 0 0 : 1 1 1 1 UAn BRS2 0 1 1 1 : 1 1 1 1 UAn BRS1 x 0 0 1 : 0 0 1 1 UAn Default BRS0 (k) x 0 1 0 : 0 1 0 1 x 4 5 6 : 252 253 254 255 Serial clock Setting prohibited fUCLK/4 fUCLK/5 fUCLK/6 : fUCLK/252 fUCLK/253 fUCLK/254 fUCLK/255 Remark fUCLK: Clock frequency selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits 456 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (4) Baud rate The baud rate is obtained by the following equation. Baud rate = fUCLK 2xk [bps] When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation). Baud rate = Remark fXX 2 m+1 xk [bps] fUCLK = Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits fXX: Main clock frequency m = Value set using the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits (m = 0 to 10) k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4 to 255) The baud rate error is obtained by the following equation. Error (%) = Actual baud rate (baud rate with error) Target baud rate (correct baud rate) fUCLK 2 x k x Target baud rate - 1 x 100 [%] = - 1 x 100 [%] When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate the baud rate error using the above equation). fXX Error (%) = 2m+1 x k x Target baud rate - 1 x 100 [%] Cautions 1. The baud rate error during transmission must be within the error tolerance on the receiving side. 2. The baud rate error during reception must satisfy the range indicated in (5) Allowable baud rate range during reception. Preliminary User's Manual U17718EJ1V0UD 457 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com To set the baud rate, perform the following calculation and set the UAnCTL1 and UAnCTL2 registers (when using internal clock). <1> Set k = fXX/(2 x Target baud rate). Set m = 0. <2> Set k = k/2 and m = m + 1 where k 256. <3> Repeat <2> until k < 256. <4> Roundup the first decimal place of k. If k = 256 by the roundup, perform <2> again (k will become 128). <5> Set m to the UAnCTL1 register and k to the UAnCTL2 register. Example: When fXX = 20 MHz and target baud rate = 153,600 bps <1> k = 20,000,000/(2 x 153,600) = 65.10..., m = 0 <2>, <3> k = 65.10... < 256, m = 0 <4> Set value of UAnCTL2 register: k = 65 = 41H, set value of UAnCTL1 register: m = 0 Actual baud rate = 20,000,000/(2 x 65) = 153,846 [bps] Baud rate error = {20,000,000/(2 x 65 x 153,600) - 1} x 100 = 0.160 [%] The representative examples of baud rate settings are shown below. Table 12-4. Baud Rate Generator Setting Data Baud Rate (bps) 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 153,600 312,500 UAnCTL1 08H 07H 06H 05H 04H 03H 02H 01H 01H 00H 00H 00H fXX = 20 MHz UAnCTL2 82H 82H 82H 82H 82H 82H 82H A0H 82H 82H 41H 20H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 0.16 0.00 UAnCTL1 0AH 0AH 09H 08H 07H 06H 05H 01H 00H 03H 02H 00H fXX = 16 MHz UAnCTL2 1AH 0DH 0DH 0DH 0DH 0DH 0DH 80H D0H 0DH 0DH 1AH ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 0.16 -1.54 UAnCTL1 07H 06H 05H 04H 03H 02H 01H 00H 00H 00H 00H 00H fXX = 10 MHz UAnCTL2 82H 82H 82H 82H 82H 82H 82H A0H 82H 41H 21H 10H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 -1.36 0.00 Remark fXX: Main clock frequency ERR: Baud rate error (%) 458 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. Figure 12-14. Allowable Baud Rate Range During Reception Latch timing UARTAn transfer rate Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax Remark n = 0 to 2 As shown in Figure 12-14, the receive data latch timing is determined by the counter set using the UAnCTL2 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. When this is applied to 11-bit reception, the following is the theoretical result. FL = (Brate)-1 Brate: UARTAn baud rate (n = 0 to 2) k: FL: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2) 1-bit data length Latch timing margin: 2 clocks Minimum allowable transfer rate: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Preliminary User's Manual U17718EJ1V0UD 459 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com Therefore, the maximum baud rate that can be received by the destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, obtaining the following maximum allowable transfer rate yields the following. 10 11 x FLmax = 11 x FL - k+2 2xk FL x 11 x FL = 21k - 2 2xk FL FLmax = 21k - 2 20 k Therefore, the minimum baud rate that can be received by the destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. Table 12-4. Maximum/Minimum Allowable Baud Rate Error Division Ratio (k) 4 8 20 50 100 255 Maximum Allowable Baud Rate Error +2.32% +3.52% +4.26% +4.56% +4.66% +4.72% Minimum Allowable Baud Rate Error -2.43% -3.61% -4.30% -4.58% -4.67% -4.72% Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2) 460 Preliminary User's Manual U17718EJ1V0UD CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. Figure 12-15. Transfer Rate During Continuous Transfer 1 data frame Start bit of 2nd byte Start bit FL Bit 0 FL Bit 1 FL Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: fUCLK, we obtain the following equation. FLstp = FL + 2/fUCLK Therefore, the transfer rate during continuous transmission is as follows. Transfer rate = 11 x FL + (2/fUCLK) Preliminary User's Manual U17718EJ1V0UD 461 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) www..com 12.7 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped. However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and UAnCTL0.UAnTXEn bits to 000. (2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0). (3) In UARTAn, the interrupt caused by a communication error does not occur. When performing the transfer of transmit data and receive data using DMA transfer, error processing cannot be performed even if errors (parity, overrun, framing) occur during transfer. for errors. (4) Start up the UARTAn in the following sequence. <1> Set the UAnCTL0.UAnPWR bit to 1. <2> Set the ports. <3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1. (5) Stop the UARTAn in the following sequence. <1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0. <2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if port setting is not changed). (6) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value to the UAnTX register by software because transmission starts by writing to this register. To transmit the same value continuously, overwrite the same value. (7) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. However, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. (8) If the break command is executed in the on-chip debug (OCD) mode and if UART receives data, an overrun error occurs. Either read the UAnSTR register after DMA transfer has been completed to make sure that there are no errors, or read the UAnSTR register during communication to check 462 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) The V850ES/HG2 has two channels of 3-wire serial interface (CSIB). 13.1 Features Transfer rate: 8 Mbps to 4.9 kbps (fXX = 20 MHz, using internal clock) Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCBnT, INTCBnR) x 2 Serial clock and data phase switchable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable 3-wire transfer SOBn: SIBn: Serial data output Serial data input SCKBn: Serial clock I/O Transmission mode, reception mode, and transmission/reception mode specifiable Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 463 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.2 Configuration The following shows the block diagram of CSIBn. Figure 13-1. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 Note CBnTX SCKBn SIBn Shift register SO latch Phase control SOBn INTCBnR Selector Phase control CBnRX Note n = 0: fBRG n = 1: TOP01 n = 2: fXX/128 Remark n = 0, 1 CSIBn includes the following hardware. Table 13-1. Configuration of CSIBn Item Registers Configuration CSIBn receive data register (CBnRX) CSIBn transmit data register (CBnTX) Control registers CSIBn control register 0 (CBnCTL0) CSIBn control register 1 (CBnCTL1) CSIBn control register 2 (CBnCTL2) CSIBn status register (CBnSTR) 464 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register. Reset sets this register to 0000H. In addition to reset input, the CBnRX register can be initialized by clearing (to 0) the CBnPWR bit of the CBnCTL0 register. After reset: 0000H R Address: CB0RX FFFFFD04H, CB1RX FFFFFD14H CBnRX (n = 0, 1) (2) CSIB transmit data register (CBnTX) The CBnTX register is a 16-bit buffer register used to write the CSIBn transfer data. This register can be read or written in 16-bit units. The transmit operation is started by writing data to the CBnTX register in the transmission enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnTXL register. Reset sets this register to 0000H. After reset 0000H R/W Address: CB0TX FFFFFD06H, CB1TX FFFFFD16H CBnTX (n = 0, 1) Remark The communication start conditions are shown below. Transmission mode (CBnTXE bit = 1, CBnRXE bit = 0): Reception mode (CBnTXE bit = 0, CBnRXE bit = 1): Write to CBnTX register Read from CBnRX register Transmission/reception mode (CBnTXE bit = 1, CBnRXE bit = 1): Write to CBnTX register Preliminary User's Manual U17718EJ1V0UD 465 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.3 Registers The following registers are used to control CSIBn. * CSIBn control register 0 (CBnCTL0) * CSIBn control register 1 (CBnCTL1) * CSIBn control register 2 (CBnCTL2) * CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. (1/3) After reset: 01H R/W Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD10H CBnCTL0 (n = 0, 1) CBnPWR CBnTXENote CBnRXENote CBnDIRNote 0 0 CBnTMSNote CBnSCE CBnPWR 0 1 Specification of CSIBn operation disable/enable Disable CSIBn operation and reset the CBnSTR register Enable CSIBn operation * The CBnPWR bit controls the CSIBn operation and resets the internal circuit. CBnTXENote 0 1 Specification of transmit operation disable/enable Disable transmit operation Enable transmit operation * The SOBn output is low level when the CBnTXE bit is 0. CBnRXENote 0 1 Specification of receive operation disable/enable Disable receive operation Enable receive operation * When the CBnRXE bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (CBnRX register) is not updated. Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set at the same time as rewriting these bits. Caution To forcibly suspend transmission/reception, clear the CBnPWR bit instead of the CBnRXE bit to 0. At this time, the clock output is stopped. 466 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (2/3) CBnDIRNote 0 1 Specification of transfer direction mode (MSB/LSB) MSB-first transfer LSB-first transfer CBnTMSNote 0 1 Single transfer mode Transfer mode specification Continuous transfer mode [In single transfer mode] The reception complete interrupt request signal (INTCBnR) is generated. Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt request signal (INTCBnT) is not generated. If the next transmit data is written during communication (CBnSTR.CBnTSF bit = 1), it is ignored and the next communication is not started. Also, if reception-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1), the next communication is not started even if the receive data is read during communication (CBnSTR. CBbTSF bit = 1). [In continuous transfer mode] The continuous transmission is enabled by writing the next transmit data during communication (CBnSTR.CBnTSF bit = 1). Writing the next transmission data is enabled after a transmission enable interrupt (INTCBnT) occurrence. If reception-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1) in the continuous transfer mode, the next reception is started continuously after a reception complete interrupt (INTCBnR) regardless of the read operation of the CBnRX register. Therefore, read immediately the receive data from the CBnRX register. If this read operation is delayed, an overrun error (CBnOVE bit = 1) occurs. Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set at the same time as rewriting these bits. Preliminary User's Manual U17718EJ1V0UD 467 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (3/3) CBnSCE 0 1 Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid * In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation. (b) In single reception mode Clear the CBnSCE bit to 0 before reading the last receive data because reception is started by reading the receive data (CBnRX register) to disable the reception startupNote 1. (c) In continuous reception mode Clear the CBnSCE bit to 0 one communication clock before reception of the last data is completed to disable the reception startup after the last data is receivedNote 2. * In slave mode This bit enables or disables the communication start trigger. Set the CBnSCE bit to 1. [Usage of CBnSCE bit] * In single reception mode <1>When reception of the last data is completed by INTCBnR interrupt servicing, clear the CBnSCE bit to 0 before reading the CBnRX register. <2>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to disable reception. To continue reception, set the CBnSCE bit to 1 to start up the next reception by dummy-reading the CBnRX register. * In continuous reception mode <1>Clear the CBnSCE bit to 0 during the reception of the last data by INTCBnR interrupt servicing. <2>Read the CBnRX register. <3>Read the last reception data by reading the CBnRX register after acknowledging the CBnTIR interrupt. <4>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to disable reception. To continue reception, set the CBnSCE bit to 1 to wait for the next reception by dummy-reading the CBnRX register. Notes 1. If the CBnSCE bit is read while it is 1, the next communication operation is started. 2. The CBnSCE bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication operation is automatically started. Caution Be sure to clear bits 3 and 2 to "0". 468 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0. After reset 00H R/W Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H CBnCTL1 (n = 0, 1) 0 0 0 CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 CBnCKP CBnDAP Communication type 1 Specification of data transmission/ reception timing in relation to SCKBn SCKBn (I/O) SOBn (output) SIBn capture D7 D6 D5 D4 D3 D2 D1 D0 0 0 Communication type 2 0 1 SCKBn (I/O) SOBn (output) SIBn capture D7 D6 D5 D4 D3 D2 D1 D0 Communication type 3 1 0 SCKBn (I/O) SOBn (output) SIBn capture D7 D6 D5 D4 D3 D2 D1 D0 Communication type 4 1 1 SCKBn (I/O) SOBn (output) SIBn capture D7 D6 D5 D4 D3 D2 D1 D0 CBnCKS2 CBnCKS1 CBnCKS0 Communication clock n=0 n=1 Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fBRG Note Master mode Master mode Master mode Master mode Master mode Master mode TMP0 (TOP01) Master mode Slave mode External clock (SCKBn) Note For details, see 13.8 Baud Rate Generator. Preliminary User's Manual U17718EJ1V0UD 469 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0. After reset: 00H R/W Address: CB0CTL2 FFFFFD02H, CB1CTL2 FFFFFD12H CBnCTL2 (n = 0, 1) 0 0 0 0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 CBnCL3 0 0 0 0 0 0 0 0 1 CBnCL2 CBnCL1 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 x CBnCL0 0 1 0 1 0 1 0 1 x 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits Serial register bit length Remarks 1. If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the LSB of the CBnTX and CBnRX registers. 2. x: don't care 470 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) Transfer bit length = 10 bits, MSB first SOBn SIBn 15 10 9 0 Insertion of 0 (ii) Transfer bit length = 12 bits, LSB first SIBn 15 12 11 0 SOBn Insertion of 0 Preliminary User's Manual U17718EJ1V0UD 471 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H. In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit. After reset 00H R/W Address: CB0STR FFFFFD03H, CB1STR FFFFFD13H CBnSTR (n = 0, 1) CBnTSF 0 0 0 0 0 0 CBnOVE CBnTSF 0 1 Communication status flag Communication stopped Communicating * During transmission, this register is set when data is prepared in the CBnTX register, and during reception, it is set when a dummy read of the CBnRX register is performed. When transfer ends, this flag is cleared to 0 at the last edge of the clock. CBnOVE 0 1 No overrun Overrun Overrun error flag * An overrun error occurs when the next reception starts without reading the value of the receive buffer by CPU, upon completion of the receive operation. The CBnOVE flag displays the overrun error occurrence status in this case. * The CBnOVE bit is valid also in the single transfer mode. Therefore, when only using transmission, note the following. * Do not check the CBnOVE flag. * Read this bit even if reading the reception data is not required. * The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it. 472 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.4 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. * Reception complete interrupt request signal (INTCBnR) * Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. Table 13-2. Interrupts and Their Default Priority Interrupt Reception complete Transmission enable Priority High Low (1) Reception complete interrupt request signal (INTCBnR) When receive data is transferred to the CBnRX register while reception is enabled, the reception complete interrupt request signal is generated. This interrupt request signal can also be generated if an overrun error occurs. When the reception complete interrupt request signal is acknowledged and the data is read, read the CBnSTR register to check that the result of reception is not an error. In the single transfer mode, the INTCBnR interrupt request signal is generated upon completion of transmission, even when only transmission is executed. (2) Transmission enable interrupt request signal (INTCBnT) In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from the CBnTX register and, as soon as writing to CBnTX has been enabled, the transmission enable interrupt request signal is generated. In the single transmission and single transmission/reception modes, the INTCBnT interrupt is not generated. Preliminary User's Manual U17718EJ1V0UD 473 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5 Operation 13.5.1 Single transfer mode (master mode, transmission/reception mode) This section shows a case of MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 13.3 (2) CSIBn control register 1 (CBnCTL1), and transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). CBnTX write (55H) CBnRX read (AAH) SCKBn pin CBnTX register 55H (transmit data) Shift register ABH 56H ADH 5AH B5H 6AH D5H AAH CBnRX register AAH 00H INTCBnR signalNote CBnTSF bit CBnSCE bit SIBn pin 1 0 1 0 1 0 1 0 (AAH) SOBn pin 0 1 0 1 0 1 0 1 (55H) (1) (2) (3) (4) (5) (6) (7) (8) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status. (4) Set the CBnPWR bit to 1 to enable the CSIBn operation. (5) Write transfer data to the CBnTX register (transmission start). (6) The reception complete interrupt request signal (INTCBnR) is output. (7) Read the CBnRX register before clearing the CBnPWR bit to 0. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop operation of CSIBn (end of transmission/reception). Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated. When communication is complete, the INTCBnR signal is generated. Remarks 1. The processing of steps (3) and (4) can be set simultaneously. 2. n = 0, 1 474 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.2 Single transfer mode (master mode, reception mode) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 13.3 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). CBnRX read (dummy read) CBnRX read (AAH) SCKBn pin CBnRX register 00H AAH 00H Shift register INTCBnR signal 01H 02H 05H 0AH 15H 2AH 55H AAH SIBn pin SOBn pin L 1 0 1 0 1 0 1 0 (AAH) CBnTSF bit CBnSCE bit (1) (5) (2) (3) (4) (6) (7) (8) (9) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the reception enabled status. (4) Set the CBnPWR bit to 1 to enable the CSIBn operation. (5) Perform a dummy read of the CBnRX register (reception start trigger). (6) The reception complete interrupt request signal (INTCBnR) is output. (7) Set the CBnSCE bit to 0 to set the final receive data status. (8) Read the CBnRX register. (9) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the CSIBn operation (end of reception). Remarks 1. The processing of steps (3) and (4) can be set simultaneously. 2. n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 475 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.3 Continuous mode (master mode, transmission/reception mode) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 3 (see 13.3 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). CBnTX register 55H AAH SCKBn pin SOBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 SIBn pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 INTCBnT signal INTCBnR signal CBnTSF bit CBnSCE bit Shift register CCH 96H SO latch CBnRX register CCH 96H 00H (1) (2) (3) (4) (5) (6) (7) (7) (8) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status. (4) Set the CBnPWR bit to 1 to enable the CSIBn operation. (5) Write transfer data to the CBnTX register (transmission start). (6) The transmission enable interrupt request signal (INTCBnT) is received and transfer data is written to the CBnTX register. (7) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). In transmission mode or transmission/reception mode, the communication is not started by reading the CBnRX register. Remark n = 0, 1 476 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.4 Continuous mode (master mode, reception mode) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 13.3 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). SCKBn pin CBnSCE bit SIBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 INTCnR signal CBnTSF bit Shift register 55H AAH CBnRX register 55H AAH 00H (1) (2) (3) (4) (5) (6) (7) (6) (8) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the reception enabled status. (4) Set the CBnPWR bit to 1 to enable the CSIBn operation. (5) Perform a dummy read of the CBnRX register (reception start trigger). (6) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. (7) Set the CBnCTL0.CBnSCE bit = 0 while the last data being received to set the final receive data status. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of reception). To continue transfer, repeat steps (5) and (6) before (7). Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 477 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.5 Continuous reception mode (error) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 13.3 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). SCKBn pin SIBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 INTCBnR signal CBnTSF bit Shift register 55H AAH CBnRX register 55H AAH 00H CBnOVE bit (1) (2) (3) (4) (5) (6) (7)(8) (9) (10) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the reception enabled status. (4) Set the CBnPWR bit = 1 to enable CSIBn operation. (5) Perform a dummy read of the CBnRX register (reception start trigger). (6) The reception complete interrupt request signal (INTCBnR) is output. (7) If the data could not be read before the end of the next transfer, the CBnSTR.CBnOVE flag is set to 1 upon the end of reception and the INTCBnR signal is output. (8) Overrun error processing is performed after checking that the CBnOVE bit = 1 in the INTCBnR interrupt servicing. (9) Clear CBnOVE bit to 0. (10) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation CSIBn (end of reception). Remark n = 0, 1 478 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.6 Continuous mode (slave mode, transmission/reception mode) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 13.3 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). CBnTX register 55H AAH SCKBn pin SOBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 SIBn pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 INTCBnT signal INTCBnR signal CBnTSF bit CBnSCE bit Shift register CCH 96H SO latch CBnRX register CCH 96H 00H (5) (1) (2) (3) (4) (6) (7) (7) (8) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnTXE, CBnRXE and CBnSCE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status. (4) Set the CBnPWR bit to 1 to enable supply of the CSIBn operation. (5) Write the transfer data to the CBnTX register. (6) The transmission enable interrupt request signal (INTCBnT) is received and the transfer data is written to the CBnTX register. (7) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 479 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.7 Continuous mode (slave mode, reception mode) This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 13.3 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0). SCKBn pin SIBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 INTCBnR signal CBnTSF bit CBnSCE bit Shift register 55H AAH CBnRX register 55H AAH 00H (1) (5) (2) (3) (4) (6) (6) (7) (1) Clear the CBnCTL0.CBnPWR bit to 0. (2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. (3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the reception enabled status. (4) Set the CBnPWR bit = 1 to enable CSIBn operation. (5) Perform a dummy read of the CBnRX register (reception start trigger). (6) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register. When reading the last data, clear the CBnCTL0.CBnSCE bit to 0 before reading the CBnRX register. (7) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of reception). To continue transfer, repeat steps (5) and (6) before (7). Remark n = 0, 1 480 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.5.8 Clock timing (1/2) (1) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit D7 D6 D5 D4 D3 D2 D1 D0 (2) Communication type 2 (CBnCKP = 0, CBnDAP = 1) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit D7 D6 D5 D4 D3 D2 D1 D0 Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. In the single transmission or single transmission/reception mode, the INTCBnT interrupt request signal is not generated, but the INTCBnR interrupt request signal is generated upon completion of communication. 2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of communication. Caution In communication type 2, the CBnTSF bit is cleared half a SCKBn clock after generation of an INTCBnR interrupt request signal. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 481 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (2/2) (3) Communication type 3 (CBnCKP = 1, CBnDAP = 0) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit D7 D6 D5 D4 D3 D2 D1 D0 (4) Communication type 4 (CBnCKP = 1, CBnDAP = 1) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit D7 D6 D5 D4 D3 D2 D1 D0 Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. In the single transmission or single transmission/reception modes, the INTCBnT interrupt request signal is not generated, but the INTCBnR interrupt request signal is generated upon completion of communication. 2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of communication. Caution In communication type 4, the CBnTSF bit is cleared half a SCKBn clock after generation of an INTCBnR interrupt request signal. Remark n = 0, 1 482 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.6 Output Pin Status with Operation Disabled (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKS2 1 CBnCKS1 1 Other than above CBnCKS0 1 CBnCKP x 0 1 SCKBn Pin Output High impedance Fixed to high level Fixed to low level Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and CBnCKS2 to CBnCKS0 bits is rewritten. 2. n = 0, 1 3. x: don't care (2) SOBn pin When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows. CBnTXE 0 1 CBnDAP x 0 1 CBnDIR x x 0 1 SOBn Pin Output Fixed to low level SOBn latch value (low level) CBnTX register value (MSB) CBnTX register value (LSB) Remarks 1. The SOBn pin output changes when any one of the CBnCTL0.CBnTXE, CBnCTL0.CBnDIR bits, and CBnCTL1.CBnDAP bit is rewritten. 2. n = 0, 1 3. x: don't care Preliminary User's Manual U17718EJ1V0UD 483 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.7 Operation Flow (1) Single transmission START Initial setting (CBnCTL0Note, CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR signal is generated? Yes No Yes Transfer data exists? No CBnPWR bit = 0 (CBnCTL0) END Note Set the CBnSCE bit to 1 in the initial setting. Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the CBnTX register is written. Remark n = 0, 1 484 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (2) Single reception START Initial setting (CBnCTL0Note, CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR signal is generated? Yes No Last data? No Yes CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) END Note Set the CBnSCE bit to 1 in the initial setting. Caution In the single mode, data cannot be correctly received if the next transfer clock is input earlier than the CBnRX register is read. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 485 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (3) Single transmission/reception START Initial setting (CBnCTL0Note 1, CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR signal is generated? Yes No Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. No Transfer end? Transfer end? No Transfer end? No Yes Write CBnTX registerNote 2. B B A Yes Write CBnTX registerNote 2. Yes A Write CBnTX registerNote 2. CBnPWR bit = 0, CBnTXE bit = CBnRXE bit = 0 (CBnCTL0) END Notes 1. Set the CBnSCE bit to 1 in the initial setting. 2. If the next transfer is reception only, dummy data is written to the CBnTX register. Caution Even in the single mode, the CBnSTR.CBnOVE flag is set to 1. If only transmission is used in the transmission/reception mode, therefore, checking the CBnOVE flag is not required. Remark n = 0, 1 486 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (4) Continuous transmission START Initial setting (CBnCTL0Note, CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT signal is generated? Yes Data to be transferred next exists? No No Yes CBnTSF bit = 1? (CBnSTR) Yes CBnPWR bit = 0 (CBnCTL0) No END Note Set the CBnSCE bit to 1 in the initial setting. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 487 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (5) Continuous reception START Initial setting (CBnCTL0Note, CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR signal is generated? Yes No CBnRX register read Yes CBnOVE bit = 1? (CBnSTR) No CBnRX register read Is data being received last data? CBnOVE bit clear (CBnSTR) No Yes CBnSCE bit = 0 (CBnCTL0) CBnRX register read INTCBnR signal is generated? Yes CBnRX register read No CBnSCE bit = 1 (CBnCTL0) END Note Set the CBnSCE bit to 1 in the initial setting Caution In the master mode, the clock is output without limit when dummy data is read from the CBnRX register. To stop the clock, execute the flow marked in the above flowchart. In the slave mode, malfunction due to noise during communication can be prevented by executing the flow marked in the above flowchart. Before resuming communication, set the CBnCTL0.CBnSCE bit to 1, and read dummy data from the CBnRX register. Remark n = 0, 1 488 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (6) Continuous transmission/reception START Initial setting (CBnCTL0Note, CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT signal is generated? Yes Is data being transferred last data? No No Yes Write CBnTX register. INTCBnR signal is generated? Yes No CBnRX register read No CBnOVE bit = 0? (CBnSTR) Yes CBnOVE bit clear (CBnSTR) Is data completely received last data? Yes No END Note Set the CBnSCE bit to 1 in the initial setting. Remark n = 0, 1 Preliminary User's Manual U17718EJ1V0UD 489 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.8 Baud Rate Generator The clock generated by the baud rate generator (prescaler 3) is supplied to the watch timer and CSIB0. (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls generation of the baud rate signal for CSIB. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF8B0H PRSM0 0 0 0 BGCE0 0 0 BGCS01 BGCS00 BGCE0 0 1 Disabled Enabled Baud rate output BGCS01 BGCS00 Count clock selection (fBGCS) 5 MHz 4 MHz 250 ns 500 ns 1 s 2 s 0 0 1 1 0 1 0 1 fX fX/2 fX/4 fX/8 200 ns 400 ns 800 ns 1.6 s Cautions 1. Do not rewrite the PRSM0 register while watch timer and CSIB0 are operating. 2. Set the PRSM0 register before setting the BGCE0 bit to 1. 490 Preliminary User's Manual U17718EJ1V0UD CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare registers. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF8B1H PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register while watch timer and CSIB are operating. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 13.8.1 Baud rate generation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. fBRG = 2 fXX k+1 xN Remark fBRG: fXX: k: N: BRG count clock Main clock oscillation frequency PRSM0 register setting value = 0 to 3 PRSCM0 register setting value = 1 to 256 However, N = 256 only when PRSCM0 register is set to 00H. Preliminary User's Manual U17718EJ1V0UD 491 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) www..com 13.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed. (2) In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then initialize CSIBn. Registers to which rewriting during operation are prohibited are shown below. * CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits * CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits * CBnCTL2 register: CBnCL3 to CBnCL0 bits (3) In communication type 2 and 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half a SCKBn clock after occurrence of a reception complete interrupt (INTCBnR). In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1), and the next communication is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0, CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during communication (CBnTSF bit = 1). Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay particular attention to the following. * To start the next transmission, confirm that CBnTSF bit = 0 and then write the transmit data to the CBnTX register. * To perform the next reception continuously when reception-only communication (CBnTXE bit = 0, CBnRXE bit = 1) is set, confirm that CBnTSF bit = 0 and then read the CBnRX register. Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode is recommended especially for using DMA. Remark n = 0, 1 492 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) The V850ES/HG2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM). 14.1 Features * 4 independent DMA channels * Transfer unit: 8/16 bits * Maximum transfer count: 65,536 (216) * Transfer type: Two-cycle transfer * Transfer mode: Single transfer mode * Transfer requests * Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts from external input pin * Requests by software trigger * Transfer targets * Internal RAM Peripheral I/O * Peripheral I/O Peripheral I/O Preliminary User's Manual U17718EJ1V0UD 493 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.2 Configuration Internal RAM On-chip peripheral I/O Internal bus On-chip peripheral I/O bus CPU Data control Address control DMA source address register n (DSAnH/DSAnL) DMA destination address register n (DDAnH/DDAnL) Count control DMA transfer count register n (DBCn) DMA channel control register n (DCHCn) DMA addressing control register n (DADCn) Channel control DMA trigger factor register n (DTFRn) DMAC V850ES/HG2 Remark n = 0 to 3 494 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DSA0H FFFFF082H, DSA1H FFFFF08AH, DSA2H FFFFF092H, DSA3H FFFFF09AH, DSA0L FFFFF080H, DSA1L FFFFF088H, DSA2L FFFFF090H, DSA3L FFFFF098H DSAnH (n = 0 to 3) DSAnL (n = 0 to 3) IR 0 0 0 0 0 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 IR 0 1 Specification of DMA transfer source On-chip peripheral I/O Internal RAM SA25 to SA16 Set the address (A25 to A16) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. SA15 to SA0 Set the address (A15 to A0) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0. 2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are read. If reading and updating conflict, the value being updated may be read (see 14.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. Preliminary User's Manual U17718EJ1V0UD 495 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DDA0H FFFFF086H, DDA1H FFFFF08EH, DA2H FFFFF096H, DDA3H FFFFF09EH, DDA0L FFFFF084H, DDA1L FFFFF08CH, DDA2L FFFFF094H, DDA3L FFFFF09CH DDAnH (n = 0 to 3) DDAnL (n = 0 to 3) IR 0 0 0 0 0 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 IR 0 1 Specification of DMA transfer destination On-chip peripheral I/O Internal RAM DA25 to DA16 Set an address (A25 to A16) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. DA15 to DA0 Set an address (A15 to A0) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0. 2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are read. If reading and updating conflict, a value being updated may be read (see 14.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. 496 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (3) DMA byte count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer. These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H, DBC2 FFFFF0C4H, DBC3 FFFFF0C6H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBCn BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 (n = 0 to 3) BC15 to BC0 0000H 0001H : FFFFH Byte transfer count setting or remaining byte transfer count during DMA transfer Byte transfer count 1 or remaining byte transfer count Byte transfer count 2 or remaining byte transfer count : Byte transfer count 65,536 (216) or remaining byte transfer count The number of transfer data set first is held when DMA transfer is complete. Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. Preliminary User's Manual U17718EJ1V0UD 497 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units. Reset sets these registers to 0000H. After reset: 0000H R/W Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H, DADC2 FFFFF0D4H, DADC3 FFFFF0D6H 15 14 13 12 11 10 9 8 DADCn (n = 0 to 3) 0 7 DS0 6 0 5 0 4 0 3 0 2 0 1 0 0 SAD1 SAD0 DAD1 DAD0 0 0 0 0 DS0 0 1 SAD1 0 0 1 1 DAD1 0 0 1 1 8 bits 16 bits SAD0 0 1 0 1 DAD0 0 1 0 1 Setting of transfer data size Setting of count direction of the transfer source address Increment Decrement Fixed Setting prohibited Setting of count direction of the destination address Increment Decrement Fixed Setting prohibited Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to "0". 2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit data (DS0 bit = 0) is set, therefore, the lower data bus is not always used. 4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an odd address. Transfer is always started from an address with the first bit of the lower address aligned to 0. 5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or destination), be sure to specify the same transfer size as the register size. For example, to execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer. 498 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write-only. If bit 1 or 2 is read, the read value is always 0.) Reset sets these registers to 00H. After reset: 00H R/W Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H, DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H 7 6 5 4 3 2 1 0 DCHCn (n = 0 to 3) TCnNote 1 0 0 0 0 INITnNote 2 STGnNote 2 Enn TCnNote 1 0 1 Status flag indicates whether DMA transfer through DMA channel n has completed or not DMA transfer had not completed. DMA transfer had completed. It is set to 1 on the last DMA transfer and cleared to 0 when it is read. INITnNote 2 If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the DMA transfer status can be initialized. When re-setting the DMA transfer status (re-setting the DDAnH, DDAnL, DSAnH, DSAnL, DBCn, and DADCn registers) before DMA transfer is completed (before the TCn bit is set to 1), be sure to initialize the DMA channel. When initializing the DMA controller, however, be sure to observe the procedure described in 14.13 Cautions. STGnNote 2 This is a software startup trigger of DMA transfer. If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA transfer is started. Enn 0 1 Setting of whether DMA transfer through DMA channel n is to be enabled or disabled DMA transfer disabled DMA transfer enabled DMA transfer is enabled when the Enn bit is set to 1. When DMA transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. To abort DMA transfer, clear the Enn bit to 0 by software. To resume, set the Enn bit to 1 again. When aborting or resuming DMA transfer, however, be sure to observe the procedure described in 14.13 Cautions. Notes 1. The TCn bit is read-only. 2. The INITn and STGn bits are write-only. Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to "0". 2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are being updated, a value indicating "transfer not completed and transfer is disabled" (TCn bit = 0 and Enn bit = 0) may be read. Preliminary User's Manual U17718EJ1V0UD 499 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H, DTFR2 FFFFF814H, DTFR3 FFFFF816H 7 6 5 4 3 2 1 0 DTFRn (n = 0 to 3) DFn 0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 DFnNote 0 1 DMA transfer request flag No DMA transfer request DMA transfer request Note The DFn bit is a write-only bit. Write 0 to this bit to clear a DMA transfer request if an interrupt that is specified as the cause of starting DMA transfer occurs while DMA transfer is disabled. Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 2. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or subIDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1). 3. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA transfer is enabled or disabled. immediately started. Remark For the IFCn5 to IFCn0 bits, see Table 14-1 DMA Start Factors. If DMA is enabled in this status, DMA transfer is 500 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com Table 14-1. DMA Start Factors (1/2) IFCn5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 IFCn4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 IFCn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 IFCn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 IFCn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 IFCn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Interrupt Source DMA request by interrupt disabled INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTTQ0OV INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 INTTP0OV INTTP0CC0 INTTP0CC1 INTTP1OV INTTP1CC0 INTTP1CC1 INTTP2OV INTTP2CC0 INTTP2CC1 INTTP3OV INTTP3CC0 INTTP3CC1 INTTM0EQ0 INTCB0R INTCB0T INTCB1R INTCB1T INTUA0R INTUA0T INTUA1R INTUA1T INTAD INTKR INTTQ1OV Remark n = 0 to 3 Preliminary User's Manual U17718EJ1V0UD 501 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com Table 14-1. DMA Start Factors (2/2) IFCn5 1 1 1 1 1 1 IFCn4 0 0 0 0 0 1 IFCn3 1 1 1 1 1 0 IFCn2 0 1 1 1 1 0 IFCn1 1 0 0 1 1 0 IFCn0 1 0 1 0 1 0 Interrupt Source INTTQ1CC0 INTTQ1CC1 INTTQ1CC2 INTTQ1CC3 INTUA2R INTUA2T Remark n = 0 to 3 502 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.4 Transfer Targets Table 14-2 shows the relationship between the transfer targets (: Transfer enabled, x: Transfer disabled). Table 14-2. Relationship Between Transfer Targets Transfer Destination Internal ROM x x x On-Chip Peripheral I/O Source On-chip peripheral I/O Internal RAM x x x Internal RAM Internal ROM Caution The operation is not guaranteed for combinations of transfer destination and source marked with "x" in Table 14-2. 14.5 Transfer Modes Single transfer is supported as the transfer mode. In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. If a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the CPU (the new transfer request of the same channel is ignored in the transfer cycle). Preliminary User's Manual U17718EJ1V0UD 503 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination. An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows. <16-bit data transfer> <1> Transfer from 32-bit bus 16-bit bus A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a write cycle (16 bits). <2> Transfer from 16-/32-bit bus to 8-bit bus A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> Transfer from 8-bit bus to 16-/32-bit bus An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> Transfer between 16-bit bus and 32-bit bus A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8bit) transfer. Remark The bus width of each transfer target (transfer source/destination) is as follows. * On-chip peripheral I/O: 16-bit bus width * Internal RAM: 32-bit bus width 504 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 14.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below. Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note destination memory access (<2>) DMA Cycle <1> DMA request response time <2> Memory access Internal RAM access Peripheral I/O register access Minimum Number of Execution Clocks 4 clocks (MIN.) + Noise elimination time 2 clocks Note 3 Note 2 1 + Transfer 3 clocks + Number of wait cycles specified by VSWC register Note 4 Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer. 2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is added (n = 0 to 10). 3. Two clocks are required for a DMA cycle. 4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.8 (2)). Preliminary User's Manual U17718EJ1V0UD 505 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3). TCn bit = 0, Enn bit = 1 STGn bit = 1 ... Starts the first DMA transfer. Confirm that the contents of the DBCn register have been updated. STGn bit = 1 ... Starts the second DMA transfer. : Generation of terminal count ... Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated. (2) Request by on-chip peripheral I/O If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA channel. If two start factors are simultaneously generated for one DMA channel, only one of them is valid. The start factor that is valid cannot be identified. 2. A new transfer request that is generated after the preceding DMA transfer request was generated or in the preceding DMA transfer cycle is ignored (cleared). 3. The transfer request interval of the same DMA channel varies depending on the setting of bus wait in the DMA transfer cycle, the start status of the other channels, or the external bus hold request. In particular, as described in Caution 2, a new transfer request that is generated for the same channel before the DMA transfer cycle or during the DMA transfer cycle is ignored. Therefore, the transfer request intervals for the same DMA channel must be sufficiently separated by the system. When the software trigger is used, completion of the DMA transfer cycle that was generated before can be checked by updating the DBCn register. 506 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.10 DMA Abort Factors DMA transfer is aborted if a bus hold occurs. The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/on-chip peripheral I/O. When the bus hold is cleared, DMA transfer is resumed. 14.11 End of DMA Transfer When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). The V850ES/HG2 does not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit. 14.12 Operation Timing Figures 14-1 to 14-4 show DMA operation timing. Preliminary User's Manual U17718EJ1V0UD 507 508 System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit Figure 14-1. Priority of DMA (1) CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) Preliminary User's Manual U17718EJ1V0UD DF1 bit DF2 bit Preparation for transfer CPU processing End processing Preparation for transfer End processing Preparation for transfer DMA transfer Read Idle Write Read Idle Write Read DMA2 processing Mode of processing DMA0 processing CPU processing DMA1 processing CPU processing Remark Transfer in the order of DMA0 DMA1 DMA2 www..com Figure 14-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) Preliminary User's Manual U17718EJ1V0UD DF1 bit DF2 bit Preparation for transfer CPU processing End processing Preparation for transfer End processing Preparation for transfer DMA transfer Read Idle Write Read Idle Write Read DMA0 processing Mode of processing DMA0 processing CPU processing DMA1 processing CPU processing Remark Transfer in the order of DMA0 DMA1 DMA0 (DMA2 is held pending.) www..com 509 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com Figure 14-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer requestNote 1 DFn bit Note 2 Note 2 Note 2 Mode of processing CPU processing DMA0 processing CPU processing DMA transfer Preparation for transfer Read cycle Write cycle Idle End processing Transfer request generated after this can be acknowledged Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit) 2. New DMA request of the same channel is ignored between when the first request is generated and the end processing is complete. 510 Preliminary User's Manual U17718EJ1V0UD Figure 14-4. Period in Which DMA Transfer Request Is Ignored (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) Preliminary User's Manual U17718EJ1V0UD DF1 bit DF2 bit Preparation for transfer CPU processing Preparation for transfer Preparation for transfer DMA transfer Read Idle Write End processing Read Idle Write End processing Read DMA0 processing Mode of processing DMA0 processing CPU processing DMA1 processing CPU processing <1> <2> <3> <4> <1> DMA0 transfer request <2> New DMA0 transfer request is generated during DMA0 transfer. A DMA transfer request of the same channel is ignored during DMA transfer. <3> Requests for DMA0 and DMA1 are generated at the same time. DMA0 request is ignored (a DMA transfer request of the same channel during transfer is ignored). DMA1 request is acknowledged. <4> Requests for DMA0, DMA1, and DMA2 are generated at the same time. DMA1 request is ignored (a DMA transfer request of the same channel during transfer is ignored). DMA0 request is acknowledged according to priority. DMA2 request is held pending (transfer of DMA2 occurs next). www..com 511 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com 14.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System wait control register (VSWC)). (2) Caution for DMA transfer executed on internal RAM When executing the following instructions located in the internal RAM, do not execute a DMA transfer that transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate correctly afterward. * Data access instruction to misaligned address located in internal RAM Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer source/destination), do not execute the above two instructions. (3) Caution for reading DCHCn.TCn bit (n = 0 to 3) The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing. To accurately clear the TCn bit, add the following processing. (a) When waiting for completion of DMA transfer by polling TCn bit Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more times. (b) When reading TCn bit in interrupt servicing routine Execute reading the TCn bit three times. 512 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels Initialize the channel executing DMA transfer using the procedure in <1> to <7> below. Note, however, that TCn bit is cleared to 0 when step <5> is executed. processing programs do not expect that the TCn bit is 1. <1> Disable interrupts (DI). <2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA transfer (transfer source/destination) is the internal RAM, execute the instruction three times. Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal RAM). * Clear DCHC0.E00 bit to 0. * Clear DCHC1.E11 bit to 0. * Clear DCHC2.E22 bit to 0. * Clear DCHC2.E22 bit to 0 again. <4> Set the INITn bit of the channel to be forcibly terminated to 1. <5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0. <6> After the operation in <5>, write the Enn bit value to the DCHCn register. <7> Enable interrupts (EI). Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels whose DMA transfer has been normally completed between <2> and <3>. Make sure that the other Preliminary User's Manual U17718EJ1V0UD 513 CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the pending request is completed. <3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held pending, clear the Enn bit to 0. <4> Again, clear the Enn bit of the channel to be forcibly terminated. If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal RAM, execute this operation once more. <5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register. <6> Set the INITn bit of the channel to be forcibly terminated to 1. <7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. If the two values do not match, repeat operations <6> and <7>. Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. If not, the remaining number of transfers is read. 2. Note that method (b) may take a long time if the application frequently uses DMA transfer for a channel other than the DMA channel to be forcibly terminated. (5) Procedure of temporarily stopping DMA transfer (clearing Enn bit) Stop and resume the DMA transfer under execution using the following procedure. <1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral I/O). <2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0). If a request is pending, wait until execution of the pending DMA transfer request is completed. <3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this operation stops DMA transfer). <4> Set the Enn bit to 1 to resume DMA transfer. <5> Resume the operation of the DMA request source that has been stopped (start the operation of the onchip peripheral I/O). (6) Memory boundary The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the DMA target (internal RAM or on-chip peripheral I/O) during DMA transfer. (7) Transferring misaligned data DMA transfer of misaligned data with a 16-bit bus width is not supported. If an odd address is specified as the transfer source or destination, the least significant bit of the address is forcibly assumed to be 0. 514 Preliminary User's Manual U17718EJ1V0UD CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) www..com (8) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU. However, the CPU can access the on-chip peripheral I/O and internal RAM to/from which DMA transfer is not being executed. (9) Registers/bits that must not be rewritten during DMA operation Set the following registers at the following timing when a DMA operation is not under execution. [Registers] * DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers * DTFRn.IFCn5 to DTFRn.IFCn0 bits [Timing of setting] * Period from after reset to start of the first DMA transfer * Time after channel initialization to start of DMA transfer * Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer (10) Be sure to set the following register bits to 0. * Bits 14 to 10 of DSAnH register * Bits 14 to 10 of DDAnH register * Bits 15, 13 to 8, and 3 to 0 of DADCn register * Bits 6 to 3 of DCHCn register (11) DMA start factor Do not start two or more DMA channels with the same start factor. If two or more channels are started with the same factor, a DMA channel with a lower priority may be acknowledged earlier than a DMA channel with a higher priority. (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately after the DSAnH register is read. (a) If DMA transfer does not occur while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Read value of DSAnL register: DSAnL = FFFFH (b) If DMA transfer occurs while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Occurrence of DMA transfer <3> Incrementing DSAn register: DSAn = 00100000H <4> Read value of DSAnL register: DSAnL = 0000H Preliminary User's Manual U17718EJ1V0UD 515 www..com CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/HG2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 55 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/HG2 can process interrupt request signals from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 15.1 Features Interrupts * Non-maskable interrupts: 2 sources * Maskable interrupts: External: 11, Internal: 42 sources * 8 levels of programmable priorities (maskable interrupts) * Multiple interrupt control according to priority * Masks can be specified for each maskable interrupt request. * Noise elimination, edge detection, and valid edge specification for external interrupt request signals. Exceptions * Software exceptions: 32 sources * Exception trap: 2 sources (illegal opcode exception, debug trap) Interrupt/exception sources are listed in Table 15-1. 516 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Table 15-1. Interrupt Source List (1/2) Type Classification Default Priority - - - Exception - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name Trigger Generating Unit Exception Code Handler Address Restored PC Interrupt Control Register Reset Nonmaskable Software exception Exception Exception trap Maskable Interrupt Interrupt Interrupt RESET NMI INTWDT2 RESET pin input Reset input by internal source NMI pin valid edge input WDT2 overflow Pin WDT2 - - - POCLVI Pin Pin Pin Pin Pin Pin Pin Pin TMQ0 TMQ0 TMQ0 TMQ0 TMQ0 TMP0 TMP0 TMP0 TMP1 TMP1 TMP1 TMP2 TMP2 0010H 0020H 004nHNote 2 005nHNote 2 0060H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01C0H 01D0H 00000010H 00000020H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001AH 000001B0H 000001C0H 000001D0H nextPC Note 1 nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC - - - - - LVIIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PIC7 TQ0OVIC TQ0CCIC0 TQ0CCIC1 TQ0CCIC2 TQ0CCIC3 TP0OVIC TP0CCIC0 TP0CCIC1 TP1OVIC TP1CCIC0 TP1CCIC1 TP2OVIC TP2CCIC0 RESET 0000H 00000000H Undefined - TRAP0nNote 2 TRAP instruction TRAP1nNote 2 TRAP instruction ILGOP/ DBG0 INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTTQ0OV Illegal opcode/ DBTRAP instruction Low voltage detection External interrupt pin input edge detection (INTP0) External interrupt pin input edge detection (INTP1) External interrupt pin input edge detection (INTP2) External interrupt pin input edge detection (INTP3) External interrupt pin input edge detection (INTP4) External interrupt pin input edge detection (INTP5) External interrupt pin input edge detection (INTP6) External interrupt pin input edge detection (INTP7) TMQ0 overflow match INTTQ0CC1 TMQ0 capture 1/compare 1 match INTTQ0CC2 TMQ0 capture 2/compare 2 match INTTQ0CC3 TMQ0 capture 3/compare 3 match INTTP0OV TMP0 overflow INTTQ0CC0 TMQ0 capture 0/compare 0 INTTP0CC0 TMP0 capture 0/compare 0 match INTTP0CC1 TMP0 capture 1/compare 1 match INTTP1OV TMP1 overflow match INTTP1CC1 TMP1 capture 1/compare 1 match INTTP2OV TMP2 overflow match INTTP1CC0 TMP1 capture 0/compare 0 INTTP2CC0 TMP2 capture 0/compare 0 Notes 1. For the restoring in the case of INTWDT2, see 15.2.2 (2) From INTWDT2 signal. 2. n = 0H to FH Preliminary User's Manual U17718EJ1V0UD 517 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Table 15-1. Interrupt Source List (2/2) Type Classification Default Priority Name Trigger Generating Unit Exception Code Handler Address Restored PC Interrupt Control Register Maskable Interrupt 22 23 24 25 26 27 28 29 30 31 32 33 INTTP2CC1 TMP2 capture 1/compare 1 match INTTP3OV TMP3 overflow TMP3 TMP3 TMP3 TMM0 CSIB0 CSIB0 CSIB1 CSIB1 UARTA0 01F0H 0200H 0210H 0220H 0230H 0240H 0250H 0260H 0270H 0280H 0290H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000280H 00000280H 00000290H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC TP3OVIC TP3CCIC0 TP3CCIC1 TM0EQIC0 CB0RIC CB0TIC CB1RIC CB1TIC UA0RIC UA0TIC UA1RIC TMP2 01E0H 000001E0H nextPC TP2CCIC1 INTTP3CC0 TMP3 capture 0/compare 0 match INTTP3CC1 TMP3 capture 1/compare 1 match INTTM0EQ0 TMM0 compare match INTCB0R INTCB0T INTCB1R INTCB1T INTUA0R INTUA0T INTUA1R CSIB0 reception completion CSIB0 consecutive transmission write enable CSIB1 reception completion CSIB1 consecutive transmission write enable UARTA0 reception completion UARTA0 transmission enable UARTA0 UARTA1 reception completion/UARTA1 reception error UARTA1 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 INTUA1T INTAD INTKR INTWTI INTWT INTP8 INTP9 INTP10 INTTQ1OV UARTA1 transmission enable UARTA1 A/D conversion completion Key return interrupt request Watch timer interval Watch timer reference time External interrupt pin input edge detection (INTP8) External interrupt pin input edge detection (INTP9) External interrupt pin input edge detection (INTP10) TMQ1 overflow TMQ1 TMQ1 TMQ1 TMQ1 TMQ1 UARTA2 UARTA2 DMA DMA DMA DMA Pin Pin A/D KR WT WT Pin 02A0H 02BH 0300H 0310H 0320H 0330H 0340H 0350H 0360H 0370H 0380H 0390H 03A0H 03B0H 03C0H 0410H 0420H 0430H 0440H 000002A0H 000002B0H 00000300H 00000310H 00000320H 00000330H 00000340H 00000350H 00000360H 00000370H 00000380H 00000390H 000003A0H 000003B0H 000003C0H 00000410H 00000420H 00000430H 00000440H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC UA1TIC ADIC KRIC WTIIC WTIC PIC8 PIC9 PIC10 TQ1OVIC TQ1CCIC0 TQ1CCIC1 TQ1CCIC2 TQ1CCIC3 UA2RIC UA2TIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 INTTQ1CC0 TMQ1 capture 0/compare 0 match INTTQ1CC1 TMQ1 capture 1/compare 1 match INTTQ1CC2 TMQ1 capture 2/compare 2 match INTTQ1CC3 TMQ1 capture 3/compare 3 match INTUA2R INTUA2T INTDMA0 INTDMA1 INTDMA2 INTDMA3 UARTA2 reception completion/error UARTA2 transmission enable DMA0 transfer end DMA1 transfer end DMA2 transfer end DMA3 transfer end 518 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started. Note, however, that the restored PC when a nonmaskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Division instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack pointer is updated) nextPC: The PC value that starts the processing following interrupt/exception processing. 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). Preliminary User's Manual U17718EJ1V0UD 519 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. This product has the following two non-maskable interrupt request signals. * NMI pin input (NMI) * Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2) The valid edge of the NMI pin can be selected from four types: "rising edge", "falling edge", "both edges", and "no edge detection". The function of the NMI pin is enabled by setting the PMC0.PMC02 bit to 1 and the INTF0.INTF02 bit and INTR0.INTR02 bit to a desired value, and specifying a desired valid edge. The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when the WDTM2.WDM21 and WDTM2.WDM20 bits are set to "01". If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). INTWDT2 > NMI If a new NMI or INTWDT2 request signal is issued while an NMI is being serviced, it is serviced as follows. (1) If new NMI request signal is issued while NMI is being serviced The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). (2) If INTWDT2 request signal is issued while NMI is being serviced The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is executed (the NMI servicing is stopped). Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request signal (INTWDT2), see 15.2.2 (2) From INTWDT2 signal. Figure 15-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2) (a) NMI and INTWDT2 request signals generated at the same time Main routine INTWDT2 servicing NMI and INTWDT2 requests (generated simultaneously) System reset 520 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable interrupt being serviced NMI Non-maskable interrupt request signal generated during non-maskable interrupt servicing NMI * NMI request generated during NMI servicing INTWDT2 * INTWDT2 request generated during NMI servicing (NP bit = 1 retained before INTWDT2 request) Main routine NMI servicing NMI (Held pending) request Servicing of pending NMI NMI request Main routine NMI servicing NMI request INTWDT2 request (Held pending) INTWDT2 servicing System reset * INTWDT2 request generated during NMI servicing (NP bit = 0 set before INTWDT2 request) Main routine NP = 0 NMI request INTWDT2 request NMI servicing INTWDT2 servicing System reset * INTWDT2 request generated during NMI servicing (NP = 0 set after INTWDT2 request) Main routine INTWDT2 request NP = 0 NMI INTWDT2 servicing servicing (Held pending) NMI request System reset INTWDT2 * NMI request generated during INTWDT2 servicing * INTWDT2 request generated during INTWDT2 servicing Main routine INTWDT2 servicing NMI request (Invalid) Main routine INTWDT2 servicing INTWDT2 request (Invalid) INTWDT2 request INTWDT2 request System reset System reset Preliminary User's Manual U17718EJ1V0UD 521 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0. <5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC, and transfers control. The servicing configuration of a non-maskable interrupt is shown in Figure 15-2. Figure 15-2. Servicing Configuration of Non-Maskable Interrupt NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW.NP 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restored PC PSW 0010H, 0020H 1 0 1 00000010H, 00000020H Interrupt request held pending 1 Interrupt servicing 522 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 1. <2> Transfers control back to the address of the restored PC and PSW. Figure 15-3 illustrates how the RETI instruction is processed. Figure 15-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. Preliminary User's Manual U17718EJ1V0UD 523 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 15-4. Software Reset Processing INTWDT2 occurs. FEPC Software reset processing address FEPSW Value that sets NP bit = 1, EP bit = 0 RETI INTWDT2 servicing routine RETI 10 times (FEPC and FEPSWNote must be set.) PSW PSW default value setting Initialization processing Software reset processing routine Note FEPSW Value that sets NP bit = 1, EP bit = 0 15.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z NP 0 1 Non-maskable interrupt servicing status No non-maskable interrupt servicing Non-maskable interrupt currently being serviced 524 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and EIPSW. 15.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0. <5> Sets the handler address corresponding to each interrupt to the PC, and transfers control. The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the RETI or LDSR instruction. How maskable interrupts are serviced is illustrated below. The V850ES/HG2 has 53 Preliminary User's Manual U17718EJ1V0UD 525 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-5. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 Yes xxMK = 0 Yes Priority higher than that of interrupt currently being serviced? No Interrupt requested? No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request CPU processing PSW.NP 0 PSW.ID 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Handler address Interrupt request held pending 1 1 Interrupt request held pending Interrupt servicing Note For the ISPR register, see 15.3.6 In-service priority register (ISPR). 526 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is 0. <2> Transfers control to the address of the restored PC and PSW. Figure 15-6 illustrates the processing of the RETI instruction. Figure 15-6. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW 1 Restores original processing Note For the ISPR register, see 15.3.6 In-service priority register (ISPR). Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. Preliminary User's Manual U17718EJ1V0UD 527 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (see Table 15-2 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 15-2 Interrupt Control Register (xxICn)). For more information, see Table 15-1 Interrupt/Exception Source List. The programmable priority control customizes interrupt request signals into eight 528 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Interrupt request a (level 3) Interrupt request b (level 2) EI Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Servicing of d Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Servicing of h Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. Preliminary User's Manual U17718EJ1V0UD 529 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Interrupt request i (level 2) EI Interrupt request j (level 3) Interrupt request k (level 1) Servicing of k Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request l (level 2) Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request t (level 2) Interrupt request u (level 2) Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Interrupt request s (level 1) Note 1 Note 2 Servicing of u Servicing of t Notes 1. Lower default priority 2. Higher default priority Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. 530 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Servicing of interrupt request b . . Default priority a>b>c Servicing of interrupt request c Interrupt request b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Servicing of interrupt request a Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. Preliminary User's Manual U17718EJ1V0UD 531 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H. Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read while interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. After reset: 47H 7 xxICn xxIFn R/W 6 xxMKn Address: FFFFF110H to FFFFF188H 0 0 0 xxPRn2 xxPRn1 xxPRn0 xxIFn 0 1 Interrupt request flagNote Interrupt request not issued Interrupt request issued xxMKn 0 1 Interrupt servicing enabled Interrupt mask flag Interrupt servicing disabled (pending) xxPRn2 0 0 0 0 1 1 1 1 xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 Interrupt priority specification bit Specifies level 0 (highest). Specifies level 1. Specifies level 2. Specifies level 3. Specifies level 4. Specifies level 5. Specifies level 6. Specifies level 7 (lowest). Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged. Remark xx: Identification name of each peripheral unit (see Table 15-2 Interrupt Control Registers (xxICn)) n: Peripheral unit number (see Table 15-2 Interrupt Control Registers (xxICn)). The addresses and bits of the interrupt control registers are as follows. 532 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Table 15-2. Interrupt Control Registers (xxICn) (1/2) Address Register 7 FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF160H FFFFF162H FFFFF164H FFFFF166H FFFFF168H FFFFF16AH LVIIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PIC7 TQ0OVIC TQ0CCIC0 TQ0CCIC1 TQ0CCIC2 TQ0CCIC3 TP0OVIC TP0CCIC0 TP0CCIC1 TP1OVIC TP1CCIC0 TP1CCIC1 TP2OVIC TP2CCIC0 TP2CCIC1 TP3OVIC TP3CCIC0 TP3CCIC1 TM0EQIC0 CB0RIC CB0TIC CB1RIC CB1TIC UA0RIC UA0TIC UA1RIC UA1TIC ADIC KRIC WTIIC WTIC PIC8 PIC9 PIC10 LVIIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 PIF7 TQ0OVIF TQ0CCIF0 TQ0CCIF1 TQ0CCIF2 TQ0CCIF3 TP0OVIF TP0CCIF0 TP0CCIF1 TP1OVIF TP1CCIF0 TP1CCIF1 TP2OVIF TP2CCIF0 TP2CCIF1 TP3OVIF TP3CCIF0 TP3CCIF1 TM0EQIF0 CB0RIF CB0TIF CB1RIF CB1TIF UA0RIF UA0TIF UA1RIF UA1TIF ADIF KRIF WTIIF WTIF PIF8 PIF9 PIF10 6 LVIMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 PMK7 TQ0OVMK TQ0CCMK0 TQ0CCMK1 TQ0CCMK2 TQ0CCMK3 TP0OVMK TP0CCMK0 TP0CCMK1 TP1OVMK TP1CCMK0 TP1CCMK1 TP2OVMK TP2CCMK0 TP2CCMK1 TP3OVMK TP3CCMK0 TP3CCMK1 TM0EQMK0 CB0RMK CB0TMK CB1RMK CB1TMK UA0RMK UA0TMK UA1RMK UA1TMK ADMK KRMK WTIMK WTMK PMK8 PMK9 PMK10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 LVIPR2 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR72 TQ0OVPR2 1 LVIPR1 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR71 TQ0OVPR1 0 LVIPR0 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60 PPR70 TQ0OVPR0 TQ0CCPR02 TQ0CCPR01 TQ0CCPR00 TQ0CCPR12 TQ0CCPR11 TQ0CCPR10 TQ0CCPR22 TQ0CCPR21 TQ0CCPR20 TQ0CCPR32 TQ0CCPR31 TQ0CCPR30 TP0OVPR2 TP0OVPR1 TP0OVPR0 TP0CCPR02 TP0CCPR01 TP0CCPR00 TP0CCPR12 TP0CCPR11 TP0CCPR10 TP1OVPR2 TP1OVPR1 TP1OVPR0 TP1CCPR02 TP1CCPR01 TP1CCPR00 TP1CCPR12 TP1CCPR11 TP1CCPR10 TP2OVPR2 TP2OVPR1 TP2OVPR0 TP2CCPR02 TP2CCPR01 TP2CCPR00 TP2CCPR12 TP2CCPR11 TP2CCPR10 TP3OVPR2 TP3OVPR1 TP3OVPR0 TP3CCPR02 TP3CCPR01 TP3CCPR00 TP3CCPR12 TP3CCPR11 TP3CCPR10 TM0EQPR02 TM0EQPR01 TM0EQPR00 CB0RPR2 CB0TPR2 CB1RPR2 CB1TPR2 UA0RPR2 UA0TPR2 UA1RPR2 UA1TPR2 ADPR2 KRPR2 WTIPR2 WTPR2 PPR82 PPR92 PPR102 CB0RPR1 CB0TPR1 CB1RPR1 CB1TPR1 UA0RPR1 UA0TPR1 UA1RPR1 UA1TPR1 ADPR1 KRPR1 WTIPR1 WTPR1 PPR81 PPR91 PPR101 CB0RPR0 CB0TPR0 CB1RPR0 CB1TPR0 UA0RPR0 UA0TPR0 UA1RPR0 UA1TPR0 ADPR0 KRPR0 WTIPR0 WTPR0 PPR80 PPR90 PPR100 Preliminary User's Manual U17718EJ1V0UD 533 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Table 15-2. Interrupt Control Registers (xxICn) (2/2) Address Register 7 FFFFF16CH FFFFF16EH FFFFF170H FFFFF172H FFFFF174H FFFFF176H FFFFF178H FFFFF182H FFFFF184H FFFFF186H FFFFF188H TQ1OVIC TQ1CCIC0 TQ1CCIC1 TQ1CCIC2 TQ1CCIC3 UA2RIC UA2TIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 TQ1OVIF TQ1CCIF0 TQ1CCIF1 TQ1CCIF2 TQ1CCIF3 UA2RIF UA2TIF DMAIF0 DMAIF1 DMAIF2 DMAIF3 6 TQ1OVMK TQ1CCMK0 TQ1CCMK1 TQ1CCMK2 TQ1CCMK3 UA2RMK UA2TMK DMAMK0 DMAMK1 DMAMK2 DMAMK3 5 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 2 TQ1OVPR2 1 TQ1OVPR1 0 TQ1OVPR0 TQ1CCPR02 TQ1CCPR01 TQ1CCPR00 TQ1CCPR12 TQ1CCPR11 TQ1CCPR10 TQ1CCPR22 TQ1CCPR21 TQ1CCPR20 TQ1CCPR32 TQ1CCPR31 TQ1CCPR30 UA2RPR2 UA2TPR2 DMAPR02 DMAPR12 DMAPR22 DMAPR32 UA2RPR1 UA2TPR1 DMAPR01 DMAPR11 DMAPR21 DMAPR31 UA2RPR0 UA2TPR0 DMAPR00 DMAPR10 DMAPR20 DMAPR30 15.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxICn.xxMKn bit. The IMRm register can be read or written in 16-bit units (m = 0 to 3). If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3). Reset sets these registers to FFFFH. Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a result, the contents of the IMRm register are also rewritten). 534 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com After reset: FFFFH 15 IMR3 (IMR3H Note R/W 14 1 6 1 Address: IMR3 FFFFF106H, IMR3L FFFFF106H, IMR3H FFFFF107H 13 12 10 9 11 1 5 1 DMAMK3 DMAMK2 DMAMK1 DMAMK0 4 3 2 1 8 1 0 ) 1 7 IMR3L 1 UA2TMK UA2RMK TQ1CCMK3 TQ1CCMK2 TQ1CCMK1 After reset: FFFFH 15 R/W 14 Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H 13 12 10 9 11 8 PMK10 5 1 PMK9 4 1 PMK8 3 ADMK WTMK 2 WTIMK 1 KRMK 0 IMR2 (IMR2HNote) TQ1CCMK0 TQ1OVMK 7 IMR2L 1 6 1 UA1TMK UA1RMK UA0TMK After reset: FFFFH 15 IMR1 (IMR1H Note R/W 14 Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H 13 12 11 10 9 8 ) UA0RMK CB1TMK CB1RMK CB0TMK CB0RMK TM0EQMK0 TP3CCMK1 TP3CCMK0 7 6 5 4 TP2OVMK 3 2 1 TP1OVMK 0 TP0CCMK1 IMR1L TP3OVMK TP2CCMK1 TP2CCMK0 R/W 14 TP1CCMK1 TP1CCMK0 After reset: FFFFH 15 IMR0 (IMR0H Note Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H 13 12 11 10 9 8 PMK7 0 LVIMK ) TP0CCMK0 7 TP0OVMK TQ0CCMK3 TQ0CCMK2 TQ0CCMK1 TQ0CCMK0 TQ0OVMK 6 PMK5 5 PMK4 4 PMK3 3 PMK2 2 PMK1 1 PMK0 IMR0L PMK6 xxMKn 0 1 Setting of interrupt mask flag Interrupt servicing enabled Interrupt servicing disabled Note To read bits 8 to 15 of the IMR0 to IMR3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of IMR0H to IMR3H registers. Caution Set bits 15 to 13 and 8 to 5 of the IMR3 register and bits 7 to 4 of the IMR2 register to "1". If the setting of these bits is changed, the operation is not guaranteed. xx: Identification name of each peripheral unit (see Table 15-2 Interrupt Control Registers (xxICn)). n: Peripheral unit number (see Table 15-2 Interrupt Control Registers (xxICn)) Remark Preliminary User's Manual U17718EJ1V0UD 535 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from nonmaskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI). After reset: 00H 7 ISPR ISPR7 R 6 Address: FFFFF1FAH 5 ISPR5 4 ISPR4 3 ISPR3 2 ISPR2 1 ISPR1 0 ISPR0 ISPR6 ISPRn 0 1 Priority of interrupt currently acknowledged Interrupt request signal with priority n not acknowledged Interrupt request signal with priority n acknowledged Remark n = 0 to 7 (priority level) 536 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.3.7 ID flag This flag controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z ID 0 1 Specification of maskable interrupt servicingNote Maskable interrupt request signal acknowledgment enabled Maskable interrupt request signal acknowledgment disabled (pending) Note Interrupt disable flag (ID) function This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0. 15.3.8 Watchdog timer mode register 2 (WDTM2) This register can be read or written in 8-bit units (for details, see CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2). Reset sets this register to 67H. After reset: 67H R/W Address: FFFFF6D0H WDTM2 0 WDM21 WDM20 0 0 0 0 0 WDM21 0 0 1 WDM20 0 1 x Selection of watchdog timer operation mode Stops operation Non-maskable interrupt request mode Reset mode (initial-value) Preliminary User's Manual U17718EJ1V0UD 537 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 15.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.EP and PSW.ID bits to 1. <5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and transfers control. Figure 15-9 illustrates the processing of a software exception. Figure 15-9. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address Exception processing Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. 538 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 15-10 illustrates the processing of the RETI instruction. Figure 15-10. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 1 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. Preliminary User's Manual U17718EJ1V0UD 539 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z EP 0 1 Exception processing status Exception processing not in progress. Exception processing in progress. 540 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/HG2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 15.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B. instruction is executed. An exception trap is generated when an instruction applicable to this illegal 15 11 10 54 0 31 27 26 23 22 16 xxxxx111111xxxxxxxxxx 0111 to xxxxxx0 1111 x: Arbitrary Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. Figure 15-11 illustrates the processing of the exception trap. Preliminary User's Manual U17718EJ1V0UD 541 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com Figure 15-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Caution DBPC and DBPSW can be accessed only during the interval between the execution of the illegal opcode and the DBRET instruction. Figure 15-12 illustrates the restore processing from an exception trap. Figure 15-12. Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 542 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1> Saves restored PC to DBPC. <2> Saves current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets handler address (00000060H) for debug trap to PC and transfers control. Figure 15-13 shows the debug trap processing format. Figure 15-13. Debug Trap Processing Format DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing Preliminary User's Manual U17718EJ1V0UD 543 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2> Control is transferred to the fetched address of the restored PC and PSW. Caution DBPC and DBPSW can be accessed only during the interval between the execution of the DBTRAP instruction and the DBRET instruction. Figure 15-14 shows the processing format for restoration from a debug trap. Figure 15-14. Processing Format of Restoration from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 544 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10) 15.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. The NMI pin can be used to release the STOP mode. In the STOP mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) Eliminating noise on INTP0 to INTP10 pins The INTP0 to INTP10 pins have an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. 15.6.2 Edge detection The valid edge of each of the NMI and INTP0 to INTP10 pins can be selected from the following four. * Rising edge * Falling edge * Both rising and falling edges * No edge detected The edge of the NMI pin is not detected after reset. Therefore, the interrupt request signal is not acknowledged unless a valid edge is enabled by using the INTF0 and INTR0 register (the NMI pin functions as a normal port pin). Preliminary User's Manual U17718EJ1V0UD 545 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 00, and then set the port mode. After reset: 00H R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H INTF0 0 INTF06 INTP3 INTF05 INTP2 INTF04 INTP1 INTF03 INTP0 INTF02 NMI 0 0 INTR0 0 INTR06 INTP3 INTR05 INTP2 INTR04 INTP1 INTR03 INTP0 INTR02 NMI 0 0 Remark For the valid edge specification combinations, see Table 15-3. Table 15-3. Valid Edge Specification INTF0n 0 0 1 1 INTR0n 0 1 0 1 No edge detected Rising edge Falling edge Both rising and falling edges Valid Edge Specification (n = 2 to 6) Caution Be sure to clear the INTF0n and INTR0n bits to 00 if the corresponding pin is not used as the NMI or INTP0 to INTP3 pins. Remark n = 2: Control of NMI pin n = 3 to 6: Control of INTP0 to INTP3 pins 546 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (2) External interrupt rising, falling edge specification register 1 (INTR1, INTF1) The INTR1 and INTF1 registers are 8-bit registers that specify detection of the rising and falling edges of the INTP9 and INTP10 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF1n and INTR1n bits to 00, and then set the port mode. After reset: 00H R/W Address: INTR1 FFFFFC22H, INTF1 FFFFFC02H INTR1 0 0 0 0 0 0 INTR11 INTP10 INTR10 INTP9 INTF1 0 0 0 0 0 0 INTF11 INTP10 INTF10 INTP9 Remark For the valid edge specification combinations, see Table 15-4. Table 15-4. Valid Edge Specification INTF1n 0 0 1 1 INTR1n 0 1 0 1 No edge detected Rising edge Falling edge Both rising and falling edges Valid Edge Specification (n = 0, 1) Caution Be sure to clear the INTF1n and INTR1n bits to 00 if the corresponding pin is not used as the INTP9 and INTP10 pins. Remark n = 0: Control of INTP9 pin n = 1: Control of INTP10 pin Preliminary User's Manual U17718EJ1V0UD 547 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (3) External interrupt rising, falling edge specification register 3 (INTR3, INTF3) The INTR3 and INTF3 registers are 8-bit registers that specify detection of the rising and falling edges of the INTP7 and INTP8 pins. These registers can be read or written in 16-bit units. However, when the higher 8 bits of INTF3 register are used as the INTF3H register and the lower 8 bits as the INTF3L register, they can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF3n and INTR3n bits to 00, and then set the port mode. After reset: 0000H R/W Address: INTF3 FFFFFC06H, INTF3L FFFFFC06H, INTF3H FFFFFC07H INTF3 (INTF3HNote) 0 0 0 0 0 0 INTF39 INTP8 0 (INTF3L) 0 0 0 0 0 0 INTF31 INTP7 0 After reset: 0000H R/W Address: INTR3 FFFFFC26H, INTR3L FFFFFC26H, INTR3H FFFFFC27H 0 0 0 0 INTR39 INTP8 0 INTR3 (INTR3HNote) 0 0 (INTR3L) 0 0 0 0 0 0 INTR31 INTP7 0 Caution When bits 8 to 15 of the INTF3 and INTR3 registers are read or written in 8-bit or 1-bit units, specify them as bits 0 to 7 of the INTF3H and INTR3H registers. Remark For the valid edge specification combinations, see Table 15-5. Table 15-5. Valid Edge Specification INTF3n 0 0 1 1 INTR3n 0 1 0 1 No edge detected Rising edge Falling edge Both rising and falling edges Valid Edge Specification (n = 1, 9) Caution Be sure to clear the INTF3n and INTR3n bits to 00 if the corresponding pin is not used as the INTP7 and INTP8 pins. Remark n = 1: Control of INTP7 pin n = 9: Control of INTP8 pin 548 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (4) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP4 to INTP6). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0, and then set the port mode. After reset: 00H 15 R/W 14 Address: INTF9H FFFFFC13H, INTR9H FFFFFC33H 13 12 11 10 9 8 INTF9H INTF915 INTF914 INTF913 INTP6 15 0 0 0 0 0 INTP5 14 INTP4 13 12 11 10 9 8 INTR9H INTR915 INTR914 INTR913 INTP6 INTP5 INTP4 0 0 0 0 0 Remark For the valid edge specification combinations, see Table 15-6. Table 15-6. Valid Edge Specification INTF9n 0 0 1 1 INTR9n 0 1 0 1 No edge detected Rising edge Falling edge Both rising and falling edges Valid Edge Specification (n = 13 to 15) Caution Be sure to clear the INTF9n and INTR9n bits to 00 if the corresponding pin is not used as INTP4 to INTP6 pins. Remark n = 13 to 15: Control of INTP4 to INTP6 pins Preliminary User's Manual U17718EJ1V0UD 549 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com (5) Noise elimination control register (NFC) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed three times. When digital noise elimination is selected, if the clock that performs sampling in the standby mode is stopped, then the INTP3 interrupt request signal cannot be used for releasing the standby mode. When fXT is used as the sampling clock, the INTP3 interrupt request signal can be used for releasing either the subclock operating mode or the IDLE1/IDLE2/STOP/sub-IDLE mode. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Time equal to the sampling clock x the number of times set by the NFSTS bit is required until the digital noise eliminator is initialized after the sampling clock has been changed. If the valid edge of INTP3 is input after the sampling clock has been changed and before the time of the sampling clock x the number of times set by the NFSTS bit passes, therefore, the interrupt request signal may be generated. Therefore, note the following points when using the interrupt and DMA functions. * When using the interrupt function, after the sampling clock x the number of times set by the NFSTS bit have elapsed, enable interrupts after the interrupt request flag (PIC3.PIF3 bit) has been cleared. * When using the DMA function (started by INTP3), enable DMA after the sampling clock x the number of times set by the NFSTS bit have elapsed. 550 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com After reset: 00H R/W Address: FFFFF318H NFC NFEN NFSTS 0 0 0 NFC2 NFC1 NFC0 NFEN 0 1 Settings of INTP3 pin noise elimination Analog noise elimination (60 ns (TYP.)) Digital noise elimination NFSTS 0 1 Setting of number of times of sampling of digital noise elimination Number of times of sampling x 3 times Number of times of sampling x twice NFC2 0 0 0 0 1 1 NFC1 0 0 1 1 0 0 NFC0 0 1 0 1 0 1 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 fXT (subclock) Digital sampling clock Other than above Setting prohibited Remarks 1. Since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. Preliminary User's Manual U17718EJ1V0UD 551 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. * In IDLE1/IDLE2/STOP mode * When the external bus is accessed * When interrupt request non-sampling instructions are successively executed (see 15.8 Interrupts Are Not Acknowledged by CPU.) * When the interrupt control register is accessed Figure 15-15. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline) (1) Minimum interrupt response time 4 system clocks Internal clock Periods in Which Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM WB IFX IDX INT1 INT2 INT3 INT4 IF ID EX (2) Maximum interrupt response time 6 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM MEM MEM WB IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 IF ID EX Remark INT1 to INT4: Interrupt acknowledgment processing IFX: IDX: Invalid instruction fetch Invalid instruction decode Condition Interrupt acknowledge time (internal system clock) Internal interrupt Minimum 4 External interrupt 4+ Analog delay time Maximum 6 6+ Analog delay time The following cases are exceptions. * In IDLE1/IDLE2/STOP mode * External bus access * Two or more interrupt request non-sample instructions are executed in succession * Access to peripheral I/O register 552 Preliminary User's Manual U17718EJ1V0UD CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION www..com 15.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the PRCMD register * The store, SET1, NOT1, or CLR1 instructions for the following registers. * Interrupt-related registers: Interrupt control register (xxICn), interrupt mask registers 0 to 4 (IMR0 to IMR3) * In-service priority register (ISPR): * Command register (PRCMD): * Power save control register (PSC) * On-chip debug mode register (OCDM) * Peripheral emulation register 1 (PEMU1): Remark xx: Identification name of each peripheral unit (see Table 15-2 (xxICn)) n: Peripheral unit number (see Table 15-2 Interrupt Control Registers (xxICn)). Interrupt Control Registers 15.9 Cautions The NMI pin alternately functions as the P02 pin. It functions as a normal port pin after reset. To enable the NMI pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using the INTF0 and INTR0 registers. Preliminary User's Manual U17718EJ1V0UD 553 www..com CHAPTER 16 KEY INTERRUPT FUNCTION 16.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Table 16-1. Assignment of Key Return Detection Pins Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 signal in 1-bit units Controls KR1 signal in 1-bit units Controls KR2 signal in 1-bit units Controls KR3 signal in 1-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units Figure 16-1. Key Return Block Diagram KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) 554 Preliminary User's Manual U17718EJ1V0UD CHAPTER 16 KEY INTERRUPT FUNCTION www..com 16.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF300H KRM KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 KRMn 0 1 Control of key return mode Does not detect key return signal Detects key return signal Caution Rewrite the KRM register after once clearing the KRM register to 00H. Remark For the alternate-function pin settings, see Table 4-19 Using Port Pin as AlternateFunction Pin. 16.3 Cautions (1) If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not generated even if the falling edge of another pin is input. (2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0). (3) If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this, change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag (KRIC.KRIF bit) to 0, and enable interrupts (EI) or clear the mask. (4) To use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the KRM register. To switch from the key return pin to the port pin, disable the operation with the KRM register and then set the port pin. Preliminary User's Manual U17718EJ1V0UD 555 www..com CHAPTER 17 STANDBY FUNCTION 17.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 17-1. Table 17-1. Standby Modes Mode HALT mode IDLE1 mode Functional Outline Mode in which only the operating clock of the CPU is stopped Mode in which all the operations of the internal circuits except the oscillator, PLL memory are stopped Note , and flash IDLE2 mode STOP mode Subclock operation mode Sub-IDLE mode Mode in which all the internal operations of the chip except the oscillator are stopped Mode in which all the internal operations of the chip except the subclock oscillator are stopped Mode in which the subclock is used as the internal system clock Mode in which all the internal operations of the chip except the oscillator are stopped, in the subclock operation mode Note The PLL holds the previous operating status. 556 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com Figure 17-1. Status Transition Reset Internal oscillation clock operation Sub-IDLE mode (fx operates, PLL operates) WDT overflow Oscillation stabilization wait Normal operation mode Subclock operation mode (fx operates, PLL operates) Clock through mode (PLL operates) PLL lockup time wait PLL mode (PLL operates) IDLE1 mode (fx operates, PLL operates) Oscillation stabilization waitNote Oscillation stabilization waitNote HALT mode (fx operates, PLL operates) Oscillation stabilization waitNote Clock through mode (PLL stops) HALT mode (fx operates, PLL stops) IDLE1 mode (fx operates, PLL stops) Subclock operation mode (fx stops, PLL stops) Sub-IDLE mode (fx stops, PLL stops) IDLE2 mode (fx operates, PLL stops) STOP mode (fx stops, PLL stops) Note If a WDT overflow occurs during an oscillation stabilization time, the CPU operates on the internal oscillation clock. Remark fX: Main clock oscillation frequency Preliminary User's Manual U17718EJ1V0UD 557 CHAPTER 17 STANDBY FUNCTION www..com 17.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 PSC 0 R/W 6 NMI1M Address: FFFFF1FEH 5 NMI0M 4 INTM 3 0 2 0 1 STP 0 0 NMI1M 0 1 Standby mode release control upon occurrence of INTWDT2 signal Standby mode release by INTWDT2 signal enabled Standby mode release by INTWDT2 signal disabled NMI0M 0 1 Standby mode release control by NMI pin input Standby mode release by NMI pin input enabled Standby mode release by NMI pin input disabled INTM 0 1 Standby mode release control via maskable interrupt request signal Standby mode release by maskable interrupt request signal enabled Standby mode release by maskable interrupt request signal disabled STP 0 1 Normal mode Standby mode Standby modeNote setting Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1 and PSMR.PSM0 bits and then set the STP bit. 2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is released. 558 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF820H PSMR 0 0 0 0 0 0 PSM1 PSM0 PSM1 0 0 1 1 PSM0 0 1 0 1 Specification of operation in software standby mode IDLE1, sub-IDLE modes STOP mode IDLE2, sub-IDLE modes STOP mode Cautions 1. Be sure to clear bits 2 to 7 to "0". 2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1. Remark IDLE1: In this mode, all operations except the oscillator operation and some other circuits (flash memory and PLL) are stopped. After the IDLE1 mode is released, the normal operation mode is restored without needing to secure the oscillation stabilization time, like the HALT mode. IDLE2: In this mode, all operations except the oscillator operation are stopped. After the IDLE2 mode is released, the normal operation mode is restored following the lapse of the setup time specified by the OSTS register (flash memory and PLL). STOP: In this mode, all operations except the subclock oscillator operation are stopped. After the STOP mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the OSTS register. Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured. Preliminary User's Manual U17718EJ1V0UD 559 CHAPTER 17 STANDBY FUNCTION www..com (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units. Reset sets this register to 06H. After reset: 06H R/W Address: FFFFF6C0H OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time/setup timeNote fX 4 MHz 5 MHz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fX 2 /fX 2 /fX 213/fX 2 /fX 2 /fX 2 /fX Setting prohibited 16 15 14 12 11 10 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms Note The oscillation stabilization time and setup time are required when the STOP mode and IDLE2 mode are released, respectively. Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the STOP mode, regardless of whether the STOP mode is released by reset or the occurrence of an interrupt request signal. STOP mode release Voltage waveform of X1 pin a VSS 2. Be sure to clear bits 3 to 7 to "0". 16 3. The oscillation stabilization time following reset release is 2 /fX (because the initial value of the OSTS register = 06H). Remark fX = Main clock oscillation frequency 560 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.3 HALT Mode 17.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 17-3 shows the operating status in the HALT mode. The average current consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the pending interrupt request. 17.3.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP10 pin input), unmasked internal interrupt request signal from a peripheral function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). After the HALT mode has been released, the normal operation mode is restored. (1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 17-2. Operation After Releasing HALT Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. The next instruction is executed. Interrupt Enabled (EI) Status Execution branches to the handler address. Interrupt Disabled (DI) Status Preliminary User's Manual U17718EJ1V0UD 561 CHAPTER 17 STANDBY FUNCTION www..com (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 17-3. Operating Status in HALT Mode Setting of HALT Mode Item Main clock oscillator Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Oscillation enabled Operable Stops operation Operable Operable Operable Operable Operable when a clock other than fXT is selected as the count clock Watch timer Operable when fX (divided BRG) is selected as the count clock Watchdog timer 2 Serial interface CSIB0, CSIB1 UARTA0 to UARTA2 A/D converter Key interrupt function (KR) Port function Internal data Operable Operable Operable Operable Operable Retains status before HALT mode was set The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the HALT mode was set. Operable Operable Operating Status When Subclock Is Not Used Oscillation enabled - Oscillation enabled When Subclock Is Used 562 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.4 IDLE1 Mode 17.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 17-5 shows the operating status in the IDLE1 mode. The IDLE1 mode can reduce the power consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE1 mode has been released, in the same manner as when the HALT mode is released. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE1 mode. 2. If the IDLE1 mode is set while an unmasked interrupt request signal is being held pending, the IDLE1 mode is released immediately by the pending interrupt request. 17.4.2 Releasing IDLE1 mode The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP10 pin input), unmasked internal interrupt request signal from a peripheral function operable in the IDLE1 mode, or reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). After the IDLE1 mode has been released, the normal operation mode is restored. (1) Releasing IDLE1 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. Cautions 1. An interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not released. 2. If eliminating digital noise is selected by using the NFC register and if the sampling clock is selected from fXX/64, fXX/128, fXX/256, fXX/512, and fXX/1024, the IDLE1 mode cannot be released by the interrupt request signal of the INTP3 pin. For details, see 15.6.2 (5) Noise elimination control register (NFC). (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE1 mode is released, but that interrupt request signal is not acknowledged. interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE1 mode is released and that interrupt request signal is acknowledged. Preliminary User's Manual U17718EJ1V0UD The 563 CHAPTER 17 STANDBY FUNCTION www..com Table 17-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. The next instruction is executed. Interrupt Enabled (EI) Status Execution branches to the handler address. Interrupt Disabled (DI) Status (2) Releasing IDLE1 mode by reset The same operation as the normal reset operation is performed. Table 17-5. Operating Status in IDLE1 Mode Setting of IDLE1 Mode Item Main clock oscillator Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Watch timer Watchdog timer 2 Serial interface CSIB0, CSIB1 UARTA0 to UARTA2 A/D converter Key interrupt function (KR) Port function Internal data Oscillation enabled Operable Stops operation Stops operation Stops operation (but standby mode release is possible) Stops operation Stops operation Operable when fR/8 is selected as the count clock Operable when fX (divided BRG) is selected as the count clock Operable Operable when the SCKBn input clock is selected as the count clock (n = 0, 1) Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) Holds operation (conversion result held) Operable Retains status before IDLE1 mode was set The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE1 mode was set. Note Operating Status When Subclock Is Not Used Oscillation enabled - Oscillation enabled When Subclock Is Used Operable when fR/8 or fXT is selected as the count clock Operable Note To realize low power consumption, stop the A/D converter before shifting to the IDLE1 mode. 564 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.5 IDLE2 Mode 17.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 17-7 shows the operating status in the IDLE2 mode. The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped, a setup time for the PLL and flash memory is required when IDLE2 mode is released. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE2 mode. 2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending, the IDLE2 mode is released immediately by the pending interrupt request. 17.5.2 Releasing IDLE2 mode The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP10 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the IDLE2 mode was set. After the IDLE2 mode has been released, the normal operation mode is restored. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released. 2. If eliminating digital noise is selected by using the NFC register and if the sampling clock is selected from fXX/64, fXX/128, fXX/256, fXX/512, and fXX/1024, the IDLE2 mode cannot be released by the interrupt request signal of the INTP3 pin. For details, see 15.6.2 (5) Noise elimination control register (NFC). (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged. interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and that interrupt request signal is acknowledged. Preliminary User's Manual U17718EJ1V0UD The 565 CHAPTER 17 STANDBY FUNCTION www..com Table 17-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the prescribed setup time. Execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. The next instruction is executed after securing the prescribed setup time. (2) Releasing IDLE2 mode by reset The same operation as the normal reset operation is performed. Table 17-7. Operating Status in IDLE2 Mode Setting of IDLE2 Mode Item Main clock oscillator Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Watch timer Watchdog timer 2 Serial interface CSIB0, CSIB1 UARTA0 to UARTA2 A/D converter Key interrupt function (KR) Port function Internal data Oscillation enabled Stops operation Stops operation Stops operation Stops operation (but standby mode release is possible) Stops operation Stops operation Operable when fR/8 is selected as the count clock Operable when fX (divided BRG) is selected as the count clock Operable Operable when the SCKBn input clock is selected as the count clock (n = 0, 1) Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) Holds operation (conversion result held) Operable Retains status before IDLE2 mode was set The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE2 mode was set. Note Operating Status When Subclock Is Not Used Oscillation enabled - Oscillation enabled When Subclock Is Used Operable when fR/8 or fXT is selected as the count clock Operable Note To realize low power consumption, stop the A/D converter before shifting to the IDLE2 mode. 566 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the ROM (flash memory) after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock IDLE mode status Interrupt request ROM circuit stopped Setup time count (2) Release by reset (RESET pin input, WDT2RES generation) This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. Preliminary User's Manual U17718EJ1V0UD 567 CHAPTER 17 STANDBY FUNCTION www..com 17.6 STOP Mode 17.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 17-9 shows the operating status in the STOP mode. Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. 2. If the STOP mode is set while an unmasked interrupt request signal is being held pending, the STOP mode is released immediately by the pending interrupt request. 17.6.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP10 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), or low-voltage detector (LVI)). After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. Cautions 1. The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and STOP mode is not released. 2. If eliminating digital noise is selected by using the NFC register and if the sampling clock is selected from fXX/64, fXX/128, fXX/256, fXX/512, and fXX/1024, the STOP mode cannot be released by the interrupt request signal of the INTP3 pin. For details, see 15.6.2 (5) Noise elimination control register (NFC). (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt request signal is acknowledged. 568 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com Table 17-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the oscillation stabilization time. Execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. The next instruction is executed after securing the oscillation stabilization time. (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. Table 17-9. Operating Status in STOP Mode Setting of STOP Mode Item Main clock oscillator Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Watch timer Watchdog timer 2 Serial interface CSIB0, CSIB1 UARTA0 to UARTA2 A/D converter Key interrupt function (KR) Port function Internal data Oscillation enabled Stops operation Stops operation Stops operation Stops operation (but standby mode release is possible) Stops operation Stops operation Operable when fR/8 is selected as the count clock Stops operation Operable when fR/8 or fXT is selected as the count clock Operable when fXT is selected as the count clock Operating Status When Subclock Is Not Used Stops oscillation - Oscillation enabled When Subclock Is Used Operable when fR is selected as the count clock Operable when the SCKBn input clock is selected as the count clock (n = 0, 1) Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) Stops operation (conversion result undefined) Operable Retains status before STOP mode was set The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set. Notes 1, 2 Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and starts operating again after the STOP mode is released. However, in that case, the A/D conversion results after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are invalid. 2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced equivalently to when the A/D converter is stopped before the STOP mode is set. Preliminary User's Manual U17718EJ1V0UD 569 CHAPTER 17 STANDBY FUNCTION www..com 17.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock STOP status Interrupt request ROM circuit stopped Setup time count (2) Release by reset This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. 570 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.7 Subclock Operation Mode 17.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only on the subclock. In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the power consumption can be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator. Table 17-10 shows the operating status in subclock operation mode. Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 5.3 (1) Processor clock control register (PCC). 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied and set the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT = 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from main clock (fXX) in accordance with the settings of the CK2 to CK0 bits 17.7.2 Releasing subclock operation mode The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is cleared to 0. If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the CK3 bit to 0. The normal operation mode is restored when the subclock operation mode is released. Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 5.3 (1) Processor clock control register (PCC). Preliminary User's Manual U17718EJ1V0UD 571 CHAPTER 17 STANDBY FUNCTION www..com Table 17-10. Operating Status in Subclock Operation Mode Setting of Subclock Operation Mode Item Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Operating Status When Main Clock Is Oscillating Oscillation enabled Oscillation enabled Operable Operable Operable Operable Operable Operable Operable Stops operation Stops operation Operable when fR/8 or fXT is selected as the count clock Watch timer Operable Operable when fXT is selected as the count clock Watchdog timer 2 Operable Operable when fR is selected as the count clock Serial interface CSIB0, CSIB1 Operable Operable when the SCKBn input clock is selected as the count clock (n = 0, 1) UARTA0 to UARTA2 Operable Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) A/D converter Key interrupt function (KR) Port function Internal data Operable Operable Settable Settable Stops operation Stops operation Note When Main Clock Is Stopped Note Be sure to stop the PLL (PLLCTL.PLLON = 0) before stopping the main clock. Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset (see 3.4.8 (2)). 572 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com 17.8 Sub-IDLE Mode 17.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other onchip peripheral functions is stopped. As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode. Table 17-12 shows the operating status in the sub-IDLE mode. Cautions 1. Following the store instruction to set the PSC register to the sub-IDLE mode, insert five or more NOP instructions. 2. If the sub-IDLE mode is set while an unmasked interrupt request signal is being held pending, the sub-IDLE mode is then released immediately by the pending interrupt request. Preliminary User's Manual U17718EJ1V0UD 573 CHAPTER 17 STANDBY FUNCTION www..com 17.8.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP10 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the sub-IDLE mode was set. When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. (1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released. 2. When the sub-IDLE mode is released, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-IDLE mode is generated to when the mode is released. 3. If eliminating digital noise is selected by using the NFC register and if the sampling clock is selected from fXX/64, fXX/128, fXX/256, fXX/512, and fXX/1024, the sub-IDLE mode cannot be released by the interrupt request signal of the INTP3 pin. For details, see 15.6.2 (5) Noise elimination control register (NFC). (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the sub-IDLE mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt request signal is acknowledged. Table 17-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. The next instruction is executed. Interrupt Enabled (EI) Status Execution branches to the handler address. Interrupt Disabled (DI) Status 574 Preliminary User's Manual U17718EJ1V0UD CHAPTER 17 STANDBY FUNCTION www..com (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed. Table 17-12. Operating Status in Sub-IDLE Mode Setting of Sub-IDLE Mode Item Subclock oscillator Internal oscillator PLL CPU DMA Interrupt controller Timer P (TMP0 to TMP3) Timer Q (TMQ0, TMQ1) Timer M (TMM0) Watch timer Watchdog timer 2 Serial interface CSIB0, CSIB1 UARTA0 to UARTA2 A/D converter Key interrupt function (KR) Port function Internal data Operating Status When Main Clock Is Oscillating Oscillation enabled Oscillation enabled Operable Stops operation Stops operation Stops operation (but standby mode release is possible) Stops operation Stops operation Operable when fR/8 or fXT is selected as the count clock Stops operation Operable when fXT is selected as the count clock Stops operation Note 1 When Main Clock Is Stopped Operable when fR is selected as the count clock Operable when the SCKBn input clock is selected as the count clock (n = 0, 1) Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) Holds operation (conversion result held) Operable Retains status before sub-IDLE mode was set The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set. Note 2 Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock. 2. To realize low power consumption, stop the A/D converter before shifting to the sub-IDLE mode. Preliminary User's Manual U17718EJ1V0UD 575 www..com CHAPTER 18 RESET FUNCTIONS 18.1 Overview The following reset functions are available. (1) Four kinds of reset sources * External reset input via the RESET pin * Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) * System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage * System reset via the detecting clock monitor (CLM) oscillation stop * System reset via the power-on clear circuit After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF). (2) Emergency operation mode If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock. Caution When the CPU is being operated with the internal oscillation clock, access to the register in which a wait state is generated is prohibited. For the register in which a wait state is generated, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. 576 Preliminary User's Manual U17718EJ1V0UD CHAPTER 18 RESET FUNCTIONS www..com 18.2 Registers to Check Reset Source The V850ES/HG2 has four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF). (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.7 Special registers). The RESF register indicates the source from which a reset signal is generated. This register is read or written in 8-bit or 1-bit units. RESET pin input or POC reset sets this register to 00H. The default value differs if the source of reset is other than the RESET pin signal. After reset: 00HNote R/W Address: FFFFF888H RESF 0 0 0 WDT2RF 0 0 CLMRF LVIRF WDT2RF 0 1 Not generated Generated Reset signal from WDT2 CLMRF 0 1 Not generated Generated Reset signal from CLM LVIRF 0 1 Not generated Generated Reset signal from LVI Note The value of the RESF register is cleared to 00H when a reset is executed via the RESET pin. When a reset is executed by watchdog timer 2 (WDT2), low-voltage detector (LVI), or clock monitor (CLM), the reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other sources are retained. Caution Only "0" can be written to each bit of this register. If writing "0" conflicts with setting the flag (occurrence of reset), setting the flag takes precedence. Preliminary User's Manual U17718EJ1V0UD 577 CHAPTER 18 RESET FUNCTIONS www..com 18.3 Operation 18.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 18-1. Hardware Status on RESET Pin Input Item Main clock oscillator (fX) Subclock oscillator (fXT) Crystal oscillation RC oscillation Internal oscillator Peripheral clock (fX to fX/1,024) During Reset Oscillation stops Oscillation continues Oscillation stops Oscillation stops Operation stops Oscillation starts Oscillation starts Operation starts after securing oscillation stabilization time Internal system clock (fCLK), CPU clock (fCPU) Operation stops Operation starts after securing oscillation stabilization time (initialized to fXX/8) Initialized Program execution starts after securing oscillation stabilization time Watchdog timer 2 Internal RAM Operation stops (initialized to 0) Operation starts After Reset Oscillation starts CPU Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Note 1 Otherwise value immediately after reset input is retained . I/O lines (ports/alternate-function pins) On-chip peripheral I/O registers Other on-chip peripheral functions High impedance Note 2 Initialized to specified status, OCDM register is set (01H). Operation stops Operation can be started after securing oscillation stabilization time Notes 1. The firmware of the V850ES/HG2 uses a part of the internal RAM after the internal system reset status has been released because it supports a boot swap function. Therefore, the contents of some RAM areas (RAM size: 12 KB (3FFC000H to 3FFC095H)) are not retained after power-on reset. 2. When the power is turned on, the following pin may output an undefined level temporarily even during reset. * P53/KR3/TIQ00/TOQ00/DDO pin Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a high level is input to the P05/DRST pin after a reset release before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS. 578 Preliminary User's Manual U17718EJ1V0UD CHAPTER 18 RESET FUNCTIONS www..com Figure 18-1. Timing of Reset Operation by RESET Pin Input fX fCLK Initialized to fXX/8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 18-2. Timing of Power-on Reset Operation VDD fX fCLK Initialized to fXX/8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Must be on-chip regulator stabilization time (1 ms (max.)) or longer. Overflow of timer for oscillation stabilization Preliminary User's Manual U17718EJ1V0UD 579 CHAPTER 18 RESET FUNCTIONS www..com 18.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released. The main clock oscillator is stopped during the reset period. Table 18-2. Hardware Status During Watchdog Timer 2 Reset Operation Item Main clock oscillator (fX) Subclock oscillator (fXT) Crystal oscillation RC oscillation Internal oscillator Peripheral clock (fXX to fXX/1,024) During Reset Oscillation stops Oscillation continues Oscillation stops Oscillation stops Operation stops Oscillation starts Oscillation starts Operation starts after securing oscillation stabilization time Internal system clock (fXX), CPU clock (fCPU) Operation stops Operation starts after securing oscillation stabilization time (initialized to fXX/8) Initialized Program execution after securing oscillation stabilization time Watchdog timer 2 Internal RAM Operation stops (initialized to 0) Operation starts After Reset Oscillation starts CPU Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Note Otherwise value immediately after reset input is retained . I/O lines (ports/alternate-function pins) On-chip peripheral I/O register On-chip peripheral functions other than above High impedance Initialized to specified status, OCDM register retains its value. Operation stops Operation can be started after securing oscillation stabilization time. Note The firmware of the V850ES/HG2 uses a part of the internal RAM after the internal system reset status has been released because it supports a boot swap function. Therefore, the contents of some RAM areas (RAM size: 12 KB (3FFC000H to 3FFC095H)) are not retained after power-on reset. 580 Preliminary User's Manual U17718EJ1V0UD CHAPTER 18 RESET FUNCTIONS www..com 18.3.3 Reset operation by power-on clear circuit The supply voltage and detection voltage are compared when the power-on clear operation is enabled. If the supply voltage drops below the detection voltage (including when power is applied), the system is reset and each hardware unit is initialized to the default status. The reset status lasts since the voltage drop has been detected until the supply voltage rises above the detection voltage, and then is automatically cleared. After the reset status is cleared, time to stabilize oscillation of the main clock oscillator (default value of OSTS register: 216/fX) elapses, and then the CPU starts program execution. For details, see CHAPTER 20 POWER-ON CLEAR CIRCUIT. 18.3.4 Reset operation by low-voltage detector When LVI operation is enabled and when the LVIM.LVIMD bit is set to "1", the supply voltage and detection voltage are compared. If the supply voltage drops below the detection voltage, the system is reset and each hardware unit is initialized to the default status. The reset status lasts from detection of the voltage drop until the supply voltage rises above the detection voltage, and then is automatically cleared. After the reset status is cleared, time to stabilize oscillation of the main clock oscillator (default value of OSTS register: 216/fX) elapses, and then the CPU starts program execution. For details, see CHAPTER 21 LOW-VOLTAGE DETECTOR. 18.3.5 Reset operation by clock monitor When the clock monitor operation is enabled, the main clock is monitored by using the sampling clock (internal oscillator). If stoppage of the main clock is detected, the system is reset and each hardware unit is initialized to the default status. For details, see CHAPTER 19 CLOCK MONITOR. Preliminary User's Manual U17718EJ1V0UD 581 www..com CHAPTER 19 CLOCK MONITOR 19.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 18.2 Registers to Check Reset Source. The clock monitor automatically stops under the following conditions. * During oscillation stabilization time after STOP mode is released * When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit = 0 during main clock operation) * When the sampling clock (internal oscillation clock) is stopped * When the CPU operates with the internal oscillation clock 19.2 Configuration The clock monitor includes the following hardware. Table 19-1. Configuration of Clock Monitor Item Control register Configuration Clock monitor mode register (CLM) Figure 19-1. Block Diagram of Clock Monitor Main clock Internal reset signal Internal oscillation clock Enable/disable CLME Clock monitor mode register (CLM) 582 Preliminary User's Manual U17718EJ1V0UD CHAPTER 19 CLOCK MONITOR www..com 19.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7 Special registers). This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 CLM 0 R/W 6 0 Address: FFFFF870H 5 0 4 0 3 0 2 0 1 0 0 CLME CLME 0 1 Clock monitor operation enable or disable Disable clock monitor operation. Enable clock monitor operation. Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other than reset. 2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the RESF.CLMRF bit is set to 1. Preliminary User's Manual U17718EJ1V0UD 583 CHAPTER 19 CLOCK MONITOR www..com 19.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. CPU Operating Clock Operation Mode Status of Main Clock Status of Internal Oscillation Clock Main clock HALT mode IDLE1, IDLE2 modes STOP mode Subclock (MCK bit of PCC register = 0) Subclock (MCK bit of PCC register = 1) Internal oscillation clock During reset - Stops Stops Stops - Stops Oscillates Note 1 Note 1 Status of Clock Monitor Operates Operates Stops Operates Note 2 Note 2 Oscillates Oscillates Stops Oscillates Oscillates Oscillates Note 1 Note 2 Oscillates Note 1 Sub-IDLE mode Oscillates Note 1 Sub-IDLE mode Stops Oscillates Note 1 Stops Stops Notes 1. The internal oscillator can be stopped by using the option byte function (see CHAPTER 24) to enable the internal oscillator to stop, and setting the RCM.RSTOP bit to 1. 2. The clock monitor is stopped while the internal oscillator is stopped. 584 Preliminary User's Manual U17718EJ1V0UD CHAPTER 19 CLOCK MONITOR www..com (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 19-2. Figure 19-2. Reset Period Due to That Oscillation of Main Clock Is Stopped Four internal oscillation clocks Main clock Internal oscillation clock Internal reset signal CLM.CLME bit RESF.CLMRF bit (2) Clock monitor status after RESET input RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by software at the end of the oscillation stabilization time of the main clock, monitoring is started. Figure 19-3. Clock Monitor Status After RESET Input (CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time) CPU operation Main clock Normal operation Reset Clock supply stopped Normal operation Oscillation stabilization time Internal oscillation clock RESET Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring Preliminary User's Manual U17718EJ1V0UD 585 CHAPTER 19 CLOCK MONITOR www..com (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started. Figure 19-4. Operation in STOP Mode or After STOP Mode Is Released CPU Normal operation operation Main clock STOP Oscillation stabilization time Normal operation Oscillation stops Internal oscillation clock Oscillation stabilization time (set by OSTS register) CLME Clock monitor status During monitor Monitor stops During monitor (4) Operation when main clock is stopped (arbitrary) During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation is automatically started when the main clock operation is started. Figure 19-5. Operation When Main Clock Is Stopped (Arbitrary) CPU operation Subclock operation PCC.MCK bit = 1 Oscillation stabilization time count by software Main clock operation Main clock Oscillation stops Oscillation stabilization time (set by OSTS register) Internal oscillation clock CLME Clock monitor status During monitor Monitor stops Monitor stops During monitor (5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1) The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1. 586 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 20 POWER-ON CLEAR CIRCUIT 20.1 Function Functions of the power-on-clear (POC) circuit are shown below. * Generates a reset signal upon power application. * Compares the supply voltage (VDD) and detection voltage (VPOC0), and generates a reset signal when VDD < VPOC0 (detection voltage (VPOC0): 3.7 V 0.2 V). Remarks 1. The V850ES/HG2 has plural internal hardware units that generate an internal reset signal. When the system is reset by watchdog timer 2 (WDT2RES), low-voltage detector (LVI), or clock monitor (CLM), a flag corresponding to the reset source is allocated to the reset source flag register (RESF). The RESF register is not cleared when an internal reset signal is generated by WDT2RES, LVI, or clock monitor, and its flag corresponding to the reset source is set to 1. For details of the RESF register, see CHAPTER 18 RESET FUNCTIONS. 2. The time from power application to starting program execution is "Time from power application to releasing reset + 16 ms" if the operating frequency of a resonator externally connected is 5 MHz. However, it varies depending on the external cause (such as a status of supply voltage to the microcontroller and the stabilization time of the resonator). 20.2 Configuration The block diagram is shown below. Figure 20-1. Block Diagram of Power-on-Clear Circuit VDD + - Internal reset signal Detection voltage source (VPOC0) Preliminary User's Manual U17718EJ1V0UD 587 CHAPTER 20 POWER-ON CLEAR CIRCUIT www..com 20.3 Operation When the supply voltage and detection voltage are compared and if the supply voltage is lower than the detection voltage (including at power application), the system is reset and each hardware is returned to the specific status. Figure 20-2. Timing of Reset Signal Generation by Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC0) Time POC detection signal Delay Internal reset signal Reset period (excluding oscillation stabilization time) Reset period Reset period (excluding oscillation stabilization time) (excluding oscillation stabilization time) 588 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 21 LOW-VOLTAGE DETECTOR 21.1 Functions The low-voltage detector (LVI) has the following functions. * Compares the supply voltage (VDD) and detection voltage (VLVI) and generates an interrupt request signal or internal reset signal when VDD < VLVI. * The level of the supply voltage to be detected can be changed by software (in two steps). * An interrupt request signal or internal reset signal can be selected. * Can operate in STOP mode. * Operation can be stopped by software. If the low-voltage detector is used to generate a reset signal, the RESF.LVIRF bit is set to 1 when the reset signal is generated. For details of the RESF register, see CHAPTER 18 RESET FUNCTIONS. 21.2 Configuration The block diagram is shown below. Figure 21-1. Block Diagram of Low-Voltage Detector VDD VDD Lowvoltage detection level selector N-ch Internal reset signal + - Selector INTLVI Detection voltage source (VLVI) LVIS0 Low-voltage detection level select register (LVIS) Internal bus LVION LVIMD LVIF Low-voltage detection register (LVIM) Preliminary User's Manual U17718EJ1V0UD 589 CHAPTER 21 LOW-VOLTAGE DETECTOR www..com 21.3 Registers (1) Low-voltage detection register (LVIM) The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the lowvoltage detector. The LVIM register is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only. After reset: 00H 7 LVIM LVION R/W 6 0 Address: FFFFF890H 5 0 4 0 3 0 2 0 1 LVIMD 0 LVIF LVION 0 1 Low voltage detection operation enable or disable Disable operation. Enable operation. LVIMD 0 1 Selection of operation mode of low voltage detection Generate interrupt request signal INTLVI when supply voltage < detection voltage. Generate internal reset signal LVIRES when supply voltage < detection voltage. LVIF 0 1 Low voltage detection flag When supply voltage > detection voltage, or when operation is disabled Supply voltage < detection voltage Cautions 1. After setting the LVION bit to 1, wait for 0.2 ms (TYP.) (target value) before checking the voltage using the LVIF bit. 2. The value of the LVIF flag is output as the output signal INTLVI when the LVION bit = 1 and LVIMD bit = 0. 3. Be sure to clear bits 2 to 6 to "0". 590 Preliminary User's Manual U17718EJ1V0UD CHAPTER 21 LOW-VOLTAGE DETECTOR www.DataShee (2) Low-voltage detection level select register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit units. After reset: 00H 7 LVIS 0 R/W 6 0 Address: FFFFF891H 5 0 4 0 3 0 2 0 1 0 0 LVIS0 LVIS0 0 1 4.4 V 0.2 V 4.2 V 0.2 V Detection level Cautions 1. This register cannot be written until a reset request due to something other than low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits are set to 1. 2. Be sure to clear bits 1 to 7 to "0". (3) Internal RAM data status register (RAMS) The RAMS register is a flag register that indicates whether the internal RAM is valid or not. The RAMS register is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special registers). For the RAMS register, see 21.5 RAM Retention Voltage Detection Operation. This register can be read or written in 8-bit or 1-bit units. Caution The following shows the specific sequence after reset. * Setting conditions: Detection of voltage lower than detection level Set by instruction Generation of reset signal by watchdog timer overflow Generation of reset signal while RAM is being accessed Generation of reset signal by clock monitor * Clearing condition: Writing of 0 in specific sequence After reset: 01H 7 RAMS 0 R/W 6 0 Address: FFFFF892H 5 0 4 0 3 0 2 0 1 0 0 RAMF RAMF 0 1 Valid Invalid Internal RAM data valid/invalid Preliminary User's Manual U17718EJ1V0UD 591 CHAPTER 21 LOW-VOLTAGE DETECTOR www..com 21.4 Operation Depending on the setting of the LVIM.LVIMD bit, an interrupt request signal (INTLVI) or an internal reset signal is generated. 21.4.1 To use for internal reset signal 592 Preliminary User's Manual U17718EJ1V0UD CHAPTER 21 LOW-VOLTAGE DETECTOR www..com Figure 21-2. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1) Supply voltage (VDD) LVI detection voltage POC detection voltage Set (by instruction, refer to <3> above) LVION bit Delay Delay LVI detection signal Delay Time Clear (by POC reset request signal) Delay Delay LVI reset request signal Cleared by instruction LVIRF bitNote 1 Delay Delay Delay POC reset request signal Note 2 Internal reset signal (active low) Notes 1. The LVIRF bit is bit 0 of the reset source flag register (RESF). For details of RESF, see CHAPTER 18 RESET FUNCTIONS. 2. During the period in which the supply voltage is the set voltage or lower, the internal reset signal is retained (internal reset state). Preliminary User's Manual U17718EJ1V0UD 593 CHAPTER 21 LOW-VOLTAGE DETECTOR www..com 21.4.2 To use for interrupt Supply voltage (VDD) LVI detection voltage POC detection voltage Set (by instruction, refer to <3> above.) LVION bit Delay LVI detection signal Delay Time Clear (by POC reset request signal) Delay Delay Delay INTLVI signal LVIF bit Delay Delay POC reset request signal Delay Internal reset signal (active low) 594 Preliminary User's Manual U17718EJ1V0UD CHAPTER 21 LOW-VOLTAGE DETECTOR www..com 21.5 RAM Retention Voltage Detection Operation The supply voltage and detection voltage are compared. When the supply voltage drops below the detection voltage (including on power application), the RAMS.RAMF bit is set (1). When the POC function is not used and when the RAM retention voltage detection function is used, be sure to input an external reset signal if the detected voltage falls below the operating voltage. Figure 21-4. Operation Timing of RAM Retention Voltage Detection Function Supply voltage (VDD) POC detection voltage RAM retention detection voltage Time Delay POC detection voltage Note Set condition detection signal Delay Set RAM retention voltage detection signal RAM retention flag (RAMF bit) Set Delay Delay Cleared by instruction Cleared by instruction Note A reset signal (WDTRES) is generated due to an overflow of the watchdog timer or RESET pin input during RAM access. Preliminary User's Manual U17718EJ1V0UD 595 CHAPTER 21 LOW-VOLTAGE DETECTOR www..com 21.6 Emulation Function When an in-circuit emulator is used, the operation of the RAM retention flag (RAMS.RAMF bit) can be pseudocontrolled and emulated by manipulating the PEMU1 register on the debugger. This register is valid only in the emulation mode. It is invalid in the normal mode. (1) Peripheral emulation register 1 (PEMU1) After reset: 00H 7 PEMU1 0 R/W 6 0 Address: FFFFF9FEH 5 0 4 0 3 0 2 EVARAMIN 1 0 0 0 EVARAMIN 0 1 Pseudo specification of RAM retention voltage detection signal Do not detect voltage lower than RAM retention voltage. Detect voltage lower than RAM retention voltage (set RAMF flag). Caution This bit is not automatically cleared. [Usage] When an in-circuit emulator is used, pseudo emulation of RAMF is realized by rewriting this register on the debugger. <1> CPU break (CPU operation stops.) <2> Set the EVARAMIN bit to 1 by using a register write command. By setting the EVARAMIN bit to 1, the RAMF bit is set to 1 on hardware (the internal RAM data is invalid). <3> Clear the EVARAMIN bit to 0 by using a register write command again. Unless this operation is performed (clearing the EVARAMIN bit to 0), the RAMF bit cannot be cleared to 0 by a CPU operation instruction. <4> Run the CPU and resume emulation. 596 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 22 REGULATOR 22.1 Overview The V850ES/HG2 includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter and output buffers). The regulator output voltage is set to 2.5 V (TYP.). Figure 22-1. Regulator AVREF0 A/D converter BVDD I/O buffer BVDD FLMD0 VDD REGC Main/sub oscillator Internal digital circuits 2.5 V (TYP.) Regulator Flash memory EVDD EVDD I/O buffer Bidirectional level shifter Preliminary User's Manual U17718EJ1V0UD 597 CHAPTER 22 REGULATOR www..com 22.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, or during reset). Be sure to connect a capacitor (4.7 F (preliminary value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below. Figure 22-2. REGC Pin Connection VDD Input voltage = 3.5 to 5.5 V REG REGC Voltage supply to main oscillator/internal logic = 2.5 V (TYP.) 4.7 F (preliminary value) VSS 598 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 23 FLASH MEMORY The following can be considered as the development environment and mass production applications using flash memory versions. For altering software after the V850ES/HG2 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models. For facilitating inventory management. For updating software after shipment. 23.1 Features 4-byte/1-clock access (when instruction is fetched) Capacity: 256 KB/128 KB Write voltage: Erase/write with a single power supply Rewriting method * Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) Flash memory write prohibit function supported (security function) Safe rewriting of entire flash memory area by self programming using boot swap function Interrupts can be acknowledged during self programming. Preliminary User's Manual U17718EJ1V0UD 599 CHAPTER 23 FLASH MEMORY www..com 23.1.1 Erasure unit The units in which the 256 or 128 KB flash memory can be erased are as follows. (1) All-area erasure The flash memory areas can be erased at the same time. (2) Block erasure The flash memory can be erased in block unitsNote. Block 0: 56 KB Block 1: 8 KB Block 2: 56 KB Block 3: 8 KB Block 4: 56 KB Block 5: 56 KB Block 6: 8 KB Block 7: 8 KB Note 4 blocks, blocks 0 to 3, for the 128 KB version (PD70F3706). 8 blocks, blocks 0 to 7, for the 256 KB version (PD70F3707). 600 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com 23.2 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/HG2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 23.2.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850ES/HG2. Figure 23-1. Environment Required for Writing Programs to Flash Memory RS-232C XXXX YYYY FLMD0 FLMD1 Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) USB Dedicated flash programmer Host machine XXXXX STATVE VDD VSS RESET UARTA0/CSIB0 V850ES/HG2 A host machine is required for controlling the dedicated flash programmer. UARTA0 or CSIB0 is used for the interface between the dedicated flash programmer and the V850ES/HG2 to perform writing, erasing, etc. A dedicated program adapter (FA series) required for off-board writing. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Preliminary User's Manual U17718EJ1V0UD 601 CHAPTER 23 FLASH MEMORY www..com 23.2.2 Communication mode Communication between the dedicated flash programmer and the V850ES/HG2 is performed by serial communication using the UARTA0 or CSIB0 interfaces of the V850ES/HG2. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 23-2. Communication with Dedicated Flash Programmer (UARTA0) FLMD0 FLMD1 XXXX YYYY FLMD0 FLMD1 VDD VSS RESET TXDA0 RXDA0 V850ES/HG2 Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx VDD GND Dedicated flash programmer RESET RxD TxD Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor of 1 k to 10 k as necessary. 2. Do not input a high level to the DRST pin. (2) CSIB0 Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 23-3. Communication with Dedicated Flash Programmer (CSIB0) FLMD0 FLMD1 VDD XXXX YYYY XXXXXX FLMD0 FLMD1 VDD VSS RESET SOB0 SIB0 SCKB0 V850ES/HG2 Axxxx Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE GND RESET Dedicated flash programmer XXXX SI SO SCK Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor of 1 k to 10 k as necessary. 2. Do not input a high level to the DRST pin. 602 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com (3) CSIB0 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 23-4. Communication with Dedicated Flash Programmer (CSIB0 + HS) FLMD0 FLMD1 FLMD0 FLMD1 VDD XXXXXX VDD VSS RESET SOB0 SIB0 SCKB0 PCM0 V850ES/HG2 Axxxx XXXX YYYY Bxxxxx Cxxxxxx GND RESET XXX YYY PG-FP4 (Flash Pro4) Dedicated flash programmer XXXXX STATVE XXXX SI SO SCK HS Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor of 1 k to 10 k as necessary. 2. Do not input a high level to the DRST pin. The dedicated flash programmer outputs the transfer clock, and the V850ES/HG2 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/HG2. For details, refer to the PG-FP4 User's Manual (U15260E). Table 23-1. Signal Connections of Dedicated Flash Programmer (PG-FP4) PG-FP4 Signal Name FLMD0 FLMD1 VDD GND CLK RESET SI/RxD SO/TxD SCK HS I/O Output Output - - Output Output Input Output Output Input Pin Function Write enable/disable Write enable/disable VDD voltage generation/voltage monitor Ground Clock output to V850ES/HG2 Reset signal Receive signal Transmit signal Transfer clock Handshake signal for CSIB0 + HS communication V850ES/HG2 Pin Name FLMD0 FLMD1 VDD VSS X1, X2 RESET SOB0, TXDA0 SIB0, RXDA0 SCKB0 PCM0 x x x x Note 2 Note 1 Note 1 Note 1 Processing for Connection UARTA0 CSIB0 CSIB0 + HS x Note 2 x Note 2 Notes 1. Wire these pins as shown in Figure 23-5, or connect then to GND via pull-down resistor on board. 2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and supply the clock. Remark : Must be connected. x: Does not have to be connected. Preliminary User's Manual U17718EJ1V0UD 603 CHAPTER 23 FLASH MEMORY www..com Table 23-2. Wiring of Flash Writing Adapter for V850ES/HG2 (FA-100GC-8EU) Flash Programmer (PG-FP4) Connection Pins Signal Name SI/RxD I/O Pin Function Pin Name on FA Board When CSIB0 + HS Is Used Pin Name Pin No. 23 22 24 - - 14 8 76 61 Pin Name Pin No. 23 22 24 - - 14 8 76 - Pin Name Pin No. 25 26 - - - 14 8 76 - When CSIB0 Is Used When UARTA0 Is Used Input Receive signal SI SO SCK X1 X2 /RESET FLMD0 FLMD1 P41/SOB0 P40/SIB0 P42/SCKB0 Not necessary Not necessary RESET FLMD0 PDL5/FLMD1 P41/SOB0 P40/SIB0 P42/SCKB0 Not necessary Not necessary RESET FLMD0 PDL5/FLMD1 Not necessary P30/TXDA0 P31/RXDA0/INTP7 Not necessary Not necessary Not necessary RESET FLMD0 PDL5/FLMD1 Not necessary SO/TxD Output Transmit signal SCK CLK Output Transfer clock Output Clock to V850ES/HG2 /RESET Output Reset signal FLMD0 FLMD1 HS Input Input Input Write voltage Write voltage Handshake signal of CSI0 + HS communication VDD - VDD voltage generation/ voltage monitor RESERVE/ PCM0 HS VDD VDD BVDD EVDD AVREF0 9 70 VDD BVDD 9 70 VDD BVDD 9 70 5, 34 1 11 2 69 33 5, 34 EVDD 1 11 2 69 33 AVREF0 VSS AVSS BVSS EVSS 5, 34 EVDD 1 11 2 69 33 AVREF0 VSS AVSS BVSS EVSS GND - Ground GND VSS AVSS BVSS EVSS Cautions 1. Be sure to connect the REGC pin to GND via a 4.7 F (preliminary value) capacitor. 2. A clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board and supply the clock from that oscillator. 604 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com Figure 23-5. Example of Wiring of V850ES/HG2 Flash Writing Adapter (FA-100GC-8EU) (in CSIB0 + HS Mode) (1/2) VD D G N D D VD D N G 70 76 Note 1 69 61 PD70F3706, PD70F3707 34 33 Connect to GND Connect to VDD 4.7 F (preliminary value) 100 1 G N D VD D Note 3 2 5 8 9 10 11 12 13 14 22 23 Note 2 24 25 26 G N D VD D RFU-3 RUF-2 RFU-1 VDE FLMD1 FLMD0 SI SO SCK X1 X2 /RESET VPP RESERVE/HS Preliminary User's Manual U17718EJ1V0UD 605 CHAPTER 23 FLASH MEMORY www..com Figure 23-5. Example of Wiring of V850ES/HG2 Flash Writing Adapter (FA-100GC-8EU) (in CSIB0 + HS Mode) (2/2) Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 2. Pins used when UARTA0 is used 3. Supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines). Here is an example of the oscillator. Example X1 X2 Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with processing of unused pins (see 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins). 2. This adapter is used for the 100-pin plastic LQFP package. 606 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com 23.2.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 23-6. Procedure for Manipulating Flash Memory Start Supplies FLMD0 pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? Yes End No Preliminary User's Manual U17718EJ1V0UD 607 CHAPTER 23 FLASH MEMORY www..com 23.2.4 Selection of communication mode In the V850ES/HG2, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 23-7. Selection of Communication Mode VDD VDD VSS VDD RESET (input) VSS VDD FLMD1 (input) VSS VDD FLMD0 (input) VSS VDD RXDA0 (input) VSS VDD TXDA0 (output) VSS Oscillation stabilized Power on Reset released Communication mode selected Flash control command communication (erasure, write, etc.) (Note) Note The number of clocks is as follows depending on the communication mode. FLMD0 Pulse 0 8 11 Other Communication Mode UARTA0 CSIB0 CSIB0 + HS RFU Remarks Communication rate: 9,600 bps (after reset), LSB first V850ES/HG2 performs slave operation, MSB first V850ES/HG2 performs slave operation, MSB first Setting prohibited Caution When UARTA0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse. 608 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com 23.2.5 Communication commands The V850ES/HG2 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/HG2 are called "commands". The response signals sent from the V850ES/HG2 to the dedicated flash programmer are called "response commands". Figure 23-8. Communication Commands Command XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Response command V850ES/HG2 Dedicated flash programmer The following shows the commands for flash memory control in the V850ES/HG2. All of these commands are issued from the dedicated flash programmer, and the V850ES/HG2 performs the processing corresponding to the commands. Table 23-3. Flash Memory Control Commands Classification Command Name CSIB0 Blank check Block blank check command Erase Chip erase command Block erase command Support CSIB0 + HS UARTA0 Checks if the contents of the memory in the specified block have been correctly erased. Erases the contents of the entire memory. Erases the contents of the memory of the specified block. Write Write command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash programmer. Checksum command Reads the checksum in the specified address range. System setting, control Silicon signature command Security setting command Disables the block erase, chip erase, program, read commands, and rewriting of the boot area. Reads silicon signature information. Function Preliminary User's Manual U17718EJ1V0UD 609 CHAPTER 23 FLASH MEMORY www..com 23.2.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS level to the FLMD0 pin. programming mode, supply a write voltage of VDD level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 23.3.5 (1) FLMD0 pin. Figure 23-9. FLMD0 Pin Connection Example In the flash memory V850ES/HG2 Dedicated flash programmer connection pin FLMD0 Pull-down resistor (RFLMD0) (2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 23-10. FLMD1 Pin Connection Example V850ES/HG2 FLMD1 Other device Pull-down resistor (RFLMD1) Caution If the VDD signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal. 610 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com Table 23-4. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 0 VDD VDD FLMD1 Don't care 0 VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface. Table 23-5. Pins Used by Serial Interfaces Serial Interface UARTA0 CSIB0 CSIB0 + HS Pins Used TXDA0, RXDA0 SOB0, SIB0, SCKB0 SOB0, SIB0, SCKB0, PCM0 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 23-11. Conflict of Signals (Serial Interface Input Pin) V850ES/HG2 Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pins In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side. Preliminary User's Manual U17718EJ1V0UD 611 CHAPTER 23 FLASH MEMORY www..com (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 23-12. Malfunction of Other Device V850ES/HG2 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/HG2 outputs affects the other device, isolate the signal on the other device side. V850ES/HG2 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. 612 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 23-13. Conflict of Signals (RESET Pin) V850ES/HG2 Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. (5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. (6) Other signal pins Connect X1, X2, XT1, and XT2 in the same status as that in the normal operation mode. During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level. (7) Power supply Supply the same power (VDD, VSS, EVDD, EVSS, BVDD, BVSS, AVREF0, AVSS, REGC) as in normal operation mode. Preliminary User's Manual U17718EJ1V0UD 613 CHAPTER 23 FLASH MEMORY www..com 23.2.7 Recommended circuit example for writing Figure 23-14 shows the recommended circuit example for writing. Figure 23-14. Procedure for Manipulating Flash Memory 5V VDD VSS RESET SOB0/TXDA0 SIB0/RXDA0 SCKB0 FLMD0 FLMD1 Pull-down resistor (RFLMD1) REGC Capacitor (capacitance = 4.7 pF) VDD VSS RESET SIB0/RXDA0 SOB0/TXDA0 SCKB0 FLMD0 FLMD1 XXXXXX Axxxx XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) V850ES/HG2 Flashpro IV 614 Preliminary User's Manual U17718EJ1V0UD XXXXX STATVE XXXX CHAPTER 23 FLASH MEMORY www..com 23.3 Rewriting by Self Programming 23.3.1 Overview The V850ES/HG2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the field. Figure 23-15. Concept of Self Programming Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory Preliminary User's Manual U17718EJ1V0UD 615 CHAPTER 23 FLASH MEMORY www..com 23.3.2 Features (1) Secure self programming (boot swap function) The V850ES/HG2 supports a boot swap function that can exchange the physical memory of blocks 0 and 1 with the physical memory of blocks 2 and 3. By writing the start program to be rewritten to blocks 2 and 3 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 and 1. Figure 23-16. Rewriting Entire Memory Area (Boot Swap) Last block : Block 4 Last block : Block 4 Boot swap Last block : Block 4 Block 3 Block 3 Block 3 Block 2 Rewriting blocks 2 and 3 Block 2 Block 2 Block 1 Block 1 Block 1 Block 0 Block 0 Block 0 (2) Interrupt support Instructions cannot be fetched from the flash memory during self programming. Conventionally, a user handler written to the flash memory could not be used even if an interrupt occurred. Therefore, in the V850ES/HG2, to use an interrupt during self programming, processing transits to the specific addressNote in the internal RAM. Allocate the jump instruction that transits processing to the user interrupt servicing at the specific addressNote in the internal RAM. Note NMI interrupt: Start address of internal RAM Maskable interrupt: Start address of internal RAM + 4 addresses 616 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com 23.3.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 23-17. Standard Self Programming Flow Flash memory manipulation Flash environment initialization processing * Disable accessing flash area * Disable setting of STOP mode * Disable stopping clock Erase processing Write processing Flash information setting processingNote 1 Internal verify processing All blocks end? Yes Boot area swap processingNote 2 No Flash environment end processing End of processing Notes 1. If a security setting is not performed, flash information setting processing does not have to be executed. 2. If boot swap is not used, flash information setting processing and boot swap processing do not have to be executed. Preliminary User's Manual U17718EJ1V0UD 617 CHAPTER 23 FLASH MEMORY www..com 23.3.4 Flash functions Table 23-6. Flash Function List Function Name FlashEnv FlashBlockErase FlashWordWrite FlashBlockIVerify FlashBlockBlankCheck FlashFLMDCheck FlashStatusCheck FlashGetInfo FlashSetInfo FlashBootSwap FlashWordRead FlashSetUserHandler Outline Initialization of flash control macro Erasure of specified one block Writing from specified address Internal verification of specified one block Blank check of specified one block Check of FLMD pin Status check of operation specified immediately before Reading of flash information Setting of flash information Swapping of boot area Data read from specified address User interrupt handler registration function Support 23.3.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0 V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD level to the FLMD0 pin during the self programming mode period via port control before the memory is rewritten. When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V. Figure 23-18. Mode Change Timing RESET signal VDD 0V Self programming mode VDD FLMD0 pin 0V Normal operation mode Normal operation mode Caution Make sure that the FLMD0 pin is at 0 V when reset is released. 618 Preliminary User's Manual U17718EJ1V0UD CHAPTER 23 FLASH MEMORY www..com 23.3.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 23-7. Internal Resources Used Resource Name Stack area (user stack + (TBD) bytes) Library code ((TBD) bytes) Description An extension of the stack used by the user is used by the library (can be used in both the internal RAM and external RAM). Program entity of library (can be used anywhere other than the flash memory block to be manipulated). Application program Executed as a user application. Calls flash functions. Maskable interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal RAM start address + 4 addresses in advance. NMI interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal RAM start address in advance. Preliminary User's Manual U17718EJ1V0UD 619 www..com CHAPTER 24 OPTION BYTE FUNCTION The option byte is stored in address 000007AH of the internal flash memory (internal ROM area) as 8-bit data. When writing a program to the V850ES/HG2, be sure to set the option data corresponding to the following option in the program at address 000007AH as default data. The data in this area cannot be rewritten during program execution. Address: 0000007AH OPB7 OPB6 - - - - OPB1 OPB0 OPB7 0 1 OPB6 0 1 Subclock operation mode setting Crystal resonator mode RC oscillator mode OPB1 0 Watchdog timer 2 mode setting Operating clock (fX/fR) selectable INTWDT2 mode/WDTRES mode selectable 1 Fixed to internal oscillation clock (fR) Fixed to WDTRES mode OPB0 0 1 Stopping internal oscillator enable/disable Stopping enabled Stopping disabled 620 Preliminary User's Manual U17718EJ1V0UD www..com CHAPTER 25 ON-CHIP DEBUG FUNCTION The V850ES/HG2 has an on-chip debug function that uses the JTAG (Joint Test Action Group) interface (DRST, DCK, DMS, DDI, and DDO pins) and that can be used via an on-chip debug emulator (MINICUBE(R)). 25.1 Features Hardware break function: 2 points Software break function: 4 points Real-time RAM monitor function: Memory contents can be read during program execution. Dynamic memory modification function (DMM function): RAM contents can be rewritten during program execution. Mask function: RESET, NMI ROM security function: 10-byte ID code authentication Caution The following functions are not supported. * Trace function * Event function * Debug interrupt interface function (DBINT) Preliminary User's Manual U17718EJ1V0UD 621 CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.2 Connection Circuit Example VDD EVDD Note 1 STATUS TARGET POWER DCK DMS DDI DDO DRST RESET FLMD0 DCK DMS DDI DDO DRSTNote 2 RESET FLMD0Note 3 FLMD1/PDL5 GND EVSS MINICUBE V850ES/HG2 Notes 1. Example of pin connection when MINICUBE is not connected 2. A pull-down resistor is provided on chip. 3. For flash memory rewriting 622 Preliminary User's Manual U17718EJ1V0UD CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.3 Interface Signals The interface signals are described below. (1) DRST This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously initializes the debug control unit. MINICUBE raises the DRST signal when it detects VDD of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. When the DRST signal goes high, a reset signal is also generated in the CPU. When starting debugging by starting the integrated debugger, a CPU reset is always generated. (2) DCK This is a clock input signal. It supplies a 20 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge. (3) DMS This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the DMS signal. (4) DDI This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK. (5) DDO This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal. (6) EVDD This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the signals output from MINICUBE (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a high-impedance state. Preliminary User's Manual U17718EJ1V0UD 623 CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com (7) FLMD0 The flash self programming function is used for the function to download data to the flash memory via the integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a pull-down resistor to the FLMD0 pin. The FLMD0 pin can be controlled in either of the following two ways. <1> To control from MINICUBE Connect the FLMD0 signal of MINICUBE to the FLMD0 pin. In the normal mode, nothing is driven by MINICUBE (high impedance). During a break, MINICUBE raises the FLMD0 pin to the high level when the download function of the integrated debugger is executed. <2> To control from port Connect any port of the device to the FLMD0 pin. The same port as the one used by the user program to realize the flash self programming function may be used. On the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. For details, refer to the ID850QB Ver. 3.10 Integrated Debugger Operation User's Manual (U17435E). (8) RESET This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM.OCDM0 bit set by the user program, on-chip debugging cannot be executed. Therefore, reset is effected by MINICUBE, using the RESET pin, to make the DRST pin valid (initialization). 624 Preliminary User's Manual U17718EJ1V0UD CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.4 Register (1) On-chip debug mode register (OCDM) The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a special register and can be written only in a combination of specific sequences (see 3.4.7 Special registers). This register is also used to specify whether a pin provided with an on-chip debug function is used as an onchip debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pulldown resistor of the P05 pin. The OCDM register can be written only while a low level is input to the P05 pin. This register can be read or written in 8-bit or 1-bit units. After reset: 01HNote R/W Address: FFFFF9FCH OCDM 0 0 0 0 0 0 0 OCDM0 OCDM0 0 Operation mode Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P05 pin. When P05 pin is low: Normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) When P05 pin is high: On-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) 1 Note The value of this register is 01H after reset by the RESET pin and is 00H after reset by power-on-clear circuit (POC). After reset by the WDTRES2 signal, clock monitor (CLM), or low-voltage detector (LVI), however, the value of the OCDM register is retained. Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins after external reset, the following actions must be taken. * Input a low level to the P05 pin. * Set the ODCM0 bit. In this case, take the following actions. <1> Clear the OCDM0 bit to 0. <2> Fix the P05 pin to the low level until <1> is completed. 2. The P05 pin has an on-chip pull-down resistor. This resistor is disconnected when the OCDM0 flag is cleared to 0. P05 OCDM0 flag (1: Pull-down ON, 0: Pull-down OFF) 10 to 100 k (30 k (TYP.)) Preliminary User's Manual U17718EJ1V0UD 625 CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag DRST Pin L H Invalid Invalid Invalid Valid 0 1 Remark L: Low-level input H: High-level input Figure 25-1. Timing When On-Chip Debug Function Is Not Used Releasing reset RESET Clearing OCDM0 bit OCDM0 P05/INTP2/DRST Low-level input After OCDM0 bit is cleared, high level can be input/output. 626 Preliminary User's Manual U17718EJ1V0UD CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.6 ROM Security Function 25.6.1 Security ID The flash memory versions of the V850ES/HG2 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication. If the IDs match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. * Set the 10-byte ID code to 0000070H to 0000079H. * Bit 7 of 0000079H is the on-chip debug emulator enable flag. (0: Disable, 1: Enable) * When the on-chip debug emulator is started, the debugger requests ID input. When the ID code input on the debugger and the ID code set in 0000070H to 0000079H match, the debugger starts. * Debugging cannot be performed if the on-chip debug emulator enable flag is 0, even if the ID codes match. 0000079H Security ID (10 bytes) 0000070H 0000000H Caution When the data in the flash memory has been deleted, all the bits are set to 1. Preliminary User's Manual U17718EJ1V0UD 627 CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com 25.6.2 Setting The following shows how to set the ID code as shown in Table 25-1. When the ID code is set as shown in Table 25-1, the ID code input in the configuration dialog box of the ID850QB is "123456789ABCDEF123D4" (not case-sensitive). Table 25-1. ID Code Address 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x12 0x34 0x56 0x78 0x9A 0xBC 0xDE 0XF1 0x23 0xD4 Value The ID code can be specified for the device file that supports the CA850 Ver. 2.60 or later and the security ID by the PM+ linker option setting. 628 Preliminary User's Manual U17718EJ1V0UD CHAPTER 25 ON-CHIP DEBUG FUNCTION www..com [Program example (when using CA850 Ver. 2.60 or later)] #-------------------------------------# SECURITYID (continue ILGOP .section .word .word .hword Remark "SECURITY_ID" 0x78563412 0xF1DEBC9A 0xD423 handler) --Interrupt handler address 0x70 --0-3 byte code --4-7 byte code --8-9 byte code #-------------------------------------- Add the above program example to the startup files. 25.7 Cautions (1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction. (2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is input from a pin. (3) Because a software breakpoint set in the internal flash memory is realized by the ROM correction function, it is made temporarily invalid by target reset or internal reset generated by watchdog timer 2. The breakpoint becomes valid again when a hardware break or forced break occurs, but a software break does not occur until then. (4) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset is generated as soon as the flash memory is rewritten by DMA or read by the RAM monitor function while the user program is being executed, the CPU and peripheral I/O may not be correctly reset. (5) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output. Preliminary User's Manual U17718EJ1V0UD 629 www..com CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) 26.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD BVDD EVDD AVREF0 VSS AVSS BVSS EVSS Input voltage VI1 VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915, RESET, FLMD0 VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VI3 Analog input voltage VIAN X1, X2, XT1, XT2 P70 to P715 -0.5 to VRO + 0.5 Note Conditions VDD = EVDD = BVDD VDD = EVDD = BVDD VDD = EVDD = BVDD Ratings -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to EVDD + 0.5 -0.5 to BVDD + 0.5 Note Unit V V V V V V V V V Note V V V -0.5 to AVREF0 + 0.5 Note Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. 3. When directly connecting the external circuit to the pin that becomes high impedance state, the timing must be designed such that output conflict is avoided on the external circuit. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 630 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 P70 to P715 Per pin Total of all pins Per pin Total of all pins PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Output current, high IOH P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 P70 to P715 Per pin Total of all pins Per pin Total of all pins Per pin Total of all pins PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Operating ambient temperature Storage temperature Tstg TA Normal operation mode Flash memory programming mode -40 to +125 C Per pin Total of all pins Ratings 4 50 4 20 4 50 -4 -50 -4 -20 -4 -50 -40 to +85 Unit mA mA mA mA mA mA mA mA mA mA mA mA C Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. 3. When directly connecting the external circuit to the pin that becomes high impedance state, the timing must be designed such that output conflict is avoided on the external circuit. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17718EJ1V0UD 631 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.2 Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = VSS = EVSS = BVSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO fX = 1 MHz, Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 10 Unit pF 26.3 Operating Conditions (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Internal system clock frequency Symbol fCLK REGC = 4.7 F, at operation with main clock REGC = 4.7 F, at operation with subclock (crystal resonator) REGC = 4.7 F, at operation with subclock (RC resonator) 12.5 Note Conditions MIN. 4 TYP. MAX. 20 Unit MHz 32 35 Note kHz 27.5 kHz Note The internal system clock frequency is half the oscillation frequency. 632 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.4 Oscillator Characteristics 26.4.1 Main clock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 4 TYP. MAX. 5 Unit MHz Oscillation stabilization time Note 2 After reset release After STOP mode release 0.5 Note 3 2 /fX Note 4 16 s ms X1 X2 After IDLE2 mode release 0.35 Note 4 ms Crystal resonator Oscillation frequency (fX) Note 1 4 16 5 MHz Oscillation stabilization time Note 2 After reset release After STOP mode release After IDLE2 mode release 0.35 0.5 Note 3 2 /fX Note 4 s ms Note 4 ms Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the crystal resonator after reset or STOP mode is released. 3. Time required to stabilize access to the internal flash memory. 4. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the subclock is operating, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. Preliminary User's Manual U17718EJ1V0UD 633 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.4.2 Subclock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz XT1 XT2 (fXT) Oscillation stabilization time Note 2 10 s RC resonator Oscillation frequency R = 390 k 5% C = 47 pF 10% Note 3 25 40 55 kHz XT1 XT2 (fXT) Notes 1, 4 Note 3 Oscillation stabilization time Note 2 100 s Notes 1. Indicates only oscillator characteristics. For the CPU operation clock, see 26.8 AC Characteristics. 2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal resonator stabilizes. 3. To avoid an adverse effect from wiring capacitance, keep the wiring length as short as possible. 4. RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2. In the case of the RC resonator, the internal system clock frequency is half the oscillation frequency: MIN. = 12.5 kHz, TYP. = 20 kHz, MAX. = 27.5 kHz. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 634 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.4.3 PLL characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches MIN.: 3.5 V Conditions MIN. 4 16 TYP. MAX. 5 20 800 Unit MHz MHz s 26.4.4 Internal oscillator characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output frequency Symbol fR Conditions MIN. 100 TYP. 200 MAX. 400 Unit kHz 26.5 Voltage Regulator Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol VDD VRO tREG After VDD reaches MIN.: 3.5 V, C = 4.7 F 20% connected to REGC pin Conditions MIN. 3.5 2.5 1 TYP. MAX. 5.5 Unit V V ms VDD 3.5 V tREG VRO RESET Preliminary User's Manual U17718EJ1V0UD 635 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.6 DC Characteristics 26.6.1 I/O level (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) (1/2) Parameter Input voltage, high Symbol VIH1 VIH2 Conditions P30, P34, P36 to P38, P41, P98, P911 P00 to P06, P10, P11, P31 to P33, P35, P39, P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VIH4 VIH5 Input voltage, low VIL1 VIL2 P70 to P715 RESET, FLMD0 P30, P34, P36 to P38, P41, P98, P911 P00 to P06, P10, P11, P31 to P33, P35, P39, P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VIL4 VIL5 P70 to P715 RESET, FLMD0 AVSS EVSS 0.3AVREF0 0.2EVDD V V BVSS 0.3BVDD V 0.7AVREF0 0.8EVDD EVSS EVSS AVREF0 EVDD 0.3EVDD 0.2EVDD V V V V 0.7BVDD BVDD V MIN. 0.7EVDD 0.8EVDD TYP. MAX. EVDD EVDD Unit V V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 636 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) (2/2) Parameter Output voltage, high Note 1 Symbol VOH1 Conditions P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 IOH = -1.0 mA IOH = -0.1 mA IOH = -1.0 mA IOH = -0.1 mA IOH = -1.0 mA IOH = -0.1 mA MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AVREF0 - 1.0 AVREF0 - 0.5 0 TYP. MAX. EVDD EVDD BVDD BVDD AVREF0 AVREF0 0.4 Unit V V V V V V V VOH2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VOH3 P70 to P715 Output voltage, low Note 1 VOL1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 IOL = 1.0 mA VOL2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 IOL = 1.0 mA 0 0.4 V VOL3 Pull-up resistor Pull-down resistor Note 2 P70 to P715 VI = 0 V VI = VDD IOL = 1.0 mA 0 10 10 30 30 0.4 100 100 V k k R1 R2 Notes 1. The maximum value of the total of IOH/IOL is 20 mA/-20 mA for each power supply (EVDD, BVDD, AVREF0). 2. DRST pin only Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 26.6.2 Pin leakage current (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions Analog pin Other than analog pin Input leakage current, low ILIL1 VIN = 0 V Analog pin Other than analog pin Output leakage current, high ILOH1 VO = VDD Analog pin Other than analog pin Output leakage current, low ILOL1 VO = 0 V Analog pin Other than analog pin MIN. TYP. MAX. +0.2 +0.5 -0.2 -0.5 +0.2 +0.5 -0.2 -0.5 Unit A A A A Caution The value of the FLMD0 pin is as follows. * Input leakage current, high: 2 A (MAX.) * Input leakage current, low: -2 A (MAX.) Preliminary User's Manual U17718EJ1V0UD 637 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.6.3 Supply current (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 Normal operation mode Conditions fXX = 20 MHz (fX = 5 MHz) All peripheral function operating All peripheral function stopped MIN. TYP. 30 MAX. 45 Unit mA 23 mA IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz) All peripheral function operating All peripheral function stopped 18 28 mA 11 mA IDD3 IDLE1 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.6 0.9 mA IDD4 IDLE2 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.25 0.7 mA IDD5 Subclock operation mode Notes 2, 3 Crystal resonator (fXT = 32.768 kHz) RC resonator (fXT = 40 kHz Note 4 200 200 20 35 7 10 15 18 400 400 120 140 50 55 65 70 A A A A A A A A ) IDD6 Sub-IDLE mode Notes 2, 3 Crystal resonator (fXT = 32.768 kHz) RC resonator (fXT = 40 kHz Note 4 ) IDD7 Stop mode Notes 2, 5 POC stopped, internal oscillator stopped POC operating, internal oscillator stopped POC stopped, internal oscillator operating POC operating, internal oscillator operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main clock oscillation is stopped. 3. POC operating, internal oscillator operating. 4. The RC oscillation frequency is 40 kHz (TYP.). 5. When the subclock oscillation is not used. This clock is internally divided by 2. 638 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.7 Data Retention Characteristics STOP Mode (TA = -40 to +85C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage retention time STOP release signal input time Data retention input voltage, high Data retention input voltage, low Symbol VDDDR IDDDR tRVD tFVD tHVD tDREL VIHDR VILDR After STOP mode release After VDD reaches MIN.: 3.5 V All input ports All input ports Conditions In STOP mode VDDDR = 2.0 V 1 1 0 0 0.9VDDDR 0 VDDDR 0.1VDDDR MIN. 1.9 6 TYP. MAX. 5.5 45 Unit V A s s ms ms V V Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit (Min.) VDD/EVDD/BVDD tFVD tRVD STOP release signal input tHVD VDDDR tDREL VIHDR RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) VIHDR STOP mode release interrupt (NMI, etc.) (Released by rising edge) VILDR Preliminary User's Manual U17718EJ1V0UD 639 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.8 AC Characteristics (1) AC test input measurement points (VDD, AVREF0, EVDD, BVDD) VDD VIH (MIN.) Measurement points VIL (MAX.) VIH (MIN.) VIL (MAX.) VSS (2) AC test output measurement points VOH (MIN.) Measurement points VOL (MAX.) VOH (MIN.) VOL (MAX.) (3) Load conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. 640 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.8.1 CLKOUT output timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Output cycle High-level width Low-level width Rise time Fall time Symbol tCYK tWKH tWKL tKR tKF Conditions MIN. 50 ns tCYK/2 - 15 tCYK/2 - 15 15 15 MAX. 80 s ns ns ns ns Unit Clock Timing tCYK tWKH tWKL CLKOUT (output) tKR tKF Preliminary User's Manual U17718EJ1V0UD 641 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.9 Basic Operation (1) Reset, interrupt timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter RESET low-level width NMI high-level width NMI low-level width INTPn Note 1 Symbol tWRSL tWNIH tWNIL tWITH Conditions MIN. 500 MAX. Unit ns ns ns ns ns ns ns Analog noise elimination Analog noise elimination Analog noise elimination (n = 0 to 10) Digital noise elimination (n = 3) 500 500 500 Note 2 500 Note 2 high-level width INTPn Note 1 low-level width tWITL Analog noise elimination (n = 0 to 10) Digital noise elimination (n = 3) Notes 1. The same value as the INTP0/P03 pin applies in the case of the ADTRG pin. The same value as the INTP2/P05 pin applies in the case of the DRST pin. 2. 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination Reset/Interrupt VDD tREG tWRSL RESET (input) tWNIH NMI (input) tWNIL tWITH INTPn (input) tWITL Remark n = 0 to 10 642 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (2) Key interrupt timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter KRn input high-level width KRn input low-level width Symbol tWKRH tWKRL Conditions Analog noise elimination (n = 0 to 7) MIN. 500 500 MAX. Unit ns ns tWKRH KRn (input) tWKRL Remark n = 0 to 7 (3) Timer input timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TIn high-level width TIn low-level width Symbol tTIH tTIL Conditions TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13 Note 2 ns MIN. Note 2 MAX. Unit ns Notes 1. Noise on the TIP00, TIP10, TIP20, TIP30, TIQ00, and TIQ10 pins can be eliminated only when a capture signal is input. The noise cannot be eliminated when an external trigger signal or an external event counter signal is input. 2. 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination tTIH TIn (input) tTIL Remark TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13 Preliminary User's Manual U17718EJ1V0UD 643 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (4) CSIB timing (a) Master mode (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKBn cycle time SCKBn high-level width SCKBn low-level width SIBn setup time (to SCKBn) SIBn hold time (from SCKBn) Output delay time from SCKBn to SOBn Symbol tKCYn tKHn tKLn tSIKn tKSIn tKSOn Conditions MIN. 125 tKCYn/2 - 15 tKCYn/2 - 15 30 25 25 MAX. Unit ns ns ns ns ns ns Remark n = 0, 1 (b) Slave mode (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKBn cycle time SCKBn high-level width SCKBn low-level width SIBn setup time (to SCKBn) SIBn hold time (from SCKBn) Output delay time from SCKBn to SOBn Symbol tKCYn tKHn tKLn tSIKn tKSIn tKSOn Conditions MIN. 200 90 90 50 50 50 MAX. Unit ns ns ns ns ns ns Remark n = 0, 1 644 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com tKCYn tKLn SCKBn (I/O) tSIKn Hi-Z tKSIn tKHn SIBn (input) Input data tKSOn SOBn (output) Output data Remark n = 0, 1 (5) UARTA timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Communication rate ASCK0 cycle time Symbol Conditions MIN. MAX. 312.5 10 Unit kbps MHz (6) A/D converter (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Resolution Overall error Note Symbol Conditions MIN. TYP. MAX. 10 Unit bit %FSR 4.0 AVREF0 5.5 V tCONV VIAN IAREF0 When using A/D converter When not using A/D converter 3.1 AVSS 0.15 0.3 16 AVREF0 Conversion time Analog input voltage AVREF0 current s V mA 5 1 10 10 A Note Excluding quantization error (0.05 %FSR). FSR: Full Scale Range Indicates the ratio to the full-scale value (%FSR). Remark Preliminary User's Manual U17718EJ1V0UD 645 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (7) POC circuit characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Power supply startup time Response delay time 1 Note 1 Symbol VPOC0 tPTH tPTHD Conditions MIN. 3.5 TYP. 3.7 MAX. 3.9 Unit V ms VDD = 0 V 3.5 V After VDD reaches 3.9 V on power application 0.002 3.0 ms Response delay time 2 Note 2 tPD After VDD drops below 3.5 V on power drop 1 ms Minimum VDD width tPW 0.2 ms Notes 1. The time required to release a reset after the detection voltage is detected. 2. The time required to output a reset after the detection voltage is detected. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD tPTHD Time 646 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (8) LVI circuit characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Symbol VLVI0 VLVI1 Response time Note 1 Conditions MIN. 4.2 4.0 TYP. 4.4 4.2 0.2 MAX. 4.6 4.4 2 Unit V V ms tLD After VDD reaches VLVI0/VLVI1 (MAX.) or drops below VLVI0/VLVI1 (MIN.) Minimum VDD width Reference voltage stabilization wait time Note 2 tLW tLWAIT After VDD reaches 3.5 V or LVION bit (LVIM.bit7) changes from 0 to 1 0.2 0.1 0.2 ms ms Notes 1. The time required to output an interrupt/reset after the detection voltage is detected. 2. Unnecessary when the POC function is used. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION bit = 0 1 tLD tLD Time Preliminary User's Manual U17718EJ1V0UD 647 CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com (9) RAM retention flag characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Supply voltage rise time Response time Note Symbol VRAMH tRAMHTH tRAMHD Conditions MIN. 1.9 TYP. 2.0 MAX. 2.1 1800 Unit V ms ms VDD = 0 V 3.5 V After the supply voltage reaches the detection voltage (MAX.) 0.002 0.2 2.0 Minimum VDD width tRAMHW 0.2 ms Note Time required to set the RAMF bit after the detection voltage is detected. VDD Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHD tRAMHW tRAMHD Time 648 Preliminary User's Manual U17718EJ1V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET) www..com 26.10 Flash Memory Programming Characteristics (1) Basic characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Operating frequency Supply voltage Number of writes Input voltage, high Input voltage, low Write time + erase time Symbol fCPU VDD CWRT VIH VIL tIWRT + tERASE Programming temperature tPRG -40 +85 C Note Conditions MIN. 4 3.5 TYP. MAX. 20 5.5 100 Unit MHz V Times V V s FLMD0 FLMD0 0.8EVDD EVSS EVDD 0.2EVSS TBD Note When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product Shipped product E P E P E P: 3 rewrites P E P E P: 3 rewrites (2) Serial write operation characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter FLMD0 setup time from RESET Count execution time FLMD0 high-level width FLMD0 low-level width FLMD0 rise time FLMD0 fall time Symbol tRFCF tCOUNT tCH tCL tR tF 10 10 Conditions MIN. 70536/fX 3 100 100 50 50 TYP. MAX. Unit s ms s s ns ns VDD RESET VSS tRFCF VDD FLMD0 VSS tCL VDD FLMD1 VSS L tF tR tCH tCOUNT Preliminary User's Manual U17718EJ1V0UD 649 www..com CHAPTER 27 PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S CD Q R 100 1 26 25 F G P H I M J K S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. S100GC-50-8EU, 8EA-2 650 Preliminary User's Manual U17718EJ1V0UD www..com APPENDIX A REGISTER INDEX (1/9) Symbol ADA0CR0 ADA0CR0H ADA0CR1 ADA0CR10 ADA0CR10H ADA0CR11 ADA0CR11H ADA0CR12 ADA0CR12H ADA0CR13 ADA0CR13H ADA0CR14 ADA0CR14H ADA0CR15 ADA0CR15H ADA0CR1H ADA0CR2 ADA0CR2H ADA0CR3 ADA0CR3H ADA0CR4 ADA0CR4H ADA0CR5 ADA0CR5H ADA0CR6 ADA0CR6H ADA0CR7 ADA0CR7H ADA0CR8 ADA0CR8H ADA0CR9 ADA0CR9H ADA0M0 ADA0M1 ADA0M2 ADA0PFM ADA0PFT ADA0S ADIC CB0CTL0 CB0CTL1 CB0CTL2 A/D conversion result register 0 A/D conversion result register 0H A/D conversion result register 1 A/D conversion result register 10 A/D conversion result register 10H A/D conversion result register 11 A/D conversion result register 11H A/D conversion result register 12 A/D conversion result register 12H A/D conversion result register 13 A/D conversion result register 13H A/D conversion result register 14 A/D conversion result register 14H A/D conversion result register 15 A/D conversion result register 15H A/D conversion result register 1H A/D conversion result register 2 A/D conversion result register 2H A/D conversion result register 3 A/D conversion result register 3H A/D conversion result register 4 A/D conversion result register 4H A/D conversion result register 5 A/D conversion result register 5H A/D conversion result register 6 A/D conversion result register 6H A/D conversion result register 7 A/D conversion result register 7H A/D conversion result register 8 A/D conversion result register 8H A/D conversion result register 9 A/D conversion result register 9H A/D converter mode register 0 A/D converter mode register 1 A/D converter mode register 2 Power-fail compare mode register Power-fail compare threshold value register A/D converter channel specification register 0 Interrupt control register CSIB0 control register 0 CSIB0 control register 1 CSIB0 control register 2 Name Unit ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC INTC CSI CSI CSI Page 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 407 402 404 405 409 409 406 533 466 469 470 Preliminary User's Manual U17718EJ1V0UD 651 APPENDIX A REGISTER INDEX www..com (2/9) Symbol CB0RIC CB0RX CB0RXL CB0STR CB0TIC CB0TX CB0TXL CB1CTL0 CB1CTL1 CB1CTL2 CB1RIC CB1RX CB1RXL CB1STR CB1TIC CB1TX CB1TXL CCLS CLM CTBP CTPC CTPSW DADC0 DADC1 DADC2 DADC3 DBC0 DBC1 DBC2 DBC3 DBPC DBPSW DCHC0 DCHC1 DCHC2 DCHC3 DDA0H DDA0L DDA1H DDA1L DDA2H DDA2L DDA3H DDA3L DMAIC0 Interrupt control register CSIB0 receive data register CSIB0 receive data register L CSIB0 status register Interrupt control register CSIB0 transmit data register CSIB0 transmit data register L CSIB1 control register 0 CSIB1 control register 1 CSIB1 control register 2 Interrupt control register CSIB1 receive data register CSIB1 receive data register L CSIB1 status register Interrupt control register CSIB1 transmit data register CSIB1 transmit data register L CPU operation clock status register Clock monitor mode register CALLT base pointer CALLT execution status saving register CALLT execution status saving register DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 Exception/debug trap status saving register Exception/debug trap status saving register DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 DMA destination address register 0H DMA destination address register 0L DMA destination address register 1H DMA destination address register 1L DMA destination address register 2H DMA destination address register 2L DMA destination address register 3H DMA destination address register 3L Interrupt control register Name Unit INTC CSI CSI CSI INTC CSI CSI CSI CSI CSI INTC CSI CSI CSI INTC CSI CSI CG CLM CPU CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA INTC Page 533 465 465 472 533 465 465 466 469 470 533 465 465 472 533 465 465 165 583 49 48 48 498 498 498 498 497 497 497 497 49 49 499 499 499 499 496 496 496 496 496 496 496 496 534 652 Preliminary User's Manual U17718EJ1V0UD APPENDIX A REGISTER INDEX www..com (3/9) Symbol DMAIC1 DMAIC2 DMAIC3 DSA0H DSA0L DSA1H DSA1L DSA2H DSA2L DSA3H DSA3L DTFR0 DTFR1 DTFR2 DTFR3 ECR EIPC EIPSW FEPC FEPSW IMR0 IMR0H IMR0L IMR1 IMR1H IMR1L IMR2 IMR2H IMR2L IMR3 IMR3H IMR3L INTF0 INTF1 INTF3 INTF3H INTF3L INTF9H INTR0 INTR1 INTR3 INTR3H INTR3L INTR9H ISPR Interrupt control register Interrupt control register Interrupt control register DMA source address register 0H DMA source address register 0L DMA source address register 1H DMA source address register 1L DMA source address register 2H DMA source address register 2L DMA source address register 3H DMA source address register 3L DMA trigger factor register 0 DMA trigger factor register 1 DMA trigger factor register 2 DMA trigger factor register 3 Interrupt source register Interrupt status saving register Interrupt status saving register NMI status saving register NMI status saving register Interrupt mask register 0 Interrupt mask register 0H Interrupt mask register 0L Interrupt mask register 1 Interrupt mask register 1H Interrupt mask register 1L Interrupt mask register 2 Interrupt mask register 2H Interrupt mask register 2L Interrupt mask register 3 Interrupt mask register 3H Interrupt mask register 3L External interrupt falling edge specification register 0 External interrupt falling edge specification register 1 External interrupt falling edge specification register 3 External interrupt falling edge specification register 3H External interrupt falling edge specification register 3L External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 1 External interrupt rising edge specification register 3 External interrupt rising edge specification register 3H External interrupt rising edge specification register 3L External interrupt rising edge specification register 9H In-service priority register Name Unit INTC INTC INTC DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA CPU CPU CPU CPU CPU INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC Page 534 534 534 495 495 495 495 495 495 495 495 500 500 500 500 46 45 45 46 46 534 534 534 534 534 534 534 534 534 534 534 534 84, 546 89, 547 95, 548 95, 548 95, 548 115, 549 84, 546 89, 547 96, 548 96, 548 96, 548 116, 549 536 Preliminary User's Manual U17718EJ1V0UD 653 APPENDIX A REGISTER INDEX www..com (4/9) Symbol KRIC KRM LOCKR LVIIC LVIM LVIS NFC OCDM OSTS P0 P00NFC P01NFC P1 P10NFC P11NFC P20NFC P21NFC P3 P30NFC P31NFC P3H P3L P4 P5 P7 P7H P7L P9 P9H P9L PC PCC PCLM PCM PCS PCT PDL PDLH PDLL PEMU1 PFC0 PFC3L PFC5 PFC9 Interrupt control register Key return mode register Lock register Interrupt control register Low-voltage detection register Low-voltage detection level select register Noise elimination control register On-chip debug mode register Oscillation stabilization time select register Port 0 TIP00 pin noise elimination control register TIP01 pin noise elimination control register Port 1 TIP10 pin noise elimination control register TIP11 pin noise elimination control register TIP20 pin noise elimination control register TIP21 pin noise elimination control register Port 3 TIP30 pin noise elimination control register TIP31 pin noise elimination control register Port 3H Port 3L Port 4 Port 5 Port 7 Port 7H Port 7L Port 9 Port 9H Port 9L Program counter Processor clock control register Programmable clock mode register Port CM Port CS Port CT Port DL Port DLH Port DLL Peripheral emulation register 1 Port function control register 0 Port function control register 3L Port function control register 5 Port function control register 9 Name Unit INTC KR CG INTC LVI LVI INTC Debug WDT Port Timer Timer Port Timer Timer Timer Timer Port Timer Timer Port Port Port Port Port Port Port Port Port Port CPU CG CG Port Port Port Port Port Port LVI Port Port Port Port Page 533 555 168 533 590 591 550 625 560 81 188 188 87 188 188 188 188 91 188 188 91 91 98 101 107 107 107 109 109 109 43 161 170 118 120 122 124 124 124 596 83 93 103 112 654 Preliminary User's Manual U17718EJ1V0UD APPENDIX A REGISTER INDEX www..com (5/9) Symbol PFC9H PFC9L PFCE3L PFCE5 PFCE9 PFCE9H PFCE9L PIC0 PIC1 PIC10 PIC2 PIC3 PIC4 PIC5 PIC6 PIC7 PIC8 PIC9 PLLCTL PLLS PM0 PM1 PM3 PM3H PM3L PM4 PM5 PM7 PM7H PM7L PM9 PM9H PM9L PMC0 PMC1 PMC3 PMC3H PMC3L PMC4 PMC5 PMC9 PMC9H PMC9L PMCCM PMCM Port function control register 9H Port function control register 9L Port function control expansion register 3L Port function control expansion register 5 Port function control expansion register 9 Port function control expansion register 9H Port function control expansion register 9L Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register PLL control register PLL lockup time specification register Port mode register 0 Port mode register 1 Port mode register 3 Port mode register 3H Port mode register 3L Port mode register 4 Port mode register 5 Port mode register 7 Port mode register 7H Port mode register 7L Port mode register 9 Port mode register 9H Port mode register 9L Port mode control register 0 Port mode control register 1 Port mode control register 3 Port mode control register 3H Port mode control register 3L Port mode control register 4 Port mode control register 5 Port mode control register 9 Port mode control register 9H Port mode control register 9L Port mode control register CM Port mode register CM Name Unit Port Port Port Port Port Port Port INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC CG CG Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Page 112 112 94 103 112 112 112 533 533 533 533 533 533 533 533 533 533 533 167 169 81 87 91 91 91 98 101 107 107 107 109 109 109 82 88 92 92 92 99 102 110 110 110 118 118 Preliminary User's Manual U17718EJ1V0UD 655 APPENDIX A REGISTER INDEX www..com (6/9) Symbol PMCS PMCT PMDL PMDLH PMDLL PRCMD PRSCM0 PRSM0 PSC PSMR PSW PU0 PU1 PU3 PU3H PU3L PU4 PU5 PU9 PU9H PU9L Q00NFC Q01NFC Q02NFC Q03NFC Q10NFC Q11NFC Q12NFC Q13NFC r0 to r31 RAMS RCM RESF SELCNT0 SYS TM0CMP0 TM0CTL0 TM0EQIC0 TP0CCIC0 TP0CCIC1 TP0CCR0 TP0CCR1 TP0CNT TP0CTL0 TP0CTL1 Port mode register CS Port mode register CT Port mode register DL Port mode register DLH Port mode register DLL Command register Prescaler compare register 0 Prescaler mode register 0 Power save control register Power save mode register Program status word Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 3H Pull-up resistor option register 3L Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 9 Pull-up resistor option register 9H Pull-up resistor option register 9L TIQ00 pin noise elimination control register TIQ01 pin noise elimination control register TIQ02 pin noise elimination control register TIQ03 pin noise elimination control register TIQ10 pin noise elimination control register TIQ11 pin noise elimination control register TIQ12 pin noise elimination control register TIQ13 pin noise elimination control register General-purpose register Internal RAM data status register Internal oscillation mode register Reset source flag register Selector operation control register 0 System status register TMM0 compare register 0 TMM0 control register 0 Interrupt control register Interrupt control register Interrupt control register TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register TMP0 control register 0 TMP0 control register 1 Name Unit Port Port Port Port Port CPU WT WT CG CG CPU Port Port Port Port Port Port Port Port Port Port Timer Timer Timer Timer Timer Timer Timer Timer CPU CG CG CG Timer CPU Timer Timer INTC INTC INTC Timer Timer Timer Timer Timer Page 120 122 124 124 124 71 386, 491 385, 490 558 559 47 83 88 95 95 95 99 105 115 115 115 288 288 288 288 288 288 288 288 43 591 165 577 265 72 375 376 533 533 533 183 185 187 176 177 656 Preliminary User's Manual U17718EJ1V0UD APPENDIX A REGISTER INDEX www..com (7/9) Symbol TP0IOC0 TP0IOC1 TP0IOC2 TP0OPT0 TP0OVIC TP1CCIC0 TP1CCIC1 TP1CCR0 TP1CCR1 TP1CNT TP1CTL0 TP1CTL1 TP1IOC0 TP1IOC1 TP1IOC2 TP1OPT0 TP1OVIC TP2CCIC0 TP2CCIC1 TP2CCR0 TP2CCR1 TP2CNT TP2CTL0 TP2CTL1 TP2IOC0 TP2IOC1 TP2IOC2 TP2OPT0 TP2OVIC TP3CCIC0 TP3CCIC1 TP3CCR0 TP3CCR1 TP3CNT TP3CTL0 TP3CTL1 TP3IOC0 TP3IOC1 TP3IOC2 TP3OPT0 TP3OVIC TQ0CCIC0 TQ0CCIC1 TQ0CCIC2 TQ0CCIC3 TMP0 I/O control register 0 TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 Interrupt control register Interrupt control register Interrupt control register TMP1 capture/compare register 0 TMP1 capture/compare register 1 TMP1 counter read buffer register TMP1 control register 0 TMP1 control register 1 TMP1 I/O control register 0 TMP1 I/O control register 1 TMP1 I/O control register 2 TMP1 option register 0 Interrupt control register Interrupt control register Interrupt control register TMP2 capture/compare register 0 TMP2 capture/compare register 1 TMP2 counter read buffer register TMP2 control register 0 TMP2 control register 1 TMP2 I/O control register 0 TMP2 I/O control register 1 TMP2 I/O control register 2 TMP2 option register 0 Interrupt control register Interrupt control register Interrupt control register TMP3 capture/compare register 0 TMP3 capture/compare register 1 TMP3 counter read buffer register TMP3 control register 0 TMP3 control register 1 TMP3 I/O control register 0 TMP3 I/O control register 1 TMP3 I/O control register 2 TMP3 option register 0 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Name Unit Timer Timer Timer Timer INTC INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC INTC INTC Page 179 180 181 182 533 533 533 183 185 187 176 177 179 180 181 182 533 533 533 183 185 187 176 177 179 180 181 182 533 533 533 183 185 187 176 177 179 180 181 182 533 533 533 533 533 Preliminary User's Manual U17718EJ1V0UD 657 APPENDIX A REGISTER INDEX www..com (8/9) Symbol TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 TQ0CNT TQ0CTL0 TQ0CTL1 TQ0IOC0 TQ0IOC1 TQ0IOC2 TQ0OPT0 TQ0OVIC TQ1CCIC0 TQ1CCIC1 TQ1CCIC2 TQ1CCIC3 TQ1CCR0 TQ1CCR1 TQ1CCR2 TQ1CCR3 TQ1CNT TQ1CTL0 TQ1CTL1 TQ1IOC0 TQ1IOC1 TQ1IOC2 TQ1OPT0 TQ1OVIC UA0CTL0 UA0CTL1 UA0CTL2 UA0OPT0 UA0RIC UA0RX UA0STR UA0TIC UA0TX UA1CTL0 UA1CTL1 UA1CTL2 UA1OPT0 UA1RIC UA1RX UA1STR UA1TIC TMQ0 capture/compare register 0 TMQ0 capture/compare register 1 TMQ0 capture/compare register 2 TMQ0 capture/compare register 3 TMQ0 counter read buffer register TMQ0 control register 0 TMQ0 control register 1 TMQ0 I/O control register 0 TMQ0 I/O control register 1 TMQ0 I/O control register 2 TMQ0 option register 0 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register TMQ1 capture/compare register 0 TMQ1 capture/compare register 1 TMQ1 capture/compare register 2 TMQ1 capture/compare register 3 TMQ1 counter read buffer register TMQ1 control register 0 TMQ1 control register 1 TMQ1 I/O control register 0 TMQ1 I/O control register 1 TMQ1 I/O control register 2 TMQ1 timer option register 0 Interrupt control register UARTA0 control register 0 UARTA0 control register 1 UARTA0 control register 2 UARTA0 option control register 0 Interrupt control register UARTA0 receive data register UARTA0 status register Interrupt control register UARTA0 transmit data register UARTA1 control register 0 UARTA1 control register 1 UARTA1 control register 2 UARTA1 option control register 0 Interrupt control register UARTA1 receive data register UARTA1 status register Interrupt control register Name Unit Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC UART UART UART UART INTC UART UART INTC UART UART UART UART UART INTC UART UART INTC Page 279 281 283 285 287 272 273 275 276 277 278 533 534 534 534 534 279 281 283 285 287 272 273 275 276 277 278 534 433 455 456 435 533 438 436 533 438 433 455 456 435 533 438 436 533 658 Preliminary User's Manual U17718EJ1V0UD APPENDIX A REGISTER INDEX www..com (9/9) Symbol UA1TX UA2CTL0 UA2CTL1 UA2CTL2 UA2OPT0 UA2RIC UA2RX UA2STR UA2TIC UA2TX VSWC WDTE WDTM2 WTIC WTIIC WTM UARTA1 transmit data register UARTA2 control register 0 UARTA2 control register 1 UARTA2 control register 2 UARTA2 option control register 0 Interrupt control register UARTA2 receive data register UARTA2 status register Interrupt control register UARTA2 transmit data register System wait control register Watchdog timer enable register Watchdog timer mode register 2 Interrupt control register Interrupt control register Watch timer operation mode register Name Unit UART UART UART UART UART INTC UART UART INTC UART CPU WDT WDT INTC INTC WT Page 438 433 455 456 435 534 438 436 534 438 73 396 394, 537 533 533 387 Preliminary User's Manual U17718EJ1V0UD 659 www..com APPENDIX B INSTRUCTION SET LIST B.1 Conventions (1) Register symbols used to describe operands Register Symbol reg1 reg2 Explanation General-purpose registers: Used as source registers. General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results. bit#3 immX dispX regID vector cccc sp ep listX 3-bit data for specifying the bit number X bit immediate data X bit displacement data System register number 5-bit data that specifies the trap vector (00H to 1FH) 4-bit data that shows the conditions code Stack pointer (r3) Element pointer (r30) X item register list (2) Register symbols used to describe opcodes Register Symbol R r w d I i cccc CCCC bbb L Explanation 1-bit data of a code that specifies reg1 or regID 1-bit data of the code that specifies reg2 1-bit data of the code that specifies reg3 1-bit displacement data 1-bit immediate data (indicates the higher bits of immediate data) 1-bit immediate data 4-bit data that shows the condition codes 4-bit data that shows the condition codes of Bcond instruction 3-bit data for specifying the bit number 1-bit data that specifies a program register in the register list 660 Preliminary User's Manual U17718EJ1V0UD APPENDIX B INSTRUCTION SET LIST www..com (3) Register symbols used in operations Register Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General-purpose register System register Expand n with zeros until word length. Expand n with signs until word length. Read size b data from address a. Write data b into address a in size c. Read bit b of address a. Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Byte Halfword Word + - ll x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflects the results in a flag. Byte (8 bits) Half word (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder from division results Logical product Logical sum Exclusive OR Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation (4) Register symbols used in execution clock Register Symbol i r l Explanation If executing another instruction immediately after executing the first instruction (issue). If repeating execution of the same instruction immediately after executing the first instruction (repeat). If using the results of instruction execution in the instruction immediately after the execution (latency). Preliminary User's Manual U17718EJ1V0UD 661 APPENDIX B INSTRUCTION SET LIST www..com (5) Register symbols used in flag operations Identifier (Blank) 0 X R No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. Explanation (6) Condition codes Condition Code (cccc) 0000 1000 0001 OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) 1001 CY = 0 No carry Not lower (Greater than or equal) 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 Z=1 Z=0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 - Zero Not zero Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (Unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Condition Formula Explanation 662 Preliminary User's Manual U17718EJ1V0UD APPENDIX B INSTRUCTION SET LIST www..com B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Clock i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 r r rr r0 01 11 0 RRRRR rrrrr010010iiiii r r rr r1 10 00 0 RRRRR iiiiiiiiiiiiiiii AND ANDI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 01 0 RRRRR r r rr r1 10 11 0 RRRRR iiiiiiiiiiiiiiii Bcond disp9 ddddd1011dddcccc if conditions are satisfied Note 1 then PCPC+sign-extend(disp9) When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll 1 1 1 x x 0 x x x x 2 2 2 GR[reg2]GR[reg2]AND GR[reg1] GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 1 1 1 0 0 x x x x GR[reg2]GR[reg2]+GR[reg1] GR[reg2]GR[reg2]+sign-extend(imm5) GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 r 1 1 1 l 1 1 1 CY OV S x x x x x x x x x Z SAT x x x Flags Note 2 Note 2 Note 2 1 1 1 wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR 1 1 1 0 wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3,disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,0) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100100 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,0) CMOV cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww011000cccc0 if conditions are satisfied then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRR if conditions are satisfied else GR[reg3]GR[reg2] CMP reg1,reg2 imm5,reg2 CTRET r r rr r0 01 11 1 RRRRR rrrrr010011iiiii 0000011111100000 0000000101000100 DBRET 0000011111100000 0000000101000110 resultGR[reg2]-GR[reg1] resultGR[reg2]-sign-extend(imm5) PCCTPC PSWCTPSW PCDBPC PSWDBPSW 3 3 3 R R R R R 1 1 3 1 1 3 1 1 3 x x R x x R x x R x x R R 1 1 1 1 1 1 3 3 3 x 3 3 3 x 4 4 4 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 wwwww011001cccc0 then GR[reg3]GR[reg1] Preliminary User's Manual U17718EJ1V0UD 663 APPENDIX B INSTRUCTION SET LIST www..com (2/6) Mnemonic Operand Opcode Operation Execution Clock i DBTRAP 1111100001000000 DBPCPC+2 (restored PC) DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL LLLLLLLLLLL00000 spsp+zero-extend(imm5 logically shift left by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3 Note 4 Note 4 Note 4 Flags r 3 l 3 CY OV S Z SAT 3 PSW.ID1 1 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 35 35 35 x x x x x x x x x x x x x x x wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r rr r0 00 01 0 RRRRR r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 GR[reg2]GR[reg2]/GR[reg1] Note 6 35 35 35 35 35 35 wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 34 34 34 wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 34 34 34 wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 Note 7 JMP JR [reg1] disp22 00000000011RRRRR PCGR[reg1] 0000011110dddddd ddddddddddddddd0 Note 7 LD.B disp16[reg1],reg2 r r rr r1 11 00 0 RRRRR dddddddddddddddd LD.BU disp16[reg1],reg2 r r rr r1 11 10 b RRRRR dddddddddddddd1 Notes 8, 10 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Byte)) adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 1 1 Note 11 Note 11 PSW.ID0 1 1 1 Stop 1 1 1 GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 x 0 x x GR[reg2]PC+4 PCPC+sign-extend(disp22) 2 2 2 3 2 3 2 3 2 PCPC+sign-extend(disp22) 664 Preliminary User's Manual U17718EJ1V0UD APPENDIX B INSTRUCTION SET LIST www..com (3/6) Mnemonic Operand Opcode Operation Execution Clock i LD.H disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd0 Note 8 LDSR reg2,regID rrrrr111111RRRRR 0000000000100000 Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 RRRRR ddddddddddddddd1 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 RRRRR ddddddddddddddd1 Note 8 MOV reg1,reg2 imm5,reg2 imm32,reg1 r r rr r0 00 00 0 RRRRR rrrrr010000iiiii GR[reg2]GR[reg1] GR[reg2]sign-extend(imm5) 1 1 2 1 1 2 1 1 2 adrGR[reg1]+sign-extend(disp16) GR[reg2]Load-memory(adr,Word) 1 1 Note 11 Flags r 1 l Note 11 CY OV S Z SAT adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Halfword)) 1 SR[regID]GR[reg2] Other than regID = PSW regID = PSW 1 1 1 1 1 1 x x x x x adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Halfword) 1 1 Note 11 00000110001RRRRR GR[reg1]imm32 iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII MOVEA imm16,reg1,reg2 r r rr r1 10 00 1 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 MOVHI imm16,reg1,reg2 r r rr r1 10 01 0 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+(imm16 ll 016) 1 1 1 MUL reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 wwwww01000100000 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 00 Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 RRRRR iiiiiiiiiiiiiiii MULU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 GR[reg2]GR[reg2] GR[reg2]GR[reg1] Note 6 GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9) 1 4 5 1 1 1 1 1 1 2 2 2 xsign-extend(imm5) ximm16 Note 6 wwwww01000100010 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 10 Note 13 NOP NOT NOT1 reg1,reg2 bit#3,disp16[reg1] 0000000000000000 Pass at least one clock cycle doing nothing. r r rr r0 00 00 1 RRRRR GR[reg2]NOT(GR[reg1]) 1 1 3 1 1 3 1 1 3 0 x x x GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) 1 4 5 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag) Note 3 Note 3 Note 3 reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100010 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag) 3 3 3 x Note 3 Note 3 Note 3 Preliminary User's Manual U17718EJ1V0UD 665 APPENDIX B INSTRUCTION SET LIST www..com (4/6) Mnemonic Operand Opcode Operation Execution Clock i OR ORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 0 RRRRR r r rr r1 10 10 0 RRRRR iiiiiiiiiiiiiiii PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, sp/immNote 15 0000011110iiiiiL LLLLLLLLLLLff011 imm16/imm32 Store-memory(sp-4,GR[reg in list12],Word) spsp+4 repeat 1 step above until all regs in list12 is stored Note 16 spsp-zero-extend (imm5) epsp/imm RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP=1 then else PC PC FEPC EIPC x x x x x x PSW FEPSW PSW EIPSW SAR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010100000 imm5,reg2 rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by GR[reg1] GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 imm5,reg2 SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 r r rr r0 00 11 0 RRRRR rrrrr010001iiiii r r rr r0 00 10 1 RRRRR r r rr r1 10 01 1 RRRRR iiiiiiiiiiiiiiii SATSUBR reg1,reg2 SETF cccc,reg2 r r rr r0 00 10 0 RRRRR rrrrr1111110cccc 0000000000000000 GR[reg2]saturated(GR[reg1]-GR[reg2]) If conditions are satisfied then GR[reg2]00000001H else GR[reg2]00000000H 1 1 1 1 1 1 x x x x x GR[reg2]saturated(GR[reg2]+GR[reg1]) GR[reg2]saturated(GR[reg2]+sign-extend(imm5) GR[reg2]saturated(GR[reg2]-GR[reg1]) GR[reg2]saturated(GR[reg1]-sign-extend(imm16) 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 0 1 1 1 0 Note17 Note17 Note17 Flags r 1 1 l 1 1 CY OV S 0 0 x x Z SAT x x GR[reg2]GR[reg2]OR GR[reg1] GR[reg2]GR[reg1]OR zero-extend(imm16) 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLL00001 spsp-4 n+2 n+2 n+2 Note 4 Note 4 Note 4 3 3 3 R R R R R 666 Preliminary User's Manual U17718EJ1V0UD APPENDIX B INSTRUCTION SET LIST www..com (5/6) Mnemonic Operand Opcode Operation Execution Clock i SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100000 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000011000000 imm5,reg2 rrrrr010110iiiii GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 r r r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) Note 18 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Load-memory(adr,Halfword)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 18, 20 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 r r r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Halfword) SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR dddddddddddddddd ST.H reg2,disp16[reg1] adrGR[reg1]+sign-extend(disp16) Store-memory(adr,GR[reg2],Byte) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 9 Flags r 3 l 3 CY OV S Z SAT x 3 Note 3 Note 3 Note 3 3 3 3 x Note 3 Note 3 Note 3 GR[reg2]GR[reg2] logically shift left by GR[reg1] 1 1 1 x x x x 0 x x x x x x x x 1 1 1 0 GR[reg2]GR[reg2] logically shift right by GR[reg1] 1 1 1 0 1 1 1 0 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 r r rr r1 11 01 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8 1 1 1 STSR regID,reg2 r r rr r1 11 11 1 RRRRR 0000000001000000 GR[reg2]SR[regID] 1 1 1 Preliminary User's Manual U17718EJ1V0UD 667 APPENDIX B INSTRUCTION SET LIST www..com (6/6) Mnemonic Operand Opcode Operation Execution Clock i SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 r r rr r0 01 10 1 RRRRR r r rr r0 01 10 0 RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] 1 1 5 r 1 1 5 l 1 1 5 CY OV S x x x x x x Z SAT x x Flags 00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1 SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) 1 1 1 SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) 1 1 1 TRAP vector 00000111111iiiii 0000000100000000 EIPC EIPSW PSW.EP PSW.ID PC PC+4 (Restored PC) PSW 1 1 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) 3 3 3 ECR.EICC Interrupt code TST TST1 reg1,reg2 bit#3,disp16[reg1] r r rr r0 01 01 1 RRRRR resultGR[reg2] AND GR[reg1] 1 3 1 3 1 3 0 x x x x 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) adrGR[reg1] Z flagNot (Load-memory-bit (adr,reg2)) GR[reg2]GR[reg2] XOR GR[reg1] GR[reg2]GR[reg1] XOR zero-extend (imm16) Note 3 Note 3 Note 3 reg2, [reg1] r r rr r1 11 11 1 RRRRR 0000000011100110 3 3 3 Note 3 Note 3 Note 3 XOR XORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 1 RRRRR r r rr r1 10 10 1 RRRRR iiiiiiiiiiiiiiii 1 1 1 1 1 1 0 0 x x x x ZXB ZXH reg1 reg1 00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0)) 1 1 1 1 1 1 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. dddddddd: Higher 8 bits of disp9. 3 if there is an instruction that rewrites the contents of the PSW immediately before. If there is no wait state (3 + the number of read access wait states). n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) RRRRR: other than 00000. The lower halfword data only are valid. ddddddddddddddddddddd: The higher 21 bits of disp22. ddddddddddddddd: The higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 668 Preliminary User's Manual U17718EJ1V0UD APPENDIX B INSTRUCTION SET LIST www..com Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14. Do not specify the same register for general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8. Preliminary User's Manual U17718EJ1V0UD 669 www..com For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [Europe] NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ Hanover Office Podbielskistrasse 164 30177 Hannover Tel: 0 511 33 40 2-0 Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52180 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Limburglaan 5 5616 HR Eindhoven The Netherlands Tel: 040 265 40 10 G05.11-1A [Asia & Oceania] NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China TEL: 010-8235-1155 http://www.cn.necel.com/ NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 http://www.cn.necel.com/ NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ |
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