 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU26110 www..com General Description SRS CSU 5.1 & Passive Matrix TruSurround XT Decoder Package The NJU26110 is a digital signal processor that provides the function of Circle Surround II 5.1 / TruSurroundXT and Mono-to-Stereo. The NJU26110 processes the stereo matrix-encoded signal into spacious sound of 5.1 channels by Circle Surround II 5.1. Also non matrix-encoded audio signal can be processed into effective spacious sound. The decoded 2-channel signal can be converted into spacious 2-channel virtual surround output by the TruSurroundXT technology. NJU26110FR1 FEATURES - Software * 5.1-Channel signal outputs by Circle Surround II 5.1 * SRS Focus * LFE by SRS TruBass * 2-Channel outputs by SRS TruSurroundXT * Mono-to-Stereo function * Master Volume * WatchDog Clock Output - Hardware * 24bit Fixed-point Digital Signal Processing * Maximum System Clock Frequency : 38MHz Max. * Digital Audio Interface : 2 Input ports / 3 Output ports * Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs * Master / Slave Mode : Master Mode MCK 1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs * Power Supply : 2.5V * Input terminal : 3.3V Input tolerant * Package : QFP32-R1 (Pb-Free) * Two kinds of micro computer interface : I2C bus (standard-mode/100kbps) : Serial interface (4 lines: clock, enable, input data, output data) The detail hardware specification is described in the " NJU26100 Series Hardware Data Sheet". Ver.2006-11-27 -1- NJU26110 www..com Function Block Diagram AD1/SDIN AD2/SSb NJU26110 DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R SDO0 SDI0 SDI1 C/LFE SDO1 BCKI SL/SR SDO2 LRI SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE PROGRAM CONTROL RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT DELAY RAM DATA RAM FIRMWARE ROM GPIO AND CONFIGURATION INTERFACE SEL1 Fig. 1 NJU26110 Block Diagram DSP Block Diagram NJU26110 Block Diagram Dialog Clarity Select L/R/L+R Mono To Stereo Circle Surround II Decoder Mono Input Mode CS decode mode C L R Ls Rs Delay Phanton Center + + L R L Output Channel Trimmer Focus TruBass Mixer (L/R,SL/SR,SW) Lt L L R C S TruSurround C R Ls Rs Sw Master Volume Input Trimmer L R Passive Matrix Rt R Stereo Input Mode TruSurround/ Through mode Focus SL SR SW Focus + 80Hz LPF TruBass L R Ls Rs SW Fig. 2 NJU26110 Function Diagram Delay -2- Ver.2006-11-27 NJU26110 www..com VDDR VDDR VDDC 18 24 23 22 21 20 19 SDI0 SDI1 TEST LRI BCKI MCK BCKO LRO 25 17 VDDC VSSR VSSR VSSC VSSC Pin Configuration 16 26 15 27 14 28 WDC VSSC VDDC RESETb VSSO XO XI VDDO NJU26110 13 12 11 31 30 29 10 32 9 1 2 3 4 5 6 7 Fig. 3 NJU26110 Pin Configuration Pin Description Table 1 Pin Description No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol SDO2 SDO1 SDO0 SEL1 *1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb VDDO XI XO VSSO RESETb VDDC VSSC WDC *2 I/O O O O I I I/O I I -I O -I --O Description Audio Data Output 2 SL/SR Audio Data Output 1 C/SW Audio Data Output 0 L/R Select I2C or Serial bus I2C Clock / Serial Clock I2C I/O / Serial Output This pin requires a pull-up resistance. I2C Address / Serial Input I2C Address / Serial Enable OSC Power Supply +2.5V X'tal Clock Input OSC Output OSC GND RESET (active Low) Core Power Supply +2.5V Core GND Clock for Watch Dog Timer No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDDC VSSC VDDR VSSR SDI0 SDI1 TEST LRI BCKI MCK BCKO LRO I/O Description Core Power Supply +2.5V Core GND I/O Power Supply +2.5V I/O GND Audio Data Input 0 L/R Audio Data Input 1 L/R Connect to GND LR Clock Input Bit Clock Input Master Clock Output Bit Clock Output LR Clock Output SDA/SDOUT AD1/SDIN SCL/SCK AD2/SSb SDO2 SDO1 SDO0 SEL1 8 ----I I I I I O O O * I : Input, O : Output, I/O: Bi-directional *1 SEL1 : Input *2 WDC : Output Ver.2006-11-27 -3- NJU26110 www..com Digital Audio Interface The NJU26110 audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified. The NJU26110 audio interface provides two data inputs, SDI0, SDI1 and three data outputs, SDO0, SDO1, SDO1, as shown in table 2, table 3 and Fig.2. An audio interface input and output data format become the same data format. Table 2 Pin No. 25 26 Table 3 Pin No. 3 2 1 Serial Audio Input Pin Symbol Description SDI0 Audio Data Input 0 L / R SDI1 Audio Data Input 1 L / R Serial Audio Output Pin Symbol Description SDO0 Audio Data Output 0 L / R SDO1 Audio Data Output 1 C /SW SDO2 Audio Data Output 2 SL/SR Host Interface The NJU26110 can be controlled via Serial Host Interface (SHI) using either of two serial bus format : 4-Wire serial bus or I2C bus.(Table 4) Data transfers are in 8 bit packets (1 byte) when using either format. Serial Host Interface Pin Description.(Table 5) Table 4 Serial Host Interface Pin Description Pin No. 4 Symbol SEL1 Setting "Low" "High" Host Interface I2C bus 4-Wire serial bus Table 5 Serial Host Interface Pin Description Symbol 4-Wire Serial bus Format Pin No. I2C bus Format (I2C bus / Serial) 5 SCL / SCK Serial Clock Serial Clock Serial Data Input/Output Serial Data Output 6 SDA / SDOUT (Open Drain Input/Output) (CMOS) 2 7 AD1 / SDIN I C bus address Bit1 Serial Data Input Serial enable 8 AD2 / SSb I2C bus address Bit2 Note : SDA /SDOUT pin is a bi-directional open drain. SDA /SDOUT output is normal CMOS output in case of 4-Wire Serial bus mode and SSb="Low". SDA /SDOUT output is Hi-Z state in case of 4-Wire Serial bus mode and SSb="High". This pin requires a pull-up resister in both 4-Wire serial and I2C bus mode. -4- Ver.2006-11-27 NJU26110 www..com I C bus 2 When the NJU26110 is configured for I2C bus communication during the Reset initialization sequence. I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26110. An address can be arbitrarily set up by the AD1 and AD2 pins. The I2C address of AD1/AD2 is decided by connection of AD1/AD2 pins. Table 6 I2C bus SLAVE Address AD2 AD1 bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 bit2 0 0 1 1 bit1 0 1 0 1 R/W bit0 R/W Start bit Slave Address ( 7bit ) R/W bit ACK * SLAVE address is 0 when AD1/2 is "Low". SLAVE address is 1 when AD1/2 is "High". Note : In case of the NJU26110, only single-byte transmission is available. The serial host interface supports "Standard-Mode (100kbps)" I2C bus data transfer. 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1 pin ="High" during the Reset initialization sequence. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor when SDOUT is Hi-Z. SSb SCK SDIN SDOUT Hi-Z bit7 MSB bit6 bit6 bit5 bit5 bit1 bit1 bit0 LSB bit7 bit0 unstable Hi-Z Fig. 4 4-Wire Serial Interface Timing Note: When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes "High". SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level. Ver.2006-11-27 -5- NJU26110 www..com WatchDog Clock The NJU26110 outputs clock pulse through WDC (No.16) pin during normal operation. The output toggle cycle (Low/High) from a WDC pin changes with sampling frequencies. (Table 7) Table7 WatchDog Clock Output Cycle Sampling Frequencies WDC Output Cycle (Low/High) Time 32 KHz 256ms 44.1KHz 186ms 48 KHz 171ms The NJU26110 generates a clock pulse through the WDC terminal after resetting the NJU26110. The WDC clock is useful to check the status of the NJU26110 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26110. When the WDC clock pulse is lost or not normal clock cycle, the NJU26110 does not operate correctly. Then reset the NJU26110 and set up the NJU26110 again. Note: If input and output of a audio signal stop and an audio interface stops, WDC can't output. That is because it has controlled based on the signal of an audio interface. -6- Ver.2006-11-27 NJU26110 www..com NJU26110 Command Table Table 8 NJU26110 Command No. Command 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Set Task CSII Mode TruBass Mode TruBass Base Control Focus Mode Focus Control Mono Input Select Sample Rate Rear Space Gain 4 Ch. Stereo Mode Delay Master Volume Input Trimmer Left Volume Right Volume Left Volume Center Volume SL Volume SR Volume SubWoofer Volume System Status TruBass Base Control SW TruBass Base Control SL / SR Focus Control L / R Focus Control SL / SR NOP Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (SRS Labs. Inc.) is required. . Ver.2006-11-27 -7- NJU26110 www..com License Information 1. The "SRS Circle SurroundII5.1", "TruSurroundXT", "TruBass", "FOCUS", "Dialog Clarity" technology rights incorporated in the NJU26110 are owned by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd.. Purchaser of NJU26110 must sign a license for use of the chip and display of the Labs trademarks. Any products incorporathing the NJU26110 must be send to SRS Labs for review. "SRS Circle SurroundII5.1", "TruSurroundXT", "TruBass", "FOCUS", "Dialog Clarity" are protected under US and foreign patents issued and/or pending. "SRS Circle SurroundII5.1", "TruSurroundXT", "TruBass", "FOCUS", "Dialog Clarity", SRS and symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the NJU26110, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set marks to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. For further information, please contact:: SRS Labs, Inc. 2909 Daimler Street. Santa Ana, CA 92705 USA Tel: 949-442-1070 Fax: 949-852-1099 http://www.srslabs.com [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -8- Ver.2006-11-27 |
Price & Availability of NJU26110
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |